Pulse signal transmission circuit

Abstract

To provide a pulse signal transmission circuit capable of transmitting a pulse signal with no fluctuation of pulse width or duty ratio, without introducing a significant increase in circuit scale or chip size.SOLUTION: In a pulse signal transmission circuit having an output transistor whose drain terminal is connected to an output terminal and having an inverter circuit for generating a signal to be inputted to its gate terminal, the output transistor and the inverter circuit are arranged between a power supply terminal to which a power supply voltage is applied and a ground point, a pulse signal inputted from an input terminal is taken as an input pulse signal, provide a delay circuit for delaying either a falling edge or a rising edge of the input pulse signal, are configured so that the pulse signal delayed by the delay circuit is inputted to the inverter circuit, and are configured so that its threshold voltage is 1 / 2 of the power supply voltage or less if the output transistor is N channel type and its threshold voltage is 1 / 2 of the power supply voltage or more if the output transistor is P channel type.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a pulse signal transmitting circuit and a technology that is effective when used in a semiconductor integrated circuit incorporating the same, and more particularly to a pulse signal transmitting circuit that has a function for preventing fluctuations in the pulse width and duty ratio of a transmitted pulse signal. [Background technology]

[0002] In a circuit that transmits or outputs a pulse signal (rectangular wave signal), a function to make the rise and fall of the output waveform have a slope to make the change gentler as a countermeasure against EMI (electromagnetic interference) is sometimes required. As an example of a pulse signal transmission circuit with such a slope control function, there is a circuit that has a resistive load type inverter with a resistive element as a load, and a CMOS inverter in the front stage that controls the on / off of the drive transistor M0 of the inverter, as shown in Figure 9.

[0003] 9, the output waveform can be given a desired slope at its rising or falling edge by the feedback capacitance Crss (=Cgd) of the gate terminal of the drive transistor M0 and the current capacity of the CMOS inverter at the previous stage that drives the drive transistor M0. By giving a slope to each of the rising and falling edges of the output waveform in this way, it is possible to suppress noise caused by a sharp change in the waveform. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-166012 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the pulse signal transmission circuit shown in Fig. 9, when a square wave signal IN as shown in Fig. 10(a) is input to the CMOS inverter in the previous stage, a signal with a waveform with gentle rising and falling edges as shown in (c) is output, but the rising delay time trise and the falling delay time tfall of the output waveform are not equal, so that the pulse width and duty ratio of the output signal OUT do not match the pulse width and duty ratio of the input signal IN. As a result, when transmitting a pulse signal having a pulse width and duty ratio required by the receiving circuit, or in a system that transmits a pulse signal with information in the pulse width and duty ratio, there is a problem that an inappropriate signal is transmitted.

[0006] Incidentally, an invention relating to a pulse width adjustment circuit having a function of adjusting the pulse width has been proposed in the past (Patent Document 1). By providing such a pulse width adjustment circuit in the preceding stage of the pulse signal transmission circuit shown in Fig. 9, it is possible to configure it to transmit a pulse signal having a desired pulse width and duty ratio. However, the pulse width adjustment circuit described in Patent Document 1 is configured to include two inverters, multiple resistive elements, and multiple switching elements, which increases the circuit size. When applied to a semiconductor integrated circuit, there is a problem that the chip size will increase significantly, especially due to the resistive elements.

[0007] This invention has been made against the background described above, and an object of the invention is to provide a pulse signal transmitting circuit that can transmit a pulse signal with no fluctuation in pulse width or duty ratio, without incurring a significant increase in circuit scale or chip size. Another object of the present invention is to provide a pulse signal transmitting circuit capable of controlling the slope of the output waveform with high precision. [Means for solving the problem]

[0008] In order to achieve the above object, the present invention provides A pulse signal transmission circuit includes an output transistor having a drain terminal connected to an output terminal, and an inverter circuit provided in a previous stage of the output transistor and generating a signal to be input to a gate terminal of the output transistor, the pulse signal transmission circuit outputting a pulse signal from the output terminal, the output transistor and the inverter circuit are disposed between a power supply voltage terminal to which a power supply voltage is applied and a ground point; a delay circuit for delaying either a rising edge or a falling edge of an input pulse signal inputted from an input terminal; The pulse signal delayed by the delay circuit is input to the inverter circuit, When the output transistor is an N-channel type, the threshold voltage of the output transistor is equal to or lower than half of a power supply voltage, When the output transistor is a P-channel type, the threshold voltage of the output transistor is set to be equal to or higher than half the power supply voltage.

[0009] According to the pulse signal transmission circuit having the above configuration, since it includes a delay circuit which receives a pulse signal and delays either the rising or falling edge of the input pulse signal, by providing the pulse signal transmission circuit with a slope control function, even if the rising delay time and falling delay time of the output waveform are not equal, the pulse signal delayed by the delay circuit is input to the inverter circuit which drives the output transistor, so that a pulse signal without fluctuation in pulse width or duty ratio can be transmitted. Also, even if an output stage for transmitting a pulse signal is configured using an output transistor in an open drain manner, and the threshold voltage of the output transistor is not 1 / 2 the power supply voltage, the duty ratio of the output pulse signal can be made to match the duty ratio of the input pulse signal by adjusting the delay time of the delay circuit.

[0010] Preferably, the inverter circuit is a CMOS inverter circuit having a P-channel MOS transistor and an N-channel MOS transistor in series, a first constant current source is connected in series with the P-channel MOS transistor between the power supply voltage terminal and an output node; A second constant current source is connected in series with the N-channel MOS transistor between the output node and the ground point. According to this configuration, the rate of change of the gate voltage of the output transistor can be adjusted by the current of the constant current source, thereby making it possible to control the rising and falling slopes of the output waveform.

[0011] Also, preferably, when the output transistor is an N-channel type, a resistive element is connected between the drain terminal of the output transistor and the power supply voltage terminal, When the output transistor is a P-channel type, a resistive element is connected between the drain terminal of the output transistor and the ground point. According to this configuration, a pulse signal can be transmitted without providing a pull-up or pull-down resistor in the circuit that receives the output pulse signal.

[0012] Furthermore, preferably, the delay circuit has a capacitor and charging and discharging means for the capacitor, and is configured to have the function of adjusting the amount of delay by changing the current value with which the discharging means discharges the capacitor in accordance with the resistance value of the resistive element.

[0013] As a result, even if the time difference between the rise delay time and the fall delay time of the output waveform varies depending on the system to which the pulse signal transmitting circuit is applied, for example due to differences in the period of the pulse signal, a pulse signal with no fluctuations in pulse width or duty ratio can be transmitted by adjusting the amount of delay in the delay circuit.

[0014] Also, preferably, the delay circuit is a switching MOS transistor and a constant current source connected in series between the power supply voltage terminal and the ground point; a capacitance element connected between a connection node of the switching MOS transistor and the constant current source and the ground point or the power supply voltage terminal; The device is configured to have the following: According to this configuration, a delay circuit that delays either the rising or falling edge of an input pulse signal can be realized by a circuit with a relatively small scale and simple configuration. Effect of the Invention

[0015] The pulse signal transmission circuit according to the present invention can transmit a pulse signal with no fluctuation in pulse width or duty ratio without causing a significant increase in circuit scale or chip size. It also has the effect of being able to precisely control the slope of the output waveform. [Brief description of the drawings]

[0016] [Figure 1] 1 is a circuit configuration diagram showing an embodiment of a pulse signal transmission circuit to which the present invention is applied. [Diagram 2] 1A, 1B, and 1C are circuit diagrams showing specific examples of falling edge delay circuits constituting the pulse signal transmission circuits of the first embodiment and the modified examples. [Diagram 3] 5A and 5B are waveform diagrams showing the relationship between the input signal IN, the potential of an internal node, and the output voltage OUT in the pulse signal transmitting circuits of the first embodiment and the modified example. [Figure 4] FIG. 2 is a circuit configuration diagram showing a first modified example of the pulse signal transmission circuit of the first embodiment. [Diagram 5] 10 is a waveform diagram showing the relationship between an input signal IN, a potential at an internal node, and an output voltage OUT in the pulse signal transmission circuit of the first modified example. FIG. [Figure 6] FIG. 4 is a circuit configuration diagram showing a second modified example of the pulse signal transmission circuit of the first embodiment. [Figure 7] FIG. 4 is a circuit configuration diagram showing a second example of a pulse signal transmission circuit according to an embodiment of the present invention. [Figure 8]11 is a waveform diagram showing the relationship between an input signal IN, a potential at an internal node, and an output voltage OUT in the pulse signal transmitting circuit of the second embodiment. FIG. [Figure 9] FIG. 1 is a circuit configuration diagram showing an example of a conventional pulse signal transmission circuit. [Figure 10] 10 is a waveform diagram showing the relationship between an input signal IN, a potential at an internal node, and an output voltage OUT in the conventional pulse signal transmitting circuit shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of a pulse signal transmission circuit to which the present invention is applied. As shown in FIG. 1, the pulse signal transmission circuit 10 of this embodiment is composed of an output stage 11 consisting of a resistive load type inverter having a resistor R0 and an N-channel MOS transistor M0 connected in series between a power supply voltage terminal and a ground point, a front-stage CMOS inverter circuit 12 that controls the on / off of the MOS transistor M0 of the output stage 11, and a falling edge delay circuit 13 that is provided in the front stage of the CMOS inverter circuit 12 and delays the falling edge of an input pulse signal IN.

[0018] The CMOS inverter circuit 12 is composed of a P-channel MOS transistor M1 and an N-channel MOS transistor M2, whose gate terminals receive a signal from the preceding falling edge delay circuit 13 in common, a constant current source CC1 connected in series between a power supply voltage terminal and the P-channel MOS transistor M1, and a constant current source CC2 connected in series between the N-channel MOS transistor M2 and a ground point, and the gate terminal of the MOS transistor M0 in the output stage 11 is connected to a connection node N2 between M1 and M2. Note that the current value I1 of the current source CC1 and the current value I2 of CC2 are the same, i.e., I1=I2.

[0019] As shown in FIG. 2A, the falling edge delay circuit 13 is composed of an inverter INV that inverts the input signal IN, a P-channel MOS transistor Mp3 and a constant current source CC3 connected in series between the power supply voltage terminal and the ground point, and a capacitor C1 connected between a connection node N1 between the transistor Mp3 and the constant current source CC3 and the ground point. The constant current sources CC1, CC2, and CC3 can be configured, for example, by current mirror circuits.

[0020] Next, the operation of the pulse signal transmitting circuit 10 of this embodiment will be described. In the conventional pulse signal transmission circuit shown in Fig. 9, the rising delay time trise and the falling delay time tfall of the output waveform are not equal as shown in Fig. 10(c) because the threshold voltage of the MOS transistor M0 in the output stage 11 is equal to or less than 1 / 2 of the power supply voltage VDD, and the timing when M0 turns on and the drain current starts to flow is before the gate terminal voltage reaches VDD / 2. In contrast, in the pulse signal transmission circuit of the embodiment in Fig. 1, a falling delay circuit 13 is provided to delay the timing when the MOS transistor M0 in the output stage 11 turns on. This makes the rising delay time trise and the falling delay time tfall of the output waveform equal.

[0021] Fig. 3(A) shows the relationship between the input signal IN, the potential V1 of the internal node N1, the gate voltage Vg of the MOS transistor M0, and the output voltage OUT in the pulse signal transmission circuit 10 of the embodiment of Fig. 1. Fig. 3(B) shows the case where the circuit of Fig. 2(B) is adopted as the falling edge delay circuit 13 in the pulse signal transmission circuit of the embodiment of Fig. 1. In Figures 3(A) and (B), Vth is the threshold voltage of the MOS transistor M0, and is smaller than VDD / 2. This relationship can be set by selecting a voltage that is more than twice Vth as the power supply voltage VDD of resistor R0. The gate voltage Vg of M0 temporarily becomes flat when it rises and falls due to the feedback capacitance of the gate terminal of the MOS transistor M0, and the output voltage OUT changes during the plateau period of Vg. In other words, by designing the circuit so that the plateau period is of an appropriate length, the net rise delay time and fall delay time of the output waveform can be set.

[0022] As shown in FIG. 3A, in the pulse signal transmission circuit 10 of the embodiment of FIG. 1, the fall of the potential V1 of the node N1 is delayed by the fall delay circuit 13 from the fall timing t1 of the input signal IN by the delay time tdelay of the delay circuit, so that the rise delay time trise and the fall delay time tfall of the output waveform are made equal. In other words, the delay time td of the falling edge delay circuit 13 is set so that trise=tfall. As a result, the pulse width and duty ratio of the output voltage OUT match those of the input signal IN, preventing fluctuations. The same is true in FIG. 3B. As described above, in the pulse signal transmission circuit shown in Fig. 9, when a square wave signal IN as shown in Fig. 10(a) is input to the CMOS inverter in the previous stage, a signal with a waveform with gentle rising and falling edges is output as shown in (c), but the rising delay time trise and the falling delay time tfall of the output waveform are not equal, and as a result, the pulse width and duty ratio of the output signal OUT do not match the pulse width and duty ratio of the input signal IN. In contrast, in the pulse signal transmission circuit 10 of this embodiment, the value of the delay time td of the falling delay circuit 13 is set so that trise=tfall, so that the pulse width and duty ratio of the output voltage OUT match the pulse width and duty ratio of the input signal IN, and fluctuations are prevented.

[0023] In addition, in the pulse signal transmission circuit 10 of the embodiment in Fig. 1, since the constant current sources CC1 and CC2 are connected in series with the P-MOS and N-MOS of the CMOS inverter circuit 12, the gate voltage Vg of M0 and the slope of the waveform at the time of rising and falling of the output voltage OUT can be adjusted with high precision to desired values, compared to a conventional pulse signal transmission circuit (see Fig. 9) without the constant current sources CC1 and CC2. However, in the pulse signal transmission circuit of the embodiment in Fig. 1, it is also possible to adopt a configuration in which the constant current sources CC1 and CC2 are omitted by adjusting the slope of the output waveform by designing the MOS transistor M0 in the output stage as in the conventional circuit.

[0024] In the pulse signal transmission circuit 10 of FIG. 1, the circuit portion excluding resistor R0 may be formed as a semiconductor integrated circuit (regulator IC) on a semiconductor chip such as single crystal silicon, and the load resistor may be connected as an external element between the external terminal and the power supply voltage terminal, or may be connected as a pull-up resistor between the input terminal and the power supply voltage terminal in the receiving circuit. Such open-drain signal transmission requiring EMI countermeasures is regulated by a communication standard for in-vehicle systems called LIN (Local Interconnect Network), for example, and the pulse signal transmission circuit of this embodiment can be applied to a signal transmission circuit constituting a system having a LIN bus. The LIN standard requires that the duty ratio of a transmission signal (pulse) be 50%. This embodiment can also be applied to a signal transmission circuit constituting an in-vehicle network system that communicates according to a standard called CAN (Controller Area Network).

[0025] In addition, when the pulse signal transmission circuit 10 of this embodiment is configured as an open-drain circuit, the fall delay circuit 13 may be provided with constant current sources CC4, CC5, etc. in parallel with the constant current source CC3, and with switches S1, S2, etc. in series with the constant current sources CC4, CC5, etc., as shown in FIG. 2B. This allows the current value for discharging the capacitor C1 to be switched according to the resistance value of the pull-up resistor on the signal receiving side, changing the fall delay time tfall of the output waveform, so that the rise delay time trise and the fall delay time tfall of the output waveform become equal regardless of the power supply voltage VDD of the pull-up resistor R0. As a result, in the open-drain pulse signal transmission circuit, it is possible to effectively prevent fluctuations in the pulse width and duty ratio of the output voltage OUT. Instead of switching the current value (constant current source) for discharging the capacitor C1, a circuit configuration that allows the capacitance value of the capacitor C1 to be switched may be adopted.

[0026] FIG. 4 shows a first modified example of the pulse signal transmitting circuit of the above embodiment. The pulse signal transmission circuit of the first modification is an application of the above embodiment (FIG. 1) to a circuit in which a P-channel MOS transistor Mp0 is used instead of an N-channel MOS transistor as the MOS transistor M0 of the output stage 11, and a rising edge delay circuit 14 is provided instead of the falling edge delay circuit 13. The threshold voltage Vthp of the MOS transistor Mp0 is higher than VDD / 2. This relationship can be set by selecting a voltage higher than twice Vthp as the power supply voltage VDD of the resistor R0. A timing chart in this modified example is shown in Fig. 5. As can be seen from Fig. 5, in this modified example as well, the rise delay circuit 14 is provided, so that the rise delay time trise and the fall delay time tfall of the waveform of the output voltage OUT can be made equal to each other, and fluctuations in the pulse width and duty ratio of the output voltage OUT can be effectively prevented.

[0027] As a specific example of the rising delay circuit 14 in this first modification example, for example, as shown in Fig. 2(C), there is a circuit including an inverter INV that inverts an input signal IN, a constant current source CC3 and an N-channel MOS transistor M3 connected in series between a power supply voltage terminal and a ground point, and a capacitor C1 connected between a connection node N1 between the transistor M3 and the constant current source CC3 and the ground point. Note that the timing chart of the pulse signal transmission circuit when the rising delay circuit 14 shown in Fig. 2(C) is used is substantially the same as the timing chart of Fig. 5 except that the rising of the potential V1 of the node N1 becomes gentle, as indicated by the dotted line A in Fig. 5. Therefore, the illustration is omitted.

[0028] Fig. 6 shows a second modification example of the pulse signal transmission circuit of the above embodiment. The pulse signal transmission circuit of the second modification example has a power supply voltage of the output stage 11 set to a voltage Vdd different from the power supply voltage VDD of the CMOS inverter circuit 12 and the falling delay circuit 13. By configuring in this way, a level shift function of outputting a signal with the potential on the high level side shifted with respect to the input signal IN can be provided to the pulse signal transmission circuit. Note that the power supply voltage Vdd of the output stage 11 can be considered to be the battery voltage, for example, when applied to an in-vehicle system. In that case, VDD < Vdd, but depending on the system used, VDD > Vdd may also be acceptable.

[0029] Next, a second embodiment of the pulse signal transmission circuit of the present invention will be described with reference to Figs. 7 and 8. As shown in Fig. 7, the pulse signal transmission circuit of the second embodiment is provided with a pulse adjustment circuit 15 that changes and outputs the pulse width of the input pulse signal IN instead of the falling delay circuit 13 in the first embodiment shown in Fig. 1. The pulse adjustment circuit 15 is configured to realize the function of the falling delay circuit 13 in the first embodiment by digital processing, and is composed of a logic circuit having a counter circuit, a logic gate circuit, etc. that operate with a clock signal ck having a period Ta sufficiently shorter than the period of the input pulse signal IN.

[0030] Specifically, the falling edge delay circuit 13 uses, for example, signals b1 to b3 having information on the cycle Tin of the input pulse signal IN as a control signal, and when the cycle Tin is long, delays the timing of the input pulse signal IN falling to a low level by one cycle Ta of the clock signal ck as shown in Fig. 8. When the cycle Tin is short, on the other hand, advances the timing of the input pulse signal IN falling to a low level by one cycle Ta of the clock signal ck. In this embodiment, the control signals a1 to a3 are 3 bits, so that the timing at which they fall to the low level can be adjusted in eight stages.

[0031] Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment. For example, in the description of the first embodiment, the current value I1 of the constant current source CC1 and the current value I2 of CC2 constituting the CMOS inverter circuit 12 are the same, but in the pulse signal transmission circuit of the second modified example having a level shift function, for example, the current value I1 of the constant current source CC1 and the current value I2 of CC2 may be made different. Furthermore, in the above embodiment, the pulse signal transmission circuit is described as being configured as one semiconductor integrated circuit, but it may be configured as a circuit that realizes the signal transmission function of a semiconductor integrated circuit having various functions. [Explanation of symbols]

[0032] 10: Pulse signal transmission circuit, 11: Output stage, 12: CMOS inverter circuit, 13: Falling edge delay circuit, 14: Rising edge delay circuit, 15: Pulse adjustment circuit, M0: Output MOS transistor, IN: Input pulse signal

Claims

1. A pulse signal transmission circuit comprising: an output transistor having a drain terminal connected to an output terminal; and an inverter circuit provided in a previous stage of the output transistor and generating a signal to be input to a gate terminal of the output transistor, the pulse signal transmission circuit outputting a pulse signal from the output terminal, the output transistor and the inverter circuit are disposed between a power supply voltage terminal to which a power supply voltage is applied and a ground point; a delay circuit for delaying either a rising edge or a falling edge of an input pulse signal inputted from an input terminal; The pulse signal delayed by the delay circuit is input to the inverter circuit, When the output transistor is an N-channel type, the threshold voltage of the output transistor is equal to or lower than half of a power supply voltage, 2. A pulse signal transmission circuit according to claim 1, wherein, when said output transistor is a P-channel type, a threshold voltage of said output transistor is equal to or higher than 1 / 2 of a power supply voltage.

2. the inverter circuit is a CMOS inverter circuit having a P-channel MOS transistor and an N-channel MOS transistor in series; a first constant current source is connected in series with the P-channel MOS transistor between the power supply voltage terminal and an output node; 2. The pulse signal transmission circuit according to claim 1, further comprising a second constant current source connected in series with said N-channel MOS transistor between said output node and said ground point.

3. When the output transistor is an N-channel type, a resistive element is connected between the drain terminal of the output transistor and the power supply voltage terminal, 3. The pulse signal transmission circuit according to claim 1, wherein when the output transistor is a P-channel type, a resistive element is connected between the drain terminal of the output transistor and the ground point.

4. 4. The pulse signal transmission circuit according to claim 3, wherein the delay circuit has a capacitor and a charging means and a discharging means for the capacitor, and is configured to have a function of adjusting the amount of delay by changing a current value with which the discharging means discharges the capacitor in accordance with a resistance value of the resistive element.

5. The delay circuit includes: a switching MOS transistor and a constant current source connected in series between the power supply voltage terminal and the ground point; a capacitance element connected between a connection node of the switching MOS transistor and the constant current source and the ground point or the power supply voltage terminal; 5. The pulse signal transmission circuit according to claim 1, further comprising:

6. 6. The pulse signal transmission circuit according to claim 1, wherein when the duty ratio of an input pulse signal is 50%, the duty ratio of the pulse signal delayed by the delay circuit is controlled to 50%.

7. 7. The pulse signal transmission circuit according to claim 1, further comprising a control circuit for controlling a rise time and a fall time of the pulse signal delayed by the delay circuit to be equal to each other.

8. 2. The pulse signal transmission circuit according to claim 1, wherein the delay circuit adjusts a delay time for delaying either the rising or falling edge of the input pulse signal so that a time (trise) required from the start of the rising edge of the input pulse signal to the rising edge of the output pulse signal output from the output terminal is equal to a time (tfall) required from the start of the falling edge of the input pulse signal to the falling edge of the output pulse signal.

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