Printed circuit board and method for manufacturing the same

Abstract

To provide a printed circuit board and a method for manufacturing the same that can prevent pad sections from separating and disappearing from the printed circuit board.SOLUTION: A printed circuit board has an insulating layer, a wiring layer embedded in the insulating layer, and a pad section protruding from the insulating layer along the height direction, the pad section includes a first portion and a second portion located below the first portion along the height direction, the width of the second portion is greater than the width of the first portion of the pad section along the planar direction that forms perpendicular to the height direction, the sidewalls of the second portion have a curved surface morphology along the height direction, and are embedded by the insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a printed circuit board and a method for manufacturing the same. [Background technology]

[0002] 2. Description of the Related Art As electronic devices in the IT field, including mobile phones, become smaller, the size of metal posts formed on printed circuit boards on which electronic components are mounted is also becoming smaller.

[0003] As the size of metal posts on printed circuit boards decreases, the metal posts may become detached and disappear from the printed circuit board. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-197133 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional problems, and an object of the present invention is to provide a printed circuit board and a manufacturing method thereof that prevent a pad portion from being separated and lost from the printed circuit board. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, a printed circuit board according to one aspect of the present invention comprises an insulating layer, a wiring layer embedded in the insulating layer, and a pad portion protruding from the insulating layer along a height direction, the pad portion includes a first portion and a second portion located below the first portion along the height direction, a width of the second portion is greater than a width of the first portion of the pad portion along a planar direction perpendicular to the height direction, a sidewall of the second portion has a curved shape along the height direction, and the sidewall of the second portion is embedded in the insulating layer.

[0007] In order to achieve the above-mentioned object, a printed circuit board according to another aspect of the present invention comprises an insulating layer, a wiring layer embedded in the insulating layer, and a pad portion protruding from the insulating layer along a height direction, wherein the pad portion includes a first portion, a second portion located below the first portion along the height direction and embedded by the insulating layer, and a third portion located above the first portion along the height direction and protruding from the insulating layer, wherein the width of the second portion is greater than the width of the first portion of the pad portion along a planar direction perpendicular to the height direction, and the width of the third portion is even greater than the width of the first portion of the pad portion along the planar direction.

[0008] The pad portion may further include a third portion located above the first portion along the height direction, and a width of the third portion may be greater than a width of the first portion of the pad portion along the planar direction. At least a part of the first portion of the pad portion and the third portion may protrude from the insulating layer along the height direction. A sidewall of the pad portion may have a concave shape toward an inside of the pad portion along the height direction. The insulating layer has a via hole overlapping the pad portion, and the pad portion can be in contact with a via located in the via hole. The insulating layer may include a first insulating layer and a second insulating layer located below the first insulating layer, the wiring layer may include a first wiring layer embedded in the second insulating layer and a second wiring layer located below the second insulating layer, the insulating layer may have a first via hole, the second insulating layer may have a second via hole, the first wiring layer and the pad portion may be connected to each other through a first via located in the first via hole, and the first wiring layer and the second wiring layer may be connected to each other through a second via located in the second via hole. The printed circuit board may further include a protective layer located below the second insulating layer, the protective layer exposing at least a portion of the second wiring layer. The printed circuit board may further include a surface treatment layer located on the pad portion. A sidewall of the pad portion may have an inward concave shape along the height direction.

[0009] In order to achieve the above object, a method for manufacturing a printed circuit board according to one aspect of the present invention includes the steps of: laminating a metal layer; forming a photoresist pattern on the metal layer; etching the metal layer using the photoresist pattern as an etching mask to form a pad portion; laminating an insulating layer in which the pad portion is embedded; forming a wiring layer to be embedded in the insulating layer; and removing a portion of the insulating layer to expose a portion of the pad portion from the insulating layer along a height direction, wherein the pad portion is formed to include a first portion and a second portion located below the first portion along the height direction, a width of the second portion is formed to be larger than a width of the first portion of the pad portion along a planar direction perpendicular to the height direction, and a sidewall of the second portion is formed to have a curved shape along the height direction, and the sidewall of the second portion is embedded in the insulating layer. Effect of the Invention

[0010] According to the printed circuit board and the manufacturing method thereof of the present invention, it is possible to prevent the pad portion from being separated and lost from the printed circuit board. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a cross-sectional view of a printed circuit board according to an embodiment. [Diagram 2] FIG. 2 is an enlarged view of a portion of FIG. [Diagram 3] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 16] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 17] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 18] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. [Figure 19] 1A to 1C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings.

[0013] As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0014] In order to clearly explain the present invention, parts that are not necessary for the explanation will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0015] Furthermore, the drawings are merely intended to facilitate understanding of the embodiments disclosed in this specification, and the drawings are not intended to limit the technical ideas disclosed in this specification, but should be understood to include all modifications, equivalents, or alternatives included in the idea and technical scope of the present invention.

[0016] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses are enlarged to clearly show various layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for convenience of explanation.

[0017] Furthermore, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, this includes not only the case where it is "directly on" another part, but also the case where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the direction opposite to gravity.

[0018] Furthermore, throughout the specification, when a part is said to "comprise" a certain element, this does not mean to exclude other elements, unless specifically stated to the contrary, but rather means that it may further include other elements.

[0019] Additionally, throughout the specification, the term "on a plane" means the part being viewed from above, and the term "on a cross section" means the part being viewed from the side, cut vertically through the cross section.

[0020] In addition, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, or that they are not only physically connected but also electrically connected, or that they are referred to by different names depending on their position or function but are integrated.

[0021] Hereinafter, various embodiments and modifications will be described in detail with reference to the drawings.

[0022] FIG. 1 is a cross-sectional view of a printed circuit board according to an embodiment, and FIG. 2 is an enlarged view of a portion of FIG.

[0023] A printed circuit board according to an embodiment will be described with reference to FIGS. 1 and 2. FIG.

[0024] Referring to FIG. 1, a printed circuit board 100 according to this embodiment includes a plurality of stacked insulating layers IL, a plurality of wiring layers ML embedded in the plurality of insulating layers IL or located on a portion of the plurality of insulating layers IL, a plurality of vias VL located in a plurality of via holes VH of the plurality of insulating layers IL, a plurality of pad portions MP, and a protective layer PL.

[0025] The plurality of insulating layers IL includes a first insulating layer IL1 and a second insulating layer IL2 overlapping along the height direction DRH. The first insulating layer IL1 and the second insulating layer IL2 include, but are not limited to, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin impregnated with a reinforcing material such as glass fiber or an inorganic filler, for example, a prepreg. In the illustrated embodiment, the plurality of insulating layers IL includes a first insulating layer IL1 and a second insulating layer IL2, but the embodiment is not limited thereto and may further include additional insulating layers.

[0026] The multiple wiring layers ML include a first wiring layer ML11 and a third wiring layer ML12 buried in a second insulating layer IL2, and a second wiring layer ML21 and a fourth wiring layer ML22 located under the second insulating layer IL2.

[0027] The multiple vias VL include a first via VL1 located in a first via hole VH1 formed in a first insulating layer IL1, and a second via VL2 located in a second via hole VH2 formed in a second insulating layer IL2.

[0028] The multiple pad portions MP include a first pad portion MP1 and a second pad portion MP2 that are partially buried in a first insulating layer IL1.

[0029] A part of the first wiring layer ML11 and a part of the first pad portion MP1 are connected to each other through the first via VL1, and a part of the first wiring layer ML11 and a part of the second wiring layer ML21 are connected to each other through the second via VL2. In the illustrated embodiment, the first via VL1 and the second via VL2 have a tapered shape in which the diameter increases downward in the height direction DRH, but the embodiment is not limited thereto.

[0030] The wiring layers ML, the vias VL, and the pads MP include a conductive metal, for example, copper, although the embodiment is not limited thereto.

[0031] The protective layer PL is located under the second insulating layer IL2 and exposes a part of the second wiring layer ML21 and the fourth wiring layer ML22. The protective layer PL is a photoresist layer, but the embodiment is not limited to this.

[0032] The second wiring layer ML21 and the fourth wiring layer ML22 are electrically connected to an external layer.

[0033] A surface treatment layer SL is disposed on the first pad portion MP1 and the second pad portion MP2.

[0034] The pad portion MP of the printed circuit board 100 according to the present embodiment will be described in more detail with reference to FIG. 2 together with FIG.

[0035] The pad part MP of the printed circuit board 100 according to the present embodiment has a side wall SC recessed toward the inside of the pad part.

[0036] Along a horizontal direction DRW perpendicular to the height direction DRH, the pad portion MP includes a middle portion (first portion) MPA having a relatively narrow width, a lower portion (second portion) MPB1 connected to the middle portion MPA and located below the middle portion MPA along the height direction DRH and having a width wider than that of the middle portion MPA, and an upper portion (third portion) MPB2 located above the middle portion MPA and having a width wider than that of the middle portion MPA. The lower portion MPB1 is embedded in the insulating layer IL, and the upper portion MPB2 protrudes from the insulating layer IL.

[0037] The side wall SC of the lower portion MPB1, which has a width greater than that of the middle portion MPA, has a curved shape along the height direction DRH.

[0038] At least the sidewall SC of the lower portion MPB1 of the sidewall SC of the pad portion MP is covered with the insulating layer IL. The sidewall SC of the lower portion MPB1 of the sidewall SC of the pad portion MP and a part of the sidewall SC of the middle portion MPA are covered with the insulating layer IL.

[0039] According to the printed circuit board 100 of the present embodiment, the pad part MP includes a middle part MPA having a sidewall SC recessed toward the inside of the pad part and having a relatively narrow width, and a lower part MPB1 and an upper part MPB2 connected to the middle part MPA and located respectively below and above the middle part MPA in the height direction DRH and having a width wider than that of the middle part MPA, and the sidewall SC of the lower part MPB1 is covered by a first insulating layer IL1. As such, the lower part MPB1 of the pad part MP, which has a relatively wide and extended width, is covered and protected by the insulating layer IL, thereby preventing the pad part MP from being separated and lost from the printed circuit board.

[0040] Therefore, the contact characteristics with the additional layer connected through the pad portion MP of the printed circuit board 100 can be improved.

[0041] 3 to 19 are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an embodiment.

[0042] A method for manufacturing a printed circuit board according to an embodiment will be described with reference to FIGS. 3 to 19 in addition to FIGS. 1 and 2.

[0043] Referring to FIG. 3, a barrier layer BL and a copper foil layer SD are formed on both sides of a carrier substrate CS including a core portion CL and thin metal layers MS laminated on both sides of the core portion CL.

[0044] 4, a first metal layer MLL is formed on a copper foil layer SD located on both sides of a carrier substrate CS. The first metal layer MLL is formed on the copper foil layer SD by a plating method, but the embodiment is not limited thereto.

[0045] Referring to Figure 5, a first photoresist layer PLL is laminated on a first metal layer MLL located on both sides of the carrier substrate CS, and multiple photoresist patterns PLP are formed at positions where multiple pad portions MP are to be formed, as shown in Figure 6.

[0046] 7, the first metal layer MLL is etched using a plurality of photoresist patterns PLP as an etching mask to form a first pad portion MP1 and a second pad portion MP2. At this time, the etching conditions are adjusted so that the plurality of pad portions MP including the first pad portion MP1 and the second pad portion MP2 have sidewalls SC recessed toward the inside of the pad portions.

[0047] As shown in FIG. 2, the first pad portion MP1 and the second pad portion MP2 include a middle portion (first portion) MPA having a relatively narrow width, and a lower portion (second portion) MPB1 and an upper portion (third portion) MPB2 connected to the middle portion MPA, located respectively below and above the middle portion MPA along the height direction DRH, and having a width wider than the middle portion MPA.

[0048] As shown in FIG. 8, the photoresist patterns PLP are removed.

[0049] As shown in FIG. 9, a first insulating layer IL1 is laminated so that a plurality of pad portions MP including a first pad portion MP1 and a second pad portion MP2 are embedded.

[0050] As shown in FIG. 10, a first via hole VH1 exposing at least a part of the first pad portion MP1 is formed in the first insulating layer IL1.

[0051] As shown in Figure 11, a first via VL1 is formed in a first via hole VH1 of a first insulating layer IL1, and a first wiring layer ML11 connected to the first via VL1 and a third wiring layer ML12 not connected to the first via VL1 are formed on the first insulating layer IL1.

[0052] As shown in FIG. 12, a second insulating layer IL2 is laminated on a first insulating layer IL1 so that the first wiring layer ML11 and the third wiring layer ML12 are embedded therein.

[0053] As shown in FIG. 13, a second via hole VH2 that exposes at least a portion of the first wiring layer ML11 is formed in the second insulating layer IL2.

[0054] As shown in Figure 14, a second via VL2 is formed in a second via hole VH2 of a second insulating layer IL2, and a second wiring layer ML21 connected to the second via VL2 and a fourth wiring layer ML22 not connected to the second via VL2 are formed on the second insulating layer IL2.

[0055] As shown in FIG. 15, a protective layer PL is formed on the second insulating layer IL2 to expose parts of the second wiring layer ML21 and the fourth wiring layer ML22.

[0056] As shown in FIG. 16, the substrate parts SUB are peeled off from both sides of the carrier substrate CS.

[0057] Hereinafter, one substrate part SUB peeled off from the carrier substrate CS will be described.

[0058] As shown in FIG. 17, the barrier layer BL is removed from the substrate portion SUB, and as shown in FIG. 18, the copper foil layer SD is removed.

[0059] 19, a portion of the first insulating layer IL1 is removed. The first insulating layer IL1 covers lower portions of the sidewalls SC of the first pad portion MP1 and the second pad portion MP2, which have a relatively wide width, but does not cover upper portions of the sidewalls SC of the first pad portion MP1 and the second pad portion MP2.

[0060] More specifically, the pad portion MP includes a middle portion MPA having an inwardly recessed sidewall SC and a relatively narrow width, and a lower portion MPB1 and an upper portion MPB2 connected to the middle portion MPA and located below and above the middle portion MPA in the height direction DRH, respectively. The lower portion MPB1 of the pad portion MP, which is relatively wide and extended, is covered with an insulating layer IL.

[0061] Finally, as shown in FIG. 1, a surface treatment layer SL is formed on the surfaces of the first pad portion MP1 and the second pad portion MP2.

[0062] The surface treatment layer SL is formed through any one of electrogold plating, electroless gold plating, immersion gold plating, OSP (organic solderability preservative) or electroless tin plating, immersion silver plating, ENIG (electroless nickel and immersion gold, electroless nickel plating / substitutional gold plating), DIG plating (Direct Immersion Gold Plating), and HASL (Hot Air Solder Levelling).

[0063] As described above, according to the method for manufacturing a printed circuit board according to this embodiment, the pad portion MP includes a relatively narrow middle portion MPA having an inwardly recessed sidewall SC, and a lower portion MPB1 and an upper portion MPB2 connected to the middle portion MPA and located respectively below and above the middle portion MPA along the height direction DRH. By forming the relatively wide and extended lower portion MPB1 of the pad portion MP to be covered with an insulating layer IL, it is possible to prevent the pad portion MP from being separated and lost, and to improve the contact characteristics with additional layers connected through the pad portion MP of the printed circuit board 100.

[0064] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0065] 100 Printed Circuit Board BL Barrier Layer CL Core CS Carrier Board IL Insulation layer IL1, IL2 First and second insulating layers ML wiring layer MLL 1st metal layer ML11, ML21, ML12, ML22 1st to 4th wiring layer MP Pad MP1, MP2 1st and 2nd pad section MPA middle part (1st part) MPB1, MPB2 lower and upper parts (2nd and 3rd parts) MS thin metal layer PL protective layer PLL 1st photoresist layer PLP photoresist pattern SC side wall SD copper foil layer SL Surface treatment layer SUB Board Section VH Via Hole VH1, VH2 1st and 2nd via holes VL Via VL1, VL2 1st and 2nd vias

Claims

1. An insulating layer; A wiring layer embedded in the insulating layer; a pad portion protruding from the insulating layer along a height direction, the pad portion includes a first portion and a second portion located below the first portion along the height direction, The width of the second portion is greater than the width of the first portion of the pad portion along a planar direction perpendicular to the height direction, The side wall of the second portion has a curved shape along the height direction, A printed circuit board according to claim 1, wherein a sidewall of the second portion is embedded in the insulating layer.

2. the pad portion further includes a third portion located above the first portion along the height direction, The printed circuit board of claim 1 , wherein the width of the third portion is greater than the width of the first portion of the pad portion along the planar direction.

3. The printed circuit board of claim 2 , wherein at least a portion of the first portion and the third portion of the pad portion protrude from the insulating layer in the height direction.

4. 4. The printed circuit board of claim 3, wherein a sidewall of the pad portion has a concave shape toward an inside of the pad portion along the height direction.

5. the insulating layer has a via hole overlapping the pad portion, The printed circuit board of claim 1 , wherein the pad portion contacts a via located in the via hole.

6. the insulating layer includes a first insulating layer and a second insulating layer located below the first insulating layer; the wiring layer includes a first wiring layer embedded in the second insulating layer and a second wiring layer located under the second insulating layer; the first insulating layer has a first via hole; the second insulating layer has a second via hole; the first wiring layer and the pad portion are connected to each other through a first via located in the first via hole; 2. The printed circuit board of claim 1, wherein the first wiring layer and the second wiring layer are connected to each other through a second via located in the second via hole.

7. a protective layer underlying the second insulating layer; The printed circuit board according to claim 6 , wherein the protective layer exposes at least a portion of the second wiring layer.

8. The printed circuit board of claim 7, further comprising a surface treatment layer located on the pad portion.

9. The printed circuit board of claim 1 , wherein a sidewall of the pad portion has a concave shape inwardly along the height direction.

10. An insulating layer; A wiring layer embedded in the insulating layer; a pad portion protruding from the insulating layer along a height direction, the pad portion includes a first portion, a second portion located below the first portion along the height direction and embedded in the insulating layer, and a third portion located above the first portion along the height direction and protruding from the insulating layer, The width of the second portion is greater than the width of the first portion of the pad portion along a planar direction perpendicular to the height direction, The printed circuit board according to claim 1, wherein the width of the third portion is greater than the width of the first portion of the pad portion along the planar direction.

11. The printed circuit board of claim 10, wherein a sidewall of the pad portion has a concave shape inwardly along the height direction.

12. depositing a metal layer; forming a photoresist pattern on the metal layer; forming a pad portion by etching the metal layer using the photoresist pattern as an etching mask; laminating an insulating layer in which the pad portion is embedded; forming a wiring layer embedded in the insulating layer; removing a portion of the insulating layer to expose a portion of the pad portion from the insulating layer along a height direction; the pad portion is formed to include a first portion and a second portion located below the first portion along the height direction, The width of the second portion is formed to be larger than the width of the first portion of the pad portion along a planar direction perpendicular to the height direction, The sidewall of the second portion is formed to have a curved shape along the height direction, a sidewall of the second portion is embedded in the insulating layer.

13. The method of claim 12, wherein at least a portion of the first portion of the pad portion protrudes from the insulating layer along the height direction.

14. the pad portion is further formed to include a third portion located on the first portion along the height direction, 13. The method of claim 12, wherein the width of the third portion is greater than the width of the first portion of the pad portion in the planar direction.

15. The method of claim 14, wherein at least a portion of the first portion and the third portion of the pad portion protrude from the insulating layer in the height direction.

16. 16. The method of claim 15, wherein a sidewall of the pad portion is formed to have a concave shape toward an inside of the pad portion in the height direction.

17. forming a via hole in the insulating layer overlapping the pad layer; 13. The method of claim 12, further comprising forming a via in contact with the pad layer and positioned within the via hole.

18. the insulating layer includes a first insulating layer and a second insulating layer located below the first insulating layer; 13. The method of claim 12, wherein the forming of the wiring layer comprises forming a first wiring layer buried in the second insulating layer to form a second wiring layer located under the second insulating layer.

19. forming a first via hole in the first insulating layer; forming a second via hole in the second insulating layer; forming a first via connecting the first wiring layer and the pad portion and positioned in the first via hole; 20. The method of claim 18, further comprising forming a second via that connects the first wiring layer and the second wiring layer and is located in the second via hole.

20. 13. The method of claim 12, wherein a sidewall of the pad portion is formed to have a concave shape inwardly along the height direction.

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