Semiconductor substrate, method for manufacturing semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device that can improve the handling ability in handling (handling) of semiconductor device.SOLUTION: A method for manufacturing a semiconductor device includes a step for preparing a main substrate, a base semiconductor part formed above the main substrate, and a compound semiconductor part formed on the base semiconductor part, and a step for separating the base semiconductor part and the compound semiconductor part so as to form a resonator surface at least on the compound semiconductor part, and separating the base semiconductor part and the compound semiconductor part into a plurality of element parts.SELECTED DRAWING: None

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate and the like.

Background Art

[0002] When miniaturizing a semiconductor device such as a semiconductor laser element, handling of the semiconductor device becomes difficult. Patent Document 1 describes a technique related to the handleability of a semiconductor laser element.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] A method for manufacturing a semiconductor device according to an aspect of the present disclosure includes a step of preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion, and a step of separating at least the base semiconductor portion and the compound semiconductor portion so as to form a resonator surface in the compound semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion into a plurality of element portions.

[0005]

[0006] Also, a template substrate in one aspect of the present disclosure includes a main substrate, a seed portion, and a mask. The mask includes a longitudinally shaped opening and a mask portion, and a notch is provided in the opening.

[0007] Also, a semiconductor device in one aspect of the present disclosure includes a base semiconductor portion and a compound semiconductor portion that is located above the base semiconductor portion and has an optical resonator including a pair of resonator surfaces. The base semiconductor portion and the compound semiconductor portion include a GaN-based semiconductor. The base semiconductor portion includes an m-plane cleavage plane of the GaN-based semiconductor.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The following description is for better understanding of the gist of the present disclosure and does not limit the present disclosure unless otherwise specified. Unless otherwise specified in this specification, "A~B" representing a numerical range means "A or more and B or less". Also, the shapes and dimensions (length, width, etc.) of the configurations shown in each drawing in this application do not necessarily reflect the actual shapes and dimensions, and are appropriately changed for clarity and simplification of the drawings.

[0010] In an embodiment of the present disclosure, a semiconductor laser diode (LD) element as an example of a semiconductor device will be described, but the semiconductor device of the present disclosure is not necessarily limited to this. The semiconductor device of the present disclosure may be, for example, a sensor having an optical resonator or a sensor having a resonator surface formed thereon.

[0011] In the following description, first, the structure of the semiconductor laser element in an embodiment of the present disclosure will be schematically described, and then the manufacturing method of the semiconductor laser element in an embodiment of the present disclosure will be described in detail.

[0012] 〔Semiconductor Laser Element〕 The semiconductor laser element 20 in an embodiment of the present disclosure will be described below with reference to FIGS. 1 and 2. FIG. 1 is a perspective view for explaining the structure of the semiconductor laser element 20. FIG. 2 is a perspective view for explaining the optical resonator LK of the semiconductor laser element 20. Note that FIG. 1 is an example, and the semiconductor laser element 20 may have a shape with the depth direction in the perspective view shown in FIG. 1 as the longitudinal direction.

[0013] In one embodiment of the present disclosure, the semiconductor laser element 20 has a structure with electrodes on the upper and lower sides (hereinafter referred to as a "double-sided electrode structure"), but is not limited thereto. For example, it may have a structure with two electrodes (anode and cathode) on the upper side (hereinafter referred to as a "single-sided two-electrode structure"). Further, the semiconductor laser element 20 may be in a state of being mounted on a support substrate (also referred to as a submount). In FIG. 1, the support substrate is omitted from the illustration.

[0014] As shown in FIGS. 1 and 2, the semiconductor laser element (semiconductor device) 20 in the present embodiment includes a base semiconductor part 8, a compound semiconductor part 9 located above the base semiconductor part 8 and including an optical resonator LK, a first electrode E1, a second electrode E2, and an insulating film DF. In the optical resonator LK, the surface from which the laser is emitted is defined as the emission surface F1, and the surface facing the emission surface F1 is defined as the opposing surface F2. The emission surface F1 and the opposing surface F2 are a pair of resonator surfaces in the optical resonator LK. Note that the specific form (element structure) of the optical resonator LK is not particularly limited.

[0015] The base semiconductor part 8 and the compound semiconductor part 9 are typically layered. Therefore, it can be said that the base semiconductor part 8 is a base semiconductor layer 8 and the compound semiconductor part 9 is a compound semiconductor layer 9. Hereinafter, they will be described as the base semiconductor layer 8 and the compound semiconductor layer 9, but the base semiconductor layer 8 and the compound semiconductor layer 9 are not necessarily limited to a layered form.

[0016] The base semiconductor layer 8 may contain, for example, a nitride semiconductor. The nitride semiconductor can be represented as, for example, AlxGayInzN (0 ≦ x ≦ 1; 0 ≦ y ≦ 1; 0 ≦ z ≦ 1; x + y + z = 1). Specific examples include gallium nitride (GaN)-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). The GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor layer 8 may be a doped type (for example, an n-type containing donors) layer or an undoped type layer.

[0017] Also, the compound semiconductor layer 9 may contain, for example, the above nitride semiconductor. Here, generally, it is difficult to reduce the defect density of the nitride semiconductor. When the surface defects of the base semiconductor layer 8 are few, the dislocations (defects) inherited from the base semiconductor layer 8 to the compound semiconductor layer 9 are reduced. Thereby, the defect density of the compound semiconductor layer 9 can be reduced. The semiconductor laser element 20 in the present embodiment may have, as the base semiconductor layer 8, a semiconductor layer formed by the ELO (Epitaxial Lateral Overgrowth) method (hereinafter sometimes referred to as an ELO semiconductor layer). Note that the base semiconductor layer 8 is not limited to the ELO semiconductor layer as long as it can reduce the defect density of the optical resonator LK included in the compound semiconductor layer 9.

[0018] The method for manufacturing the base semiconductor layer 8 is not particularly limited. For example, the base semiconductor layer 8 may be a general semiconductor layer containing a nitride semiconductor. This "general semiconductor layer" means a semiconductor layer epitaxially grown in the vertical direction on a growth substrate. In this specification, for convenience of explanation, such a general semiconductor layer may sometimes be referred to as a "GE semiconductor layer". Since the GE semiconductor layer can be formed by a known method, the description thereof is omitted.

[0019] In this specification, the substrate used for growing various semiconductor layers of a semiconductor laser element may be referred to as a "substrate for growth".

[0020] In this embodiment, as shown in FIG. 1, a semiconductor laser element 20 in which a base semiconductor layer 8 is an ELO semiconductor layer will be described. A method for manufacturing the base semiconductor layer 8 using the ELO method will be described later.

[0021] The base semiconductor layer 8, which is an ELO semiconductor layer, includes a first part (first portion) B1, a second part (second portion) B2 and a third part (third portion) B3 in which the density of threading dislocations KD extending in the thickness direction (Z direction) (threading dislocation density) is smaller than that of the first part B1. The second part B2, the first part B1, and the third part B3 are arranged in this order in the X direction, and the first part B1 is located between the second part B2 and the third part B3. The threading dislocation KD is a dislocation (defect) that extends from the lower surface or inside of the base semiconductor layer 8 to its surface or surface layer along the thickness direction of the base semiconductor layer 8. The threading dislocation density of the second part B2 and the third part B3 may be 1 / 5 or less (for example, 5×10 6 / cm 2 or less) of the threading dislocation density of the first part B1.

[0022] In the semiconductor laser element 20, a compound semiconductor layer 9 including a plurality of layers is laminated on the base semiconductor layer 8, and this lamination direction can be defined as the "upward direction". Hereinafter, the positive Z-axis side of the XYZ coordinate axes shown in FIG. 1 may be referred to as the "upper side", and the negative Z-axis side may be referred to as the "lower side". Also, the surface on the positive Z-axis side of each member may be referred to as the "upper surface", and the surface on the negative Z-axis side of each member may be referred to as the "lower surface". For an object in the shape of a substrate or substantially a substrate such as the semiconductor laser element 20, viewing the object with a line of sight parallel to the normal direction of the upper surface can be referred to as "plan view". Hereinafter, although not repeatedly described, similarly in other figures, the vertical direction is defined and the expression "in plan view" may be used.

[0023] The compound semiconductor layer 9 includes, in this order from above the base semiconductor layer 8, an n-type semiconductor portion (first-type semiconductor portion) 9N, an active portion 9K, and a p-type semiconductor portion (second-type semiconductor portion) 9P. The n-type semiconductor portion 9N, the active portion 9K, and the p-type semiconductor portion 9P are typically in a layer form. Therefore, the n-type semiconductor portion 9N can also be referred to as an n-type semiconductor layer 9N. The active portion 9K can also be referred to as an active layer 9K. The p-type semiconductor portion 9P can also be referred to as a p-type semiconductor layer 9P. Hereinafter, they will be described as the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P, but the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P are not necessarily limited to a layer form.

[0024] The p-type semiconductor layer 9P may have a ridge portion RJ. The n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P may contain the aforementioned nitride semiconductor. The various layers included in the compound semiconductor layer 9 will be specifically described later. The compound semiconductor layer 9 may be affected by the first portion B1 of the base semiconductor layer 8 and may have an increased threading dislocation density above the first portion B1.

[0025] The compound semiconductor layer 9 has an optical resonator LK at a position overlapping the second portion B2 in plan view. The optical resonator LK includes a waveguide extending between an emission surface F1 and an opposing surface F2 that constitute a pair of resonator surfaces. The distance between the emission surface F1 and the opposing surface F2 can be defined as the resonator length (resonance length) L1 of the optical resonator LK. The end faces of the active layer 9K included in the emission surface F1 and the end faces of the active layer 9K included in the opposing surface F2 may each be coated with a reflective film (for example, a dielectric film).

[0026] At least one of the emission surface F1 and the opposing surface F2 of the semiconductor laser element 20 may be an m-plane or a c-plane of the compound semiconductor layer 9 containing a nitride semiconductor. In FIG. 1 and other figures, in the XYZ coordinate axes, the positive X-axis direction can be the [11-20] direction of the nitride semiconductor, the positive Y-axis direction can be the [-1100] direction of the nitride semiconductor, and the positive Z-axis direction (thickness direction) can be the

[0001] direction of the nitride semiconductor. The m-plane that at least one of the emission surface F1 and the opposing surface F2 may have is a plane parallel to the (1-100) plane (or (-1100) plane) of the nitride semiconductor. The c-plane that at least one of the emission surface F1 and the opposing surface F2 may have is a plane parallel to the (0001) plane of the nitride semiconductor.

[0027] In the semiconductor laser element 20, at least one of the emission surface F1 and the opposing surface F2 may be included in the cleavage plane of the compound semiconductor layer 9. Each of the emission surface F1 and the opposing surface F2 may be included in the cleavage plane of the compound semiconductor layer 9. The semiconductor laser element 20 can also be configured such that the resonator length L1 is 200 [μm] or less.

[0028] The semiconductor laser element 20 is provided with a first electrode E1 and a second electrode E2 for supplying current to the optical resonator LK. The first electrode E1 can be arranged so as to overlap the optical resonator LK in a plan view when viewed in the thickness direction of the base semiconductor layer 8. Note that "two members overlap" in a plan view means that at least a part of one member overlaps the other member in a plan view when viewed in the thickness direction of each member (including a perspective plan view), and these members may or may not be in contact with each other.

[0029] The first electrode E1 is located above the compound semiconductor layer 9, may have a shape that overlaps at least a part of the ridge portion RJ in a plan view, and extends along the longitudinal direction of the optical resonator LK. The first electrode E1 is electrically connected to the ridge portion RJ in the p-type semiconductor layer 9P and functions as an anode. The first electrode E1 and the ridge portion RJ may be in contact with each other or may be connected via another layer.

[0030] The second electrode E2 may be located below the compound semiconductor layer 9. For example, it may be disposed on the lower surface of the base semiconductor layer 8. The second electrode E2 may have a shape that overlaps at least a part of the first electrode E1 in a plan view. The second electrode E2 is electrically connected to the base semiconductor layer 8 and functions as a cathode. The second electrode E2 and the base semiconductor layer 8 may be in contact with each other, or may be connected via another layer. The second electrode E2 may be in contact with the compound semiconductor portion 9 (for example, the n-type semiconductor layer 9N).

[0031] The insulating film DF is located in an upper layer than the compound semiconductor layer 9. The insulating film DF may cover the upper surface of the p-type semiconductor layer 9P except for the contact portion between the first electrode E1 and the ridge portion RJ.

[0032] 〔Manufacture of semiconductor laser element〕 A semiconductor laser may be manufactured from a laminate including a plurality of semiconductor layers (referred to as a conventional method CT). In the conventional method CT, a plurality of semiconductor lasers are formed on a growth substrate, and the plurality of semiconductor lasers are divided together with the growth substrate.

[0033] The inventors of the present invention have intensively studied a method different from the conventional method CT and have conceived a method for manufacturing the semiconductor laser element of the present disclosure. The semiconductor laser element 20 in the present embodiment is manufactured by a method including a step of forming an optical resonator on a growth substrate (forming a resonator surface at least on the compound semiconductor layer 9), generally speaking.

[0034] Hereinafter, a method for manufacturing a semiconductor laser element (a semiconductor laser element in which the base semiconductor layer 8 is an ELO semiconductor layer) in an embodiment of the present disclosure will be described. FIG. 3 is a flowchart showing an example of a method for manufacturing a semiconductor laser element in the present embodiment. FIG. 4 is a plan view and a cross-sectional view showing the configuration of a template substrate in the present embodiment.

[0035] (Step of preparing a template substrate) As shown in FIG. 3, in the method for manufacturing a semiconductor laser device according to an embodiment of the present disclosure, first, a template substrate is prepared. As shown in FIG. 4, the template substrate 7 in the present embodiment includes a main substrate 1, a base portion 4 located above the main substrate 1, and a mask 6 located above the main substrate 1 and having an opening KS and a mask portion 5. Hereinafter, the main substrate 1 and the base portion 4 may be collectively referred to as a base substrate UK. The base substrate UK and the template substrate 7 are examples of the growth substrate described above.

[0036] The base portion 4 and the mask 6 are typically layered. Therefore, the base portion 4 can also be referred to as a base layer 4, and the mask 6 can also be referred to as a mask layer 6. Hereinafter, they will be described as the base layer 4 and the mask layer 6, but the base layer 4 and the mask layer 6 are not necessarily limited to being layered. The mask 6 may be a mask pattern including the mask portion 5 and the opening KS. The opening KS is a region where the mask portion 5 does not exist, and the opening KS does not have to be surrounded by the mask portion 5.

[0037] A heterogeneous substrate having a lattice constant different from that of the nitride semiconductor can be used for the main substrate 1. Examples of the heterogeneous substrate include a silicon (Si) substrate, a sapphire (Al 2 O 3 ) substrate, a silicon carbide (SiC) substrate, and the like. The plane orientation of the main substrate 1 is, for example, the (111) plane of the Si substrate, the (0001) plane of the Al 2 O 3 substrate, or the 6H-SiC(0001) plane of the SiC substrate. However, these are merely examples, and the main substrate 1 may be any substrate and plane orientation capable of growing the base semiconductor layer 8 by the ELO method, and is not particularly limited.

[0038] The template substrate 7 may have a buffer portion 2 and a seed portion 3 in this order from the main substrate 1 side as the base layer 4. The buffer portion 2 and the seed portion 3 are typically layered. Therefore, the buffer portion 2 can also be referred to as a buffer layer 2, and the seed portion 3 can also be referred to as a seed layer 3. Hereinafter, they will be described as the buffer layer 2 and the seed layer 3, but the buffer layer 2 and the seed layer 3 are not necessarily limited to being layered.

[0039] The buffer layer 2 is a melting suppression layer that can reduce the possibility that the main substrate 1 and the seed layer 3 directly contact and melt with each other. It also has the effect of enhancing the crystallinity of the seed layer 3. The seed layer 3 is a layer that serves as a growth starting point for the base semiconductor layer 8 to be formed later. Note that, for example, when using a main substrate 1 that does not melt with the seed layer 3 which is a GaN-based semiconductor, a configuration without providing the buffer layer 2 is also possible. On the other hand, when using an Si substrate or the like for the main substrate 1, when the GaN-based semiconductor contained in the seed layer 3 comes into contact with the Si substrate, the GaN-based semiconductor and the Si substrate can melt with each other. Therefore, for example, a buffer layer 2 such as an AlN layer or an SiC layer is provided. Thereby, the possibility that the GaN-based semiconductor and the Si substrate melt can be reduced.

[0040] The mask layer 6 formed on the underlying substrate UK has a plurality of mask portions 5 and a plurality of openings KS. Both the mask portion 5 and the opening KS may have a longitudinal shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the longitudinal direction. The opening KS may have a tapered shape (a shape with a narrower width downward). As the mask layer 6, an inorganic insulating film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride film (SiON), or a titanium nitride (TiNx) film can be used. A laminated film containing the above materials may be used for the mask layer 6, and for example, a laminated film containing a silicon oxide film and a silicon nitride film can also be used.

[0041] The mask layer 6 may be formed, for example, as follows. That is, after forming an SiO 2 film on the entire surface of the underlying substrate UK using a sputtering method, wet etching is performed while partially protecting with a resist. By removing a part of the SiO 2 film, the mask portion 5 and the opening KS are formed.

[0042] The opening KS of the mask layer 6 has the function of a growth start hole that exposes the seed layer 3 and initiates the growth of the base semiconductor layer 8, and the mask portion 5 of the mask layer 6 has the function of a selective growth mask that laterally grows the base semiconductor layer 8. The width WK of the opening KS may be, for example, about 0.1 μm to 20 μm. The smaller the width of the opening KS, the smaller the number of through dislocations propagating from the opening KS to the base semiconductor layer 8. Also, in a later process, the peeling of the base semiconductor layer 8 can be facilitated. Furthermore, the areas of the second part B2 and the third part B3 with fewer surface defects can be increased. The width WM of the mask portion 5 may be, for example, about 25 μm to 200 μm.

[0043] In the method for manufacturing a semiconductor laser element according to the present embodiment, for example, in the step of preparing the template substrate 7, the mask layer 6 may be formed so that the opening KS has a shape with a notch, in other words, so that the mask portion 5 partially protrudes in the X direction. Hereinafter, the portion of the mask portion 5 that partially protrudes in the X direction will be referred to as a starting point inducing portion. By the mask layer 6 having the starting point inducing portion, the base semiconductor layer 8 and the compound semiconductor layer 9 can be formed on the template substrate 7 so as to have a starting point portion that serves as a cleavage starting point. Details will be described in Example 1 below.

[0044] (Step of forming a semiconductor layer) FIG. 5 is a cross-sectional view for explaining the semiconductor substrate in the present embodiment. The method for manufacturing a semiconductor laser element according to one aspect of the present disclosure may include a step of forming a semiconductor layer (see FIG. 3). In the step of forming a semiconductor layer, for example, after forming the base semiconductor layer 8 on the template substrate 7 by the ELO method, a compound semiconductor layer 9 is formed on a layer above the base semiconductor layer 8.

[0045] In the ELO method, for example, a seed layer 3 containing a GaN-based semiconductor is used, and SiO is used for the mask layer 6. 2Using an inorganic compound film such as a film, the base semiconductor layer 8 can be laterally grown on the mask portion 5. The thickness direction (Z direction) of the base semiconductor layer 8 formed by the ELO method is the <0001> direction (c-axis direction) of the GaN-based crystal, the width direction (X direction) of the opening KS is the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y direction) of the opening KS can be the <1-100> direction (m-axis direction) of the GaN-based crystal.

[0046] As shown in FIG. 5, the base semiconductor layer 8 includes a second portion B2 and a third portion B3 that overlap the mask portion 5 in plan view and have relatively few threading dislocations KD, and a first portion B1 that overlaps the opening KS in plan view and has more threading dislocations KD than the second portion B2 and the third portion B3. The compound semiconductor layer 9 contains a large number of threading dislocations KD above the first portion B1 under the influence of the threading dislocations KD existing on the surface of the first portion B1. The optical resonator LK can be provided so as to overlap the second portion B2 in plan view. Thereby, the possibility that the performance of the optical resonator LK is deteriorated due to the influence of the threading dislocations KD can be reduced. This is because in the compound semiconductor layer 9 on the second portion B2, the amount of dislocations (defects) introduced due to the surface defects of the second portion B2 is relatively small when the compound semiconductor layer 9 is formed.

[0047] The threading dislocation KD is a dislocation (defect) that extends from the lower surface or the inside of the base semiconductor layer 8 to its surface or surface layer along the thickness direction of the base semiconductor layer 8. The threading dislocation KD can be observed, for example, by performing CL (Cathode luminescence) measurement on the surface (parallel to the c-plane) of the base semiconductor layer 8.

[0048] The second portion B2 or the third portion B3 can be configured such that the density of non-threading dislocations in a cross section parallel to the <0001> direction is greater than the density of threading dislocations on the upper surface. The non-threading dislocation is a dislocation measured by CL in a cross section by a plane parallel to the thickness direction, and is mainly a basal plane (c-plane) dislocation.

[0049] The semiconductor substrate 10 in the present embodiment may include a template substrate 7 and a base semiconductor layer 8 formed on the template substrate 7. Further, the semiconductor substrate 10 may include the template substrate 7, the base semiconductor layer 8, and a compound semiconductor layer 9 formed on a layer above the base semiconductor layer 8.

[0050] In the semiconductor substrate 10 of the present embodiment, a plurality of base semiconductor layers 8 are formed such that a gap Gp is provided between different base semiconductor layers 8. The width WG of the gap Gp may be 4 μm or less, and may be 3 μm or less. Note that the semiconductor substrate 10 is not limited to having the gap Gp, and the base semiconductor layers 8 laterally grown from the seed layer 3 exposed at two adjacent openings KS may be in contact (joined) with each other on the mask portion 5.

[0051] When forming the base semiconductor layer 8 using the ELO method, a template substrate 7 including the main substrate 1 and the mask layer 6 on the main substrate 1 may be used, and the template substrate 7 may include a growth suppression region (for example, a region that suppresses crystal growth in the Z direction) corresponding to the mask portion 5 and a seed region corresponding to the opening KS. For example, a growth suppression region and a seed region may be formed on the main substrate 1, and the base semiconductor layer 8 may be formed on the growth suppression region and the seed region using the ELO method.

[0052] (Step of element isolation on the template substrate) FIG. 6A is a plan view for explaining an example of the element isolation step. FIG. 6B is a cross-sectional view taken along the arrow B-VI shown in FIG. 6A.

[0053] In the method for manufacturing a semiconductor laser device according to the present embodiment, on the template substrate 7, the base semiconductor layer 8 and the compound semiconductor layer 9 may be separated into a plurality of semi-element parts (first element parts) sDS so as to form resonator surfaces on at least the compound semiconductor layer 9. Here, the "semi-element part sDS" means a part (laminated body) including one piece 8V of the base semiconductor layer 8 and one piece 9V of the compound semiconductor layer 9 located above the one piece 8V of the base semiconductor layer 8 among a plurality of individual pieces aligned along the Y-axis direction, which is formed by dividing the base semiconductor layer 8 and the compound semiconductor layer 9 on the template substrate 7. The semi-element part sDS can be said to be a kind of element part, but in that it does not have members such as electrodes for driving as an element, it can be in a state during the manufacturing process of the element part as a product, that is, in the position of a semi-finished product. Such a semi-element part sDS also falls within the scope of the semiconductor device of the present disclosure. The boundary between adjacent semi-element parts sDS is referred to as a division part PS, and in FIGS. 6A and 6B, the division part PS is indicated by a thick black line.

[0054] In this specification, separating the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of semi-element parts sDS on the template substrate 7 may be referred to as "element separation". "Element separation" means the following (i) and (ii). (i) At the time when the base semiconductor layer 8 and the compound semiconductor layer 9 are separated on the template substrate 7, each of the plurality of semi-element parts sDS has an optical resonator LK individually (in other words, each of the plurality of semi-element parts sDS has a resonator surface formed at least on the compound semiconductor layer 9 individually). (ii) Before the semi-element part sDS becomes an element part (second element part) DS by a subsequent process, the one piece 8V of the base semiconductor layer 8 and the one piece 9V of the compound semiconductor layer 9 included in the semi-element part sDS are not further divided.

[0055] In FIG. 6B, various forms of the division portion PS are illustrated, but the present invention is not limited thereto. As shown in FIG. 6B, in the step of element isolation on the template substrate 7, in the division portion PS, part or all of the mask portion 5 in the thickness direction of the semiconductor substrate 10 may be divided, the mask portion 5 may not be divided, or the mask portion 5 and the underlying layer 4 may be divided. In this step, it may be configured such that not all of the main substrate 1 in the thickness direction is divided. Note that cracks may occur in a part of the main substrate 1 in the thickness direction.

[0056] In the method for manufacturing a semiconductor laser element according to the present embodiment, the specific method of the step of element isolation on the template substrate 7 is not particularly limited. For example, as described above, after forming the mask layer 6 such that the mask portion 5 has a starting point inducing portion, the base semiconductor layer 8 may be formed. In this case, the base semiconductor layer 8 can have a starting point portion that is a portion likely to be a cleavage starting point. Similarly to the base semiconductor layer 8, the compound semiconductor layer 9 can also have a cleavage starting point portion. By causing cleavage to occur from the starting point portion by thermal stress or physical external force, a plurality of semi-element portions sDS may be formed. Note that cleavage may be caused in the base semiconductor layer 8 before forming the compound semiconductor layer 9. In this case, after cleaving the base semiconductor layer 8, the compound semiconductor layer 9 may be formed on each of a plurality of pieces of the base semiconductor layer 8. By cleaving or dividing the compound semiconductor layer 9, element isolation can be performed into a plurality of semi-element portions sDS.

[0057] Further, for example, the mask portion 5 may not have a starting point inducing portion. In this case, a cleavage starting point may be formed in the base semiconductor layer 8 or the compound semiconductor layer 9 by processing such as scribing. By applying an external force to at least one of the base semiconductor layer 8 and the compound semiconductor layer 9, cleavage may be caused to occur from the starting point. Also, by scribing the compound semiconductor layer 9, cleavage may be allowed to naturally progress due to the internal stress of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0058] Further, for example, element isolation can also be performed on a plurality of semiconductor element portions sDS by etching the base semiconductor layer 8 or the compound semiconductor layer 9. In this case, the divided portion PS may be a groove portion (trench) formed by etching.

[0059] As described above, in the method for manufacturing a semiconductor laser element according to the present embodiment, (i) a step of preparing the main substrate 1, a base semiconductor portion 8 formed above the main substrate 1, and a compound semiconductor portion 9 formed on the base semiconductor portion 8, and (ii) separating the base semiconductor portion 8 and the compound semiconductor portion 9 so as to form resonator surfaces at least in the compound semiconductor portion 9, and separating the base semiconductor portion 8 and the compound semiconductor portion 9 into a plurality of element portions (for example, semiconductor element portions sDS) may be included. In the step of separating into the plurality of element portions, element separation may be performed on a plurality of semiconductor element portions sDS having resonator surfaces (for example, the emission surface F1 and the opposing surface F2) on a growth substrate (for example, on the template substrate 7). By separating the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of element portions (for example, semiconductor element portions sDS), an optical resonator LK including resonator surfaces (for example, the emission surface F1 and the opposing surface F2) may be formed.

[0060] Further, in the method for manufacturing a semiconductor laser element according to the present embodiment, (i) a step of preparing the main substrate 1, a base semiconductor portion 8 formed above the main substrate 1, and a compound semiconductor portion 9 formed on the base semiconductor portion 8, and (ii) a step of dividing the base semiconductor portion 8 and the compound semiconductor portion 9 to form a plurality of optical resonators LK each including resonator surfaces (for example, the emission surface F1 and the opposing surface F2) are included. For example, on a growth substrate (for example, on the template substrate 7), the base semiconductor layer 8 and the compound semiconductor layer 9 may be divided to form a plurality of optical resonators LK each including a resonator surface. In the step of forming the plurality of optical resonators LK, the main substrate 1 may not be divided, or the main substrate 1 may be divided into a number less than the plurality of optical resonators LK. For example, the main substrate 1 may be divided such that a plurality of semiconductor element portions sDS are provided on one piece among the plurality of pieces formed by dividing the main substrate 1.

[0061] According to the method for manufacturing a semiconductor laser element in the present embodiment, even if the semiconductor laser element 20 is miniaturized, it is easy to form the resonator surface. Therefore, it is easy to form the optical resonator LK. Then, by peeling the element portion DS formed as described later from the growth substrate, the element portion DS can be mounted on the support substrate to manufacture the semiconductor laser element 20. Thereby, the handleability can be improved. In addition, a substrate suitable for mounting can be used as the support substrate.

[0062] (Step of forming the element structure) And in the method for manufacturing a semiconductor laser element in the present embodiment, a step of forming an element structure on the semi-element portion sDS is performed on the template substrate 7. Thereby, the element portion DS is formed. At this stage, the base semiconductor layer 8 included in the element portion DS is bonded to the mask portion 5 by van der Waals force, and the element portion DS may be a part of the semiconductor substrate 10.

[0063] In the step of forming the element structure, for example, after forming a ridge portion RJ in the p-type semiconductor layer 9P in the compound semiconductor layer 9, an insulating film DF is formed, and then a first electrode E1 (anode) is formed at a position in contact with the ridge portion RJ. Then, for example, when the semiconductor laser element 20 has a single-sided two-electrode structure, after exposing a part of the upper surface of the base semiconductor layer 8 by etching or the like, a second electrode E2 may be formed on the upper surface of the base semiconductor layer 8. Thereby, the element portion DS can be obtained. By providing the ridge portion RJ and the insulating film DF, the current path between the first electrode E1 and the base semiconductor layer 8 is narrowed on the anode side, and efficient light emission can be achieved within the resonator LK. Further, the ridge portion RJ may overlap with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in plan view and may not overlap with the first portion B1. The second electrode E2 may overlap with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in plan view. Thereby, the current path from the first electrode E1 through the compound semiconductor portion 9 and the base semiconductor portion 8 to the second electrode E2 is formed in a portion overlapping with the second portion B2 (portion with few through dislocations) in plan view, and the light emission efficiency in the active layer 9K is enhanced. This is because through dislocations act as non-light-emitting recombination centers. Further, the second electrode E2 may overlap with the second portion B2 and the third portion B3 (low dislocation portion) of the base semiconductor portion 8 in plan view. In this case, the electron injection efficiency from the second electrode E2 to the base semiconductor portion 8 is enhanced.

[0064] When the semiconductor laser element 20 has a double-sided electrode structure, the second electrode E2 may be formed in a subsequent process. In this specification, an element having an element structure without the second electrode E2 obtained by the step of forming the element structure is also referred to as the element portion DS.

[0065] (Step of mounting the element portion) FIG. 7 is a flowchart showing an example of the mounting stage of the method for manufacturing a semiconductor laser element according to the present embodiment.

[0066] As shown in Fig. 7, first, a step of separating the element portion DS from the template substrate 7 is performed. For example, after bonding the first electrode E1 to the pad of the support substrate, the element portion DS can be separated from the template substrate 7 using the support substrate. Thereafter, a semiconductor laser element 20 may be formed by performing a step of coating the end face of the optical resonator LK included in the element portion DS. The support substrate on which the element portion DS is mounted may be divided to form the semiconductor laser element 20. The support substrate may have a function as a submount, whereby a chip having the semiconductor laser element 20 mounted thereon can be formed on the divided support substrate. A specific example of the support substrate will be described later.

[0067] According to the method for manufacturing the semiconductor laser element 20 in the present embodiment, the template substrate 7 or the base substrate UK can also be reused. Further, the semiconductor laser element 20 can be formed by transferring the element portion DS from a substrate not suitable for mounting to a substrate (support substrate) suitable for mounting.

[0068] 〔Manufacturing Apparatus〕 Fig. 8 is a block diagram showing an example of the manufacturing apparatus. As shown in Fig. 8, the manufacturing apparatus 70 includes a semiconductor layer forming portion 72 that forms a base semiconductor layer 8 and a compound semiconductor layer 9 on the template substrate 7, a processing portion 73 that forms an element structure, and a control portion 74 that controls the semiconductor layer forming portion 72 and the processing portion 73.

[0069] The semiconductor layer forming portion 72 may include, for example, an MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus, forms the base semiconductor layer 8 using the ELO method, and forms the compound semiconductor layer 9 on the base semiconductor layer 8. When taking out the object to be processed from a processing apparatus (film forming apparatus) such as an MOCVD apparatus, a step of element separation may be performed. The semiconductor layer forming portion 72 may be controlled such that after forming the base semiconductor layer 8, the object to be processed is once taken out from the processing apparatus and then re-introduced into the processing apparatus to form the compound semiconductor layer 9 on the base semiconductor layer 8. The semiconductor layer forming portion 72 may have a function of manufacturing the template substrate 7.

[0070] The processing unit 73 may perform an element separation process to form a semi-element part sDS. The processing unit 73 performs various processes on the semi-element part sDS located on the template substrate 7 to form an element part DS. The processing unit 73 may perform a process of separating the element part DS from the template substrate 7 using a support substrate, or may perform a process of coating the end face of the optical resonator LK.

[0071] The control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor layer forming unit 72 and the processing unit 73, for example, by executing a program stored in a built-in memory, a communicable communication device, or an accessible network. The above program and the recording medium on which the above program is stored are also included in the present embodiment.

[0072] 〔Other Embodiments〕 (a) In the method for manufacturing the semiconductor laser element 20 in another embodiment of the present disclosure, a GaN substrate may be used as a growth substrate instead of the base substrate UK. In this case, the main substrate 1 may be a GaN substrate. That is, the main substrate 1 may be a growth substrate. It is also possible to use a semiconductor substrate on which a semiconductor layer (the aforementioned GE semiconductor layer) containing a nitride semiconductor is formed without forming the mask layer 6 on the GaN substrate.

[0073] For example, by removing a part of the GE semiconductor layer in the semiconductor substrate by etching, a plurality of island-shaped semiconductor layers having the shape shown in FIG. 5 can be formed. Then, after forming a compound semiconductor layer on this semiconductor layer, an element separation process may be performed to form a plurality of semi-element parts sDS.

[0074] (b) In the manufacturing method of the semiconductor laser element 20 in other embodiments of the present disclosure, it is not limited to using the template substrate 7 configured such that the seed layer 3 overlaps the entire mask portion 5. Since the seed layer 3 only needs to be exposed from the opening KS, a template substrate 7 locally formed so that the seed layer 3 does not overlap a part or all of the mask portion 5 may be used. For example, the buffer layer 2 may be located on the main substrate 1, and the seed layer 3 may be locally provided on the buffer layer 2 so as to overlap the opening KS of the mask layer 6.

[0075] (c) In the manufacturing method of the semiconductor laser element 20 in other embodiments of the present disclosure, a base substrate UK having a configuration in which the buffer layer 2 is not provided between the main substrate 1 and the seed layer 3 may be used as a growth substrate. That is, a template substrate 7 including the base substrate UK having the main substrate 1 and the seed layer 3, and the mask layer 6 formed on the base substrate UK may be used. When using a main substrate 1 made of a material that does not melt and combine with the seed layer 3, or when using a seed layer 3 made of a material having low reactivity with the main substrate 1, the template substrate 7 can be configured without the buffer layer 2. Thereby, since the film formation process of the buffer layer 2 is omitted, the cost of the film formation process can be reduced.

[0076] For example, the seed layer 3 may be made of a material having low reactivity with the main substrate 1 and capable of serving as a growth starting point for the base semiconductor layer 8. The seed layer 3 may be, for example, an AlN layer or a SiC layer, or may be a layer containing at least one of AlN and SiC.

[0077] (d) The semiconductor laser element 20 in other embodiments of the present disclosure may have a configuration in which the base semiconductor layer 8 does not have the first part B1, that is, may have a configuration having one second part B2. For example, before separating the element portion DS from the template substrate 7, the first part B1 may be removed by etching or the like.

[0078] 〔Example 1〕 Hereinafter, the manufacturing method of the semiconductor device of the present disclosure and the like will be described in more detail with reference to examples. However, the present disclosure is not limited to each configuration described below, and various modifications are possible within the scope shown in the claims. In the following, each configuration of a plurality of embodiments of the present disclosure will be described with the same or corresponding parts in the drawings denoted by the same reference numerals. However, unless otherwise specified, forms obtained by appropriately combining the technical means disclosed in the above-described embodiment and a plurality of different embodiments described below are also included in the technical scope of the present disclosure.

[0079] FIG. 9 is a flowchart showing an example of a method for manufacturing the semiconductor laser element 20 in Example 1. In Example 1, the mask layer 6 of the template substrate 7 includes a mask portion 5 having a starting point inducing portion. Then, an ELO semiconductor layer having a starting point is formed on the template substrate 7. As shown in FIG. 9, in Example 1, first, a template substrate 7 including a starting point inducing portion is prepared on the mask layer 6, and then a semiconductor layer (base semiconductor layer 8 and compound semiconductor layer 9) including a starting point is formed on the template substrate 7.

[0080] (Step of preparing the template substrate) FIG. 10 is a cross-sectional view showing the configuration of the template substrate 7 in Example 1. FIG. 11A is an enlarged view of the main part of FIG. 10. As the main substrate 1 in the template substrate 7, a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor can be used. By using the main substrate 1 as an Si substrate, the manufacturing cost of the template substrate 7 can be reduced. As a result, the manufacturing cost of the semiconductor laser element 20 can be reduced. The main substrate 1 may be an Al 2 O 3 substrate or an SiC substrate. The main substrate 1 may be any material and plane orientation capable of growing an ELO semiconductor layer, and the material and plane orientation of the main substrate 1 are not particularly limited.

[0081] In Example 1, the underlying substrate UK may be manufactured by forming an underlying layer 4 (see FIG. 4) on the main substrate 1, or a previously prepared underlying substrate UK may be used. When using a previously prepared underlying substrate UK, it is easier to stably grow the base semiconductor layer 8 and the like. This is because when the process of forming the underlying layer 4 is performed, the influence of this process can occur in the base semiconductor layer 8 and the like.

[0082] The template substrate 7 may include, for example, a seed layer 3 as the underlying layer 4. The seed layer 3 is a layer that serves as a growth starting point for the base semiconductor layer 8 when the base semiconductor layer 8 is formed. The seed layer 3 may include a GaN-based semiconductor, aluminum nitride (AlN), SiC, graphene, or the like. The silicon carbide used for the seed layer 3 may be hexagonal 6H-SiC or 4H-SiC. The seed layer 3 may be, for example, an AlGaN layer, or may be a graded layer in which the Al composition gradually increases so as to approach GaN. The seed layer 3 can be configured to include a GaN layer. In this case, the seed layer 3 may be a single GaN layer, or the uppermost layer of the graded layer that is the seed layer 3 may be a GaN layer. The seed layer 3 may be any material and plane orientation that can grow the base semiconductor layer 8 including a nitride semiconductor.

[0083] The template substrate 7 may include a buffer layer 2 (see FIG. 4) located between the main substrate 1 and the seed layer 3 as the underlying layer 4. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, by providing a buffer layer 2 between the silicon substrate and the GaN-based semiconductor, it is possible to reduce the melting of the silicon substrate and the GaN-based semiconductor with each other. Further, the buffer layer 2 may have at least one of the effect of enhancing the crystallinity of the seed layer 3 and the effect of relaxing the internal stress of the seed layer 3.

[0084] The buffer layer 2 may typically be an AlN layer or may be a SiC layer. The SiC used for the buffer layer 2 may be either hexagonal (6H-SiC, 4H-SiC) or cubic (3C-SiC). The buffer layer 2 may be a multilayer film including at least one of an AlN film and a SiC film. The buffer layer 2 may contain a strain relaxation layer. Examples of the strain relaxation layer include a superlattice structure of AlGaN and a graded structure in which the Al composition of AlGaN is changed stepwise. The longitudinal stress of the base semiconductor layer 8 can be relaxed by the strain relaxation layer. An AlN layer, which is an example of the buffer layer 2, can be formed to a thickness of about 10 nm to about 5 μm using, for example, a MOCVD apparatus.

[0085] The base layer 4 can be formed by laminating various layers on the main substrate 1 using a MOCVD apparatus, a sputtering apparatus, or the like. For example, at least one of a buffer layer 2 (e.g., aluminum nitride) and a seed layer 3 (e.g., a GaN-based semiconductor) can be formed on the main substrate 1 using a sputtering apparatus (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). Thereby, the base substrate UK can be manufactured.

[0086] The template substrate 7 is manufactured by forming a mask layer 6 on the base substrate UK. As the mask layer 6, for example, a single-layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 °C or higher), or a laminated film including at least two of these can be used.

[0087] In Example 1, a mask layer 6 is formed on the lower base substrate UK such that a starting point inducing portion 5Y is provided in a part of the mask portion 5. The starting point inducing portion 5Y in Example 1 has a triangular shape in plan view. The starting point inducing portion 5Y has, in plan view, a vertex 5P and two sides 5A and 5B intersecting at the vertex 5P. In plan view, a virtual line segment connecting the end of side 5A and the end of side 5B, which is on the side opposite to the vertex 5P, is referred to as side 5C. A virtual triangle is formed by side 5A, side 5B, and side 5C. Side 5C can also be said to be the base of the virtual triangle. The angle formed by side 5A and side 5B is referred to as θ1, and the angle formed by side 5B and side 5C is referred to as θ2. The distance from side 5C to the vertex 5P is referred to as the protruding length H1 of the starting point inducing portion 5Y.

[0088] The starting point inducing portion 5Y may have the same thickness as the other parts of the mask portion 5. The angle θ1 may be 30° or approximately 30°, for example, about 20° to 40°. In this specification, "approximately" means within a variation range of ±10%. The angle θ1 and the angle θ2 may be the same as each other, and may be of the same degree as each other. Side 5A may have a length of, for example, about 0.1 μm to 20 μm. Side 5A and side 5B may have the same length as each other, and may have lengths of the same degree as each other. In this specification, "of the same degree" means within a range of 10% difference based on the larger value. The starting point inducing portion 5Y may have a protruding length H1 of, for example, about 0.1 μm to 10 μm.

[0089] The starting point inducing portion 5Y only needs to be able to form a portion that serves as a cleavage starting point in the base semiconductor layer 8 as described later, and the specific shape is not particularly limited. The starting point inducing portion 5Y is not limited to a shape in which the tip of the vertex 5P is sharp in plan view, and the vertex 5P may have a rounded shape. The angle θ1 and the angle θ2 of the starting point inducing portion 5Y may be different from each other. Further, the starting point inducing portion 5Y may have a rectangular shape in plan view, or may have other shapes. The portion other than the starting point inducing portion 5Y in the mask portion 5 is referred to as the main portion, and the starting point inducing portion 5Y and the main portion may have different thicknesses from each other. Further, the starting point inducing portion 5Y and the main portion may be integrally formed, or the starting point inducing portion 5Y may be formed after the main portion is formed.

[0090] The opening KS is longitudinally shaped except for the portion where the starting point inducing portion 5Y is provided, and the width is relatively narrow at the portion where the starting point inducing portion 5Y is provided. In Example 1, by providing the starting point inducing portion 5Y, the mask layer 6 is formed so as to have a notch in the opening KS. A plurality of openings KS may be periodically arranged with a first period in the X direction. The width of the opening KS may be about 0.1 μm to 20 μm. The smaller the width of the opening KS, the smaller the number of through dislocations propagating from the opening KS to the base semiconductor layer 8. Also, the peeling of the base semiconductor layer 8 in a subsequent process becomes easier. Furthermore, the area of the second portion B2 with few surface defects can be increased.

[0091] In Example 1, the mask layer 6 having the mask portion 5 may be formed, for example, as follows. First, a silicon oxide film with a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed over the entire surface of the base layer 4 using a sputtering method. Then, a resist is applied over the entire surface of the silicon oxide film. After that, the resist is patterned using a photolithography method to form a resist having a plurality of stripe-shaped openings. At this time, in Example 1, the resist at the position corresponding to the starting point inducing portion 5Y is not removed. Then, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form the mask portion 5 including the plurality of openings KS and the starting point inducing portion 5Y. Next, the mask layer 6 is formed by removing the resist by organic cleaning.

[0092] Note that in the mask layer 6, for example, in one mask portion 5, the protruding directions of the plurality of starting point inducing portions 5Y, in other words, the directions of the plurality of notches of the openings KS, may be aligned in one direction. Thereby, as will be described later, the semiconductor laser element 20 manufactured using the template substrate 7 can form, for example, a pair of resonator surfaces (emission surface F1 and opposing surface F2) on the second portion B2 (see FIG. 1 etc.) located farther from the starting point inducing portion 5Y among the second portion B2 and the third portion B3. The influence of the starting point inducing portion 5Y is less likely to occur in the second portion B2. As a result, the possibility of deterioration in the quality of the pair of resonator surfaces can be reduced. However, it goes without saying that the mask layer 6 can be formed by appropriately changing the direction of the starting point inducing portion 5Y.

[0093] (Example of the shape of the starting point inducing portion) An example of another specific shape of the starting point inducing portion 5Y will be described as follows.

[0094] FIG. 11B is a plan view showing an example of the starting point inducing portion 5Y. As shown in FIG. 11B, the starting point inducing portion 5Y of an example may have a shape in which the vertex 5P does not exceed the center of the opening KS. That is, the protruding length H1 of the starting point inducing portion 5Y may be, for example, 0.1 μm or more and less than (WK / 2) (WK: width of the opening KS). The starting point inducing portion 5Y may be, for example, an isosceles triangle or an equilateral triangle in plan view.

[0095] FIG. 11C is a plan view showing another example of the starting point inducing portion 5Y. As shown in FIG. 11C, the starting point inducing portion 5Y of an example may have a shape in which the vertex 5P exceeds the center of the opening KS. That is, the protruding length H1 of the starting point inducing portion 5Y may be, for example, (WK / 2) or more and less than WK. Also, for example, the angle θ1 and the angle θ2 may exceed 40°.

[0096] FIG. 11D is a plan view showing another example of the starting point inducing portion 5Y. As shown in FIG. 11D, the starting point inducing portion 5Y of an example may have a virtual pentagonal shape formed by combining a virtual triangle 5Y1 and a virtual quadrilateral 5Y2 in plan view. The virtual quadrilateral 5Y2 may be a square or a rectangle. The length of the virtual side 5D in which the width direction of the opening KS is the length direction of the virtual quadrilateral 5Y2 may be, for example, about 0.1 μm to 10 μm. The side 5D may be a line segment extending parallel or substantially parallel to the width direction of the opening KS. The virtual quadrilateral 5Y2 may be, for example, a trapezoid. The vertex 5P of the virtual triangle 5Y1 may be at a position exceeding the center of the opening KS or may not exceed it.

[0097] FIG. 11E is a plan view showing another example of the starting point inducing portion 5Y. As shown in FIG. 11E, the starting point inducing portion 5Y of an example may have a rectangular shape in plan view. In this case, it does not have the vertex 5P, and the distance between the side 5E in the longitudinal direction of the opening KS, which is the length direction, and the main portion of the mask portion 5 is defined as the protruding length H1. The side 5E may have a length of, for example, about 0.1 μm to 10 μm. The starting point inducing portion 5Y may be, for example, trapezoidal or parallelogram-shaped in plan view. The side 5E may be located at a position exceeding the center of the opening KS or may not be at such a position. That is, the side 5D may have a length of, for example, about 0.1 μm to 20 μm.

[0098] (Step of forming a semiconductor layer) Next, a base semiconductor layer 8 is formed on the template substrate 7. In Example 1, for example, the template substrate 7 is loaded into an MOCVD apparatus, and a GaN-based semiconductor layer is formed by the ELO method. FIG. 12 is a cross-sectional view showing an example of the lateral growth of the base semiconductor layer 8 in Example 1. The base semiconductor layer 8 in Example 1 is a nitride semiconductor (for example, a GaN-based semiconductor layer) and is obtained by forming a film on the c-plane on the template substrate 7. The base semiconductor layer 8 may be an n-type semiconductor layer having a donor. In FIG. 12 and the like, the [-1100] direction of the GaN-based semiconductor is the positive Y-axis direction, the [11-20] direction of the GaN-based semiconductor is the positive X-axis direction, and the

[0001] direction of the GaN-based semiconductor is the positive Z-axis direction (thickness direction).

[0099] As shown in FIG. 12, in the ELO method, first, an initial growth layer SL is formed on the seed layer 3, and then the base semiconductor layer 8 can be laterally grown from the initial growth layer SL. The initial growth layer SL is the starting point of the lateral growth of the base semiconductor layer 8 and is a part of the first portion B1. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the base semiconductor layer 8 in the Z direction (c-axis direction) or in the X direction (a-axis direction).

[0100] Here, the deposition of the initial growth layer SL is stopped at the timing immediately before the edge of the initial growth layer SL climbs onto the upper surface of the mask portion 5 (the stage of contacting the upper end of the side surface of the mask portion 5) or immediately after climbing onto the upper surface of the mask portion 5 (that is, at this timing, the ELO deposition conditions are switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions). Thus, the lateral deposition is performed from the state where the initial growth layer SL slightly protrudes from the mask portion 5, so that it becomes difficult for the material to be consumed in the thickness direction growth of the base semiconductor layer 8, and the base semiconductor layer 8 can be laterally grown at high speed. The initial growth layer SL may be formed to have a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0101] In Example 1, the base semiconductor layer 8 was an n-type GaN layer, and using an MOCVD apparatus, ELO deposition of Si-doped GaN was performed on the template substrate 7. As an example of the ELO deposition conditions, the substrate temperature: 1120 °C, the growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH 3 : 15 slm, V / III = 6000 (the ratio of the supply amount of group V raw material to the supply amount of group III raw material) can be adopted. The initial growth layer SL selectively grows on the seed layer 3 (the GaN layer that is the uppermost layer of the seed layer 3) exposed in the opening KS, and subsequently laterally grows on the mask portion 5. Then, the lateral growths were stopped before the base semiconductor layers 8 that laterally grow from both sides on the mask portion 5 meet.

[0102] Here, in Example 1, since the mask layer 6 includes the starting point inducing portion 5Y, disturbance may occur in the lateral growth of the base semiconductor layer 8 in the portion where the starting point inducing portion 5Y exists. FIG. 13 is a plan view for explaining the base semiconductor layer 8 in Example 1.

[0103] As shown in FIG. 13, in Example 1, the base semiconductor layer 8 has a starting point portion 8K that serves as a starting point for cleavage. The starting point portion 8K is naturally formed in the base semiconductor layer 8 by growing the base semiconductor layer 8 from an opening KS having a notch-shaped configuration. Note that the relationship between the shape of the starting point inducing portion 5Y and the shape of the starting point portion 8K can vary depending on the growth conditions of the base semiconductor layer 8. The starting point portion 8K may be smaller than, larger than, or of the same degree as the shape of the starting point inducing portion 5Y. An example of the starting point portion 8K will be described below.

[0104] For example, the base semiconductor layer 8 may have an oblique meeting portion 8N that extends from the position of the starting point inducing portion 5Y of the mask layer 6 to the position of the starting point portion 8K of the base semiconductor layer 8 in a plan view. This oblique meeting portion 8N is a portion where semiconductor layers grown in an oblique direction with respect to the X direction (a-axis direction) meet. The oblique meeting portion 8N may be, for example, a grain boundary, or a portion having a greater crystal structure disorder (i.e., more lattice defects) than other portions in the base semiconductor layer 8. In FIG. 13, the oblique meeting portion 8N is illustrated by a solid line. When the base semiconductor layer 8 has the oblique meeting portion 8N, the oblique meeting portion 8N can be observed, for example, by performing CL measurement.

[0105] FIG. 14 is an enlarged view for explaining the growth state of the base semiconductor layer 8 around the starting point inducing portion 5Y in Example 1. As shown in FIG. 14, first, an initial growth layer SL is formed from the opening KS. At this time, in portions other than the periphery of the starting point inducing portion 5Y in the opening KS, the initial growth layer SL is formed so as to climb onto the upper surface of the mask portion 5 by lateral growth in the <11-20> direction (i.e., the a-axis direction) of the GaN-based semiconductor. On the other hand, in the peripheral portion of the starting point inducing portion 5Y in the opening KS, due to the presence of the starting point inducing portion 5Y, a notch may occur in a part of the initial growth layer SL that has grown so as to climb from the opening KS onto the upper surface of the mask portion 5. For example, in a plan view, the direction orthogonal to the side 5A of the starting point inducing portion 5Y may be the m-plane direction (e.g., [10-10] direction) of the GaN-based semiconductor, and the direction orthogonal to the side 5B may be another m-plane direction (e.g., [01-10] direction) of the GaN-based semiconductor. The growth rate in the m-plane direction in the GaN-based semiconductor is smaller than the growth rate in the a-plane direction. The base semiconductor layer 8 may grow while maintaining the notch formed in the initial growth layer SL.

[0106] The inclined junction portion 8N can be generated, for example, by the joining of semiconductor layers grown in the [10-10] direction and the [01-10] direction. After the inclined junction portion 8N is generated in the vicinity of the mask portion 5, it can also exist on the surface of the base semiconductor layer 8 after film formation by affecting (propagating) to the surface of the base semiconductor layer 8. The starting point portion 8K may have a shape with a thin tip such as a triangular shape in a plan view. As a result, stress is likely to concentrate at one point during cleavage. As a result, a good cleavage plane can be easily obtained. Further, the starting point portion 8K may have an end face that is the m-plane of the GaN-based semiconductor. Note that the end face of the starting point portion 8K does not have to be the m-plane of the GaN-based semiconductor.

[0107] When the interval between a plurality of starting points 8K in the base semiconductor layer 8 (the distance between the tips of two starting points 8K) is defined as L2 (see FIG. 17), this interval L2 corresponds to the resonator length L1 (see FIG. 2). The length of the interval L2 may be about 20 μm to 200 μm. When the interval L2 is short, the number of locations where internal stress is released by cleavage increases. Therefore, when cleaving during cooling, which will be described later, the possibility of element separation occurring at unintended locations can be reduced. The interval L2 may be 300 μm or more. When the interval L2 is increased, the possibility of the existence of starting points 8K where cleavage does not occur during cleavage during cooling, which will be described later, can be reduced, and the yield of semiconductor device manufacturing can be improved.

[0108] In the film formation of the base semiconductor layer 8, it is preferable to reduce the mutual reaction between the base semiconductor layer 8 and the mask portion 5 and maintain a state in which the base semiconductor layer 8 and the mask portion 5 are in contact with each other by van der Waals forces. That is, the base semiconductor layer 8 and the mask portion 5 may be in contact mainly by van der Waals forces.

[0109] (Step of forming a compound semiconductor layer) In Example 1, after manufacturing a semiconductor substrate 10 in which a base semiconductor layer 8 is formed on a template substrate 7 using an MOCVD apparatus, without once taking out the semiconductor substrate 10 from the MOCVD apparatus, a compound semiconductor layer 9 is formed on the base semiconductor layer 8 using the MOCVD apparatus. Further, without taking out from the MOCVD apparatus during the formation of the laminated structure which is the compound semiconductor layer 9, the film formation process of the above laminated structure is continuously performed using the MOCVD apparatus. The compound semiconductor layer 9 includes a nitride semiconductor layer (for example, a GaN-based semiconductor layer).

[0110] FIG. 15 is a cross-sectional view showing the structure of the compound semiconductor layer 9 in Example 1. As shown in FIG. 15, the compound semiconductor layer 9 is formed by sequentially forming an n-type semiconductor layer 9N having a donor, an active layer 9K, and a p-type semiconductor layer 9P having an acceptor. The n-type semiconductor layer 9N is formed by sequentially forming a first contact layer 9A, a first cladding layer 9B, and a first optical guide layer 9C. The p-type semiconductor layer 9P is formed by sequentially forming a second optical guide layer 9D, an electron blocking layer 9E, a second cladding layer 9F, and a second contact layer 9G. Note that in the compound semiconductor portion 9, the second optical guide layer 9D and the electron blocking layer 9E may be arranged to be interchanged with each other in the p-type semiconductor layer 9P. For example, the p-type semiconductor layer 9P may be formed by sequentially forming an electron blocking layer 9E, a second optical guide layer 9D, a second cladding layer 9F, and a second contact layer 9G.

[0111] For example, an n-type GaN layer can be used for the first contact layer 9A, and an n-type AlGaN layer can be used for the first cladding layer 9B. The first cladding layer 9B may be an n-type GaN-based semiconductor layer, an n-type AlGaN-based semiconductor layer, or an n-type AlInGaN-based semiconductor layer, and may have a layer thickness of about 0.8 μm to 2 μm, for example. When GaN that does not contain Al or the like is used for the first cladding layer 9B, deposition of the GaN-based semiconductor on the surface of the mask portion 5 can be suppressed, and the yield at the time of peeling (at the time of the step of separating the element portion DS from the template substrate 7, which will be described later) is improved. Further, for example, an n-type GaN layer may be used for the first optical guide layer 9C, and it may be an InGaN layer having an In composition of about 3 to 10%. The first optical guide layer 9C may have a layer thickness of about 50 nm.

[0112] For example, an MQW (Multi-Quantum Well) structure including an InGaN layer can be used for the active layer 9K. The active layer 9K may typically have a structure of 5 to 6 periods. The In composition varies depending on the target emission wavelength. For example, for blue emission (near a wavelength of 450 nm), the In concentration may be about 15 to 20%. For green emission (near a wavelength of 530 nm), the In concentration may be about 30%.

[0113] For the second optical guide layer 9D, for example, a p-type AlGaN layer can be used. The second optical guide layer 9D may have, for example, an Al composition of about 15 to 25%, and may have a layer thickness of about 5 to 25 nm. For the electron blocking layer 9E, for example, a p-type GaN layer may be used, and it may be an InGaN layer with an In composition of about 3 to 10%. The electron blocking layer 9E may have a layer thickness of about 50 nm. For the second cladding layer 9F, for example, a p-type AlGaN layer may be used. The second cladding layer 9F may be a p-type GaN-based semiconductor layer, an AlGaN-based semiconductor layer, or an AlInGaN-based semiconductor layer, and may have a layer thickness of about 0.1 μm to 1 μm. For the second contact layer 9G, for example, a p-type GaN layer can be used. The second contact layer 9G may have a layer thickness of about 0.1 μm to 0.3 μm. Although not shown, a high-doped layer with a layer thickness of about 10 nm using Mg as a dopant may be formed on the surface of the second contact layer 9G.

[0114] Regarding the thickness of each layer of the compound semiconductor layer 9, it can be such that the base semiconductor layer 8 > the first cladding layer 9B > the first optical guide layer 9C > the active layer 9K, and the base semiconductor layer 8 > the second cladding layer 9F > the second optical guide layer 9D > the active layer 9K. Also, regarding the refractive index of each layer of the compound semiconductor layer 9 (the refractive index of the light generated in the active layer 9K), it can be such that the first cladding layer 9B < the first optical guide layer 9C < the active layer 9K, and the insulating film DF < the second cladding layer 9F < the second optical guide layer 9D < the active layer 9K.

[0115] FIG. 16 is a plan view for explaining the compound semiconductor layer 9 in Example 1. As shown in FIG. 16, the compound semiconductor layer 9 is formed in a shape having a starting portion 9T corresponding to the starting portion 8K of the base semiconductor layer 8. This is because it is difficult to form the compound semiconductor layer 9 at the position of the starting portion 8K of the base semiconductor layer 8. The starting portion 9T may have an end face that is the m-plane of the GaN-based semiconductor by being formed in a shape corresponding to the starting portion 8K. Note that the end face of the starting portion 9T does not have to be the m-plane of the GaN-based semiconductor.

[0116] The steps described above can be organized as follows. That is, in Example 1, first, a step of preparing a main substrate 1, a base semiconductor layer 8 formed above the main substrate 1, and a compound semiconductor layer 9 formed on the base semiconductor layer 8 is performed. A notch is formed in the opening KS of the mask layer 6. As a result, a starting point 8K is naturally formed in the base semiconductor layer 8. Then, the compound semiconductor layer 9 is formed on the base semiconductor layer 8 having the starting point 8K. As a result, a starting point 9T is naturally formed in the compound semiconductor layer 9.

[0117] (Step of element isolation on the template substrate) Next, by cooling the semiconductor substrate 10 on which the compound semiconductor layer 9 is formed, element isolation is performed on the template substrate 7 into a plurality of semi-element portions sDS. FIG. 17 is a plan view for explaining an example of the element isolation step in Example 1.

[0118] The film formation of the compound semiconductor layer 9 may be performed under high temperature conditions using an MOCVD apparatus. In this case, a cooling step exists in the MOCVD apparatus.

[0119] Here, in Example 1, the thermal expansion coefficients of the base semiconductor layer 8 and the compound semiconductor layer 9 may be different from the thermal expansion coefficient of the main substrate 1. In this case, due to the difference in thermal expansion coefficient between the base semiconductor layer 8 and the compound semiconductor layer 9 and the main substrate 1, internal stress is generated in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0120] Also, in Example 1, the main substrate 1 and the base semiconductor layer 8 may have different lattice constants from each other. In this case, due to the difference in lattice constant between the main substrate 1 and the base semiconductor layer 8, internal stress is generated in the base semiconductor layer 8. Affected by the internal stress of the base semiconductor layer 8, internal stress may also be generated in the compound semiconductor layer 9. By using a heterogeneous substrate (for example, an Si substrate) different from the GaN-based semiconductor for the main substrate 1, it is possible to easily generate internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0121] As shown in FIG. 17, when the semiconductor substrate 10 is cooled, due to the internal stress of the base semiconductor layer 8 and the compound semiconductor layer 9, a split portion PS may be generated by splitting starting from the starting portions 8K and 9T having a notch shape. That is, in the first embodiment, splitting may occur spontaneously during the cooling of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0122] The base semiconductor layer 8 and the compound semiconductor layer 9 may each have starting portions 8K and 9T in which the tips of the notches are thin. In this case, since stress is likely to concentrate at one point, it is easy to generate a high-quality cleavage plane by cleavage. The shapes of the starting portions 8K and 9T are affected by the shape of the starting portion inducing portion 5Y of the mask portion 5 in the mask layer 6. The shape of the starting portion inducing portion 5Y can affect the quality of the cleavage plane.

[0123] Also, tensile stress may be generated as internal stress in the base semiconductor layer 8. For example, when the thermal expansion coefficient of the main substrate 1 is larger than that of the base semiconductor layer 8, compressive stress is generated in the base semiconductor layer 8, and when the thermal expansion coefficient of the main substrate 1 is smaller than that of the base semiconductor layer 8, tensile stress is generated in the base semiconductor layer 8. When splitting the base semiconductor layer 8 in which tensile stress is generated, the possibility that the individual pieces of the split base semiconductor layer 8 come into contact with each other can be reduced. Therefore, the possibility that the end faces of the split base semiconductor layer 8 are damaged can be reduced. And if splitting occurs so that the base semiconductor layer 8 is torn from the starting portion 8K, the cleavage plane is likely to become smooth.

[0124] In Example 1, when cooling the semiconductor substrate 10, the base semiconductor layer 8 and the compound semiconductor layer 9 may be cleaved and separated into a plurality of semi-element parts sDS having the optical resonator LK on the template substrate 7. In this case, it is not necessary to separately perform a process for cleaving the base semiconductor layer 8 and the compound semiconductor layer 9, and the manufacturing cost of the semiconductor laser element 20 can be reduced. In addition, a semi-element part sDS having an optical resonator LK with a short resonator length can be manufactured. For example, the length of the interval L2 can be set to about 20 μm to 200 μm, and therefore, the resonator length L1 can be set to about 20 μm to 200 μm.

[0125] Further, after cooling the semiconductor substrate 10, when there is a portion where no split portion PS occurs from the starting portion 9T, that is, when there is a starting portion 9T where no cleavage has occurred, a process of cleaving the starting portion 9T may be further performed. For example, a cleavage may be generated in the starting portion 9T by applying a blade to the portion of the starting portion 9T and applying a force in a direction perpendicular to the plane direction. In this case, since the cleavage can be generated in the starting portion 9T relatively reliably, the yield can be improved. Alternatively, a cleavage may be generated in the starting portion 9T by applying vibration to the portion of the starting portion 9T. In this case, since the process can be performed relatively easily, the manufacturing process can be simplified. Further, by raising or lowering the temperature of the semiconductor substrate 10 from room temperature, a thermal stress may be applied to the starting portion 9T by utilizing the difference in the thermal expansion coefficients of the main substrate 1 and the base semiconductor layer 8 to generate cleavage.

[0126] FIG. 18 is an exploded perspective view for explaining the configuration of the semi-element part sDS in Example 1. In FIG. 18, for convenience of explanation, the template substrate 7 and the base semiconductor layer 8 are shown virtually separated, but actually, the base semiconductor layer 8 and the mask part 5 are in contact with each other. Further, the base semiconductor layer 8 has a joint part 8S corresponding to the initial growth layer SL on the lower surface, and the joint part 8S and the seed layer 3 are joined to each other. Further, in FIG. 18, only a part of the template substrate 7 is shown, not the whole.

[0127] As shown in FIG. 18, the base semiconductor layer 8 in the semi-element portion sDS has a first base end face 8X and a second base end face 8Y adjacent to the first base end face 8X at an angle. The base semiconductor layer 8 may have a third base end face 8Z adjacent to the second base end face 8Y at an angle and corresponding to the a-plane of the GaN-based semiconductor (for example, parallel to the a-plane). The second base end face 8Y may be located between the first base end face 8X and the third base end face 8Z. The semi-element portion sDS may have two first base end faces 8X and two second base end faces 8Y as end faces of the third portion B3.

[0128] The first base end face 8X may include a first partial face 8X1, a second partial face 8X2, and a third partial face 8X3. The first partial face 8X1 is a part of the first base end face 8X and is the face at the position corresponding to the first portion B1 of the base semiconductor layer 8. The second partial face 8X2 is the partial face at the position corresponding to the second portion B2 on the first base end face 8X. The third partial face 8X3 is the partial face at the position corresponding to the third portion B3 on the first base end face 8X. The first partial face 8X1 is located between the second partial face 8X2 and the third partial face 8X3.

[0129] The third partial face 8X3 may be a face where the portion corresponding to the aforementioned oblique meeting portion 8N is divided, and may be an m-plane cleavage face formed by cleavage of the base semiconductor layer 8 starting from the starting portion 8K. The second partial face 8X2 may be an m-plane cleavage face formed by cleavage of the base semiconductor layer 8 starting from the starting portion 8K and may be flush with the emission face F1 of the optical resonator LK. Also, the first partial face 8X1, the second partial face 8X2, and the third partial face 8X3 may be flush with each other. The surface roughness of the second partial face 8X2 may be smaller than that of the third partial face 8X3. The density of dislocations (dislocations measured by CL on the cleavage face, mainly basal plane dislocations) in the second partial face 8X2 may be equal to or greater than the through dislocation density of the second portion B2.

[0130] The second base end face 8Y is the face included in the starting point portion 8K of the notch shape in the base semiconductor layer 8 before cleavage, and is not the cleavage face formed by cleavage. Depending on the shape of the starting point inducing portion 5Y of the mask portion 5, the starting point portion 8K may have the end face of the ELO semiconductor layer grown in the m-axis direction. In this case, the second base end face 8Y, although not a cleavage face, may be the m-plane of the GaN-based semiconductor. Further, the compound semiconductor portion 9 may have a side face 9S located above the second base end face 8Y. The surface roughness of at least one of the pair of resonator faces (emission face F1 and opposing face F2) can be made smaller than the surface roughness of the side face 9S.

[0131] The angle (inner angle) formed by the first base end face 8X and the second base end face 8Y is referred to as θ3. The angle θ3 may be an obtuse angle, for example, 120° or approximately 120°, and for example, may be about 110° to 130°.

[0132] As described above, in Example 1, by element-separating the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of first element portions (half-element portions sDS), an optical resonator LK (see FIGS. 1 and 2) including a resonator face can be formed. In FIG. 18, the optical resonator LK is exemplarily shown at a position overlapping the second portion B2 in plan view, but in the half-element portion sDS, the position of the optical resonator LK in the X direction is not necessarily limited. The optical resonator LK will be described in more detail later.

[0133] Also, in Example 1, it can be said that an optical resonator LK including a resonator face is formed by dividing the base semiconductor layer 8 and the compound semiconductor layer 9 so that not all of the main substrate 1 in the thickness direction is divided.

[0134] The emission surface F1 and the opposing surface F2 of the optical resonator LK may each be the m-plane of the compound semiconductor layer 9 and may be included in the cleavage plane of the compound semiconductor layer 9. Each of the emission surface F1 and the opposing surface F2 can be formed by m-plane cleavage of the compound semiconductor layer 9, which is a nitride semiconductor layer (for example, a GaN-based semiconductor layer). In the semi-element portion sDS, a trace of a cleavage starting point (for example, the second base end face 8Y) for cleavage may be present in at least one of the base semiconductor layer 8 and the compound semiconductor layer 9. Since the emission surface F1 and the opposing surface F2 are the m-plane, the reflectivity of the resonator surface of the optical resonator LK can be improved.

[0135] (Step of forming an element structure) Next, a step of forming an element structure is performed on the semiconductor substrate 10 having a plurality of semi-element portions sDS. For example, a ridge portion RJ is formed in the p-type semiconductor layer 9P, and then an insulating film DF and a first electrode E1 are formed to form the element portion DS. In Example 1, a semiconductor laser element 20 having a double-sided electrode structure is manufactured. Therefore, the element portion DS does not include the second electrode E2, and the second electrode E2 may be provided in a later step.

[0136] FIG. 19 is a perspective view for explaining the configuration of the element portion DS in Example 1. In FIG. 19, the template substrate 7 is omitted from the illustration. FIG. 20 is a cross-sectional view showing the configuration of the element portion DS in Example 1.

[0137] As shown in FIGS. 19 and 20, the compound semiconductor layer 9 may include a ridge portion (ridge portion) RJ that overlaps the first electrode E1 in plan view. The ridge portion RJ may include a part of the second cladding layer 9F and the electron blocking layer 9E (see FIG. 15) (the portion that overlaps the first electrode E1 in plan view). The ridge portion RJ has a shape with the Y direction as the longitudinal direction, and an insulating film DF may be provided so as to cover the side surface of the ridge portion RJ. For the insulating film DF, for example, a single-layer film or a laminated film containing oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta can be used. The film thickness of the insulating film DF can be set to about 10 to 500 nm.

[0138] The refractive index of the insulating film DF is smaller than the refractive indices of the second optical guide layer 9D and the second cladding layer 9F. By providing the ridge portion RJ and the insulating film DF, the current path between the first electrode E1 and the base semiconductor layer 8 is narrowed on the anode side, and efficient light emission can be achieved within the resonator LK.

[0139] The first electrode E1 is provided, for example, on the upper surface of the ridge portion RJ and functions as an anode. Examples of the material of the first electrode E1 include single-layer films or multi-layer films such as metals or alloys of Ni, Rh, Cr, Au, W, Pt, Ti, Al, etc., and conductive oxides containing at least one selected from Zn, In, and Sn. Examples of the conductive oxide include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), GZO (Gallium-doped Zinc Oxide), etc. The thickness of the first electrode E1 may be, for example, about 0.1 to 2 μm.

[0140] The optical resonator LK includes a part of each of the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P (the portion overlapping the first electrode E1 in plan view). For example, the optical resonator LK is composed of including a part of each of the first cladding layer 9B, the first optical guide layer 9C, the active layer 9K, the second optical guide layer 9D, the electron blocking layer 9E, and the second cladding layer 9F (the portion overlapping the first electrode E1 in plan view).

[0141] In the optical resonator LK, the refractive index (optical refractive index) decreases in the order of the active layer 9K, the first optical guide layer 9C, and the first cladding layer 9B, and also decreases in the order of the active layer 9K, the second optical guide layer 9D, and the second cladding layer 9F. Therefore, the light generated by the combination of the holes supplied from the first electrode E1 and the electrons supplied from the second electrode E2 within the active layer 9K is confined within the optical resonator LK (especially the active layer 9K), and laser oscillation occurs due to the stimulated emission and feedback action in the active layer 9K. The laser light generated by the laser oscillation is emitted from the light emission region EA of the emission surface F1.

[0142] Since the output surface F1 and the opposing surface F2 of the optical resonator LK are formed by m-plane cleavage, they are excellent in flatness and perpendicularity to the c-plane (parallelism between the output surface F1 and the opposing surface F2), and have a high light reflectivity. Therefore, the reflection loss can be reduced, and stable laser oscillation is possible even at a short resonance length of 200 μm or less where the optical gain is small. Since the output surface F1 and the opposing surface F2 are formed above the second part B2 which is a low dislocation part, the flatness of the cleavage surface is excellent and a high light reflectivity is realized.

[0143] In Example 1, the sum T1 of the thickness of the base semiconductor layer 8 and the thickness of the compound semiconductor layer 9 can be 50 [μm] or less. If this sum of thicknesses T1 is too large, it may become difficult to cleave so that the resonator length becomes 200 μm or less. The ratio of the resonator length L1 (see Fig. 2) to the thickness of the second part B2 of the base semiconductor layer 8 can be set to 1 to 20. Also, the direction orthogonal to the direction of the resonator length L1 is the first direction (X direction), the size of the second part B2 in the X direction is defined as the width W2 of the second part B2, and the ratio of the resonator length L1 to the width W2 of the second part B2 can be set to 1 to 10. Further, the size of the first part B1 in the X direction is defined as the width W1 of the first part, and the ratio of the resonator length L1 to the width W1 of the first part can be set to 1 to 200.

[0144] (Step of separating the element part from the template substrate) Next, a step of separating the element part DS from the template substrate 7 is performed. Fig. 21 is a cross-sectional view schematically showing the step of separating the element part DS from the template substrate 7 in the manufacturing method of the semiconductor laser element of Example 1. In Fig. 21, only one element part DS is illustrated, but it goes without saying that the process of separating a plurality of element parts DS from the template substrate 7 may be performed. Also, in Fig. 21, the illustration of the ridge part RJ is simplified.

[0145] As shown in FIG. 21, first, the mask portion 5 of the template substrate 7 may be removed by etching using hydrofluoric acid, buffered hydrofluoric acid, or the like. The insulating film DF may be protected by a resist or the like so that the insulating film DF is not removed together with the mask portion 5. In Example 1, after the element portion DS is formed on the template substrate 7, the mask portion 5 may be removed. In this case, since the mask portion 5 can be removed while the element portion DS is fixed to the template substrate 7, the yield in the manufacture of the semiconductor laser element 20 can be improved. By removing the mask portion 5, the base semiconductor layer 8 and the underlying substrate UK are coupled via the joining portion 8S (weak portion), and the element portion DS can be easily separated from the underlying substrate UK.

[0146] Next, for example, a step of separating the element portion DS from the template substrate 7 may be performed so as to also serve as a step of bonding the element portion DS to the support substrate SK. The specific shape of the support substrate SK is not particularly limited. However, the support substrate SK in Example 1 will be described as follows with reference to FIGS. 22 and 23. FIG. 22 is a perspective view schematically showing a state in which the element portion DS is bonded to the support substrate SK. FIG. 23 is a cross-sectional view schematically showing a state in which the element portion DS is bonded to the support substrate SK.

[0147] As shown in FIGS. 21 to 23, the support substrate SK includes conductive first and second pads P1 and P2. For example, the first electrode E1 may be connected to the first pad P1 via the first junction A1. By joining at least the first electrode E1 and the first junction A1, the element portion DS is supported by the support substrate SK. As a result, the junction portion 8S (fragile portion) protruding downward on the back surface of the base semiconductor layer 8 is broken, and the element portion DS can be separated from the template substrate 7. Further, the insulating film DF and the second pad P2 may be joined to each other via a second junction A2 (not shown). In this case, the stability of the state in which the element portion DS is supported by the support substrate SK can be improved. The back surface of the base semiconductor layer 8 may be flattened by polishing or CMP (Chemical Mechanical Polish) or the like. Then, with the element portion DS supported by the support substrate SK, the second electrode E2 can be formed on the lower surface of the base semiconductor layer 8 of the element portion DS.

[0148] Next, (i) an insulating film D1 covering the side surfaces of the base semiconductor layer 8 and the compound semiconductor layer 9, and (ii) a conductive film MF are formed. The conductive film MF electrically connects the second electrode E2 and the second junction A2 or the second pad P2. The material of the conductive film MF is not particularly limited. The first pad P1 and the second pad P2 may be provided separately from each other. The conductive film MF may be in contact with at least one of the second electrode E2, the insulating film D1, and the second junction A2 and the second pad P2.

[0149] In Example 1, the second electrode E2 is located on the back surface of the base semiconductor portion 8, and the compound semiconductor portion 9 and the first electrode E1 are closer to the support substrate SK than the base semiconductor portion 8 (junction down type).

[0150] On the support substrate SK, a plurality of element portions DS are arranged in a direction (X direction) orthogonal to the direction defining the resonator length so that the directions of the resonator lengths are aligned, and the support substrate SK may be provided with first and second pads P1 and P2 corresponding to each of the plurality of element portions DS.

[0151] The support substrate SK can be formed, for example, as follows. That is, a plurality of recesses HL (rectangular in plan view) are provided in a matrix on a Si substrate, SiC substrate, AlN substrate, etc., and a plurality of first pads P1, a plurality of second pads P2, and a plurality of first joints A1 are provided in the non-recessed portions, whereby it can be formed. Note that a plurality of second joints A2 may be provided. The material constituting the main body of the support substrate SK is not particularly limited, and the support substrate SK may be formed of, for example, an insulator or a semi-insulator, or may be formed of a conductive material. Examples of the conductive material include metal materials containing Cu, Al, etc. When the support substrate SK is formed of a conductive material, an insulating layer can be disposed on the upper surface of the support substrate SK, and wirings can be disposed on the insulating layer.

[0152] The shape of the support substrate SK is not particularly limited either, and it may be, for example, a substantially quadrangular prism shape (substantially rectangular parallelepiped shape), a substantially pentagonal prism shape, a substantially hexagonal prism shape, etc., or other shapes. In Example 1, the shape of the support substrate SK is a substantially rectangular parallelepiped shape.

[0153] The first pad P1 and the second pad P2 may have, for example, a metal layer containing Au, Ti, Ni, etc. The first joint A1 and the second joint A2 may be composed of a single-layer metal layer or a multi-layer metal layer. When the first joint A1 and the second joint A2 are composed of a multi-layer metal layer, the outermost surface may be a metal layer made of Au. Thereby, corrosion of the first joint A1 and the second joint A2 can be suppressed. The first joint A1 is, for example, a solder material such as AuSi or AuSn. The first pad P1 and the first electrode E1 may be metal-metal joined without providing the first joint A1, and the second pad P2 and the second electrode E2 may be metal-metal joined without providing the second joint A2. In that case, for example, an Au-Au joint can be made.

[0154] The first pad P1 and the second pad P2 may be located on the same plane. In Example 1, the second joint A2 may not be provided. The first joint A1 may be, for example, a solder material, and the element portion DS may be held by the first joint A1 and placed on the support substrate SK.

[0155] (Step of forming a reflective film on the resonator surface) Next, a mirror film UF is formed on the emission surface F1 and the opposing surface F2 of the optical resonator LK in the element portion DS mounted on the support substrate SK. Thereby, the semiconductor laser element 20 can be manufactured. FIG. 24 is a cross-sectional view schematically showing the step of forming a reflective film on the resonator surface in the method for manufacturing a semiconductor laser element according to Example 1. FIG. 25 is a plan view showing the configuration of the compound semiconductor layer 9 after the mirror film UF is formed.

[0156] As shown in FIGS. 24 and 25, a mirror film UF (for example, a dielectric film) is formed on the first end surface including the end surface of the base semiconductor layer 8 and the end surface of the compound semiconductor layer 9. The first end surface includes the emission surface F1 of the optical resonator LK. Examples of the material of the mirror film UF include SiO 2 , Al 2 O 3 , AlN, AlON, Nb 2 O 5 , Ta 2 O 5 , ZrO 2 and other dielectrics. The mirror film UF may be a multilayer film. The mirror film UF can be formed by electron beam evaporation, electron cyclotron resonance sputtering, chemical vapor deposition, or the like.

[0157] The semiconductor laser element 20 can be configured such that at least one of the pair of resonator surfaces (emission surface F1 and opposing surface F2) has a light reflectivity of 98% or more and the resonator length L1 is 200 [μm] or less. The difference between the emission surface F1 and the opposing surface F2 may be the reflectivity. The resonator surface with the lower reflectivity can be set as the emission surface F1. The reflectivity can be controlled by the type, structure, film thickness, etc. of the mirror film UF.

[0158] A reflective film UF may be provided so as to cover the opposing surface F2. The light reflectance of each of the emission surface F1 and the opposing surface F2 may be 98% or more. The light reflectance of the opposing surface F2 on the light reflecting surface side is greater than the light reflectance of the emission surface F1. The reflective film UF can be formed over the entire cleavage plane (m-plane) of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0159] As described above, the element portion DS can be electrically connected to the support substrate SK and mechanically fixed thereto. Thereby, the element portion DS is disposed on the support substrate SK with its end face exposed. Therefore, it becomes possible to form a reflective film on the emission surface F1 and the opposing surface F2 of the optical resonator LK at the end face of the element portion DS in the next process. In other words, in the state where the element portion DS is disposed on the template substrate 7 (before separating the element portion DS from the template substrate 7), since the resonator surface is not exposed to the outside in the divided portion PS, it is difficult to form a reflective film on the emission surface F1 and the opposing surface F2 of the optical resonator LK.

[0160] Generally, in the manufacture of a semiconductor laser element, a dielectric layer can be formed (end face coating) so that the resonator surfaces of a plurality of elements have a desired reflectance.

[0161] On the other hand, by using the support substrate SK, it is possible to appropriately coat the resonator surface of the element portion DS after element separation. The support substrate SK has a role as a jig when coating the end face of the optical resonator LK and also has a function as a submount in the final device (semiconductor laser element 20). In Example 1, by performing a coating process on the element portion DS fixed to the support substrate SK, it becomes possible to increase the reflection efficiency at the opposing surface F2 and obtain a semiconductor laser element 20 having excellent luminous efficiency. Further, it becomes possible to suppress end face optical damage of the emission surface F1 and obtain a semiconductor laser element 20 having excellent reliability.

[0162] In addition, in the conventional CT method, for example, when forming the resonator surface of an optical resonator by cleavage, both the growth substrate and the structure formed on the growth substrate need to be cleaved. Therefore, there is a limit to the range in which the resonator length can be shortened. As far as the present inventors are aware, the resonator length of a semiconductor laser that has been put into practical use and is manufactured by a method of forming a resonator surface by cleavage is about 300 μm for the semiconductor laser with the shortest resonator length. In contrast, the semiconductor laser element 20 can have an ultra-short resonator such as 20 to 200 μm. Since at least one of the light reflectivities of the resonator surfaces (emission surface F1 and opposing surface F2) is high and the reflection loss is small, stable laser oscillation is possible even at a short resonator length of 200 μm or less where the optical gain is small. Due to the short resonator, power consumption can be reduced in low optical output applications such as wearable devices.

[0163] (Step of dividing the support substrate) Next, the support substrate SK may be divided into a plurality of supports ST. Thereby, a semiconductor laser chip 21 in which one or more semiconductor laser elements 20 are held by the support ST can be obtained. FIG. 26 is a cross-sectional view schematically showing the step of dividing the support substrate SK in the method for manufacturing a semiconductor laser element of Example 1.

[0164] As shown in FIG. 26, the support substrate SK is divided to form a plurality of semiconductor laser chips 21 each having a semiconductor laser element 20 disposed therein. The support ST can be used as a substrate (also referred to as a submount) of the semiconductor laser chip 21. The semiconductor laser chip 21 functions as a COS (Chip on Submount).

[0165] The support substrate SK may be divided into supports ST using a known cutting method such as dicing or scribing. Any portion of the support substrate SK may be cut while avoiding damage to the semiconductor laser element 20. The support ST may include one semiconductor laser element 20 or may include two or more semiconductor laser elements 20.

[0166] In the first embodiment as described above, since the base semiconductor layer 8 and the compound semiconductor layer 9 are spontaneously cleaved on the template substrate 7 to separate the elements into a plurality of semi-element portions sDS, there is no need to separately add a process for cleaving the base semiconductor layer 8 and the compound semiconductor layer 9. As a result, the manufacturing cost of the semiconductor laser element 20 can be reduced.

[0167] 〔Alternative Configuration Example 1〕 (1A) It is not limited to forming a plurality of base semiconductor layers 8 in an island shape by the ELO method. By making the growth time relatively long when forming the base semiconductor layer 8, adjacent base semiconductor layers 8 may be joined together. In this case, the upper surface of the base semiconductor layer 8 may be polished. The compound semiconductor layer 9 can be formed on the flat base semiconductor layer 8. By dry etching or the like the base semiconductor layer 8 and the compound semiconductor layer 9, a compound semiconductor layer 9 having a starting point portion 9T may be formed. A base semiconductor layer 8 having a starting point portion 8K may also be formed. Thereby, a semiconductor substrate 10 capable of separating elements on the template substrate 7 can be obtained. For example, a semiconductor substrate 10 having a base semiconductor layer 8 and a compound semiconductor layer 9 in the form shown in FIG. 16 may be used.

[0168] (1B) After growing the base semiconductor layer 8 on the template substrate 7 in the MOCVD apparatus, before forming the compound semiconductor layer 9, the semiconductor substrate 10 may be temporarily taken out from the MOCVD apparatus. In this case, by taking out the semiconductor substrate 10 from the MOCVD apparatus, cleavage may occur in the base semiconductor layer 8. Thereafter, the semiconductor substrate 10 having the cleaved base semiconductor layer 8 may be loaded into the MOCVD apparatus, and a compound semiconductor layer 9 having a starting point portion 9T may be formed. In this case, the emission surface F1 and the opposing surface F2 are included in the end face of the epitaxially grown compound semiconductor layer 9. By epitaxially growing the compound semiconductor layer 9 on the base semiconductor layer 8 having a high-quality cleavage surface, the end face of the compound semiconductor layer 9 can be made of high quality. Therefore, the end face of the epitaxially grown compound semiconductor layer 9 can be used as the resonator surface.

[0169] (1C) In the first embodiment, the mask portion 5 was removed after forming the element portion DS on the template substrate 7. However, in another configuration example, the mask portion 5 may be removed before the step of forming the element portion DS. For example, after forming the semi-element portion sDS by element isolation on the template substrate 7, the mask portion 5 may be removed before forming the element portion DS. In this case, there is an advantage that it is not necessary to protect the insulating film DF so that the insulating film DF is not removed when removing the mask portion 5.

[0170] (1D) In another configuration example, after forming the second electrode E2 and the mirror film UF in a state where the element portion DS is supported using a temporary substrate, the semiconductor laser element 20 may be mounted on the support substrate SK. Further, both the temporary substrate DK and the support substrate SK may be divided in a state where the semiconductor laser element 20 is sandwiched between the temporary substrate and the support substrate SK. In this case, the individual pieces of the divided temporary substrate DK may be removed.

[0171] Alternatively, a first support substrate having wirings may be used instead of the temporary substrate DK. In this case, both the first support substrate and the support substrate SK (second support substrate) may be cut in a state where the semiconductor laser element 20 is sandwiched between the first support substrate and the support substrate SK. Thereby, a semiconductor laser chip 21 including the individual piece of the first support substrate and the support ST may be obtained.

[0172] (1E) FIG. 27 is a plan view for explaining another example of the base semiconductor layer 8 in Example 1. As shown in FIG. 27, the base semiconductor layer 8 in one example may have a starting point portion 8K in which a notch is formed up to a position close to the starting point inducing portion 5Y in a plan view. The tip at the starting point portion 8K is referred to as a tip portion 8P. For example, the starting point portion 8K may be at a position where the tip portion 8P overlaps the starting point inducing portion 5Y in a plan view. Further, the starting point portion 8K may have a virtual triangular shape in a plan view. A virtual line segment corresponding to the base of the virtual triangle with the tip portion 8P as the vertex is referred to as a side 8C. The distance from the side 8C to the tip portion 8P is referred to as a notch length H2 of the starting point portion 8K. The notch length H2 may be WM / 4 or more and may be WM / 3 or more using the width WM (see FIG. 4) of the mask portion 5. Further, the notch length H2 may be WM / 2 or less.

[0173] By forming the compound semiconductor layer 9 on the base semiconductor layer 8, the compound semiconductor layer 9 is formed in a shape having a starting point portion (not shown) corresponding to the starting point portion 8K. The starting point portion formed in the compound semiconductor layer 9 may have an end face that is the m-plane of the GaN-based semiconductor by being formed in a shape corresponding to the starting point portion 8K. The starting point portion formed in the compound semiconductor layer 9 may not have an end face that is the m-plane of the GaN-based semiconductor.

[0174] FIG. 28 is an exploded perspective view for explaining the configuration of the semiconductor element portion sDS formed by element separation of the base semiconductor layer 8 and the compound semiconductor layer 9. In FIG. 28, for convenience of explanation, the template substrate 7 and the base semiconductor layer 8 are shown virtually separated, but actually, the base semiconductor layer 8 and the mask portion 5 are in contact with each other. Further, the base semiconductor layer 8 has a joint portion 8S corresponding to the initial growth layer SL on the lower surface, and the joint portion 8S and the seed layer 3 are joined to each other. Further, in FIG. 28, only a part of the template substrate 7 is shown, not the whole.

[0175] As shown in FIG. 28, in the base semiconductor layer 8 of an example of the half-element section sDS, the first base end face 8X may not have the third partial face 8X3. The angle (inner angle) formed by the second base end face 8Y and the third base end face 8Z is referred to as θ4. θ4 may be an obtuse angle, for example, it may be 120° or approximately 120°, for example, it may be about 110° to 130°. Alternatively, θ4 may exceed 130°. The second base end face 8Y may be the m-plane of the GaN-based semiconductor.

[0176] (1F) In another configuration example of Example 1, in the element section DS, a part of the compound semiconductor layer 9 may be removed by etching or the like, or the compound semiconductor layer 9 may be partially formed on the base semiconductor layer 8. In this case, the first electrode E1 may be connected to the first pad P1 via the first junction A1, and the second electrode E2 may be connected to the second pad P2 via the conductive film MF and the second junction A2. In this example, it is not necessary to form the insulating film D1 that covers the side surfaces of the base semiconductor layer 8 and the compound semiconductor layer 9, and the element section DS can be mounted on the support substrate SK.

[0177] 〔Example 2〕 In Example 1, the semiconductor laser element 20 had a double-sided electrode structure, but in Example 2, the semiconductor laser element 20 may have a single-sided two-electrode structure. FIG. 29 is a cross-sectional view showing the configuration of the semiconductor laser element 20 in Example 2.

[0178] As shown in FIG. 29, the semiconductor laser element 20 in Example 2 may include an element section DS including a base semiconductor layer 8 and a compound semiconductor layer 9, and a support substrate SK that holds the element section DS. Examples of the material of the support substrate SK include Si, SiC, and AlN. The support substrate SK is arranged such that the compound semiconductor layer 9, the first electrode E1, and the second electrode E2 are located between the support substrate SK and the base semiconductor layer 8.

[0179] The first electrode E1 overlaps with an optical resonator LK (not shown) in a plan view and also overlaps with the second part B2 of the base semiconductor layer 8. The second electrode E2 is provided on the same side of the base semiconductor layer 8 as the first electrode E1. The second electrode E2 is in contact with the base semiconductor layer 8, and in a plan view, the first electrode E1 and the second electrode E2 do not overlap with each other. Specifically, the base semiconductor layer 8 has a larger width in the X direction than the compound semiconductor layer 9, and the second electrode E2 is formed on an exposed portion where the compound semiconductor layer 9 is not formed. The exposed portion may be formed by removing a part of the compound semiconductor layer 9 by reactive ion etching (RIE) or the like, or may be formed by partially depositing the compound semiconductor layer 9 on the base semiconductor layer 8. Although not shown, the compound semiconductor layer 9 may have an optical resonator LK, and a pair of resonator surfaces of the optical resonator LK may be covered by a mirror film UF.

[0180] The support substrate SK includes a conductive first pad P1 and a second pad P2. The first electrode E1 is connected to the first pad P1 via a first joint A1, and the second electrode E2 is connected to the second pad P2 via a second joint A2. In Example 2, the second joint A2 has a greater thickness than the first joint A1, and the difference in thickness between the first joint A1 and the second joint A2 is equal to or greater than the thickness of the compound semiconductor layer 9. Thereby, the connection between the first and second electrodes E1 and E2 and the first and second pads P1 and P2 located in the same plane becomes possible.

[0181] The support substrate SK may be a divided support ST. In this case, the semiconductor laser element 20 may be a semiconductor laser chip 21. The support ST can be used as a substrate (also referred to as a submount) of the semiconductor laser chip 21. The semiconductor laser chip 21 functions as a COS (Chip on Submount).

[0182] FIG. 30 is a schematic cross-sectional view showing an example of a method for manufacturing the semiconductor laser element 20 in Example 2. As shown in FIG. 30, in Example 2, a step of preparing a template substrate 7 including a lower base substrate UK and a mask layer 6, and a step of forming a first semiconductor layer S1 (and a third semiconductor layer S3) that becomes the base semiconductor layer 8 by the ELO method (described later), and a step of forming a second semiconductor layer S2 (and a fourth semiconductor layer S4) that becomes the compound semiconductor layer 9 are included. A mask layer 6 having a starting point inducing portion 5Y may be formed in the mask portion 5. In this case, the first semiconductor layer S1 (and the third semiconductor layer S3) has a starting point portion 8K. Further, when the second semiconductor layer S2 is formed at a position including the starting point portion 8K on the first semiconductor layer S1, it can be formed so as to have a starting point portion 9T.

[0183] The starting point portion 8K may be formed in the third portion B3, and the second semiconductor layer S2 may be provided above the second portion B2. In this case, an optical resonator LK is provided at a position overlapping the second portion B2 in plan view. The second semiconductor layer S2 does not necessarily have a starting point portion 9T, and a starting point for cleavage may be formed by scribing as described later (Example 3, etc.).

[0184] Next, the semi-element portion sDS is formed by element isolation on the template substrate 7. Thereafter, a ridge portion RJ is formed in the first semiconductor layer S1, and a first electrode E1, a second electrode E2, etc. are formed. Thereby, an element portion DS having a one-sided two-electrode structure is formed on the template substrate 7.

[0185] Then, a step of bonding the element portion DS to the support substrate SK and separating the first semiconductor layer S1 from the template substrate 7 is performed. For example, after forming the element portion DS, the mask portion 5 is etched away, and the element portion DS is bonded to the support substrate SK in a state where the first and second bonding portions A1 and A2 (e.g., solder) of the support substrate SK are heated and melted. Then, either one or both of the support substrate SK and the base substrate UK are displaced so that the support substrate SK and the base substrate UK move away from each other. As a result, the joint portion (lower protruding portion) of the back surface of the first semiconductor layer S1 with the base substrate UK breaks, and the first semiconductor layer S1 is separated from the template substrate 7. As a result, a two-dimensional arrangement type semiconductor laser substrate (see FIG. 22) is formed.

[0186] Then, the two-dimensional arrangement type semiconductor laser substrate may be divided for each row to form a one-dimensional arrangement type (bar-shaped) semiconductor laser substrate, and then, a reflective mirror film UF is formed on each of the emission surface F1 and the opposing surface F2. Next, a step of dividing the support substrate SK into a plurality of supports ST may be performed. By holding one or more semiconductor laser elements 20 in each support ST, a plurality of semiconductor laser chips 21 can be formed.

[0187] 〔Example 3〕 In Example 3, a template substrate 7 having no starting point inducing portion 5Y in the mask portion 5 may be used. In Example 3, a semiconductor laser element 20 having a one-sided two-electrode structure is manufactured. FIG. 31 is a flowchart showing an example of a method for manufacturing a semiconductor laser element in Example 3.

[0188] As shown in FIG. 31, in Example 3, first, a template substrate 7 (see FIG. 4) having no starting point inducing portion in the mask layer 6 is prepared, and then, a base semiconductor layer 8 and a compound semiconductor layer 9 are formed on the template substrate 7.

[0189] In Example 3, for example, the template substrate 7 may be prepared as follows. First, a silicon oxide film with a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed over the entire surface of the underlayer 4 using sputtering, CVD, evaporation, or the like. Then, a resist is applied over the entire surface of the silicon oxide film. Thereafter, the resist is patterned using photolithography to form a resist having a plurality of stripe-shaped openings. Then, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings KS and mask portions 5. Next, the mask layer 6 is formed by removing the resist by organic cleaning. Thus, a template substrate 7 as shown in FIG. 4 can be obtained.

[0190] Next, the template substrate 7 is loaded into a MOCVD apparatus, and a GaN-based semiconductor layer is formed by the ELO method. In Example 3, the base semiconductor layer 8 was an n-type GaN layer, and using a MOCVD apparatus, ELO film formation of Si-doped GaN was performed on the template substrate 7. As an example of the ELO film formation conditions, the substrate temperature: 1120 °C, the growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH 3 : 15 slm, V / III = 6000 (the ratio of the supply amount of group V raw material to the supply amount of group III raw material) can be adopted. The initial growth layer SL selectively grows on the seed layer 3 (the GaN layer which is the uppermost layer of the seed layer 3) exposed in the opening KS, and subsequently grows laterally on the mask portion 5. Then, these lateral growths were stopped before the base semiconductor layers 8 growing laterally from both sides thereof meet on the mask portion 5.

[0191] Note that the film formation time may be further extended to cause adjacent base semiconductor layers 8 to meet. When they are made to meet, after forming the compound semiconductor layer 9 on the base semiconductor layer 8, the meeting portion of the base semiconductor layer 8 may be removed by dry etching or the like.

[0192] FIG. 32 is a plan view showing the configuration of the semiconductor substrate 10 on which the base semiconductor layer 8 in Example 3 is formed. As shown in FIG. 32, in Example 3, the base semiconductor layer 8 does not have a starting point 8K.

[0193] Next, a step of forming the compound semiconductor layer 9, a step of forming the element structure, and a step of forming a starting point for cleavage are performed. FIG. 33 is a plan view showing the configuration of the semiconductor substrate 10 on which the element structure in Example 3 is formed. FIG. 34 is a cross-sectional view showing the configuration of the semiconductor substrate 10 in FIG. 33. In FIG. 34, the template substrate 7 is omitted from the illustration.

[0194] The compound semiconductor layer 9 may be formed on the entire surface of the base semiconductor layer 8. In this case, a part of the base semiconductor layer 8 may be exposed by reactive ion etching. Alternatively, the compound semiconductor layer 9 may be partially formed on the upper surface of the base semiconductor layer 8. The second electrode E2 may be formed on the exposed portion of the base semiconductor layer 8. Then, a ridge portion RJ is formed in the compound semiconductor layer 9, and the insulating film DF and the first electrode E1 are formed. Thereby, the semiconductor substrate 10 having the template substrate 7 and the element structure 22 formed on the template substrate 7 can be obtained.

[0195] Next, a starting point for cleavage is formed in the element structure 22. The starting point for cleavage may be formed in the base semiconductor layer 8 or in the compound semiconductor layer 9. The method of forming the starting point for cleavage is not particularly limited. For example, the starting point for cleavage may be formed by diamond scribing. In this case, since the starting point can be made into a thin shape, the starting point for cleavage is likely to concentrate at one location. Therefore, a smooth cleavage surface can be easily obtained. Note that since the insulating film DF formed on the compound semiconductor layer 9 is thin, the presence of the insulating film DF can be ignored and the starting point for cleavage can be formed in the compound semiconductor layer 9. It is not necessary to form the insulating film DF in the portion of the compound semiconductor layer 9 where the starting point for cleavage is formed. That is, the compound semiconductor layer 9 may be exposed in the portion of the insulating film DF where the starting point for cleavage is formed.

[0196] Alternatively, for example, a starting portion for cleavage may be formed by laser scribing. In this case, the variation in the length of the scribing can be reduced, improving the yield. The length of the laser scribing is the scanning distance of the laser. Also, the starting portion for cleavage may be formed by dry etching or wet etching. In this case, since the cleavage proceeds without deviating from the cleavage plane, it is easy to obtain a smooth cleavage plane.

[0197] The starting portion for cleavage may be formed by combining the above-described methods. In that case, the advantages of each method can be enjoyed simultaneously. The starting portion formed by diamond scribing or laser scribing may be further wet-etched. In this case, the shape of the starting portion for cleavage can be shaped. Also, the starting portion formed by dry etching may be further wet-etched. In this case, the shape of the starting portion for cleavage can be shaped.

[0198] Next, the element structure 22 having the starting portion for cleavage formed thereon is cleaved. For example, cleavage may be generated at the starting portion for cleavage by applying a blade to the starting portion for cleavage and applying a force in a direction perpendicular to the plane direction. In this case, since a strong force can be applied to the starting portion for cleavage, the yield is improved. Also, cleavage may be generated at the starting portion for cleavage by applying vibration to the starting portion for cleavage. In this case, since the process can be performed relatively easily, the manufacturing process can be simplified.

[0199] Also, by raising or lowering the temperature of the semiconductor substrate 10 from room temperature, a thermal stress may be applied to the starting portion to generate cleavage by utilizing the difference in the thermal expansion coefficients between the main substrate 1 and the base semiconductor layer 8. When the difference in the thermal expansion coefficients is utilized, the variation in the in-plane direction of the applied force disappears, improving the yield.

[0200] Alternatively, by bending the template substrate 7 obtained by thinning the main substrate 1 through polishing or the like, stress may be applied to the element structure 22 on the template substrate 7 to perform cleavage. In this case, the element structure 22 can be separated into elements, and a plurality of element portions DS can be formed at once. Therefore, the manufacturing cost can be reduced.

[0201] The element structure 22 may be cleaved by combining the above-described cleavage methods. In that case, the advantages of each method can be enjoyed simultaneously.

[0202] In Example 3, the timing for removing the mask portion 5 to separate the element portion DS from the template substrate 7 is desirably set after the formation of the starting portion for cleavage or after cleavage. Thereby, the formation of the starting portion or cleavage can be stably performed, and the yield is improved.

[0203] In Example 3, internal stress may be generated in the base semiconductor layer 8 due to a difference in thermal expansion coefficient between the template substrate 7 and the base semiconductor layer 8. Also, internal stress may be generated in the base semiconductor layer 8 due to a difference in lattice constant between the template substrate 7 and the base semiconductor layer 8. The occurrence of internal stress in the base semiconductor layer 8 can make cleavage more likely to occur.

[0204] For example, internal stress is generated in the base semiconductor layer 8 and the compound semiconductor layer 9 due to the difference in thermal expansion coefficient between the base semiconductor layer 8 and the compound semiconductor layer 9, and the main substrate 1. For example, when the base semiconductor layer 8 is formed by the ELO method on a heterogeneous substrate such as an Si substrate, the film formation temperature can be as high as 1000°C or more. Therefore, when the temperature is lowered to room temperature, stress is generated in the base semiconductor layer 8. Also, strain occurs in the base semiconductor layer 8 due to the difference in lattice constant between the main substrate 1 and the base semiconductor layer 8.

[0205] Here, if the coefficient of thermal expansion of the main substrate 1 is larger than that of the base semiconductor layer 8, compressive stress is generated in the base semiconductor layer 8, and if the coefficient of thermal expansion of the main substrate 1 is smaller than that of the base semiconductor layer 8, tensile stress is generated in the base semiconductor layer 8. When tensile stress is generated in the base semiconductor layer 8, cleavage may occur by scribing the compound semiconductor layer 9. When cleaving the base semiconductor layer 8 in which tensile stress is generated, the possibility that the individual pieces of the divided base semiconductor layer 8 come into contact with each other can be reduced. Therefore, the possibility that the end faces of the divided base semiconductor layer 8 are damaged can be reduced. Further, if cleavage occurs so that the element structure 22 is torn from the starting point due to the application of tensile stress, the cleavage surface is likely to become smooth.

[0206] For example, by scribing the base semiconductor layer 8, the internal stress of the base semiconductor layer 8 may be released, and the cleavage of the element structure 22 may proceed naturally. Further, by scribing the compound semiconductor layer 9, the internal stress of the base semiconductor layer 8 may be released, and the cleavage of the element structure 22 may proceed naturally. The fact that cleavage proceeds naturally by scribing means that scribing and cleavage occur at the same or substantially the same timing (spontaneously cleaving with scribing). Thereby, the latter of the process of forming the starting point portion (scribing process) and the process of cleaving the starting point portion (break process) can be omitted. Therefore, the manufacturing cost of the semiconductor laser element 20 can be reduced.

[0207] Next, the element portion DS is separated from the template substrate 7. Since the subsequent steps are the same as those in the first and second embodiments, the description thereof is omitted.

[0208] As described above, in the third embodiment, after forming the element structure, the starting point portion of cleavage can be formed at an arbitrary position. Therefore, the position where the starting point portion of cleavage is formed can be controlled. As a result, the position where cleavage occurs can be controlled, and the resonator length L1 can be adjusted. Therefore, it is easy to improve the yield.

[0209] 〔Another configuration example 3〕 In Example 3 above, after the step of forming the element structure, the step of forming the starting portion and the step of separating the elements on the template substrate 7 were performed, but the order is not limited to this. After the step of forming the starting portion is performed, the step of forming the element structure may be performed, and then the step of separating the elements on the template substrate 7 may be performed.

[0210] 〔Example 4〕 In Example 4, element separation may be performed by etching instead of cleavage. FIG. 35 is a plan view showing an example of element separation in Example 4.

[0211] As shown in FIG. 35, after the base semiconductor layer 8 and the compound semiconductor layer 9 are formed on the template substrate 7, a plurality of trenches TR (separation grooves) are formed in the semiconductor substrate 10 by performing etching. Thereby, element separation may be performed on the plurality of semi-element portions sDS having the optical resonator LK on the template substrate 7. The trench TR penetrates the compound semiconductor layer 9 and the base semiconductor layer 8. The mask portion 5 and the seed layer 3 or the main substrate 1 may be exposed in the trench TR.

[0212] Note that a taper angle may occur at the end face of the compound semiconductor layer 9 due to etching (the end face is deviated from the vertical). Therefore, for example, element separation may be performed as follows. That is, first, the semiconductor substrate 10 is set in a slightly inclined state in the apparatus for performing the etching process. Next, the trench TR corresponding to one side in the Y direction of the semi-element portion sDS to be formed by the subsequent etching process is formed by etching. As a result, one of the pair of resonator surfaces of the semi-element portion sDS (for example, the emission surface F1) is formed. As a result, for example, the emission surface F1 can be formed perpendicular or substantially perpendicular. Next, in the apparatus for performing the etching process, the semiconductor substrate 10 is set in a slightly inclined state on the opposite side (the side opposite to when the trench TR is formed). Then, the trench TR corresponding to one side in the Y direction of the semi-element portion sDS is formed by etching. As a result, the other of the pair of resonator surfaces of the semi-element portion sDS (for example, the opposing surface F2) is formed. As a result, for example, the opposing surface F2 can be formed perpendicular or substantially perpendicular.

[0213] 〔Example 5〕 FIG. 36 is a schematic diagram showing the configuration of the electronic device according to Example 5. The electronic device 50 in FIG. 36 includes a semiconductor laser device ZD (semiconductor laser element 20 or semiconductor laser chip 21) and a control unit 80 that includes a processor and controls the semiconductor laser device ZD. Examples of the electronic device 50 include a lighting device, a display device, a communication device, an information processing device, a medical device, an electric vehicle (EV), and the like.

[0214] 〔Example 6〕 In Example 1, the compound semiconductor part 9 is provided on the c-plane of the base semiconductor part 8, and the pair of resonator planes are the m-planes of the nitride semiconductor, but it is not limited thereto. For example, the compound semiconductor part 9 can be provided on the m-plane ((1-100) plane) of the base semiconductor part 8, and the pair of resonator planes can be the c-plane ((0001) plane) of the nitride semiconductor. The resonator length L1 is the length in the c-axis direction. The emission surface F1 and the opposing surface F2 can be formed, for example, by cleavage of the c-plane of the nitride semiconductor.

[0215] 〔Supplementary Notes〕 As described above, the invention according to the present disclosure has been described based on the various drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments. That is, the invention according to the present disclosure can be variously modified within the scope shown in the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that those skilled in the art can easily make various deformations or modifications based on the present disclosure. Also, note that these deformations or modifications are included in the scope of the present disclosure.

Explanation of Reference Numerals

[0216] 1 Main substrate 5 Mask part 5Y Starting point inducing part 6 Mask layer (mask) 7 Template substrate 8 Base semiconductor layer (base semiconductor section) 8K, 9T starting point (starting point) 9 Compound semiconductor layer (compound semiconductor section) 20 Semiconductor laser element (semiconductor device) 21 Semiconductor laser chip 70 Manufacturing apparatus B1 First section B2 Second section B3 Third section DS Element section E1 First electrode E2 Second electrode F1 Emission surface (resonator surface) F2 Opposing surface (resonator surface) LK Optical resonator RJ Ridge section sDS Half-element section (element section) SK Support substrate

Claims

1. A main board; a mask pattern formed above the main substrate and having a mask portion and an opening whose longitudinal direction is the first direction and whose lateral direction is the second direction; a base semiconductor portion including a nitride semiconductor, the base semiconductor portion having a first portion located above the opening and a second portion extending from the first portion to above the mask portion, The base semiconductor portion has a recess recessed from an end of the second portion toward the first portion in a plan view of the semiconductor substrate.

2. The semiconductor substrate according to claim 1 , wherein the recess is formed across the thickness of the second portion.

3. The semiconductor substrate according to claim 1 , wherein the base semiconductor portion has a plurality of recesses aligned in the first direction, including the recess.

4. The semiconductor substrate according to claim 1 , wherein an outer periphery of the recess includes an m-plane of the nitride semiconductor.

5. The semiconductor substrate according to claim 1 , comprising a plurality of base semiconductor portions aligned in the second direction, including the base semiconductor portion.

6. The semiconductor substrate according to claim 1 , wherein the recess includes a portion that tapers in a direction toward the first portion.

7. The semiconductor substrate according to claim 1 , wherein the main substrate is a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor.

8. 8. The semiconductor substrate according to claim 1, wherein the base semiconductor portion has a third portion extending from the first portion to a side opposite to the second portion.

9. 8. The semiconductor wafer according to claim 1, wherein the threading dislocation density of the second portion is equal to or less than 1 / 5 of the threading dislocation density of the first portion.

10. 8. The semiconductor substrate according to claim 1, wherein the first direction is an a-axis direction of the nitride semiconductor, and the second direction is an m-axis direction of the nitride semiconductor.

11. 8. The semiconductor substrate according to claim 1, wherein the depth direction of the recess is the a-axis direction of the nitride semiconductor.

12. a step of preparing a semiconductor substrate comprising: a main substrate; a mask pattern formed above the main substrate, the mask pattern having a mask portion and an opening with a first direction as a longitudinal direction and a second direction as a lateral direction; and a base semiconductor portion including a nitride semiconductor, the base semiconductor portion having a first portion located above the opening and a second portion extending from the first portion above the mask portion, the base semiconductor portion having a recess recessed from an end of the second portion toward the first portion in a plan view; and forming a compound semiconductor portion above the semiconductor substrate.

13. The method for manufacturing a semiconductor device according to claim 12 , further comprising the step of dividing a stack including the base semiconductor portion and the compound semiconductor portion into a plurality of stacks.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, further comprising the step of cleaving the base semiconductor portion and the compound semiconductor portion.

15. The method for manufacturing a semiconductor device according to claim 12 or 13, further comprising the step of isolating the first portion and the compound semiconductor portion from the main substrate.

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