Bonded semiconductor substrate and method for manufacturing bonded semiconductor substrate

Abstract

To provide a bonded semiconductor substrate and a method for manufacturing a bonded semiconductor substrate, capable of sufficiently ensuring the bonding strength between a first semiconductor substrate and a second semiconductor substrate and also capable of preventing occurrence of a bonding failure caused by a pit on a bonding target surface.SOLUTION: There is provided a method for manufacturing a bonded semiconductor substrate that includes a first semiconductor substrate and a second semiconductor substrate that comes into contact with the first semiconductor substrate. The method includes: an amorphous layer stacking step of stacking an amorphous layer, which has the same composition as the first semiconductor substrate, on at least one of a surface of a first bonding target surface, which is a surface of the first semiconductor substrate bonded to the second semiconductor substrate, and a surface of a second bonding target surface, which is a surface of the second semiconductor substrate bonded to the first semiconductor substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface after the amorphous layer stacking step and forming a bonded substrate including a bonding interface; and a heat-treatment step of heat-treating the bonded substrate. The amorphous layer stacking step and the bonding step are carried out in one apparatus.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate.

Background Art

[0002] Silicon carbide (hereinafter sometimes referred to as "SiC") is cited as a substrate material for power devices. However, the manufacturing cost of a single-crystalline SiC substrate itself is high, which has been an obstacle to practical use of the single-crystalline SiC substrate alone. In contrast, a bonded semiconductor substrate has been developed in which a high-quality single-crystalline SiC substrate is used only for the portion of the layer where the device is formed, and a support substrate such as a low-cost polycrystalline SiC substrate reinforces the single-crystalline SiC substrate for the other portions. For example, a technique related to a bonded semiconductor substrate is disclosed in Patent Document 1.

[0003] In a bonded semiconductor substrate, when a polycrystalline SiC substrate is used as a support substrate, since various plane orientations are exposed on the surface of the polycrystalline SiC substrate, when attempting to planarize the surface by the CMP method, the etching rate changes according to the plane orientation, and thus it is greatly affected by crystal grains, resulting in a decrease in the surface flatness. When the surface of the polycrystalline SiC substrate in this state is bonded to the highly flat surface of the single-crystalline SiC substrate, gaps are generated at the bonding interface, resulting in bonding failure.

[0004] Therefore, in Patent Document 1, even for a polycrystalline SiC substrate that is difficult to planarize to the same extent as the surface of the single-crystalline SiC substrate, the surfaces of the single-crystalline SiC substrate and the polycrystalline SiC substrate are irradiated with a neutral atom beam of argon using an FAB gun (Fast Atom Beam Gun) so as to have a bonding surface with high bonding strength. By this irradiation, the surfaces of the single-crystalline SiC substrate and the polycrystalline SiC substrate are amorphized, and after bonding the single-crystalline SiC substrate and the polycrystalline SiC substrate, heat treatment is performed to crystallize the amorphized layer to obtain a bonded semiconductor substrate.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent No. 6061251 [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2009-117533 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] In the method of Patent Document 1, by directly bonding a single-crystalline SiC substrate and a polycrystalline SiC substrate, the bonding strength at the bonding interface is improved, and the defective bonding portion can be reduced.

[0007] However, in Patent Document 1, before bonding with the single-crystalline SiC substrate, the surface of the polycrystalline SiC substrate used as a support substrate is polished to suppress its surface roughness. Nevertheless, there are still a plurality of pits on the polished surface of the polycrystalline SiC substrate, and due to this, defective bonding portions may occur at the bonding interface after bonding.

[0008] Therefore, in order to solve the above problems, the present invention provides a bonded semiconductor substrate obtained by bonding a first semiconductor substrate and a second semiconductor substrate, which can sufficiently ensure the bonding strength between the first semiconductor substrate and the second semiconductor substrate, and suppress the occurrence of defective bonding caused by pits on the surface of the bonding target surface, and a method for manufacturing the bonded semiconductor substrate. [Means for Solving the Problems]

[0009] In order to solve the above problems, a method for manufacturing a bonded semiconductor substrate according to the present invention is a method for manufacturing a bonded semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, wherein at least one of a first bonding target surface which is a surface of the first semiconductor substrate for bonding with the second semiconductor substrate, or a second bonding target surface which is a surface of the second semiconductor substrate for bonding with the first semiconductor substrate, an amorphous layer forming step of laminating an amorphous layer composed of the same composition as the first semiconductor substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface after the amorphous layer forming step to form a bonded substrate having a bonding interface; and a heat treatment step of heat treating the bonded substrate, and the amorphous layer forming step and the bonding step are performed in the same apparatus.

[0010] The first semiconductor substrate and the second semiconductor substrate are any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), and diamond, the first semiconductor substrate may be polycrystalline, and the second semiconductor substrate may be single crystal.

[0011] The amorphous layer forming step may be a step of laminating the amorphous layer by sputtering film formation by a sputtering method on at least one of the first bonding target surface or the second bonding target surface.

[0012] The method for manufacturing a bonded semiconductor substrate may include an oxide removing step of removing at least one of an oxide on the first bonding target surface or an oxide on the second bonding target surface before the amorphous layer forming step.

[0013] The oxide removing step may be a step of removing at least one of an oxide on the first bonding target surface or an oxide on the second bonding target surface by using at least one of the first bonding target surface or the second bonding target surface as a target and by a sputtering method.

[0014] The heat treatment step may be a step of maintaining the temperature of the bonding substrate at 1500°C to 2200°C.

[0015] Before the amorphous layer lamination step, an ion implantation step of implanting hydrogen ions or helium ions into the second bonding target surface to form an ion implantation layer inside the second semiconductor substrate may be provided.

[0016] After the bonding step and before the heat treatment step, a peeling step may be provided. The peeling step may be a step of peeling a part of the second semiconductor substrate using a microbubble layer formed by heating the ion implantation layer as a peeling surface.

[0017] The amorphous layer lamination step may be a step of laminating an amorphous layer having a thickness of 10 nm to 30 nm.

[0018] Also, in order to solve the above problems, a bonded semiconductor substrate of the present invention includes a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, and the bonded semiconductor substrate has a disk shape with a diameter of 100 to 210 mm, and the number of bonding defective portions at the bonding interface is 0.05 pcs / cm 2 or less.

Advantages of the Invention

[0019] According to the present invention, in a bonded semiconductor substrate obtained by bonding a first semiconductor substrate and a second semiconductor substrate, it is possible to sufficiently secure the bonding strength between the first semiconductor substrate and the second semiconductor substrate, and to provide a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate capable of suppressing the occurrence of bonding defects caused by pits on the surface of the bonding target surface.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

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Figure 7

Embodiments for Carrying Out the Invention

[0021] In this specification, a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate are disclosed. The bonded semiconductor substrate is obtained by laminating an amorphous layer on at least one of the surfaces of the first semiconductor substrate and the second semiconductor substrate, then bonding these semiconductor substrates together to form a bonded substrate having a bonding interface, and then recrystallizing the amorphous layer by subsequent heat treatment.

[0022] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

[0023] [Bonded Semiconductor Substrate] The bonded semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded via a bonding interface.

[0024] [Configuration of Bonded Semiconductor Substrate] Figure 2 is a perspective view showing an example of the bonded semiconductor substrate of the present invention. The bonded semiconductor substrate 10 of the present invention is formed, for example, in a disk shape having an orientation flat. The bonded semiconductor substrate 10 includes a support substrate 11 which is an example of a first semiconductor substrate, and a single crystal substrate 13 which is an example of a second semiconductor substrate. The single crystal substrate 13 is bonded to the support substrate 11 and has a bonding interface 14.

[0025] The single crystal substrate 13 may be, for example, a compound semiconductor (e.g., silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 )), a single element semiconductor (e.g., silicon (Si), carbon (C)), or diamond. These elements are semiconductor materials that can be used in semiconductor device fabrication. Note that the above carbon (C) is other than diamond, and is, for example, graphite or the like.

[0026] Various materials can be used for the support substrate 11. The support substrate 11 preferably has resistance to various heat processes applied to the single crystal substrate 13. For example, the support substrate 11 can be made of any of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), diamond, sapphire (Al 2 O 3 ), and quartz (SiO 2 ), etc. Note that the above carbon (C) is other than diamond, and is, for example, graphite or the like.

[0027] Also, the support substrate 11 is preferably made of a material with a small difference in thermal expansion coefficient from the single-crystalline substrate 13. For this reason, the support substrate 11 is preferably a polycrystalline substrate made of the same material as the single-crystalline substrate 13. For example, even if the single-crystalline substrate 13, which is an example of the second semiconductor substrate, is a single-crystalline silicon carbide substrate (single-crystalline SiC substrate), and the support substrate 11, which is an example of the first semiconductor substrate, is a polycrystalline silicon carbide substrate (polycrystalline SiC substrate).

[0028] As the single-crystalline SiC substrate, for example, a 4H-SiC single-crystalline substrate produced by the sublimation method can be used. The shape of the single-crystalline SiC substrate is, for example, a substantially disk shape with an orientation flat, and a substrate with a diameter of 4 to 8 inches (100 to 210 mm) can be used.

[0029] Also, as the polycrystalline SiC substrate, various polytypes and SiC crystals with different plane orientations may be mixed. Since a polycrystalline SiC substrate with various polytypes and plane orientations mixed can be manufactured without strict temperature control, it is possible to reduce the cost of manufacturing the support substrate 11. For example, a 3C-SiC polycrystalline substrate obtained by depositing a SiC polycrystal by chemical vapor deposition can be used. Also, the shape of the polycrystalline SiC substrate may be substantially the same as that of the single-crystalline SiC substrate, for example, a substantially disk shape with an orientation flat, and a substrate with a diameter of 4 to 8 inches (100 to 210 mm) can be used.

[0030] The thickness TT1 of the support substrate 11 may be determined so as to obtain a mechanical strength that can withstand the formation of the epitaxial layer and subsequent processing such as forming semiconductor elements and semiconductor devices thereon. For example, when the diameter of the support substrate 11 is 6 inches (about 150 mm), the thickness TT1 may be about 350 (μm), and a substrate with a thickness TT1 of 300 to 500 μm can be used.

[0031] The bonded semiconductor substrate is disk-shaped with a diameter of 4 to 8 inches (100 to 210 mm), and the number of defective bonding portions at the bonding interface is 0.05 pcs / cm2 It is as follows. For example, the number of defective bonding parts in the case of a bonded semiconductor substrate with a diameter of 4 inches is 4 pcs or less, the number of defective bonding parts in the case of a bonded semiconductor substrate with a diameter of 6 inches is 7 pcs or less, and the number of defective bonding parts in the case of a bonded semiconductor substrate with a diameter of 8 inches is 12 pcs or less.

[0032] The defective bonding at the bonding interface means a state where a gap is generated at the bonding interface and the first semiconductor substrate and the second semiconductor substrate are not bonded. For example, due to a plurality of pits existing on the polished surface of a polycrystalline SiC substrate, there may be a case where a portion that becomes defective bonding occurs at the bonding interface after bonding.

[0033] Here, the defective bonding parts can be measured by a wafer surface defect inspection device, and the number of voids (<8 pcs) formed at the single crystal substrate interface and the polycrystalline substrate interface detected within the area of the effective region (for example, in the case of a 6-inch substrate, 161 cm 2 ) where a device can be fabricated on the single crystal substrate side is divided by the area of the effective region to obtain the defect density (pcs / cm 2 ). Note that the defective bonding targets regions with a diameter of 10 μm or more.

[0034] [Manufacturing Method of Bonded Semiconductor Substrate] Next, as an example of a manufacturing method of a bonded semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate of the present invention, a manufacturing method of a bonded semiconductor substrate 10 in which a support substrate 11 as the first semiconductor substrate is a polycrystalline SiC substrate and a single crystal substrate 13 as the second semiconductor substrate is a single crystal 4H-SiC substrate will be described. Here, a case where the bonded semiconductor substrate 10 is manufactured using the peeling technique of the single crystal substrate 13 by ablation of hydrogen atoms will be described while referring to a flowchart or the like showing an example of the manufacturing method of the bonded semiconductor substrate shown in FIG. 1.

[0035] As the first semiconductor substrate and the second semiconductor substrate, silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O3 ) and any of diamond may be used. Note that the carbon (C) is other than diamond, for example, graphite or the like.

[0036] The first semiconductor substrate may be polycrystalline, and the second semiconductor substrate may be single crystal. When a single crystal SiC substrate is used for the single crystal substrate 13, it is not limited to a single crystal 4H-SiC substrate, and various polytype single crystal SiC substrates such as 3C-SiC and 6H-SiC can be used as the single crystal substrate 13. Further, when a polycrystalline SiC substrate is used for the support substrate 11, it is not limited to a polycrystalline 3C-SiC substrate, and various polytype polycrystalline SiC substrates can be used.

[0037] First, the support substrate 11 and the single crystal substrate 13 are prepared. The support substrate 11 and the single crystal substrate 13 can be obtained with the bonding target surfaces already flattened. The flattening may be performed by grinding or cutting, or may be performed by the CMP method. Also, the flattening of the bonding target surface may be performed by oneself.

[0038] 〈Hydrogen ion implantation step (step S0)〉 In step S0 of FIG. 1, a hydrogen ion implantation step of implanting hydrogen ions from the bonding target surface 13a of the single crystal substrate 13 is performed. When hydrogen ions are implanted into the single crystal substrate 13, the hydrogen ions reach a depth corresponding to the incident energy and are distributed at a high concentration. As a result, as shown in the side schematic view of FIG. 3, a hydrogen implantation layer 15 indicated by a dotted line is formed at a predetermined depth from the bonding target surface 13a. For example, the hydrogen implantation layer 15 is formed at a position about 0.6 μm deep from the bonding target surface 13a.

[0039] Helium may be ion implanted instead of hydrogen to form a helium implantation layer, or hydrogen and helium may be alternately ion implanted to form an implantation layer, and a similar peeling effect in the peeling step described later can be expected.

[0040] Note that the hydrogen ion implantation process is not an essential process in the present invention, and the single crystal substrate 13 after hydrogen ion implantation may be obtained by purchasing it, etc., and the present invention may be implemented using the same.

[0041] Further, the hydrogen ion implantation process is a process that can be adopted including, for example, the case where the first semiconductor substrate is a SiC polycrystalline substrate and the second semiconductor substrate is a SiC single crystal substrate, or the case where the first semiconductor substrate is a Si substrate and the second semiconductor substrate is a Si substrate, and it is a process that can be performed before or after the amorphous layer stacking process described later.

[0042] 〈Oxide removal step (step S1)〉 This step is a step of removing at least one of the oxide on the first bonding target surface or the oxide on the second bonding target surface before the amorphous layer stacking step. By removing the oxide, bonding hands such as Si and C can be exposed on the first bonding target surface and the second bonding target surface, so that the first semiconductor substrate and the second semiconductor substrate can be bonded more firmly.

[0043] As a specific method of the oxide removal step, there is no particular limitation as long as it is a method capable of removing the oxide on the first bonding target surface or the oxide on the second bonding target surface. For example, a method of removing the oxide and the adsorption layer on these surfaces by the sputtering phenomenon by colliding atoms or molecules with the first bonding target surface or the second bonding target surface, or a method of chemically reacting a reactive gas with the oxide on the first bonding target surface or the second bonding target surface and removing it by etching can be used.

[0044] In the present invention, in the amorphous layer lamination step of the next process, when the sputtering method is used, it is preferable to remove the oxide by the sputtering method also in the oxide removal step. That is, at least one of the first bonding target surface or the second bonding target surface may be used as a target, and at least one of the oxide on the first bonding target surface or the oxide on the second bonding target surface may be removed by the sputtering method. Specifically, the oxide may be removed by irradiating argon ions used in the sputtering method not on the target material but on the bonding target surface 11a or the bonding target surface 13a (Fig. 5).

[0045] The oxide removal step is performed in step S1 of Fig. 1. For example, as shown in Fig. 5, the single crystal substrate 13 and the support substrate 11 are installed in the chamber 101 of the sputtering apparatus and processed while facing the sputtering targets 102 and 103 respectively. For example, by setting the output of argon ions to a low output of 0.5 kw to 2.0 kw compared to the normal sputtering method and irradiating argon ions to at least one of the bonding target surface 11a or the bonding target surface 13a, the oxide adhering to these surfaces can be removed. The degree of vacuum in the chamber 101 may be, for example, about 10 to 1×10 -2 Pa.

[0046] Also, by performing the oxide removal step and the amorphous layer lamination step of the next process by the sputtering method and as continuous steps in the same apparatus, since these are processes in a vacuum, the bonding target surfaces 11a and 13a can laminate the amorphous layer while maintaining the active state without being oxidized, etc., and it is possible to suppress bonding failure due to oxide, so that the manufacturing time can be shortened and the first semiconductor substrate and the second semiconductor substrate can be bonded more firmly.

[0047] Note that the oxide removal step is not an essential step and can be omitted if two substrates can be joined by the bonding step described later to form a bonded semiconductor substrate without any problems. Further, when performing the oxide removal step, if the oxide exists only on either the first bonding target surface or the second bonding target surface, it is sufficient to remove the oxide only on that one surface, and it is not necessarily required to perform it on both of these surfaces.

[0048] 〈Amorphous layer deposition step (Step S2)〉 This step is a step of depositing an amorphous layer 12 having the same composition as the first semiconductor substrate on the first bonding target surface of the first semiconductor substrate, the second bonding target surface of the second semiconductor substrate, or both surfaces thereof. That is, it is a step of depositing and laminating the amorphous layer 12 on at least one of the bonding target surface 11a or the bonding target surface 13a, and the amorphous layer 12 may be laminated on both the bonding target surface 11a and the bonding target surface 13a.

[0049] In FIG. 1, in step S2, the amorphous layer 12 is deposited on the bonding target surface 13a of the single crystal substrate 13. The amorphous layer 12 only needs to be a layer in which the regularity of the element arrangement is absent, that is, it is not a crystal and the elements are arranged irregularly.

[0050] For depositing the amorphous layer 12, it is preferable to use a physical vapor deposition method. For example, vapor deposition methods and sputtering methods can be mentioned.

[0051] In the present invention, atomic diffusion bonding is performed in the subsequent bonding process. In Patent Document 1, the surfaces of a single crystal substrate and a polycrystalline substrate are irradiated with a neutral atom beam of argon using an FAB gun to amorphize these surfaces, and then heat treatment is performed to crystallize the amorphized layer for bonding. However, the method described in Patent Document 1 is a method of amorphizing (making amorphous) the surfaces of these substrates themselves, and there are also limitations on the thickness of the amorphous layer that can be formed. In Patent Document 1, for example, the thickness of the amorphous layer is 2 nm. Therefore, when pits or the like occur on the surface of the polycrystalline substrate, the pits may remain as they are even after bonding the single crystal substrate and the polycrystalline substrate, and bonding failure portions may occur.

[0052] The bonding process of the present invention is atomic diffusion bonding, which is direct bonding at room temperature similar to that in Patent Document 1, but the amorphous layer is formed by physical vapor deposition for direct bonding. Since room temperature bonding can be adopted as the bonding process, a heating process is not required, and since warping of the substrate due to thermal stress does not occur, high-precision bonding is easy. In addition, since covalent bonding occurs at the atomic level, the bonding strength is strong, and the reliability and durability as a bonded semiconductor substrate are excellent. Furthermore, since the amorphous film is formed by physical vapor deposition, the amorphous layer can be deposited with an arbitrary thickness, so the occurrence of bonding failure due to the surface roughness of the bonding surface can be reduced compared to the method of Patent Document 1. Details will be described later.

[0053] As the physical vapor deposition method, it is more preferable to adopt a sputtering method in particular because the formed amorphous layer can be formed with a uniform thickness over the entire surface to be laminated. Note that a commercially available sputtering apparatus can be used for the sputtering method.

[0054] The amorphous layer 12 is preferably composed of the same composition as the support substrate 13. By forming it with the same composition, while maintaining strong bonding strength, it is possible to reduce the strain generated at the bonding interface during bonding, and suppress the warping of the substrate generated during the heat treatment in the semiconductor element manufacturing process due to the difference in the linear expansion coefficient. In addition, since the optical properties of the amorphous layer 12 can be matched with those of the support substrate 13, it is possible to reduce the noise from the bonding interface in the optical defect inspection of the finally manufactured bonded semiconductor substrate, and ensure the defect detection accuracy. When the support substrate is polycrystalline SiC, the amorphous layer 12 is preferably composed of SiC having the same composition as the support substrate.

[0055] As an example of an embodiment of the present invention, a method of laminating the amorphous layer 12 by sputtering film formation using the sputtering method will be described in detail.

[0056] First, as shown in FIG. 5, the single crystal substrate 13 and the support substrate 11 are placed in the chamber 101, and sputtering treatment is performed with each substrate facing the sputtering targets 102 and 103. As the sputtering target, considering the sputtering yield, a SiC target in which the ratio of Si to C in the SiC of the amorphous layer to be deposited is approximately 1:1 can be adopted. Note that the ratio of Si to C in the SiC target may be adjusted as appropriate. For example, a SiC target having a composition rich in Si may be adopted. If it is an amorphous layer formed using a SiC target having a composition rich in Si, the heating temperature in the heat treatment step of diffusing and polycrystallizing the amorphous layer can be made lower than the softening point of the polycrystalline substrate, so it is more preferable to use a SiC target having a composition rich in Si.

[0057] The atmosphere in the chamber 101 during the lamination process of the amorphous layer is set to a vacuum, and the degree of vacuum may be, for example, about 10 to 1×10 -2 Pa. Also, the output is 0.5 to 5.0 kW, and can be set to 1 kW, for example.

[0058] In addition, at least one of nitrogen (N), phosphorus (P), and boron (B) can be added to the amorphous layer for the purpose of controlling conductivity. For example, nitrogen (N) can be introduced into the atmosphere in chamber 101 at 0.1 to 50% by volume in addition to the inert gas argon (Ar), and then sputtering deposition can be performed to add nitrogen (N) to the amorphous layer.

[0059] The thickness of the stacked amorphous layer is preferably 10 nm or more. For example, amorphous layers of 5 nm each can be formed on the bonding target surfaces 11a and 13a, respectively, so that the total thickness is 10 nm, or an amorphous layer of 10 nm can be formed on only one of the surfaces. There is no upper limit on the thickness of the amorphous layer, but considering the productivity of the sputtering process, it is preferably 30 nm or less.

[0060] By stacking such an amorphous layer 12, the elements in the amorphous layer 12 are likely to move in the subsequent heat treatment process, so that the phenomenon that the elements move into the pits in the SiC polycrystalline substrate of the support substrate 11 and fill the pits is likely to occur, and as a result, the occurrence of bonding failure can be suppressed.

[0061] For example, when the amorphous layer 12 is formed on the single crystal substrate 13, as shown in the side schematic view of FIG. 4, a structure in which the amorphous layer 12 is stacked on the surface of the single crystal substrate 13 is formed.

[0062] 〈Bonding step (step S3)〉 This step is a step of bonding the first bonding target surface and the second bonding target surface after the amorphous layer stacking step to form a bonded substrate having a bonding interface.

[0063] In step S3 of FIG. 1, a bonding process is performed. In the bonding process, for example, after aligning the bonding target surface 11a of the support substrate 11 on which the amorphous layer 12 is laminated and the bonding target surface 13a of the single crystal substrate 13 in the chamber 101, they are brought into contact in a vacuum. Then, the bonds existing on the active bonding target surface 11a and the bonding target surface 13a are connected to each other, and the support substrate 11 and the single crystal substrate 13 can be bonded. As a result, as shown in the schematic diagram of FIG. 6, a structure in which the support substrate 11 and the single crystal substrate 13 are bonded is formed.

[0064] The bonding temperature may be room temperature, and the pressure during bonding may be such that warping of the substrate is suppressed and a flat surface can be ensured. For example, it may be 100 N to 500 N.

[0065] Note that the bonding process is preferably performed as a continuous process in the same apparatus as the amorphous layer lamination process. This is because it is possible to continuously process the amorphous layer lamination process and the bonding process under the same vacuum conditions, so that the surfaces of the amorphous layer 12 on the bonding target surface 11a and the bonding target surface 13a are not oxidized and the active state is maintained, ensuring stable bonding.

[0066] Furthermore, the oxide removal process, the amorphous layer lamination process, and the bonding process may be performed as continuous processes in the same apparatus. As a result, since continuous processing can be performed in a vacuum, the bonding target surface 11a and the bonding target surface 13a can laminate and bond the amorphous layer while maintaining the active state without being oxidized, and it is possible to suppress bonding defects caused by oxides, so that the manufacturing time can be shortened and the first semiconductor substrate and the second semiconductor substrate can be bonded more strongly.

[0067] <Peeling Process (Step S4)> This process is a process that can be performed after the bonding process and before the heat treatment process. When heat is applied during the peeling process, a microbubble layer is formed in the hydrogen implantation layer 15, and a part of the second semiconductor substrate is peeled off using the microbubble layer as a peeling surface. That is, the single crystal substrate 13 is peeled off using the hydrogen implantation layer 15 in which the microbubble layer is formed in the single crystal substrate 13 as a peeling surface.

[0068] In step S4 of FIG. 1, the peeling process is performed. Specifically, the support substrate 11 and the single crystal substrate 13 bonded to each other are heated to about 800° C. or higher. The atmosphere during peeling may be at least one of an inert gas such as argon (Ar) or nitrogen (N), or a vacuum. The degree of vacuum may be, for example, about 1×10 -4 ~1×10 -6 Pa. The peeling may be performed using rapid thermal annealing (RTA) or a furnace. Thereby, the single crystal substrate 13 can be separated by the hydrogen implantation layer 15. Therefore, as shown in the schematic diagram of FIG. 7, a bonded substrate 30 having a structure in which a thin single crystal substrate 13 having a thickness of, for example, 0.6 μm is bonded on the support substrate 11 can be formed.

[0069] 〈Heat treatment process (step S5)〉 This process is a process of heat-treating the bonded substrate. The bonded semiconductor substrate 10 is completed by the heat treatment process.

[0070] In step S5 of FIG. 1, a heat treatment process is performed. In the heat treatment process, the bonded substrate 30 including the support substrate 11, the amorphous layer 12, and the single crystal substrate 13 is heat treated. The heat treatment temperature may be set so that the temperature of the bonded substrate 30 is 1500°C to 2200°C, preferably about 1700°C. When the heat treatment temperature (i.e., the temperature of the bonded substrate 30) is 1500°C to 2200°C, the bonded substrate can be heat treated without problems to form a bonded semiconductor substrate. If the heat treatment temperature is less than 1500°C, the amorphous layer 12 may remain and the bonding strength of the bonding interface 14 may decrease. Further, if the heat treatment temperature exceeds 2200°C, the material of the substrate may sublime, resulting in a rough surface on the surface of the bonded substrate 30.

[0071] The atmosphere for the heat treatment may be at least one of an inert gas such as argon (Ar) or nitrogen (N), or a vacuum. The degree of vacuum may be, for example, about 1×10-4 to 1×10-6 Pa. The heat treatment process may be performed in the furnace in which the peeling process has been performed. Also, if the heat treatment temperature is maintained for 1 minute or more, the amorphous layer 12 can be completely crystallized and eliminated. The upper limit of the holding time of the heat treatment temperature is not particularly limited, but considering the manufacturing efficiency, for example, 100 hours may be set as the upper limit of the holding time. For example, the holding time of the heat treatment temperature can be set between 1 minute and 10 hours.

[0072] In the heat treatment process of step S5, when the elements of the amorphous layer 12 are recrystallized, the elements move, and it is easy for the elements to move into the pits in the SiC polycrystalline substrate of the support substrate 11 to fill the pits. As a result, it is possible to suppress bonding defects at the bonding interface 14.

[0073] By the above manufacturing method, a bonded semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface can be manufactured. The bonded semiconductor substrate is in a disk shape with a diameter of 101.6 to 203.2 mm, and the number of bonding defect portions at the bonding interface is 0.05 pcs / cm 2 The following is a bonded semiconductor substrate.

[0074] Also, in the method for manufacturing a bonded semiconductor substrate of the present invention, after the heat treatment step (step S5), a single crystal layer having a required thickness may be epitaxially grown on the single crystal substrate 13. The epitaxial layer thus obtained serves as a formation region for various elements of the semiconductor device. The thickness of the epitaxial layer required for forming various elements is not particularly limited, but for example, in the case of a SiC bonded semiconductor substrate, it is generally 5 μm or more.

[0075] <Analysis of bonding strength> A bonded semiconductor substrate was created by bonding a single crystal SiC substrate and a polycrystalline SiC substrate based on the above method for manufacturing a bonded semiconductor substrate, and a tensile test of the bonded semiconductor substrate was performed. Even when a load of 20 (MPa), which is the upper limit of the device, was applied, the bonded surface did not peel off. Thus, it can be seen that even when the surface to be bonded has a surface roughness large enough that it cannot be bonded by the conventional direct bonding method (for example, Patent Document 2), by using the method for manufacturing a bonded semiconductor substrate according to the present invention, the single crystal SiC substrate and the polycrystalline SiC substrate can be bonded to have sufficient bonding strength to withstand semiconductor processes and the like.

[0076] <Analysis of bonding defective parts> Based on the method for manufacturing a bonded semiconductor substrate of the present invention, five 6-inch bonded semiconductor substrates were produced by bonding a single crystal SiC substrate and a polycrystalline SiC substrate, and for each of these substrates, the number of occurrences of bonding defective parts was confirmed with a wafer surface defect inspection apparatus (SICA88 manufactured by Lasertec Corporation). Also, as a comparative example, five 6-inch bonded semiconductor substrates were produced by bonding a single crystal SiC substrate and a polycrystalline SiC substrate based on the method for manufacturing a semiconductor substrate described in Patent Document 1, and for each of these substrates, the number of occurrences of bonding defective parts was similarly confirmed.

[0077] The number of bonding defective parts of the bonded semiconductor substrate produced based on the method for manufacturing a semiconductor substrate described in Patent Document 1 is 0.1 to 0.5 pcs / cm 2On the other hand, using a polycrystalline SiC substrate having a bonding target surface with the same surface roughness as that of the bonding target surface of the polycrystalline SiC substrate used in the manufacturing method described in Patent Document 1, the number of bonding transfer portions of the bonded semiconductor substrate produced by the manufacturing method of the bonded semiconductor substrate of the present invention was less than 0.05 pcs / cm for all five substrates. 2 It became like this.

[0078] Also, the number of defective bonding portions of the bonded semiconductor substrate produced based on the manufacturing method of the semiconductor substrate described in Patent Document 1 has a strong positive correlation with the surface roughness of the bonding target surface of the polycrystalline SiC substrate used as the support substrate, and it was found that as the surface roughness increases, the number of defective bonding portions tends to increase. On the other hand, the positive correlation between the number of defective bonding portions of the bonded semiconductor substrate produced by the manufacturing method of the bonded semiconductor substrate of the present invention and the surface roughness of the bonding target surface of the polycrystalline SiC substrate used as the support substrate is small, and it was confirmed that by adjusting the thickness of the amorphous layer to be deposited, it is possible to reduce the number of defective bonding portions generated.

[0079] From the above, it can be seen that the manufacturing method of the bonded semiconductor substrate of the present invention can suppress the occurrence of defective bonding of the produced bonded semiconductor substrate.

[0080] <Effect> In the manufacturing method of the bonded semiconductor substrate of the present invention, by laminating an amorphous layer on at least one of the first bonding target surface of the first semiconductor substrate or the second bonding target surface of the second semiconductor substrate, the atoms constituting the semiconductor are made more mobile, and for example, it becomes easier for an element to move into a pit on the bonding target surface of a polycrystalline SiC substrate used as a support substrate and fill the pit, making it possible to suppress the occurrence of defective bonding portions.

[0081] (Summary) From the above, according to the present invention, it is possible to provide a bonded semiconductor substrate and a manufacturing method of a bonded semiconductor substrate that can suppress the occurrence of defective bonding due to pits and prevent peeling of the substrate at the bonding interface, which is industrially useful.

Description of Symbols

[0082] 10: Semiconductor substrate, 11: Support substrate, 11a: Bonding target surface, 12: Amorphous layer, 13: Single crystal substrate, 13a: Bonding target surface, 14: Bonding interface, 15: Hydrogen implantation layer, 30: Bonded substrate, 101: Chamber, 102: Sputtering target, 103: Sputtering target

Claims

1. A method for manufacturing a bonded semiconductor substrate, comprising a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, the method comprising: An amorphous layer stacking step of stacking an amorphous layer having the same composition as the first semiconductor substrate on at least one of a first bonding target surface which is a surface of the first semiconductor substrate to be bonded to the second semiconductor substrate, or a second bonding target surface which is a surface of the second semiconductor substrate to be bonded to the first semiconductor substrate; A bonding step of bonding the first bonding target surface and the second bonding target surface after the amorphous layer stacking step to form a bonded substrate having a bonding interface; A heat treatment step of heat-treating the bonded substrate, wherein the amorphous layer stacking step and the bonding step are performed in the same apparatus. A method for manufacturing a bonded semiconductor substrate, characterized by this.

2. The first semiconductor substrate and the second semiconductor substrate are any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), and diamond, and the manufacturing method of the bonded semiconductor substrate according to claim 1, wherein the first semiconductor substrate is polycrystalline and the second semiconductor substrate is single crystal.

3. The method for manufacturing a bonded semiconductor substrate according to claim 1, wherein the amorphous layer stacking step is a step of stacking the amorphous layer by sputtering film formation by a sputtering method on at least one of the first bonding target surface or the second bonding target surface.

4. The method for manufacturing a bonded semiconductor substrate according to claim 1, further comprising an oxide removing step of removing at least one of an oxide on the first bonding target surface or an oxide on the second bonding target surface before the amorphous layer stacking step.

5. The method for manufacturing a bonded semiconductor substrate according to claim 4, wherein the oxide removing step targets at least one of the first bonding target surface or the second bonding target surface, and removes at least one of an oxide on the first bonding target surface or an oxide on the second bonding target surface by a sputtering method.

6. The method for manufacturing a bonded semiconductor substrate according to claim 1, wherein the heat treatment step is a step of maintaining the temperature of the bonded substrate at 1500°C to 2200°C.

7. The method for manufacturing a bonded semiconductor substrate according to claim 1, further comprising an ion implantation step of implanting hydrogen ions or helium ions into the second bonding target surface before the amorphous layer stacking step to form an ion implantation layer inside the second semiconductor substrate.

8. A peeling step is provided after the bonding step and before the heat treatment step, The manufacturing method of the bonded semiconductor substrate according to claim 7, wherein the peeling step is a step of peeling a part of the second semiconductor substrate using a microbubble layer formed by heating the ion implantation layer as a peeling surface.

9. The manufacturing method of the bonded semiconductor substrate according to claim 1, wherein the amorphous layer stacking step is a step of stacking an amorphous layer having a thickness of 10 nm to 30 nm.

10. A bonded semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, wherein the bonded semiconductor substrate has a disk shape with a diameter of 100 to 210 mm. The number of defective bonding portions at the bonding interface is 0.05 pcs / cm ２ The bonded semiconductor substrate, wherein the number is 0.05 pcs / cm or less.

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