Semiconductor device

Abstract

To inhibit increase in a chip size and process costs, in a semiconductor device having an insulation type signal transmission element.SOLUTION: In a plan view, a semiconductor device 1010 is divided into a low potential region 1 taking the ground as its reference potential, a high potential region 2 taking floating potential as its reference potential, and a high breakdown voltage isolation region 3 provided between the low potential region 1 and the high potential region 2 to separate both regions. The semiconductor device 1010 comprises a signal transmission element provided on an element structure 21 in the high breakdown voltage isolation region 3. The signal transmission element comprises: a primary coil 18 that is provided on the side of low potential region 1 of the high breakdown voltage isolation region 3 and is connected to the low potential region 1; and a secondary coil 19 that is provided on the side of high potential region 2 of the high breakdown voltage isolation region 3 and is connected to the high potential region 2. The primary coil 18 and the secondary coil 19 are magnetically coupled with each other by a magnetic field in a direction in parallel with a principal surface of a p-type substrate 4.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a configuration in which, in the configuration of an HVIC (High Voltage IC), instead of a transistor driven at a high voltage, a magnetic coupling element is used to realize a signal transmission function with insulation and level shift.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the conventional technology, an insulated signal transmission element (a magnetic coupling element in Patent Document 1) is integrated on one chip of an HVIC. However, since the signal transmission element is large in size and becomes an ineffective region, there is a problem that the chip size increases. In addition, in order to increase the breakdown voltage, it is necessary to thicken the interlayer dielectric between wirings, resulting in an increase in the process cost.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to suppress an increase in chip size and an increase in process cost in a semiconductor device having an insulated signal transmission element.

Means for Solving the Problems

[0006] The semiconductor device of the present disclosure is a semiconductor device including a semiconductor substrate and an element structure formed on the semiconductor substrate. In a plan view, the semiconductor device is divided into a low potential region having a ground as a reference potential, a high potential region having a floating potential as a reference potential, and a high breakdown voltage separation region provided between the low potential region and the high potential region to separate the two. The semiconductor device includes a signal transmission element provided on the element structure in the high breakdown voltage separation region. The signal transmission element includes a primary side element provided on the low potential region side of the high breakdown voltage separation region and connected to the low potential region, and a secondary side element provided on the high potential region side of the high breakdown voltage separation region and connected to the high potential region. The primary side element and the secondary side element are magnetically coupled or capacitively coupled to each other by a magnetic field or an electric field in a direction parallel to the main surface of the semiconductor substrate.

Effects of the Invention

[0007] Since the semiconductor device of the present disclosure includes a signal transmission element in the high breakdown voltage separation region which is an inactive region, an increase in the additional inactive region due to the provision of the signal transmission element does not occur, and an increase in the chip size can be suppressed. Further, since the vertical potential difference between the signal transmission element and the element structure is small, the interlayer film thickness of the wiring can be thinned, and the process cost is reduced.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] In the following description, N-type and P-type represent the conductivity types of semiconductors. N+ type means that the N-type impurity concentration is higher than that of the N-type.

[0010] <A. Embodiment 1> <A-1. Configuration> FIG. 1 is a top view of a semiconductor device 1010 according to Embodiment 1. FIG. 2 is a cross-sectional view of the semiconductor device 1010 taken along line A-A' of FIG. 1. Hereinafter, the configuration of the semiconductor device 1010 will be described using these figures.

[0011] The semiconductor device 1010 is an HVIC (High Voltage Integrated Circuit) chip that drives and controls a power device. Here, the power device is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (metal-oxide-semiconductor field-effect transistor).

[0012] As shown in FIG. 1, the semiconductor device 1010 is divided into three regions in a plan view: a low potential region 1, a high potential region 2, and a high breakdown voltage isolation region 3. The high breakdown voltage isolation region 3 is provided between the low potential region 1 and the high potential region 2, and electrically isolates the low potential region 1 and the high potential region 2. In the example of FIG. 1, the high breakdown voltage isolation region 3 is formed surrounding the high potential region 2.

[0013] The low potential region 1 has the ground (GND) as the reference potential. The high potential region 2 has a floating voltage electrically separated from the GND as the reference voltage.

[0014] As shown in FIG. 2, the semiconductor device 1010 includes a P-type substrate 4 that is a semiconductor substrate, an element structure 21 formed on the P-type substrate 4, and a metal structure 22 composed of three layers of metal wiring formed on the element structure 21.

[0015] The element structure 21 includes an N+-type buried layer 5, a P-type well layer 6, an N-type well layer 7, a P-type anti-inversion layer 8, an N-type anti-inversion layer 9, a LOCOS oxide film 10 for element isolation, a doped polysilicon electrode 11, a high-resistance polysilicon field plate 12, a P-type body region 13, a P-type contact region 14, and an N-type contact region 15.

[0016] The N+-type buried layer 5 is provided on the P-type substrate 4 in the high potential region 2 by ion implantation.

[0017] The P-type well layer 6 and the N-type well layer 7 are formed by performing epitaxial growth on the P-type substrate 4 and the N+-type buried layer 5 and then performing ion implantation. The P-type well layer 6 is formed on the P-type substrate 4 in the low potential region 1. The N-type well layer 7 is formed on the P-type substrate 4 in the high breakdown voltage isolation region 3 and on the N+-type buried layer 5 in the high potential region 2. The N-type well layer 7 is a resurf layer. That is, the high breakdown voltage isolation region 3 has a resurf isolation structure. Note that either the P-type well layer 6 or the N-type well layer 7 may use the epitaxial growth layer as it is.

[0018] The P-type anti-inversion layer 8, the N-type anti-inversion layer 9, and the LOCOS oxide film 10 for device isolation are formed by implanting ions into the epitaxial growth layer and then performing a thermal oxidation treatment. The P-type anti-inversion layer 8 is formed on the P-type well layer 6 in the low potential region 1. The N-type anti-inversion layer 9 is formed on the N-type well layer 7 in the high potential region 2. The LOCOS oxide film 10 for device isolation is formed on the N-type well layer 7 in the high breakdown voltage isolation region 3.

[0019] For stabilizing the potential gradient of the N-type well layer 7, a doped polysilicon electrode 11 is formed on the N-type well layer 7, and a high-resistance polysilicon field plate 12 is formed on the LOCOS oxide film 10 for device isolation on the N-type well layer 7. Thus, the device structure 21 of the high breakdown voltage isolation region 3 has a resistive field plate.

[0020] For connection to the P-type substrate 4, a P-type body region 13, a P-type contact region 14, and an N-type contact region 15 are formed. The P-type body region 13 is formed on the P-type well layer 6, and the P-type contact region 14 is formed on the P-type body region 13. The N-type contact region 15 is formed on the N-type anti-inversion layer 9. The above is the configuration of the device structure 21.

[0021] In this embodiment, the metal structure 22 is composed of three layers of metal wiring. The first layer of metal wiring constitutes the aluminum wiring field plates 16 and 17. The aluminum wiring field plate 16 is formed on the low potential region 1 side of the high withstand voltage isolation region 3 and contacts the doped polysilicon electrode 11 and the P-type contact region 14. The aluminum wiring field plate 17 is formed on the high potential region 2 side of the high withstand voltage isolation region 3 and contacts the doped polysilicon electrode 11 and the N-type contact region 15.

[0022] As shown in FIG. 1, one end of the high resistance polysilicon field plate 12 is connected to the low potential region 1 via the aluminum wiring field plate 16. Further, the high resistance polysilicon field plate 12 spirally winds around the high withstand voltage isolation region 3, and the other end thereof is connected to the high potential region 2 via the aluminum wiring field plate 17.

[0023] The second layer of metal wiring includes a second layer of metal wiring 182 provided on the low potential region 1 side of the high withstand voltage isolation region 3 and a second layer of metal wiring 192 provided on the high potential region 2 side of the high withstand voltage isolation region 3. The third layer of metal wiring includes a third layer of metal wiring 183 provided on the low potential region 1 side of the high withstand voltage isolation region 3 and a third layer of metal wiring 193 provided on the high potential region 2 side of the high withstand voltage isolation region 3.

[0024] The second layer of metal wiring 182 and the third layer of metal wiring 183 constitute a horizontal primary coil 18. The primary coil 18 is provided on the low potential region 1 side of the high withstand voltage isolation region 3. Also, the second layer of metal wiring 192 and the third layer of metal wiring 193 constitute a horizontal secondary coil 19. The secondary coil 19 is provided on the high potential region 2 side of the high withstand voltage isolation region 3. Note that the fact that the primary coil 18 and the secondary coil 19 are horizontal means that the coil axes of the primary coil 18 and the secondary coil 19 are parallel to the plane direction of the P-type substrate 4. The primary coil 18 is connected to the low potential region 1, and the secondary coil 19 is connected to the high potential region 2.

[0025] As shown in FIG. 1, the coil axis of the primary coil 18 and the coil axis of the secondary coil 19 face each other. That is, the coil axis of the secondary coil 19 exists on the extension line of the coil axis of the primary coil 18. Thereby, the primary coil 18 and the secondary coil 19 are magnetically coupled by the magnetism on the coil axis. That is, the primary coil 18 is a primary-side element, the secondary coil 19 is a secondary-side element, and the primary coil 18 and the secondary coil 19 function as a signal transmission element in a pair.

[0026] The semiconductor device 1010 described above includes a P-type substrate 4 that is a semiconductor substrate and an element structure 21 formed on the P-type substrate 4. In a plan view, the semiconductor device is divided into a low potential region 1 having GND as a reference potential, a high potential region 2 having a floating potential as a reference potential, and a high breakdown voltage isolation region 3 provided between the low potential region 1 and the high potential region 2 to insulate the two. The semiconductor device 1010 includes a signal transmission element provided on the element structure 21 in the high breakdown voltage isolation region 3. The signal transmission element includes a primary-side element provided on the low potential region 1 side of the high breakdown voltage isolation region 3 and connected to the low potential region 1, and a secondary-side element provided on the high potential region 2 side of the high breakdown voltage isolation region 3 and connected to the high potential region 2. The primary-side element and the secondary-side element are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the P-type substrate 4.

[0027] In the semiconductor device 1010, the primary-side element is a primary coil 18 that is a horizontal coil having a coil axis in a direction parallel to the main surface of the P-type substrate 4. The secondary-side coupling element is a secondary coil 19 that is a horizontal coil having a coil axis in a direction parallel to the main surface of the P-type substrate 4. The primary coil 18 and the secondary coil 19 are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the P-type substrate 4.

[0028] According to the semiconductor device 1010 described above, the following effects can be obtained. The maximum potential difference HV between the primary coil 18 and the secondary coil 19 is, for example, 600 V or 1200 V. However, since the primary coil 18 and the secondary coil 19 are horizontal, if the distance between the primary coil 18 and the secondary coil 19 is ensured by the layout pattern, the breakdown voltage between the two can be relatively easily ensured.

[0029] Also, since both the primary coil 18 and the secondary coil 19 are arranged on the high breakdown voltage isolation region 3, the potential difference in the vertical direction, that is, the thickness direction of the P-type substrate 4, is reduced. For example, in the conventional structure where both the primary coil 18 and the secondary coil 19 are provided in the low potential region 1, the maximum potential difference in the vertical direction between the lead wiring of the secondary coil and the high resistance polysilicon field plate 12 is HV.

[0030] In contrast, in the semiconductor device 1010, the maximum potential difference in the vertical direction between the primary coil 18 and the high resistance polysilicon field plate 12 is HV / 2, and the maximum potential difference in the vertical direction between the secondary coil 19 and the high resistance polysilicon field plate 12 is also HV / 2. Thus, the potential difference in the vertical direction is halved compared to the conventional structure. As a result, the thinning of the interlayer dielectric film thickness between the wirings becomes possible, and the process cost is reduced.

[0031] Also, in the semiconductor device 1010, since the primary coil 18 and the secondary coil 19 are provided in the high breakdown voltage isolation region 3 which is an inactive region, an increase in the inactive region due to the provision of the primary coil 18 and the secondary coil 19 does not occur. Therefore, the chip size can be reduced compared to the conventional structure.

[0032] <A-2. First Modified Example> FIG. 3 is a top view of a semiconductor device 1011 according to a first modified example of Embodiment 1. FIG. 4 is a cross-sectional view of the semiconductor device 1011 taken along the line A-A' of FIG. 3. Hereinafter, the configuration of the semiconductor device 1011 will be described with reference to these figures.

[0033] The semiconductor device 1011 is different from the semiconductor device 1010 only with respect to the metal structure 22. The metal structure 22 in the semiconductor device 1011 consists of N layers of metal wiring. Here, N is a natural number of 4 or more.

[0034] In the example of FIG. 4, the metal structure 22 consists of four layers of metal wiring. The fourth layer of metal wiring includes a fourth layer of metal wiring 184 provided on the low potential region 1 side of the high breakdown voltage isolation region 3 and a fourth layer of metal wiring 194 provided on the high potential region 2 side of the high breakdown voltage isolation region 3.

[0035] The second layer of metal wiring 182 and the fourth layer of metal wiring 184 constitute a horizontal primary coil 18. Also, the second layer of metal wiring 192 and the fourth layer of metal wiring 194 constitute a horizontal secondary coil 19. The third layer of metal wiring 183 connects the second layer of metal wiring 182 and the fourth layer of metal wiring 184 that constitute the primary coil 18 in the vertical direction. Similarly, the third layer of metal wiring 193 connects the second layer of metal wiring 192 and the fourth layer of metal wiring 194 that constitute the secondary coil 19 in the vertical direction.

[0036] In the example of FIG. 4, the metal structure 22 consists of four layers of metal wiring, and the horizontal coils are connected in the vertical direction by the third layer of metal wiring. When the metal structure 22 consists of five layers of metal wiring, the horizontal coils may be connected in the vertical direction by the third and fourth layers of metal wiring.

[0037] That is, the semiconductor device 1011 includes N layers of metal wiring formed on the element structure 21, where N is a natural number of 4 or more. The horizontal coils are constituted by the second and Nth layers of metal wiring. The second and Nth layers of metal wiring constituting one horizontal coil are connected in the vertical direction by the metal wiring from the third layer to the (N - 1)th layer. Thereby, an effect is obtained in which the cross-sectional areas of the primary coil 18 and the secondary coil 19 increase, and the magnetic coupling strength between the primary coil 18 and the secondary coil 19 is improved.

[0038] However, the configuration of the semiconductor device 1011 is preferably applied when the number of wiring layers increases and the process cost increases, when multilayer wiring is required in other circuit regions, or when it is necessary to improve the magnetic coupling strength to ensure the operation margin of signal transmission or the like.

[0039] <A-3. Second Modified Example> FIG. 5 is a top view of a semiconductor device 1012 according to a second modified example of Embodiment 1. FIG. 6 is a cross-sectional view of the semiconductor device 1012 taken along line A-A' of FIG. 5. Hereinafter, the configuration of the semiconductor device 1012 will be described with reference to these figures.

[0040] In the semiconductor device 1012, in the configuration of the semiconductor device 1011, the metal wiring from the third layer to the (N-1)th layer is made of a magnetic material, and is inserted flatly into the primary coil 18 and the secondary coil 19 composed of the metal wiring of the second layer and the Nth layer to form a coil core 20.

[0041] FIG. 6 shows a case where the metal structure 22 is composed of four layers of metal wiring. In this example, the metal wiring of the third layer is inserted into the primary coil 18 and the secondary coil 19 to form a coil core 20.

[0042] That is, the semiconductor device 1012 includes N layers of metal wiring formed on the element structure, where N is a natural number of 4 or more. The horizontal coil is composed of the metal wiring of the second layer and the Nth layer, and the metal wiring from the third layer to the (N-1)th layer is made of a magnetic material and constitutes the coil core 20 of the horizontal coil. With the above configuration, the magnetic coupling strength between the primary coil 18 and the secondary coil 19 is improved.

[0043] Note that cobalt is suitable as the magnetic material used for the coil core 20 because cobalt has been put into practical use as a wiring material for semiconductors. However, nickel may be used in addition to cobalt, or an alloy of cobalt or nickel may be used.

[0044] However, the configuration of the semiconductor device 1012 is preferably applied when the number of wiring layers increases and the process cost increases, when multilayer wiring is required in other circuit regions, or when it is necessary to improve the magnetic coupling strength to ensure the operation margin of signal transmission or the like.

[0045] <A-4. Third Modified Example> FIG. 7 is a top view of a semiconductor device 1013 according to a third modified example of Embodiment 1. FIG. 8 is a cross-sectional view of the semiconductor device 1013 taken along line A-A' in FIG. 7. Hereinafter, the configuration of the semiconductor device 1013 will be described with reference to these figures.

[0046] The semiconductor device 1013 differs from the semiconductor device 1010 only with respect to the metal structure 22. The metal structure 22 in the semiconductor device 1013 consists of two layers of metal wiring. The first layer of metal wiring includes, in addition to the aluminum wiring field plates 16 and 17, the first-layer metal wiring 181 that forms the primary coil 18 and the first-layer metal wiring 191 that forms the secondary coil 19. That is, the first-layer metal wirings 181 and 191 are aluminum wirings.

[0047] The primary coil 18 is formed by the first-layer metal wiring 181 and the second-layer metal wiring 182. Also, the secondary coil 19 is formed by the first-layer metal wiring 191 and the second-layer metal wiring 192.

[0048] That is, the semiconductor device 1013 includes two-layer metal wiring formed on the element structure 21, and the horizontal coil is composed of the first-layer and second-layer metal wirings. According to the semiconductor device 1013, since the metal structure 22 is composed of two-layer metal wiring, which is less than that of the other semiconductor devices 1010, 1011, and 1012 described above, the process cost is reduced. However, it is necessary to form the lower-layer wiring of the horizontal coil with aluminum wiring in the same layer as the aluminum wiring field plates 16 and 17. Therefore, the area where the horizontal coil can be formed is narrow, the number of turns of the coil decreases, and the magnetic coupling strength becomes weak. In addition, since the vertical distance between the primary coil 18 and the secondary coil 19 and the high-resistance polysilicon field plate 12 becomes short, the electric field strength increases and the breakdown voltage decreases. However, if the necessary breakdown voltage and the operation margin of signal transmission are still ensured, the semiconductor device 1013 is the most inexpensive and preferable embodiment.

[0049] <A-5. Fourth Modified Example> FIG. 9 is a top view of a semiconductor device 1014 according to a fourth modified example of the first embodiment. FIG. 10 is a cross-sectional view of the semiconductor device 1014 taken along the line A-A' in FIG. 9. Hereinafter, the configuration of the semiconductor device 1014 will be described with reference to these figures.

[0050] The semiconductor device 1014 is different from the semiconductor device 1013 in that the metal structure 22 is composed of N-layer metal wiring. Here, N is a natural number of 3 or more.

[0051] In the example of FIG. 10, the metal structure 22 is composed of three-layer metal wiring. The first-layer metal wirings 181 and 191 have the same configuration as that of the semiconductor device 1013. The first-layer metal wiring 181 and the third-layer metal wiring 183 constitute a horizontal primary coil 18. Also, the first-layer metal wiring 191 and the third-layer metal wiring 193 constitute a horizontal secondary coil 19. The second-layer metal wiring 182 vertically connects the first-layer metal wiring 181 and the third-layer metal wiring 183 that constitute the primary coil 18. Similarly, the second-layer metal wiring 192 vertically connects the first-layer metal wiring 191 and the third-layer metal wiring 193 that constitute the secondary coil 19.

[0052] In the example of FIG. 10, the metal structure 22 is composed of three layers of metal wiring, and the horizontal coil is connected in the vertical direction by the second layer of metal wiring. When the metal structure 22 is composed of four layers of metal wiring, the horizontal coil may be connected in the vertical direction by the second and third layers of metal wiring. That is, when N layers of metal wiring are used, the horizontal coil may be connected in the vertical direction by the metal wiring from the second layer to the (N-1) layer.

[0053] That is, the semiconductor device 1014 includes N layers of metal wiring formed on the element structure 21, where N is a natural number of 3 or more. The horizontal coil is composed of the first and Nth layers of metal wiring. The second and Nth layers of metal wiring constituting one horizontal coil are connected in the vertical direction by the metal wiring from the second layer to the (N-1) layer. With the above configuration, the cross-sectional areas of the primary coil 18 and the secondary coil 19 increase, and the magnetic coupling strength between the primary coil 18 and the secondary coil 19 is improved. Depending on the number of wiring layers as a process or constraints on the layout, etc., the structure of the semiconductor device 1014 can be optimized.

[0054] <A-6. Fifth Modification Example> FIG. 11 is a top view of a semiconductor device 1015 according to a fifth modification example of Embodiment 1. FIG. 12 is a cross-sectional view of the semiconductor device 1015 taken along line A-A' of FIG. 11. Hereinafter, the configuration of the semiconductor device 1015 will be described with reference to these figures.

[0055] The semiconductor device 1015 is obtained by forming the metal wiring from the second layer to the (N-1) layer of the semiconductor device 1014 with a magnetic material and inserting it flatly into the primary coil 18 and the secondary coil 19 composed of the first and Nth layers of metal wiring to form a coil core 20.

[0056] FIG. 12 shows the case where the metal structure 22 is composed of three layers of metal wiring. In this example, the second layer of metal wiring is inserted into the primary coil 18 and the secondary coil 19 to form the coil core 20.

[0057] That is, the semiconductor device 1015 includes N metal wirings formed on the element structure, where N is a natural number of 3 or more. The horizontal coil is composed of the metal wirings of the first layer and the Nth layer. The metal wirings from the second layer to the (N - 1)th layer are made of a magnetic material and constitute the coil core of the horizontal coil. With the above configuration, the magnetic coupling strength between the primary coil 18 and the secondary coil 19 is improved. Depending on the number of wiring layers as a process or constraints on the layout, etc., the structure of the semiconductor device 1015 can be optimized.

[0058] <B. Embodiment 2> <B-1. Configuration> FIG. 13 is a top view of the semiconductor device 1020 according to Embodiment 2. The semiconductor device 1020 is different from the semiconductor device 1010 according to Embodiment 1 only in that the primary coil 18 and the secondary coil 19 are arranged such that their coil axes are parallel to each other.

[0059] In the semiconductor device 1020, the primary coil 18 and the secondary coil 19 perform magnetic coupling by the magnetic flux around their coils, not on their coil axes. The magnetic flux density around the coil is lower than that on the coil axis. However, since the coil axes of the primary coil 18 and the secondary coil 19 are parallel to the circumferential direction of the high breakdown voltage isolation region 3, there is an advantage that the coil lengths of the primary coil 18 and the secondary coil 19 can be easily lengthened and the number of turns can be increased.

[0060] <B-2. Modification> FIG. 14 is a top view of the semiconductor device 1021 according to a modification of Embodiment 2. The semiconductor device 1021 is obtained by forming the metal structure 22 with N metal wirings of 4 layers or more in the semiconductor device 1020 and forming the coil core 20 with the metal wirings from the third layer to the (N - 1)th layer. In other words, the semiconductor device 1021 is obtained by applying the arrangement in which the coil axes of the primary coil 18 and the secondary coil 19 are parallel to the semiconductor device 1012 according to the second modification of Embodiment 1.

[0061] According to the configuration of the semiconductor device 1021, the number of turns of the coil can be increased, and since the primary coil 18 and the secondary coil 19 are magnetically coupled by the magnetic flux on the coil axis passing through the coil core 20, a high magnetic coupling strength can be obtained.

[0062] <C. Embodiment 3> <C-1. Configuration> FIG. 15 is a top view of the semiconductor device 1030 according to Embodiment 3. FIG. 16 is a cross-sectional view of the semiconductor device 1030 taken along the line A-A' in FIG. 15. Hereinafter, the configuration of the semiconductor device 1030 will be described using these figures.

[0063] The metal structure 22 of the semiconductor device 1030 includes a primary flat electrode 31 provided on the low potential region 1 side of the high voltage isolation region 3 and connected to the low potential region 1, and a secondary flat electrode 32 provided on the high potential region 2 side of the high voltage isolation region 3 and connected to the high potential region 2. The primary flat electrode 31 corresponds to the primary side element, and the secondary flat electrode 32 corresponds to the secondary side element.

[0064] The primary flat electrode 31 has a first surface 311 parallel to the thickness direction of the P-type substrate 4. The secondary flat electrode 32 has a second surface 321 parallel to the thickness direction of the P-type substrate 4 and facing the first surface 311. The primary flat electrode 31 and the secondary flat electrode 32 are capacitively coupled to each other by the electric field between the first surface 311 and the second surface 321, and signal transmission is thereby performed.

[0065] That is, in the semiconductor device 1030, the primary side element is the primary flat electrode 31 having a first surface 311 parallel to the thickness direction of the P-type substrate 4. The secondary side element is the secondary flat electrode 32 having a second surface 321 parallel to the thickness direction of the P-type substrate 4 and facing the first surface 311. The primary flat electrode 31 and the secondary flat electrode 32 are capacitively coupled to each other by the electric field in the direction parallel to the main surface of the P-type substrate 4 between the first surface 311 and the second surface 321.

[0066] According to the above configuration, the vertical potential difference between the primary flat electrode 31 and the high-resistance polysilicon field plate 12 becomes HV / 2. Also, the vertical potential difference between the secondary flat electrode 32 and the high-resistance polysilicon field plate 12 also becomes HV / 2. That is, similar to Embodiments 1 and 2 where a horizontal coil is used for the capacitive coupling element, the vertical potential difference is reduced by half from the conventional structure. Therefore, it becomes possible to thin the interlayer dielectric film between the wirings, and the process cost is reduced.

[0067] <C - 2. Modification Example> Although illustration is omitted, the capacitance value may be increased by making the first surface 311 and the second surface 321, which are the capacitance formation surfaces between the primary flat electrode 31 and the secondary flat electrode 32, meander and form a pattern that meshes in a comb shape. However, in that case, since the vertical electric field strength increases at the convex portions of each comb tooth, it is necessary to determine the pattern while taking a balance with ensuring the breakdown voltage.

[0068] In Embodiments 1 to 3, the signal transmission element was provided on only one side out of the four sides of the high breakdown voltage isolation region 3. However, the signal transmission element may be provided on two or more sides of the high breakdown voltage isolation region 3, or may be provided on the entire surface including the arc portion of the high breakdown voltage isolation region 3. Thereby, the magnetic coupling strength or the capacitive coupling strength can be increased. Alternatively, a plurality of pairs of signal transmission elements can be provided.

[0069] <D. Embodiment 4> <D - 1. Configuration> FIG. 17 is a top view of a semiconductor device 1040 according to Embodiment 4. The semiconductor device 1040 is a semiconductor device 1012 according to the second modification example of Embodiment 1, in which the primary coil 18 is disposed in the low potential region 1 and the secondary coil 19 is disposed in the high potential region 2.

[0070] The metal wirings from the third layer to the (N - 1)th layer are made of a magnetic material and are inserted flatly into the primary coil 18 and the secondary coil 19 across the low potential region 1 to the high potential region 2 to form a coil core 20. The coil core 20 ensures the magnetic coupling strength.

[0071] That is, in the semiconductor device 1040, the signal transmission element includes a primary coil 18 provided in the low potential region 1, a secondary coil 19 provided in the high potential region 2, and a coil core 20 made of a magnetic material inserted into both the primary coil 18 and the secondary coil 19 across the high breakdown voltage isolation region 3. According to the above configuration, since the primary coil 18 and the secondary coil 19, which are signal transmission elements, are arranged on the circuit region, the chip size increases. However, since the vertical potential difference between the horizontal coil and the high-resistance polysilicon field plate 12 disappears, it is possible to reduce the thickness of the interlayer oxide film and the process cost.

[0072] <D - 2. Modification Example> FIG. 18 is a top view of a semiconductor device 1041 according to a modification example of Embodiment 4. In the semiconductor device 1040, the primary coil 18 and the secondary coil 19 are arranged such that their coil axes face each other. In contrast, in the semiconductor device 1041, the primary coil 18 and the secondary coil 19 are arranged such that their coil axes are parallel to each other.

[0073] <E. Embodiment 5> FIG. 19 is a cross-sectional view of a semiconductor device 1050 according to Embodiment 5. The cross-section shown in FIG. 19 corresponds to the cross-section of the semiconductor device 1010 shown in FIG. 2.

[0074] The semiconductor device 1050 is obtained by using a capacitive coupling type field plate 25 instead of the high-resistance polysilicon field plate 12 in the semiconductor device 1010 according to Embodiment 1.

[0075] The element structure 21 of the semiconductor device 1050 includes a lower layer field plate 251 in the same layer as the doped polysilicon electrode 11 in the high breakdown voltage isolation region 3. The metal structure 22 of the semiconductor device 1050 is composed of three layers of metal wiring. Among them, the first layer of metal wiring includes an upper layer field plate 252 in addition to the aluminum wiring field plates 16 and 17. That is, the upper layer field plate 252 is composed of aluminum wiring.

[0076] The capacitive coupling type field plate 25 is constituted by a lower layer field plate 251 and an upper layer field plate 252. According to the semiconductor device 1050, since aluminum wiring is used for the upper layer field plate 252, the electric field strength in the vertical direction becomes high. However, when the RESURF separation distance is short and using the high-resistance polysilicon field plate 12 results in large leakage current and power consumption and is not suitable, it is preferable to apply this structure.

[0077] Note that the configuration of this embodiment using the capacitive coupling type field plate 25 is also applicable to semiconductor devices that do not use the first layer metal wiring as a horizontal coil among the various semiconductor devices described above.

[0078] <F. Embodiment 6> FIG. 20 is a cross-sectional view of a semiconductor device 1060 according to Embodiment 6. The cross-section shown in FIG. 20 corresponds to the cross-section of the semiconductor device 1010 shown in FIG. 2.

[0079] The semiconductor device 1060 is the semiconductor device 1010 according to Embodiment 1, which is provided with a separation structure by trenches 26 (hereinafter referred to as trench separation structure) instead of the junction separation structure. The trench 26 penetrates the N-type well layer 7 in the thickness direction in the high breakdown voltage separation region 3. That is, the element structure 21 in the high breakdown voltage separation region 3 is dielectrically separated by the trench 26. An embedded oxide film layer 27 is provided between the P-type substrate 4, the P-type well layer 6, and the N-type well layer 7.

[0080] According to the semiconductor device 1060, since there is no field plate on the high breakdown voltage separation region 3, the electric field strength in the vertical direction weakens, but the process cost increases due to the trench separation structure. Therefore, when a dielectric separation structure is required in the low potential region 1 or the high potential region 2, it is preferable to apply the structure of this embodiment.

[0081] Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

[0082] Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0083] (Appendix 1) A semiconductor substrate, An element structure formed on the semiconductor substrate, a semiconductor device comprising: In a plan view, the semiconductor device A low potential region having a ground as a reference potential, A high potential region having a floating potential as a reference potential, Is divided into a high breakdown voltage separation region provided between the low potential region and the high potential region and separating the two, The semiconductor device includes a signal transmission element provided on the element structure in the high breakdown voltage separation region, The signal transmission element A primary side element provided on the low potential region side of the high breakdown voltage separation region and connected to the low potential region, A secondary side element provided on the high potential region side of the high breakdown voltage separation region and connected to the high potential region, comprising: The primary side element and the secondary side element are magnetically coupled or capacitively coupled to each other by a magnetic field or an electric field in a direction parallel to the main surface of the semiconductor substrate. Semiconductor device.

[0084] (Appendix 2) The primary side element is a primary coil which is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, The secondary side element is a secondary coil which is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, The primary coil and the secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the semiconductor substrate. The semiconductor device according to Appendix 1.

[0085] (Appendix 3) Let N be a natural number of 4 or more, and include N layers of metal wiring formed on the element structure. The horizontal coil is composed of the metal wiring of the second layer and the Nth layer. The metal wiring of the second layer and the Nth layer constituting one horizontal coil are vertically connected by the metal wiring of the third layer to the (N - 1)th layer. The semiconductor device according to Appendix 2.

[0086] (Appendix 4) Let N be a natural number of 4 or more, and include N layers of metal wiring formed on the element structure. The horizontal coil is composed of the metal wiring of the second layer and the Nth layer. The metal wiring of the third layer to the (N - 1)th layer is made of a magnetic material and constitutes the coil core of the horizontal coil. The semiconductor device according to Appendix 2.

[0087] (Appendix 5) Include two layers of metal wiring formed on the element structure. The horizontal coil is composed of the metal wiring of the first layer and the second layer. The semiconductor device according to Appendix 2.

[0088] (Appendix 6) Let N be a natural number of 3 or more, and include N layers of metal wiring formed on the element structure. The horizontal coil is composed of the metal wiring of the first layer and the Nth layer. The metal wiring of the second layer and the Nth layer constituting one horizontal coil are vertically connected by the metal wiring of the second layer to the (N - 1)th layer. The semiconductor device according to Appendix 2.

[0089] (Appendix 7) Let N be a natural number of 3 or more, and include N layers of metal wiring formed on the element structure. The horizontal coil is composed of the metal wiring of the first layer and the Nth layer. The metal wiring from the second layer to the (N-1)th layer is made of a magnetic material and constitutes the coil core of the horizontal coil. The semiconductor device according to Supplementary Note 2.

[0090] (Supplementary Note 8) The primary coil and the secondary coil are arranged such that their coil axes are parallel to each other. The semiconductor device according to Supplementary Note 2.

[0091] (Supplementary Note 9) The primary side element is a primary flat electrode having a first surface parallel to the thickness direction of the semiconductor substrate. The secondary side element is a secondary flat electrode having a second surface parallel to the thickness direction of the semiconductor substrate and facing the first surface. The primary flat electrode and the secondary flat electrode are capacitively coupled to each other by an electric field in a direction parallel to the main surface of the semiconductor substrate between the first surface and the second surface. The semiconductor device according to Supplementary Note 1.

[0092] (Supplementary Note 10) The first surface and the second surface are meandering and meshed with each other in a comb shape in a plan view. The semiconductor device according to Supplementary Note 9.

[0093] (Supplementary Note 11) The signal transmission element is provided on the entire surface of the high breakdown voltage isolation region. The semiconductor device according to Supplementary Note 1.

[0094] (Supplementary Note 12) A semiconductor substrate, An element structure formed on the semiconductor substrate, and a semiconductor device comprising the same, In a plan view, the semiconductor device A low potential region having a ground as a reference potential, A high potential region having a floating potential as a reference potential, Is divided into a high breakdown voltage isolation region provided between the low potential region and the high potential region and separating the two. The semiconductor device includes a signal transmission element provided on the element structure across the low potential region, the high breakdown voltage isolation region, and the high potential region. The signal transmission element includes a primary coil provided in the low potential region, a secondary coil provided in the high potential region, and a coil core made of a magnetic material inserted into both the primary coil and the secondary coil across the high breakdown voltage isolation region. The primary coil and the secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the semiconductor substrate. Semiconductor device.

[0095] (Appendix 13) The magnetic material is cobalt. The semiconductor device according to any one of Appendix 4, Appendix 7, or Appendix 12.

[0096] (Appendix 14) The element structure of the high breakdown voltage isolation region has a resistive field plate. The semiconductor device according to any one of Appendices 1 to 12.

[0097] (Appendix 15) The element structure of the high breakdown voltage isolation region has a capacitively coupled field plate. The semiconductor device according to any one of Appendices 1 to 12.

[0098] (Appendix 16) The element structure of the high breakdown voltage isolation region is dielectrically isolated by trenches. The semiconductor device according to any one of Appendices 1 to 12.

Explanation of reference numerals

[0099] 1 Low potential region, 2 High potential region, 3 High voltage isolation region, 4 P-type substrate, 5 N+-type buried layer, 6 P-type well layer, 7 N-type well layer, 8 P-type anti-inversion layer, 9 N-type anti-inversion layer, 10 LOCOS oxide film for device isolation, 11 Doped polysilicon electrode, 12 High-resistance polysilicon field plate, 13 P-type body region, 14 P-type contact region, 15 N-type contact region, 16, 17 Aluminum wiring field plate, 18 Primary coil, 19 Secondary coil, 20 Coil core, 21 Element structure, 22 Metal structure, 25 Capacitively coupled field plate, 26 Trench, 27 Buried oxide film layer, 31 Primary flat electrode, 32 Secondary flat electrode, 181, 182, 183, 184, 191, 192, 193, 194 Metal wiring, 251 Lower field plate, 252 Upper field plate, 311 First surface, 321 Second surface, 1010, 1011, 1012, 1013, 1014, 1015, 1020, 1021, 1030, 1040, 1041, 1050, 1060 Semiconductor device.

Claims

1. A semiconductor device comprising a semiconductor substrate and an element structure formed on the semiconductor substrate, wherein: in a plan view, the semiconductor device is divided into a low potential region having a ground as a reference potential, a high potential region having a floating potential as a reference potential, and a high breakdown voltage separation region provided between the low potential region and the high potential region to separate the two; the semiconductor device includes a signal transmission element provided on the element structure in the high breakdown voltage separation region; the signal transmission element includes a primary element provided on the low potential region side of the high breakdown voltage separation region and connected to the low potential region, and a secondary element provided on the high potential region side of the high breakdown voltage separation region and connected to the high potential region; the primary element and the secondary element are magnetically coupled or capacitively coupled to each other by a magnetic field or an electric field in a direction parallel to the main surface of the semiconductor substrate. A semiconductor device.

2. The primary element is a primary coil which is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, the secondary element is a secondary coil which is a horizontal coil having a coil axis in a direction parallel to the main surface of the semiconductor substrate, the primary coil and the secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the semiconductor substrate. The semiconductor device according to Claim 1.

3. With N being a natural number of 4 or more, the element structure is provided with N layers of metal wiring, the horizontal coil is composed of the second layer and the Nth layer of the metal wiring, the second layer and the Nth layer of the metal wiring constituting one horizontal coil are vertically connected by the third layer to the (N - 1)th layer of the metal wiring. The semiconductor device according to Claim 2.

4. With N being a natural number of 4 or more, the element structure is provided with N layers of metal wiring, the horizontal coil is composed of the second layer and the Nth layer of the metal wiring, the third layer to the (N - 1)th layer of the metal wiring are made of a magnetic material and constitute the coil core of the horizontal coil. The semiconductor device according to Claim 2.

5. The element structure is provided with two layers of metal wiring, the horizontal coil is composed of the first layer and the second layer of the metal wiring. The semiconductor device according to Claim 2.

6. With N being a natural number of 3 or more, the element structure is provided with N layers of metal wiring, the horizontal coil is composed of the first layer and the Nth layer of the metal wiring. ​ ​ ​ ​ ​ ​ The metal wirings of the second layer and the Nth layer that constitute one of the horizontal coils are vertically connected by the metal wirings of the second layer to the (N - 1)th layer. The semiconductor device according to claim 2.

7. Assuming N is a natural number of 3 or more, it includes N layers of metal wirings formed on the element structure. The horizontal coil is composed of the metal wirings of the first layer and the Nth layer. The metal wirings of the second layer to the (N - 1)th layer are made of a magnetic material and constitute the coil core of the horizontal coil. The semiconductor device according to claim 2.

8. The primary coil and the secondary coil are arranged such that their coil axes are parallel to each other. The semiconductor device according to claim 2.

9. The primary side element is a primary flat electrode having a first surface parallel to the thickness direction of the semiconductor substrate. The secondary side element is a secondary flat electrode having a second surface parallel to the thickness direction of the semiconductor substrate and facing the first surface. The primary flat electrode and the secondary flat electrode are capacitively coupled to each other by an electric field in a direction parallel to the main surface of the semiconductor substrate between the first surface and the second surface. The semiconductor device according to claim 1.

10. The first surface and the second surface are meandering and meshing with each other in a comb-like shape in a plan view. The semiconductor device according to claim 9.

11. The signal transmission element is provided on the entire surface of the high breakdown voltage isolation region. The semiconductor device according to claim 1.

12. A semiconductor substrate, An element structure formed on the semiconductor substrate, A semiconductor device comprising: In a plan view, the semiconductor device A low potential region having a ground as a reference potential, A high potential region having a floating potential as a reference potential, It is divided into a high breakdown voltage isolation region provided between the low potential region and the high potential region to separate the two. The semiconductor device includes a signal transmission element provided on the element structure across the low potential region, the high breakdown voltage isolation region, and the high potential region. The signal transmission element A primary coil provided in the low potential region, A secondary coil provided in the high potential region, A coil core made of a magnetic material inserted into both the primary coil and the secondary coil across the high breakdown voltage isolation region. The primary coil and the secondary coil are magnetically coupled to each other by a magnetic field in a direction parallel to the main surface of the semiconductor substrate. Semiconductor device.

13. The magnetic material is cobalt. The semiconductor device according to any one of claims 4, 7, or 12.

14. The element structure of the high breakdown voltage isolation region has a resistive field plate. The semiconductor device according to any one of claims 1 to 12.

15. The element structure of the high breakdown voltage isolation region has a capacitively coupled field plate. The semiconductor device according to any one of claims 1 to 12.

16. The element structure of the high breakdown voltage isolation region is dielectrically isolated by trenches. The semiconductor device according to any one of claims 1 to 12.

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