Semiconductor device

Abstract

To provide a semiconductor device in which the circuit operation can be suppressed appropriately.SOLUTION: A circuit 200 of a semiconductor device 100 includes a first circuit that outputs a first voltage, a second circuit that outputs a second voltage that is different from the first voltage, a first P-type transistor 40 that is connected to a pad shared by the circuits and that is included in the first circuit, a comparison circuit 70 that compares the first voltage and the second voltage and outputs a comparison result signal, a switch circuit 60 that switches the potential to be applied to a base of the transistor 40 to the first voltage or the second voltage in accordance with the level of the comparison result signal, and a CMOS inverter circuit 12 that includes an N-type transistor 14 having a source and a gate connected to a gate of the first P-type transistor, a drain connected to a drain of a second P-type transistor 13 and a gate of the transistor 40, the gate connected to a gate of the transistor 13 and a control circuit 11, and the source grounded, and that inverts the potential of the signal output from the control circuit and applies the potential to the gate of the transistor 40.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses an analog switch circuit that suppresses current flow through a power supply terminal when the voltage of a signal input to a terminal becomes equal to or higher than the power supply voltage input to the power supply terminal. The analog switch circuit of Patent Document 1 continues to maintain an off state even when the VA voltage input to the terminal becomes equal to or higher than the power supply voltage input to the power supply terminal D. Thereby, even when the VA voltage input to terminal A is higher than the VDD voltage input to the power supply terminal D, current flow through the power supply terminal is suppressed.

[0003] On the other hand, in the case of a semiconductor device including a PAD that is a terminal sharing an input / output port that outputs a general-purpose port such as a power supply voltage VDD and an LCD port that outputs a voltage VL supplied to an LCD driver, the input / output port may have a first P-type MOSFET (PMOS1) connected to the PAD and a CMOS switch whose output is connected to the gate of PMOS1.

[0004] The CMOS switch may be interpreted as an analog switch circuit including a second P-type MOSFET (PMOS2) and an N-type MOSFET (NMOS) having different channel types and connected in parallel.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In such a semiconductor device, when the voltage selected by the voltage selection circuit that selects the voltages of the power supply voltage VDD and the voltage VL is applied to the PAD via the PMOS1 described above, the following problems may occur.

[0007] Specifically, when PMOS1 turns from on to off, the input voltage (N1) of the CMOS switch changes from a specific voltage VSS to the power supply voltage VDD. At this time, since the gate voltage of PMOS2 is equal to the power supply voltage VDD, PMOS2 is in the off state.

[0008] For this reason, the output voltage (N2) of the CMOS switch, that is, the gate voltage of PMOS1, may require a certain amount of time until PMOS1 changes from the on state to the off state. That is, in the prior art, since the gate voltage of PMOS1 is controlled using a CMOS switch, the switching operation of PMOS1 may be delayed. That is, a certain delay may occur until PMOS1 transitions from the on state to the off state. Therefore, a delay may occur until the voltage selected by the voltage selection circuit is reflected on the PAD.

[0009] As described above, in the prior art, there is room for improvement in controlling the operation of a circuit (such as PMOS1) of a semiconductor device including a terminal that is a PAD sharing an input / output port and an LCD port.

[0010] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of appropriately suppressing the operation of a circuit.

Means for Solving the Problems

[0011] To solve the above problems, a semiconductor device according to the present disclosure includes a first circuit that outputs a first output voltage, a second circuit that outputs a second output voltage different from the first output voltage and drives a liquid crystal display, a pad that supplies at least one of the first output voltage and the second output voltage to a drive circuit of the liquid crystal display and is a terminal shared by the first circuit and the second circuit, a first P-type transistor included in the first circuit and connected to the pad, a comparison circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal that is a signal of a high-level or low-level potential corresponding to the comparison result, a switching circuit that switches the potential applied to the base of the first P-type transistor to the first output voltage or the second output voltage according to the level of the comparison result signal, a second P-type transistor whose source and gate are connected to the gate of the first P-type transistor and the switching circuit, whose gate is connected to a control circuit, and whose drain is connected to the gate of the first P-type transistor, and an N-type transistor whose drain is connected to the drain of the second P-type transistor and the gate of the first P-type transistor, whose gate is connected to the gate of the second P-type transistor and the control circuit, and whose source is grounded, and a CMOS inverter circuit that inverts the potential of a signal of a specific potential output from the control circuit and applies it to the gate of the first P-type transistor.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are assigned to the same functions and configurations, and the description thereof will be omitted as appropriate.

[0014] (Embodiment) FIG. 1 is a diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be interpreted as a circuit 200 including a second circuit 20 that supplies a specific voltage to a liquid crystal display (LCD). The specific voltage may include a voltage VP and a voltage VN.

[0015] Here, both the voltage VP and the voltage VN are voltages obtained by dividing a voltage VL described later. Note that in this embodiment, VP > VN is described, but it is not limited thereto. The voltage VL may be interpreted as a voltage output by a booster circuit (not shown) provided in the second circuit 20.

[0016] Furthermore, the range of the voltage VL may be 2.85 [V] to 5.175 [V]. When the power supply voltage VDD is within the voltage range described later, the voltage VL may be set within this range. When the power supply voltage VDD is lower than a specific value, the voltage VL may be a value higher than the power supply voltage VDD. Specifically, when VDD is 3 [V], the voltage VL may be 5 [V].

[0017] The semiconductor device 100 may include one or more first circuits 10, a second circuit 20, pads 30, a first P-type transistor 40, an analog switch circuit 50, and a voltage selection circuit 80.

[0018] In the semiconductor device 100, the output of the voltage selection circuit 80 that selects the power supply VDD and the LCD driving voltage VL may be used as the power supply for the final stage of the pre-driver 15. The pre-driver 15 may be interpreted as a driver for the first P-type transistor 40.

[0019] (First circuit 10) The first circuit 10 may be interpreted as an input / output port that outputs a first output voltage. The first output voltage may be interpreted as the power supply voltage VDD or the voltage VSS. Hereinafter, the power supply voltage VDD may be simply referred to as VDD, and the voltage VSS may be simply referred to as VSS. Here, the power supply voltage VDD may be applied from a power supply circuit (not shown) provided outside the first circuit 10. Also, the range of VDD may be 1.8 [V] to 5.5 [V]. The input / output port may be interpreted as a port input / output circuit, a port input / output terminal, or a general-purpose port.

[0020] The first circuit 10 may include a first P-type transistor 40, a control circuit 11, and a CMOS inverter circuit 12. The control circuit 11 and the CMOS inverter circuit 12 may constitute a pre-driver 15.

[0021] (First P-type transistor 40) The first P-type transistor 40 may be interpreted as a PMOS transistor connected to the pad 30. The first P-type transistor 40 may be included in the first circuit 10.

[0022] VDD is applied to the source of the first P-type transistor 40. The gate of the first P-type transistor 40 may be connected to the drain of the second P-type transistor 13 and the drain of the N-type transistor 14. The drain of the first P-type transistor 40 may be connected to the pad 30. The back gate of the first P-type transistor 40, that is, the NWELL region of the first P-type transistor 40, may be connected to the switching circuit 60. Hereinafter, the back gate of the first P-type transistor 40 may be described as the NWELL region of the first P-type transistor 40 in some cases.

[0023] (CMOS inverter circuit 12) The CMOS inverter circuit 12 may be interpreted as a circuit that inverts the potential of a signal of a specific potential output from the control circuit 11 and applies it to the gate of the first P-type transistor 40. The CMOS inverter circuit 12 may include a second P-type transistor 13 and an N-type transistor 14.

[0024] (The second P-type transistor 13) The second P-type transistor 13 may be interpreted as a PMOS transistor. The source of the second P-type transistor 13 and the NWELL region (the back gate of the second P-type transistor 13) may be connected to the switching circuit 60.

[0025] The drain of the second P-type transistor 13 may be connected to the drain of the N-type transistor 14 and the gate of the first P-type transistor 40.

[0026] The gate of the second P-type transistor 13 may be connected to the control circuit 11 and the gate of the N-type transistor 14.

[0027] (The N-type transistor 14) The N-type transistor 14 may be interpreted as an NMOS transistor. The drain of the N-type transistor 14 may be connected to the drain of the second P-type transistor 13 and the gate of the first P-type transistor 40.

[0028] The gate of the N-type transistor 14 may be connected to the gate of the second P-type transistor 13 and the control circuit 11. The source of the N-type transistor 14 may be grounded.

[0029] (The second circuit 20) The second circuit 20 may be interpreted as an LCD output port that outputs a second output voltage for driving an LCD, which is different from the first output voltage. The second output voltage may be interpreted as the voltage VP or the voltage VN. Hereinafter, the voltage VP may be simply referred to as VP, and the voltage VN may be simply referred to as VN.

[0030] The second circuit 20 may include a control circuit 21, a PMOS transistor 22, and an NMOS transistor 23.

[0031] A power supply voltage VP may be applied to the source of the PMOS transistor 22. The gate of the PMOS transistor 22 may be connected to the control circuit 21. The drain of the PMOS transistor 22 may be connected to the drain of the NMOS transistor 23 and a pad 30.

[0032] The drain of the NMOS transistor 23 may be connected to the drain of the PMOS transistor 22 and the pad 30. The gate of the NMOS transistor 23 may be connected to the control circuit 21. A VN may be applied to the source of the NMOS transistor 23.

[0033] (Pad 30) The pad 30 may supply a second output to a driving circuit of an LCD (not shown) and may be interpreted as a terminal shared by the first circuit 10 and the second circuit 20. The pad 30 may be interpreted as a metal portion for wire bonding to the semiconductor device 100.

[0034] The pad 30 may be connected to the first circuit 10, the second circuit 20, and the analog switch circuit 50. VDD, VP, or VN may be applied to the pad 30.

[0035] Specifically, when the first circuit 10 is operating, VDD may be applied to the pad 30. This VDD may be interpreted as an output from the first circuit 10.

[0036] When the second circuit 20 is operating and VL is greater than VDD (VL > VDD), VP or VN may be applied to the pad 30. This VP and VN may be interpreted as the VP and VN output from the second circuit 20.

[0037] When the second circuit 20 is operating and VDD is greater than VL (VDD > VL), VP or VN may be applied to the pad 30. This VP and VN may be interpreted as the VP and VN output from the second circuit 20.

[0038] (Voltage selection circuit 80) The voltage selection circuit 80 may include a comparison circuit 70, an AND circuit 300, a level shift circuit 1, an inverter circuit 2, an inverter circuit 3, and a switching circuit 60.

[0039] (Comparison circuit 70) The comparison circuit 70 may be interpreted as a circuit that compares a first output voltage and a second output voltage and outputs a comparison result signal. The comparison result signal may be interpreted as a signal having a high level (H) or low level (L) potential corresponding to the comparison result.

[0040] Specifically, the comparison circuit 70 compares the respective values of VL and VDD. When VL > VDD, the comparison circuit 70 becomes high level (H). When VDD > VL, the comparison circuit 70 becomes low level (L). The comparison result signal is input to the AND circuit 300.

[0041] (AND circuit 300) The AND circuit 300 may be connected to the output side of the comparison circuit 70. The AND circuit 300 may input the comparison result signal and a control signal lcd_en for controlling the operation of the second circuit 20.

[0042] The AND circuit 300 may output a signal having a level corresponding to the logical product result of the comparison result signal and the control signal. The signal is input to the first switch 61, the inverter circuit 2, and the level shift circuit 1.

[0043] The signal having a level corresponding to the logical product result may be interpreted as a signal including a low level (L) or high level (H) voltage.

[0044] For example, when the first circuit 10 is in use, by setting the control signal lcd_en = L, the output of the AND circuit 300 always becomes L. Therefore, regardless of the state of the comparison result signal, the voltage of the NWELL region of the first P-type transistor 40 becomes VDD. Hereinafter, the NWELL region of the first P-type transistor 40 may be simply referred to as the NWELL region.

[0045] When the second circuit 20 is in use, by setting the control signal lcd_en = H, the states of the first switch 61 and the second switch 62 are switched according to the comparison result signal. Details of the first switch 61 and the second switch 62 will be described later.

[0046] (Level shift circuit 1) The level shift circuit 1 may be interpreted as a circuit that outputs a voltage with a value different from the input voltage in the same waveform as the input voltage. Specifically, the level shift circuit 1 may convert VDD to VL and output it. The output of the level shift circuit 1 is input to the first switch 61 and the inverter circuit 3.

[0047] (Inverter circuit 2 and inverter circuit 3) The inverter circuit 2 and the inverter circuit 3 may invert the value of the input voltage and input it to the second switch 62. Specifically, the inverter circuit 2 may invert the voltage from the AND circuit 300 and input it to the second switch 62. The inverter circuit 3 may invert the voltage from the level shift circuit 1 and input it to the second switch 62.

[0048] (Switching circuit 60) The switching circuit 60 may be interpreted as a circuit that switches the potential applied to the NWELL region of the first P-type transistor 40 and the source and back gate of the second P-type transistor 13 between VDD and VL according to the level of the comparison result signal. The switching circuit 60 may include the first switch 61 and the second switch 62.

[0049] (First switch 61) The first switch 61 may include two PMOS transistors. Among the two PMOS transistors, the first transistor inputs the voltage from the level shift circuit 1, and the second transistor inputs the voltage from the AND circuit 300.

[0050] When VL > VDD, the first switch 61 is turned off, so that VDD is not applied to the NWELL region of the first P-type transistor 40.

[0051] When VDD > VL, the first switch 61 turns on, and VDD can be applied to the NWELL region of the first P-type transistor 40. Specifically, when VDD > VL, the first switch 61 can input the level of the comparison result signal without inverting it, and apply VDD to the NWELL region of the first P-type transistor 40. The level of the comparison result signal may be interpreted as the output voltage level of the logical product circuit 300.

[0052] (The second switch 62) Similar to the first switch 61, the second switch 62 may include two PMOS transistors. Among the two PMOS transistors, the first transistor may input the voltage from the inverter circuit 2, and the second transistor may input the voltage from the inverter circuit 3.

[0053] When VL > VDD, the second switch 62 inverts the level of the comparison result signal and inputs it, and VL can be applied to the NWELL region of the first P-type transistor 40. Specifically, when VL > VDD, the second switch 62 turns on, and VL can be applied to the NWELL region of the first P-type transistor 40.

[0054] When VDD > VL, the second switch 62 turns off, so that VL is not applied to the NWELL region of the first P-type transistor 40.

[0055] (Operation of the semiconductor device 100) Next, the operation of the semiconductor device 100 will be described with reference to FIGS. 2 to 4. FIGS. 2, 3, and 4 are timing charts for explaining the operation of the semiconductor device according to the embodiment.

[0056] FIG. 2 shows the voltage when the first circuit 10, which is a port input / output circuit, is used. FIGS. 3 and 4 show the voltage when the second circuit 20, which is an LCD circuit, is used. FIG. 3 shows the voltage when VDD > VL. FIG. 4 shows the voltage when VL > VDD.

[0057] Figures 2, 3, and 4 show the pad 30, the voltage applied to the NWELL region of the first P-type transistor 40, and the like. To the NWELL region of the first P-type transistor 40, the power supply voltage VDD and the voltage generated at the pad 30 (PAD voltage) can be applied by the voltage selection circuit 80.

[0058] N1 is the voltage between the CMOS inverter circuit 12 and the control circuit 11. N2 is the voltage between the CMOS inverter circuit 12 and the first P-type transistor 40. N3 is the voltage between the NMOS transistor connected to the drain of the first P-type transistor 40 and the control circuit 11.

[0059] N4 is the voltage between the PMOS transistor 22 and the control circuit 21. N5 is the voltage between the NMOS transistor 23 and the control circuit 21.

[0060] N6 is the output between the comparison result signal, that is, the comparison circuit 70 and the AND circuit 300. N7 is the output of the AND circuit 300. N8 is the output of the inverter circuit 2. N9 is the output of the level shift circuit 1. N10 is the output of the inverter circuit 3.

[0061] (When using the port input / output circuit) When using the port input / output circuit, that is, when using the first circuit 10, a voltage similar to the voltage of N1 is generated at the pad 30. The voltage of the NWELL region rises to VDD. The pre-driver 15 operates as a normal inverter with VDD as the power supply.

[0062] Specifically, when using the first circuit 10, the control signal lcd_en = L. As a result, the first switch 61 turns on and the second switch 62 turns off. Therefore, VDD is applied to the back gate of the first P-type transistor 40, that is, the NWELL region of the first P-type transistor 40.

[0063] When the first switch 61 is on, it can be interpreted that the gate potentials of the two PMOS transistors included in the first switch 61 become L, that is, 0 [V], and it can also be interpreted that the two PMOS transistors are in the on state.

[0064] When the second switch 62 is off, it can be interpreted that among the two PMOS transistors included in the second switch 62, VDD is applied to the gate of the first transistor and VL is applied to the gate of the second transistor, so that either one or both of the two PMOS transistors are in the off state. With this configuration, regardless of the magnitude relationship between VL and VDD, at least one of the two PMOS transistors is in the off state, and the second switch 62 is off.

[0065] Since the second circuit 20, which is an LCD circuit, is in an inoperative state, each value of VL, VP, and VN can be a specific voltage from 0 [V] to VDD. That is, VL, VP, and VN are values between VDD and VSS.

[0066] (Example 1 when using the second circuit 20) When using the LCD circuit, that is, when using the second circuit 20, as shown in FIG. 3, when the input of the comparison circuit 70 is VDD>VL, the comparison result signal becomes L. As a result, the first switch 61 turns on and the second switch 62 turns off. Therefore, VDD, which is the first output voltage, is applied to the gate of the first P-type transistor 40 and the NWELL region of the first P-type transistor 40.

[0067] (Example 2 when using the LCD circuit) When using the LCD circuit, as shown in FIG. 4, when the input of the comparison circuit 70 is VL>VDD, the comparison result signal becomes H. As a result, the first switch 61 turns off and the second switch 62 turns on. Therefore, VL, which is the second output voltage, is applied to the back gate of the first P-type transistor 40, that is, the NWELL region of the first P-type transistor 40.

[0068] Here, in order to set the port output (the output of the second circuit 20) to the HiZ state, as shown in FIGS. 3 and 4, the voltage of N1 is set to 0 [V]. Setting the voltage of N1 to 0 [V] means that the output voltage of the control circuit 11 becomes 0 [V]. The HiZ state can be interpreted as a state where the second P-type transistor 13 and the N-type transistor 14 connected to the pad 30 are in the off state and the impedance (resistance) is extremely high.

[0069] Since the power supply of the final stage of the pre-driver 15 is the NWELL region, the gate voltage of the first P-type transistor 40 is equal to the NWELL region. Since the voltage of the NWELL region is the higher voltage of VDD and VL, it is higher than the voltage of the pad 30. Therefore, the first P-type transistor 40 is in the off state, and the output of the second circuit becomes HiZ.

[0070] According to the present disclosure, the gate of the first P-type transistor 40 can be controlled by a CMOS type inverter circuit 12 equivalent to a normal inverter circuit. Therefore, no delay occurs until the first P-type transistor 40 transitions from the on state to the off state.

[0071] That is, by driving the first P-type transistor 40 with the CMOS type inverter circuit 12, since the first P-type transistor 40 remains in the on state and is connected to the NWELL region, the NWELL region has a low resistance. As a result, no delay time occurs until the first P-type transistor 40 transitions from the on state to the off state.

[0072] (Comparative Example) FIG. 6 is a diagram showing the configuration of a semiconductor device according to a comparative example. The semiconductor device 100A according to the comparative example has a different configuration of the first circuit 10A. The first circuit 10A includes an analog switch circuit 16 instead of the CMOS type inverter circuit 12 shown in FIG. 1.

[0073] The analog switch circuit 16 may be interpreted as a CMOS switch circuit. Specifically, the analog switch circuit 16 may be interpreted as a circuit including an NMOS transistor 17 and a PMOS transistor 18 which have different channel types and are connected in parallel.

[0074] VDD is applied to the gate of the NMOS transistor 17. The gate of the NMOS transistor 17 may be connected to the source of the first P-type transistor 40 and the gate of the P-type transistor 14A.

[0075] The drain of the NMOS transistor 17 may be connected to the gate of the first P-type transistor 40 and the drain of the PMOS transistor 18.

[0076] The source of the NMOS transistor 17 may be connected to the control circuit 11 and the source of the PMOS transistor 18.

[0077] The drain of the PMOS transistor 18 may be connected to the drain of the NMOS transistor 17, the gate of the first P-type transistor 40, and the source of the P-type transistor 14A.

[0078] The gate of the PMOS transistor 18 may be connected to the gate of the P-type transistor 14A, the drain of the first P-type transistor 40, and the pad 30.

[0079] The source of the PMOS transistor 18 may be connected to the control circuit 11 and the source of the NMOS transistor 17.

[0080] (Operation of the semiconductor device according to the comparative example)

[0081] FIG. 6 is a diagram for explaining the operation of the semiconductor device according to the comparative example. FIG. 6 shows a graph indicating the relationship between the resistance between the sources of the drains of the NMOS transistor 17 and the PMOS transistor 18 and the voltage applied to the gate.

[0082] In the PMOS transistor 18, the gate voltage becomes high resistance near VSS and low resistance near VDD. In the NMOS transistor 17, the gate voltage becomes low resistance near VSS and high resistance near VDD.

[0083] In the analog switch circuit 16 formed by combining transistors having such characteristics, the following state is assumed. Specifically, consider a state where the gate voltage of the NMOS transistor 17 is VDD and the gate voltage of the PMOS transistor 18 is the voltage of the pad 30 (= VDD).

[0084] When the voltage of N1 is low, the voltage of N1 is transmitted to N2 through the NMOS transistor 17, so the voltage change of N1 is immediately reflected in N2. When the voltage of N1 becomes high, the resistance of the NMOS transistor 17 increases. When the gate voltage of the PMOS transistor 18 is VSS, the voltage of N1 is transmitted to N2 through the PMOS transistor 18.

[0085] However, when the voltage of N1 becomes high, the gate voltage of the NMOS transistor 17 becomes VDD, so the NMOS transistor 17 is turned off and the NMOS transistor 17 becomes high resistance. Therefore, the voltage transmitted to N2 changes quickly up to a certain point in time series and changes slowly from the middle.

[0086] In the semiconductor device 100A including the analog switch circuit 16, the following problems may occur when the first P-type transistor 40 changes from the on state to the off state. Specifically, when the first P-type transistor 40 changes from the on state to the off state, the input voltage (N1) of the analog switch circuit 16 changes from a specific voltage VSS to the power supply voltage VDD. At this time, since the gate voltage of the PMOS transistor 18 is equal to the power supply voltage VDD, the PMOS transistor 18 is in the off state. For this reason, the output voltage (N2) of the analog switch circuit 16, that is, the gate voltage of the first P-type transistor 40, may require a certain time T until the first P-type transistor 40 changes from the on state to the off state (see the waveform on the right side of FIG. 5).

[0087] That is, in the semiconductor device 100A according to the comparative example, since the analog switch circuit 16 is used to control the gate voltage of the first P-type transistor 40, the switching operation of the first P-type transistor 40 may be delayed. That is, a certain delay may occur until the first P-type transistor 40 transitions from the on state to the off state. Therefore, a delay may occur until the voltage selected by the voltage selection circuit 80 is reflected in the pad 30.

[0088] (Operation and Effect) In the semiconductor device 100 of the present disclosure, instead of the analog switch circuit 16, the gate of the first P-type transistor 40 can be driven by the CMOS inverter circuit 12 with the power supply connected to the NWELL region. Therefore, when using the LCD circuit, that is, when using the second circuit 20, the port output (the output of the second circuit 20) can be set to the HiZ state, while when using the port input / output circuit, that is, when using the first circuit 10, by operating the pre-driver 15 as a normal inverter with VDD as the power supply, it is possible to reduce the delay until the first P-type transistor 40 transitions from the on state to the off state.

[0089] The CMOS inverter circuit 12 of the present disclosure is also applicable to the analog switch circuit 50.

[0090] As described above, according to the present disclosure, it is possible to provide a semiconductor device that can appropriately suppress the operation of the circuit.

[0091] Note that the following additional remarks are disclosed regarding the above description.

[0092] (Additional Remark 1) A first circuit that outputs a first output voltage, A second circuit that outputs a second output voltage for driving a liquid crystal display, which is different from the first output voltage, Supply at least one of the first output voltage and the second output voltage to the drive circuit of the liquid crystal display, and a pad which is a terminal shared by the first circuit and the second circuit, A first P-type transistor included in the first circuit and connected to the pad, A comparison circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal which is a signal of a high-level or low-level potential corresponding to the comparison result, A switching circuit that switches the potential applied to the base of the first P-type transistor to the first output voltage or the second output voltage according to the level of the comparison result signal, An N-type transistor having a source and a gate connected to the gate of the first P-type transistor and the switching circuit, the gate being connected to a control circuit, the drain being connected to the drain of the second P-type transistor and the gate of the first P-type transistor, the gate being connected to the gate of the second P-type transistor and the control circuit, and the source being grounded, and a CMOS inverter circuit that inverts the potential of the signal of a specific potential output from the control circuit and applies it to the gate of the first P-type transistor, A semiconductor device comprising the above. (Appendix 2) The semiconductor device according to Appendix 1, wherein the first circuit includes the CMOS inverter circuit.

Explanation of symbols

[0093] 1 Level shift circuit 2 Inverter circuit 3 Inverter circuit 10 First circuit 10A First circuit 11 Control circuit 12 CMOS inverter circuit 13 Second P-type transistor 14 N-type transistor 14A P-type transistor 15 Predriver 16 Analog switch circuit 17 NMOS transistor 18 PMOS transistor 20 Second circuit 21 Control circuit 22 PMOS transistor 23 NMOS transistor 30 Pad 40 First P-type transistor 50 Analog switch circuit 60 Switching circuit 61 First switch 62 Second switch 70 Comparison circuit 80 Voltage selection circuit 100 Semiconductor device 100A Semiconductor device 200 Circuit 300 AND circuit

Claims

1. a first circuit that outputs a first output voltage; a second circuit that outputs a second output voltage different from the first output voltage and drives a liquid crystal display; a pad that supplies at least one of the first output voltage and the second output voltage to a drive circuit of the liquid crystal display and is a terminal shared by the first circuit and the second circuit; a first P-type transistor included in the first circuit and connected to the pad; a comparison circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal that is a signal of a high-level or low-level potential corresponding to the comparison result; a switching circuit that switches the potential applied to the base of the first P-type transistor to the first output voltage or the second output voltage according to the level of the comparison result signal; a CMOS inverter circuit including a second P-type transistor having a source and a gate connected to the gate of the first P-type transistor and the switching circuit, the gate being connected to a control circuit, and a drain connected to the gate of the first P-type transistor, and an N-type transistor having a drain connected to the drain of the second P-type transistor and the gate of the first P-type transistor, a gate connected to the gate of the second P-type transistor and the control circuit, and a source grounded, and inverting the potential of a signal of a specific potential output from the control circuit and applying it to the gate of the first P-type transistor; A semiconductor device comprising:

2. The semiconductor device according to claim 1, wherein the first circuit includes the CMOS inverter circuit.

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