Method for manufacturing packaging substrate

Abstract

To provide a method for manufacturing packaging substrates with an improved convenience of manufacturing process and improved electrical reliability.SOLUTION: A method for manufacturing a packaging substrate according to an embodiment includes: a preparation step of preparing a base substrate 100 comprising a core layer 10 and an insulating layer 20 formed on the core layer 10; a patterning step of selectively plasma etching the insulating layer 20 with an etching mask 30 to form a patterned insulating layer 21; and a manufacturing step of manufacturing a packaging substrate from the base substrate on which the patterned insulating layer is formed. The etching mask includes an organic compound. The atmosphere temperature during the patterning step is 120°C or less. In this case, packaging substrates may be manufactured with an improved convenience of packaging substrate manufacturing process and improved electrical reliability.SELECTED DRAWING: Figure 2B

Description

Technical Field

[0001] The embodiment relates to a method for manufacturing a packaging substrate.

Background Art

[0002] In manufacturing electronic components, forming a circuit on a semiconductor wafer in the front-end (FE) process and assembling the wafer into a state where it can be used in an actual product in the back-end (BE) process, and the packaging process is included in this back-end process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has developed into various forms such as line widths in nano units below micro, more than 10 million cells, high-speed operation, and a large amount of heat dissipation. However, there is no technology that can perfectly package this relatively. Therefore, the electrical performance of the semiconductor may sometimes be determined by the packaging technology and the electrical connection thereby, rather than the performance of the semiconductor technology itself.

[0004] Recently, research has been carried out on applying ceramic materials to high-end packaging substrates. By forming through-holes in the ceramic material substrate and applying a conductive substance to these through-holes, the wiring length between the element and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] The purpose of the embodiment is to provide a method for manufacturing a packaging substrate with improved process convenience and improved electrical reliability.

Means for Solving the Problem

[0007] The method for manufacturing a packaging substrate according to an embodiment of the present specification includes a preparation step of preparing a base substrate including a core layer and an insulating layer formed on the core layer, a patterning step of selectively plasma etching the insulating layer with an etching mask to form a patterned insulating layer, and a manufacturing step of manufacturing a packaging substrate from the base substrate on which the patterned insulating layer is formed.

[0008] The etching mask contains an organic compound.

[0009] The ambient temperature of the patterning step is 120°C or lower.

[0010] In the patterning step, the etching mask may be disposed in contact with the upper surface of the insulating layer.

[0011] The insulating layer can include an etching target region.

[0012] The patterning step can include an etching process of etching a part of the insulating layer in the etching target region and a stabilization process of lowering the ambient temperature of the patterning step.

[0013] In the patterning step, taking performing the etching process and the stabilization process as one cycle, two or more cycles can be performed for each layer of the insulating layer.

[0014] The etching process may be performed for 200 seconds to 700 seconds each time.

[0015] The etching process may be performed in an atmosphere containing a first etching gas and a second etching gas.

[0016] The first etching gas may be a fluorine-based gas.

[0017] The second etching gas may be oxygen gas.

[0018] The plasma power of the etching process may be 1.5 kW or more and 3 kW or less.

[0019] The thickness of the etching mask may be 5 μm to 40 μm.

[0020] After the patterning step and before the manufacturing step, a cleaning step of ultrasonically cleaning the base substrate may be further included.

[0021] The vibration frequency of the cleaning step may be 30 kHz to 200 kHz.

[0022] The patterned insulating layer may include through holes formed in the thickness direction of the insulating layer.

[0023] The diameter of the through holes may be 3 μm to 50 μm.

[0024] The packaging substrate may include the core layer and the patterned insulating layer disposed on the core layer.

[0025] The packaging substrate may include an electrically conductive layer formed in contact with at least a part of the upper surface of the patterned insulating layer.

[0026] The peel strength of the electrically conductive layer with respect to the upper surface of the patterned insulating layer may be 200 gf / cm or more.

Advantages of the Invention

[0027] The manufacturing method of the packaging substrate according to the embodiment can manufacture a packaging substrate with improved process convenience and improved electrical reliability.

Brief Description of the Drawings

[0028]

Figure 1

Figure 2A

Figure 2B

Figure 3

Best Mode for Carrying Out the Invention

[0029] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement them. However, the present invention can be realized in various different forms and is not limited to the embodiments described herein. The same reference numerals are given to similar parts throughout the specification.

[0030] Throughout this specification, the term "these combinations" included in the Markush-form expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-form expression, and means including one or more selected from the group consisting of the said components.

[0031] Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms from each other. Also, the singular expression includes the plural expression unless the context clearly indicates otherwise.

[0032] In this specification, the "~" series may mean including a compound corresponding to "~" or a derivative of "~" in the compound.

[0033] In this specification, the meaning that B is located on A means that B is located directly in contact with A or B is located on A while another layer is located between them, and it is not construed as being limited to B being located in contact with the surface of A.

[0034] In this specification, the meaning that B is connected to A means that A and B are directly connected or A and B are connected via other components between them, and unless otherwise specified, it is not construed as being limited to A and B being directly connected.

[0035] In this specification, a singular expression is construed to include the singular or plural as construed in the context unless otherwise explained.

[0036] In this specification, the form, relative size, angle, etc. of each component in the drawings are exemplary and may be exaggerated for the purpose of explanation, and the rights are not construed as being limited to the drawings.

[0037] In this specification, the statement that A and B are adjacent means that A and B are in contact with each other or A and B are not in contact but are located close to each other. In this specification, the expression that A and B are adjacent is not construed as being limited to A and B being in contact with each other unless otherwise specified.

[0038] In this specification, a fine line means a line having a width of 5 μm or less unless otherwise explained, and exemplarily means a line having a width of 1 to 4 μm or less.

[0039] Hereinafter, embodiments will be described.

[0040] The manufacturing method of the packaging substrate of the embodiment includes a preparation step of preparing a base substrate including a core layer and an insulating layer formed on the core layer, a patterning step of selectively plasma etching the insulating layer with an etching mask to provide a patterned insulating layer, and a manufacturing step of manufacturing a packaging substrate from the base substrate on which the patterned insulating layer is formed.

[0041] FIG. 1 is a conceptual diagram for explaining the preparation step of the embodiment. The manufacturing method of the packaging substrate of the embodiment will be described with reference to FIG. 1.

[0042] Preparation step In the preparation step, a base substrate 100 including a core layer 10 and an insulating layer 20 formed on the core layer 10 can be prepared.

[0043] The core layer 10 can have the shape of a substrate. The core layer 10 is not limited as long as it is a substrate applicable as an electronic component.

[0044] As the material of the core layer 10, an organic material, glass, alumina, aluminum nitride, silicon carbide, or silicon nitride may be applied.

[0045] The core layer 10 may be a glass core. Exemplarily, an alkali borosilicate plate glass, a non-alkali borosilicate plate glass, a non-alkali alkaline earth borosilicate plate glass, etc. may be applied to the core layer 10. The core layer 10 is applicable to a glass substrate for an electronic device, and exemplarily, those manufactured by Schott, AGC, Corning, etc. may be applied, but it is not limited thereto.

[0046] The core layer 10 can include an upper surface and side surfaces connected to the upper surface and formed in the thickness direction of the core layer 10. The surface of the core layer 10 can include a lower surface facing the upper surface.

[0047] The statement that the side surface is formed in the thickness direction of the core layer 10 is interpreted to mean that not only does the side surface form a perpendicular to the upper surface of the core layer 10, but also at least a part of the side surface forms an angle (tilt angle) other than 90° with the upper surface.

[0048] The side surface may be a flat surface or a curved surface.

[0049] The core layer 10 can include a cavity (not shown) which is a space formed by a part of the core layer 10 being recessed inward.

[0050] The cavity may be formed by a part of the upper surface and / or the lower surface side of the core layer 10 being recessed in the thickness direction of the core layer 10, or may penetrate in the thickness direction of the core layer 10.

[0051] The cavity can provide a space for mounting elements. The elements mounted in the cavity can be electrically connected to other components within the packaging substrate. The elements may be not only semiconductor elements such as CPUs, GPUs, memory chips, etc., but also capacitor elements, transistor elements, impedance elements, and other modules. That is, any element to be mounted in the semiconductor device can be applied as the element without limitation.

[0052] The core layer 10 can include a through-via portion (not shown) that penetrates the core layer 10 in the thickness direction.

[0053] The through-via portion includes a via space which is a space where an electrically conductive layer is disposed, and a via inner diameter surface that surrounds the via space. The via inner diameter surface means the surface of the core layer 10 formed inside the through-via portion.

[0054] The via space may have a substantially uniform inner diameter in the thickness direction of the core layer 10. The via space may have an inner diameter that varies in the thickness direction of the core layer 10.

[0055] In the preparation step, when applying a glass core as the core layer 10, the glass core can be etched to provide a through-via portion. Specifically, defects can be formed at predetermined positions within the surface of the glass core. As methods for forming defects, methods such as mechanical etching and laser irradiation may be applied.

[0056] A through-via portion can be formed in the region where the defect is formed through physical or chemical etching. When applying chemical etching, wet etching through an etching solution can be performed. The etching solution is not limited as long as it can generally be applied to etch a glass substrate. Exemplarily, the etching solution may include a sulfuric acid solution, a nitric acid solution, a hydrofluoric acid solution, etc.

[0057] In the process of etching, the surface of the remaining glass core excluding the region where the defect is formed may be masked, or etching may be performed without masking.

[0058] Defects can be formed at one point within the upper surface of the glass core, and defects can be formed at another point within the lower surface of the glass core facing the one point, and etching is performed to provide the core layer 10 in which a through-via portion is formed.

[0059] The base substrate 100 can include an electrically conductive layer formed in the via space. The electrically conductive layer may be formed by filling at least a part of the via space, or may be formed in a thin film shape on the inner diameter surface of the via. When the electrically conductive layer is formed in a thin film shape on the inner diameter surface of the via, the remaining space other than the space occupied by the electrically conductive layer in the via space can be filled with an insulating layer.

[0060] The electrically conductive layer disposed in the via space can transmit an electrical signal in the thickness direction of the core layer 10, and can electrically connect an element to a main board, a redistribution layer, etc. to each other.

[0061] Descriptions of materials such as the insulating layer and the electrically conductive layer are omitted because they overlap with the following content.

[0062] The base substrate 100 can further include an insulating layer 20 formed on the core layer 10. The insulating layer 20 can be formed in contact with the upper surface of the core layer 10. The base substrate 100 can further include an electrically conductive layer (not shown) disposed between the core layer 10 and the insulating layer 20. The insulating layer 20 can be disposed on the electrically conductive layer and surround the electrically conductive layer.

[0063] The insulating layer 20 is not limited as long as it can be applied as the insulating layer 20 to semiconductor elements or packaging substrates. Exemplarily, the insulating layer 20 may include an epoxy resin containing a filler or the like. The insulating layer 20 may be formed, for example, through a build-up layer material such as Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Inc., an undercoat material, etc., but is not limited thereto.

[0064] The electrically conductive layer corresponds to a conducting wire for transmitting an electrical signal. The electrically conductive layer can include an electrically conductive material. Exemplarily, the electrically conductive layer can include at least any one of copper, nickel, aluminum, gold, and silver. Copper or the like may be applied as the material of the electrically conductive layer.

[0065] In the preparation step, a base substrate 100 having an insulating layer 20 pre-formed on the core layer 10 may be prepared. In the preparation step, an insulating layer 20 may be formed on the core layer 10 to prepare the base substrate 100.

[0066] An insulating layer 20 can be formed by laminating a film-like insulating resin on the core layer 10. Exemplarily, a film-like insulating layer 20 may be laminated on the core layer 10 under reduced pressure to form the base substrate 100. In such a case, the surface of the electrically conductive layer disposed under the insulating layer 20 can be surrounded without voids.

[0067] Patterning step FIG. 2A and FIG. 2B are conceptual diagrams explaining the patterning steps of an embodiment. With reference to FIGS. 2A and 2B, a method for manufacturing a packaging substrate of the embodiment will be described.

[0068] The base substrate 100 includes a core layer 10 and an insulating layer 20 formed on the core layer 10. The specific configuration of the base substrate 100 is directly applicable to that described in FIG. 1 above. The following will focus on the different parts for explanation.

[0069] In the patterning step, the insulating layer 20 can be selectively plasma-etched with an etching mask 30 to form a patterned insulating layer 21.

[0070] The etching mask 30 can help to form a pattern of a pre-designed shape on the insulating layer 20 in the patterning step. The etching mask 30 can include a pattern of the same shape as the pattern to be formed on the insulating layer 20 in the patterning step. The etching mask 30 can include a hole pattern of the same shape as the hole pattern to be formed on the insulating layer 20 in the patterning step.

[0071] The etching mask 30 can include an organic compound. The etching mask 30 may be a patterned resist layer. Different from the metal etching mask 30 of the embodiment, after the patterning of the insulating layer 20, the etching mask 30 can be easily removed through peeling without a separate etching process. Through this, the etching mask 30 can substantially leave no residue on the insulating layer 20 without causing excessive damage to the insulating layer 20 during the removal process. Also, in this case, a decrease in the bonding force between the electrically conductive layer formed on the insulating layer 20 and the insulating layer 20 can be suppressed.

[0072] The resist layer is not limited as long as it is commonly used in the field of packaging substrates. The resist layer can include an amine-based resist. The resist layer can include a positive resist. The resist layer can include a negative resist.

[0073] The etching mask 30 can be disposed in contact with the upper surface of the insulating layer 20. Specifically, a resist composition can be applied and cured on the insulating layer 20 to form a resist layer, and the resist layer can be patterned to form the etching mask 30.

[0074] When forming the resist layer, the resist composition can be applied so as to cover the entire insulating layer 20. The thickness of the applied resist composition and the thickness of the cured resist layer can be adjusted in consideration of the thickness of the etching mask 30 to be manufactured.

[0075] When patterning the resist layer, after selectively irradiating the resist layer with light along the shape of the pattern to be formed on the insulating layer 20, the light-irradiated resist layer can be developed to form the etching mask 30. Exemplarily, the irradiation of the resist layer can be performed via an electron beam.

[0076] The thickness of the etching mask 30 can be 5 μm to 40 μm. The thickness may be 10 μm or more. The thickness may be 15 μm or more. The thickness may be 35 μm or less. The thickness may be 30 μm or less. In such a case, the etching mask 30 remains even after the patterning step is completed, can assist in the selective etching of the insulating layer 20, and can contribute to realizing the precise patterning of the insulating layer 20.

[0077] In the patterning step, the insulating layer 20 can be patterned through plasma etching. The ambient temperature of the patterning step may be 120°C or less.

[0078] After placing the base substrate 100 with the etching mask 30 formed thereon in the etching chamber, an etching gas is introduced into the chamber, and plasma power is applied to perform plasma etching on the insulating layer.

[0079] In the patterning step, the insulating layer 20 can be selectively plasma-etched through the etching mask 30 to form the patterned insulating layer 21. Specifically, the etching target region 22 included in the insulating layer 20 can be plasma-etched to form the patterned insulating layer 21. The etching target region 22 is a region included in the insulating layer 20 and is a region to be removed by plasma etching in the patterning step. The etching target region 22 corresponds to a region where the upper surface of the insulating layer 20 is exposed to the outside in the insulating layer 20 with the etching mask 30 disposed thereon.

[0080] In the process of continuously performing plasma etching, the ambient temperature in the patterning step, specifically, the temperature inside the etching chamber, can continuously rise. In this case, the etching mask 30 may be denatured by heat. The denatured etching mask 30 becomes sticky and is not easily removed from the surface of the insulating layer 20, and its shape is also deformed, which may cause problems in realizing a delicate pattern on the insulating layer 20. As a result, after the removal of the etching mask 30, a large number of foreign substances may remain on the insulating layer, and the electrical reliability of the manufactured packaging substrate may be reduced.

[0081] The embodiment can help suppress the deterioration of the etching mask 30 and enable a more delicate and stable realization of a high-density rewiring layer on the core layer 10 by controlling the ambient temperature in the patterning step, that is, the temperature inside the chamber, within a preset range in the embodiment.

[0082] The ambient temperature during the patterning step may be 120°C or lower. The temperature may be 115°C or lower. The temperature may be 110°C or lower. The temperature may be 100°C or lower. The temperature may be 30°C or higher. The temperature may be 50°C or higher. The temperature may be 70°C or higher. The temperature may be 80°C or higher. In such cases, denaturation of the etching mask 30 can be suppressed, and a stable plasma state can be maintained while the patterning step is being performed.

[0083] The patterning step can include an etching process of etching a part of the insulating layer 20 in the etching target region 22 and a stabilization process of lowering the ambient temperature of the patterning step.

[0084] In one etching process, the entire insulating layer 20 in the etching target region 22 is not continuously etched. Instead, the insulating layer 20 disposed in the etching target region can be divided in the thickness direction of the insulating layer 20 and etched multiple times. Through this, it is possible to suppress the etching mask 30 from being exposed to high temperatures for a long time.

[0085] The etching process can be performed for 200 seconds to 700 seconds per time. The etching process may be performed for 250 seconds or more per time. The etching process may be performed for 300 seconds or more per time. The etching process may be performed for 350 seconds or more per time. The etching process may be performed for 650 seconds or less per time. The etching process may be performed for 600 seconds or less per time. The etching process may be performed for 550 seconds or less per time. In such cases, a pattern with a fine pitch can be formed more precisely on the insulating layer 20, and it is possible to suppress the residue of the etching mask 30 from adsorbing on the insulating layer 20 during the process of removing the etching mask 30.

[0086] The etching process can be carried out in an atmosphere containing a first etching gas and a second etching gas. The first etching gas may be a fluorine-based gas. The first etching gas may be any one of carbon fluoride, nitrogen fluoride, sulfur fluoride, and combinations thereof.

[0087] Carbon fluoride is, by way of example, CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, or any one of combinations thereof.

[0088] Nitrogen fluoride may be NF 3 . Sulfur fluoride may be SF 6 .

[0089] The first etching gas may be nitrogen fluoride.

[0090] The second etching gas may be oxygen gas.

[0091] In an embodiment, both the first etching gas and the second etching gas can be applied as atmosphere gases in the etching process to further increase the etching rate for the insulating layer 20.

[0092] In the etching process, the plasma power can be 1.5 kW or more and 3 kW or less. The plasma power may be 1.7 kW or more. The plasma power may be 2 kW or more. The plasma power may be 2.7 kW or less. The plasma power may be 2.5 kW or less. In such a case, an etching rate above a certain level for the insulating layer 20 can be ensured, and over-damage to the insulating layer 20 by plasma etching can be prevented.

[0093] In an embodiment, after completing one etching process, the etching mask 30 can be prevented from overheating through a stabilization process. Specifically, in the stabilization process, the supply of plasma power can be interrupted, and the atmospheric temperature in the stabilization process can be adjusted to be lower than the atmospheric temperature in the etching process.

[0094] The stabilization process can be performed until the atmospheric temperature, that is, the temperature inside the chamber reaches the target temperature. The target temperature may be a value 5°C or more lower than the maximum value of the atmospheric temperature in the etching process. The target temperature may be a value 10°C or more lower than the maximum value of the atmospheric temperature in the etching process. The target temperature may be a value 15°C or more lower than the maximum value of the atmospheric temperature in the etching process. Through this, it can help prevent deformation of the etching mask 30 and make it easier to peel off the etching mask 30 after patterning.

[0095] In the patterning step, the temperature of the etching mask 30 can be lowered by allowing a cooling fluid to pass around the outside of the etching chamber, particularly around the portion where the base substrate 100 in the chamber is disposed. The cooling fluid can pass around the portion where the base substrate 100 is disposed during the etching process and the stabilization process.

[0096] The cooling fluid may be a liquid or a gas. When the cooling fluid is a liquid, a pipe through which the cooling fluid flows can be disposed on the outer periphery of the etching chamber, and the cooling fluid can be made to flow through the pipe to cool the inside of the chamber. The cooling fluid may be water.

[0097] When the cooling fluid is a gas, similar to the case where the cooling fluid is a liquid, the gas can be made to flow through the pipe or the gas can be injected outside the chamber to cool the inside of the chamber. The cooling fluid may be air or a gas with low reactivity such as helium or nitrogen.

[0098] In the patterning step, taking one cycle of performing the etching process and the stabilization process, two or more cycles may be performed for each layer of the insulating layer 20. In the patterning step, three or more cycles may be performed for each layer of the insulating layer. In the patterning step, ten or less cycles may be performed for each layer of the insulating layer. In such a case, while adjusting the time taken for the patterning step, it can be useful for realizing delicate patterning of the insulating layer 20.

[0099] The patterned insulating layer 21 provided through the etching process may include a through hole 25 formed in the thickness direction of the insulating layer 20. The through hole 25 can spatially connect the upper surface side and the lower surface side of the insulating layer 20. An electrically conductive layer (not shown) may be disposed in the through hole 25. The electrically conductive layer disposed in the through hole 25 can electrically connect the electrically conductive layer (not shown) disposed on the insulating layer 20 and the electrically conductive layer (not shown) disposed under the insulating layer 20.

[0100] The diameter of the through hole 25 can be 3 μm to 50 μm. The diameter may be 5 μm or more. The diameter may be 7 μm or more. The diameter may be 40 μm or less. The diameter may be 30 μm or less. The diameter may be 20 μm or less. The diameter may be 15 μm or less. In such a case, an electrically conductive layer having a higher degree of integration can be stably formed.

[0101] In the patterning step, after the patterning of the insulating layer 20 is completed, the etching mask 30 can be removed. The etching mask 30 has a regulated bonding force with respect to the upper surface of the insulating layer 20, and the etching mask 30 can be physically easily peeled off and removed. Through this, since a separate complex process such as an etching process is not required for the removal of the etching mask 30, the convenience of the process is improved, and damage to the insulating layer 20 can be reduced to a certain level or less. Further, after the etching mask 30 is removed by the method as described above, the upper surface of the insulating layer 20 has a smooth surface with substantially no residue of the etching mask 30 remaining, so the electric conduction layer formed on the upper surface of the insulating layer 20 can have an excellent bonding force with respect to the insulating layer 20.

[0102] The removal of the etching mask 30 can be performed at an ambient temperature of 30°C to 60°C. The ambient temperature may be 35°C or higher. The ambient temperature may be 40°C or higher. The ambient temperature may be 55°C or lower. The ambient temperature may be 50°C or lower. In such a case, it is possible to effectively suppress the residue of the etching mask from remaining on the insulating layer.

[0103] Cleaning step The method for manufacturing the packaging substrate of the embodiment can further include a cleaning step of ultrasonically cleaning the base substrate 100 after the patterning step and before the manufacturing step.

[0104] In the process of plasma etching the insulating layer 20, particles caused by the insulating layer 20 may be generated. The particles may remain and be adsorbed on the through holes 25 having a fine pitch in the insulating layer 20 and on the upper surface side of the insulating layer 20, and may induce defects in the process of forming the electric conduction layer on the through holes 25 and the upper surface side of the insulating layer 20.

[0105] In the cleaning step of the embodiment, the base substrate 100 on which the particles remain can be immersed in a water tank, and ultrasonic vibration can be applied to the water tank to generate a cavitation phenomenon. Through this, the base substrate 100 is not excessively damaged in the cleaning step, and the particles can be easily removed.

[0106] In the cleaning step of the embodiment, the vibration frequency can be 30 kHz to 200 kHz. The vibration frequency may be 50 kHz or more. The vibration frequency may be 70 kHz or more. The vibration frequency may be 100 kHz or more. The vibration frequency may be 150 kHz or less. In such a case, even if the insulating layer 20 has a fine and complex pattern structure, the base substrate 100 can be effectively cleaned without being greatly damaged.

[0107] Manufacturing step FIG. 3 is a conceptual diagram for explaining a packaging substrate manufactured by the manufacturing method of the embodiment. With reference to FIG. 3, the manufacturing method of the packaging substrate of the embodiment will be described.

[0108] In the manufacturing step, a packaging substrate 200 can be manufactured from the base substrate 100 on which the patterned insulating layer 21 is formed.

[0109] In the manufacturing step, an electrical conduction layer 40 can be formed in a region where the insulating layer 20 is etched and removed, particularly in a through hole, through plasma etching to manufacture a first rewiring layer 50.

[0110] The electrical conduction layer 40 may be formed by a dry method or a wet method.

[0111] The dry method is a method of forming a seed layer by performing sputtering on the region where the electric conduction layer 40 is disposed, and forming the electric conduction layer 40 by plating the region where the seed layer is formed. When forming the seed layer, metals such as titanium, chromium, and nickel may be sputtered, or the metals and copper may be applied together for sputtering. Through sputtering, an anchor effect appears in which the surface where the electric conduction layer 40 is disposed interacts with the deposited metal particles, and the adhesion of the electric conduction layer 40 can be improved.

[0112] The wet method is a method of applying metal plating after treating a primer on the portion where formation of the electric conduction layer 40 is required. The primer can include a compound having a functional group such as an amine. Depending on the intended degree of adhesion, the primer can include both a compound having a functional group such as an amine and a silane coupling agent. When applying the silane coupling agent, after pretreating the surface to be primer-treated with the silane coupling agent, a compound having an amine group can be applied to the pretreated region to form a primer layer.

[0113] After forming the seed layer or the primer layer, metal can be plated to form the electric conduction layer 40. Copper plating may be applied when forming the electric conduction layer 40, but is not limited thereto. Before metal plating, the portion where formation of the electric conduction layer 40 in the seed layer or the primer layer is unnecessary can be inactivated, or the portion where formation of the electric conduction layer 40 is required can be activated, and then plating can be performed. As the activation or inactivation treatment method, light irradiation treatment such as irradiating a laser of a specific wavelength or chemical treatment may be applied. However, after performing metal plating without applying the activation or inactivation treatment, the electric conduction layer 40 can be etched and patterned according to a pre-designed shape.

[0114] When the patterned insulating layer 21 includes a via pattern, an electrically conductive layer 40 can be formed in the through hole in the insulating layer 20. The electrically conductive layer 40 can electrically connect an electrically conductive layer (not shown) located on the upper side with respect to the electrically conductive layer 40 and an electrically conductive layer (not shown) located on the lower side.

[0115] When the structure of the pre-designed first rewiring layer 50 is a multilayer structure, other patterned insulating layers (not shown) and electrically conductive layers (not shown) can be formed on the patterned insulating layer 21 and the electrically conductive layer 40. Other patterned insulating layers and electrically conductive layers disposed on the patterned insulating layer 21 and the electrically conductive layer 40 can be formed by the method described above.

[0116] When the first rewiring layer 50 has a multilayer structure, in the first rewiring layer 50, electrically conductive layers with smaller widths can be disposed as going upward. In the first rewiring layer 50, electrically conductive layers with thinner thicknesses can be disposed as going upward. In the first rewiring layer 50, electrically conductive layers with smaller pitches can be formed as going upward. Through this, the first rewiring layer 50 can form a stable electrical connection with a semiconductor element having a fine pattern.

[0117] The manufacturing step can further include a process of forming a second rewiring layer disposed under the core layer 10 as needed. The second rewiring layer may be a single-layer structure or a multilayer structure. The rewiring layer formed under the core layer 10 may be formed by the same method as the method described above.

[0118] The second rewiring layer may have a single-layer structure or a multilayer structure.

[0119] When the second rewiring layer has a multilayer structure, in the second rewiring layer, an electrical conduction layer with a wider width can be arranged as it goes downward. In the second rewiring layer, an electrical conduction layer with a greater thickness can be arranged as it goes downward. In the second rewiring layer, an electrical conduction layer with a larger pitch can be formed as it goes downward. Through this, the second rewiring layer can form a stable electrical connection with the main board where a wide or thick electrical conduction layer is formed.

[0120] In the manufacturing step, after forming a rewiring layer having a pre-designed structure on the upper side and / or the lower side of the core layer 10, the packaging substrate 200 can be provided.

[0121] If necessary, in the manufacturing step, upper terminals or the like can be additionally formed on the upper part and / or the side of the packaging substrate 200, and bumps can be additionally formed on the lower part of the packaging substrate 200. The bumps can be arranged in a predetermined form under the rewiring layer arranged under the core layer 10. Exemplarily, the bumps may be arranged on a part of the lower surface of the packaging substrate 200 so as to contact the main board or the like.

[0122] The manufactured packaging substrate The packaging substrate 200 manufactured by the manufacturing method of the packaging substrate of the embodiment can include the core layer 10 and the patterned insulating layer 21 arranged on the core layer 10.

[0123] The packaging substrate 200 can further include an electrical conduction layer (not shown) formed in contact with at least a part of the upper surface of the patterned insulating layer 21.

[0124] Explanation of the materials and structures of the core layer 10 and the patterned insulating layer 21 and the like is omitted because it overlaps with the above-described content.

[0125] The patterned insulating layer 21 may include a through hole (not shown) formed in the thickness direction of the insulating layer 20. An electrically conductive layer 40 may be formed in the through hole.

[0126] The electrically conductive layer formed in contact with at least a part of the upper surface of the patterned insulating layer 21 may be formed by the above-described dry method or wet method on the patterned insulating layer 21 and the electrically conductive layer.

[0127] In the packaging substrate 200 manufactured by the manufacturing method of the packaging substrate of the embodiment, the electrically conductive layer formed in contact with the upper surface of the patterned insulating layer 21 can have excellent bonding strength to the insulating layer 20. This is because after the patterning of the insulating layer is completed, the etching mask can be easily removed without substantially inducing damage or deformation of the patterned insulating layer 21, and it is considered that the etching mask does not substantially leave residues on the surface of the patterned insulating layer 21. Through this, it can help to maintain a smooth surface on the upper surface of the patterned insulating layer 21 even after the etching mask is removed.

[0128] The peel strength between the patterned insulating layer 21 and the electrically conductive layer is measured by the following method. After cutting the electrically conductive layer formed on the patterned insulating layer 21 into a length of 1 cm in width, a peel rate of 847 μm / s is applied using a UTM (Universal Testing Machine), and the peel strength is measured while peeling 3 cm of the electrically conductive layer from the insulating layer 20. The average value of the peel strength in the saturation section in the measured peel strength distribution is calculated, and this value is taken as the peel strength between the patterned insulating layer 21 and the electrically conductive layer.

[0129] The peel strength of the electrical conduction layer with respect to the upper surface of the patterned insulating layer 21 may be 200 gf / cm or more. The peel strength may be 250 gf / cm or more. The peel strength may be 300 gf / cm or more. The peel strength may be 320 gf / cm or more. The peel strength may be 500 gf / cm or less. In such a case, the electrical conduction layer can be stably fixed to the upper surface of the patterned insulating layer 21, and the manufactured packaging substrate 200 can have excellent electrical reliability.

[0130] The diameter of the through hole 25 included in the patterned insulating layer 21 can be 3 μm to 50 μm. The diameter may be 5 μm or more. The diameter may be 7 μm or more. The diameter may be 40 μm or less. The diameter may be 30 μm or less. The diameter may be 20 μm or less. The diameter may be 15 μm or less. In such a case, a through hole 25 pattern having a higher pattern density can be stably embodied in the insulating layer.

[0131] Hereinafter, the embodiments will be described more specifically through specific examples. The following examples are merely illustrative for helping the understanding of the embodiments, and the scope of the embodiments is not limited thereto.

[0132] Manufacturing Example: Manufacturing of a Packaging Substrate Example 1: An insulating layer was formed by vacuum laminating the Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Inc. on the upper surface of a glass plate SG7.8 of Corning Incorporated, and a base substrate was provided.

[0133] A resist composition, which is DRY FILM PHOTEC (RY series) of RESONAC Co., Ltd., was applied and cured on the insulating layer to form a resist layer having a thickness of 5 to 40 μm. The resist layer was exposed with an electron beam, and the exposed resist layer was developed to form an etching mask in which a large number of hole patterns having a diameter of 7 to 10 μm were formed.

[0134] The base substrate with the etching mask formed thereon was placed in an etching chamber, and the insulating layer was plasma-etched and patterned. During the plasma etching, a plasma power of 1.5 kW was applied, and NF 3 as the first etching gas was supplied at 150 sccm, and O 2 as the second etching gas was supplied at 150 sccm.

[0135] The plasma etching was performed 3 times in total, with each time lasting for 500 seconds. After each plasma etching, the etching was interrupted for 60 seconds. During the patterning of the insulating layer, helium gas was injected to the lower side of the etching chamber, and the temperature inside the chamber was controlled to be less than 120 °C.

[0136] After the patterning of the insulating layer was completed, the etching mask was peeled off in an atmosphere of 30 °C to 55 °C. The base substrate with the etching mask peeled off was immersed in a water-filled water tank, and then ultrasonic cleaning was performed for 300 seconds by applying a vibration frequency of 100 kHz.

[0137] After cleaning, sputtering was performed on the etched space in the insulating layer to form a titanium layer and a copper layer disposed on the titanium layer. Copper electroplating was performed on the copper layer to form an electrical conduction layer, and the packaging substrate was completed.

[0138] Example 2: A packaging substrate was manufactured under the same conditions as in Example 1, except that a vibration frequency of 50 kHz was applied during ultrasonic cleaning.

[0139] Example 3: A packaging substrate was manufactured under the same conditions as in Example 1, except that a vibration frequency of 130 kHz was applied during ultrasonic cleaning.

[0140] Comparative Example 1: A packaging substrate was manufactured under the same conditions as in Example 1, except that the cooling process through the injection of helium gas was not performed during the patterning process of the insulating layer.

[0141] Comparative Example 2: A packaging substrate was manufactured under the same conditions as in Example 1, except that ultrasonic cleaning was not performed after patterning of the insulating layer was completed.

[0142] Evaluation Example: Evaluation of Etching Mask Removal The upper surface of the patterned insulating layer for each of the examples and comparative examples was visually observed to check for the presence of remnants of the etching mask. If no such remnants were found, it was evaluated as Pass; if remnants were found, it was evaluated as Fail.

[0143] The measured values for each of the examples and comparative examples are shown in Table 1 below.

[0144] Evaluation Example: Evaluation of Cleaning In the packaging substrates for each of the examples and comparative examples, the through-holes in the patterned insulating layer were observed with an optical microscope to check for the presence of residual particles. If no such particles were found, it was evaluated as Pass; if particles were found, it was evaluated as Fail.

[0145] The measured values for each of the examples and comparative examples are shown in Table 1 below.

[0146] Evaluation Example: Evaluation of Peel Strength of Electric Conductive Layer In Examples 1 to 3 and Comparative Example 2, an additional electric conductive layer was formed on the patterned insulating layer. A titanium target was applied and sputtering was performed to form a titanium layer with a thickness of 50 nm. A copper target was applied on the titanium layer and sputtering was performed to form a copper layer with a thickness of 100 nm. Copper electroplating was performed on the copper layer to additionally form a copper layer with a thickness of 20 μm.

[0147] The peel strength of the electrically conductive layer with respect to the patterned insulating layer was measured by the following method. After cutting the electrically conductive layer formed on the patterned insulating layer into a length of 1 cm in width, a peel rate of 847 μm / s was applied using a UTM (Universal Testing Machine), and the peel strength was measured while peeling 3 cm of the electrically conductive layer from the insulating layer. In the distribution of the measured peel strength, the average value of the peel strength in the saturation interval was calculated, and this value was taken as the peel strength between the patterned insulating layer and the electrically conductive layer.

[0148] The measured values for each of the examples and comparative examples are shown in Table 1 below.

[0149]

Table 1

[0150] In the evaluation of the presence or absence of peeling in Table 1 above, Examples 1 to 3 were evaluated as Pass, while Comparative Example 1 was evaluated as Fail. This means that when the ambient temperature is adjusted within the range preset in the embodiment during the patterning step, the etching mask can be easily removed.

[0151] In the evaluation of cleaning, Examples 1 to 3 were evaluated as Pass, while Comparative Example 2 was evaluated as Fail. This means that through ultrasonic cleaning, the particles adsorbed in the through-holes in the patterned insulating layer can be easily removed.

[0152] In the evaluation of the peel strength, Examples 1 to 3 were evaluated as 250 gf / cm or more, while Comparative Example 2 was evaluated as 100 gf / cm or less. This is presumably because the remnants of the insulating layer generated by etching remain on the upper surface of the patterned insulating layer, preventing the bonding between the electrically conductive layer and the patterned insulating layer.

[0153] Although the preferred embodiments of the present invention have been described in detail above, the scope of the rights of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the appended claims also belong to the scope of the rights of the present invention.

Explanation of Reference Numerals

[0154] 100 Base substrate 10 Core layer 20 Insulating layer 21 Patterned insulating layer 22 Etching target region 25 Through hole 30 Etching mask 40 Electrically conductive layer 50 First rewiring layer 200 Packaging substrate

Claims

1. A preparation step of preparing a base substrate including a core layer and an insulating layer formed on the core layer; a patterning step of selectively plasma etching the insulating layer through an etching mask to form a patterned insulating layer; and a manufacturing step of manufacturing a packaging substrate from the base substrate on which the patterned insulating layer is formed, the etching mask comprises an organic compound; The method for manufacturing a packaging substrate, wherein the patterning step is performed at an atmospheric temperature of 120° C. or less.

2. The method for manufacturing a packaging substrate according to claim 1 , wherein in the patterning step, the etching mask is disposed in contact with an upper surface of the insulating layer.

3. the insulating layer includes an area to be etched; The patterning step includes an etching process for etching a portion of the insulating layer in the etching target region, and a stabilization process for lowering an atmosphere temperature of the patterning step, 2. The method for manufacturing a packaging substrate according to claim 1, wherein in the patterning step, a cycle consisting of the etching process and the stabilization process is performed two or more times for each of the insulating layers.

4. The method of claim 3, wherein the etching process is performed for 200 to 700 seconds per cycle.

5. The etching process is performed in an atmosphere including a first etching gas and a second etching gas, the first etching gas is a fluorine-based gas; The method for manufacturing a packaging substrate according to claim 3 , wherein the second etching gas is oxygen gas.

6. The method for manufacturing a packaging substrate according to claim 3, wherein the plasma power in the etching process is 1.5 kW or more and 3 kW or less.

7. The method for manufacturing a packaging substrate according to claim 1, wherein the etching mask has a thickness of 5 μm to 40 μm.

8. After completing the patterning step, and before the manufacturing step, the method further includes a cleaning step of ultrasonically cleaning the base substrate; The method for manufacturing a packaging substrate according to claim 1 , wherein the vibration frequency in the cleaning step is 30 kHz to 200 kHz.

9. the patterned insulating layer includes a through hole formed in a thickness direction of the insulating layer, The method for manufacturing a packaging substrate according to claim 1 , wherein the through hole has a diameter of 3 μm to 50 μm.

10. the packaging substrate includes the core layer and the patterned insulating layer disposed on the core layer; the packaging substrate includes an electrically conductive layer at least partially formed on an upper surface of the patterned insulating layer; The method for manufacturing a packaging substrate according to claim 1 , wherein a peel strength of the electrically conductive layer with respect to the upper surface of the patterned insulating layer is 200 gf / cm or more.

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