Chip resistor and method for manufacturing the same and electronic circuit device

Abstract

To provide a chip resistor that can improve the reliability of an electronic circuit device including the chip resistor.SOLUTION: A chip resistor 1 has an insulating substrate 10, a resistive element layer 20, a first electrode 30, and a second electrode 40. The insulating substrate 10 has a front surface 11, a back surface 12, a first end surface 13, and a second end surface 14. The first electrode 30 includes a first end electrode 36 and a first back surface electrode 33. The second electrode 40 includes a second end electrode 46 and a second back surface electrode 43. The first end surface 13 bulges out from a connection 15b between the back surface 12 and the first end surface 13. The second end surface 14 bulges out from a connection 16b between the back surface 12 and the second end surface 14.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a chip resistor, a method for manufacturing the same, and an electronic circuit device.

Background Art

[0002] International Publication No. 2020 / 189217 (Patent Document 1) discloses a chip resistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] An object of the present disclosure is to provide a chip resistor capable of improving the reliability of an electronic circuit device including the chip resistor.

[0005] The chip resistor of the present disclosure includes an insulating substrate, a resistor layer, a first electrode, and a second electrode. The insulating substrate has a front surface, a back surface opposite to the front surface, a first end surface, and a second end surface opposite to the first end surface. The first end surface and the second end surface are each connected to the front surface and the back surface. The resistor layer is disposed on the front surface. The first electrode and the second electrode are spaced apart from each other in a direction in which the first end surface and the second end surface are spaced apart from each other. The first electrode includes a first front surface electrode, a first end surface electrode, and a first back surface electrode. The first front surface electrode is disposed on the front surface and is connected to the resistor layer. The first end surface electrode is disposed on the first end surface and is connected to the first front surface electrode. The first back surface electrode is disposed on the back surface and is connected to the first end surface electrode. The second electrode includes a second front surface electrode, a second end surface electrode, and a second back surface electrode. The second front surface electrode is disposed on the front surface and is connected to the resistor layer. The second end surface electrode is disposed on the second end surface and is connected to the second front surface electrode. The second back surface electrode is disposed on the back surface and is connected to the second end surface electrode. The first end surface bulges from a first connection portion between the back surface and the first end surface. The second end surface bulges from a second connection portion between the back surface and the second end surface.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

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Figure 10

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Figure 12

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Figure 15

[0007] Details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be arbitrarily combined.

[0008] With reference to FIGS. 1 to 4, the chip resistor 1 according to the embodiment will be described. The chip resistor 1 mainly includes an insulating substrate 10, a resistor layer 20, a first electrode 30, and a second electrode 40. The chip resistor 1 may further include a protective layer 24. In FIGS. 1 and 4, for convenience, a part of the first electrode 30, a part of the second electrode 40, and the protective layer 24 are not shown.

[0009] The insulating substrate 10 is formed of an insulating material such as alumina (Al 2 O 3 2O3). The insulating substrate 10 has a front surface 11, a back surface 12 on the side opposite to the front surface 11, a first end surface 13, and a second end surface 14 on the side opposite to the first end surface 13.

[0010] The front surface 11 and the back surface 12 each extend along the x direction and the y direction perpendicular to the x direction. The x direction is the longitudinal direction of the insulating substrate 10. The y direction is the short side direction of the insulating substrate 10. The front surface 11 and the back surface 12 are separated from each other in the z direction perpendicular to the x direction and the y direction. The z direction is the thickness direction of the insulating substrate 10. The front surface 11 and the back surface 12 are both end faces in the thickness direction of the insulating substrate 10. As shown in FIG. 5, when the chip resistor 1 is mounted on the circuit board 50, the back surface 12 faces the circuit board 50. The thickness t of the insulating substrate 10 is the distance between the front surface 11 and the back surface 12, and is, for example, 0.5 mm or more and 1.0 mm or less.

[0011] The first end surface 13 and the second end surface 14 are each connected to the front surface 11 and the back surface 12. The first end surface 13 and the second end surface 14 each extend along the y direction and the z direction. The first end surface 13 and the second end surface 14 are, for example, both end faces in the longitudinal direction of the insulating substrate 10.

[0012] The first end face 13 bulges from the connection portion 15a between the front face 11 and the first end face 13. The first end face 13 bulges from the connection portion 15b between the back face 12 and the first end face 13. The second end face 14 bulges from the connection portion 16a between the front face 11 and the second end face 14. The second end face 14 bulges from the connection portion 16b between the back face 12 and the second end face 14. Referring to FIG. 3, the first bulge angle α of the first end face 13 at the connection portion 15b is 20° or more and 40° or less. The first bulge angle α is the angle between the tangential direction of the first end face 13 at the connection portion 15b and the thickness direction (z direction) of the insulating substrate. The second bulge angle β of the second end face 14 at the connection portion 16b is 20° or more and 40° or less. The second bulge angle β is the angle between the tangential direction of the second end face 14 at the connection portion 16b and the thickness direction (z direction) of the insulating substrate.

[0013] The ratio h of the first bulge height h of the first end face 13 to the thickness t of the insulating substrate 10 1 of h 1 / t is, for example, 0.05 or more and 0.17 or less. The ratio h of the second bulge height h of the first end face 13 to the thickness t of the insulating substrate 10 2 of h 2 / t is, for example, 0.05 or more and 0.17 or less. The thickness t of the insulating substrate 10 is the distance between the front face 11 and the back face 12. The first bulge height h of the first end face 13 1 is the maximum height of the first end face 13 from the first virtual plane connecting the connection portion 15b and the connection portion 15a. The second bulge height h of the second end face 14 2 is the maximum height of the second end face 14 from the second virtual plane connecting the connection portion 16b and the connection portion 16b.

[0014] The length L of the insulating substrate 10 in the longitudinal direction (x-direction) of the insulating substrate 10 is, for example, 3.2 mm or more. The length L may be 4.0 mm or more, may be 5.0 mm or more, or may be 6.0 mm or more. The length L of the insulating substrate 10 is the length of the back surface 12 in the direction (x-direction) in which the first end surface 13 and the second end surface 14 face each other. In other words, the length L of the insulating substrate 10 is the distance between the connection portion 15b and the connection portion 16b in the direction (x-direction) in which the first end surface 13 and the second end surface 14 face each other.

[0015] The resistor layer 20 has, for example, a function of limiting current or a function of detecting current. The resistor layer 20 is disposed on the front surface 11 of the insulating substrate 10. The resistor layer 20 is formed of, for example, a conductive material containing conductive particles such as ruthenium oxide (RuO 2 ) or a silver-palladium alloy and glass.

[0016] The protective layer 24 may have a two-layer structure. The protective layer 24 includes, for example, a first insulating protective layer 25 and a second insulating protective layer 26.

[0017] The first insulating protective layer 25 covers the resistor layer 20 and protects the resistor layer 20. The first insulating protective layer 25 may further cover a part of the first front surface electrode 31 of the first electrode 30 and a part of the second front surface electrode 41 of the second electrode 40. The first insulating protective layer 25 is formed of an insulating material such as glass, for example.

[0018] The second insulating protective layer 26 covers the first insulating protective layer 25. The second insulating protective layer 26 may further cover a part of the first front surface electrode 31 of the first electrode 30 and a part of the second front surface electrode 41 of the second electrode 40. The second insulating protective layer 26 is formed of an insulating resin such as an epoxy resin, for example.

[0019] The first electrode 30 and the second electrode 40 are spaced apart from each other in the direction (x direction) in which the first end face 13 and the second end face 14 are spaced apart from each other. The first electrode 30 is disposed on the first end face 13 side of the insulating substrate 10. The first electrode 30 is closer to the first end face 13 than the second electrode 40. The second electrode 40 is disposed on the second end face 14 side of the insulating substrate 10. The second electrode 40 is closer to the second end face 14 than the first electrode 30. The first electrode 30 and the second electrode 40 are connected to the resistor layer 20.

[0020] The first electrode 30 includes a first front surface electrode 31, a first back surface electrode 33, and a first end face electrode 36. The first electrode 30 may further include a first auxiliary electrode 32, a first inner plating film 37, and a first outer plating film 38.

[0021] The first front surface electrode 31 is disposed on the front surface 11 of the insulating substrate 10. The first front surface electrode 31 is disposed on a portion of the front surface 11 on the first end face 13 side. The first front surface electrode 31 is disposed on a portion of the front surface 11 closer to the first end face 13. The first front surface electrode 31 is connected to the resistor layer 20. The first front surface electrode 31 is formed of a conductive material including, for example, metal particles (e.g., silver particles) and glass.

[0022] The first auxiliary electrode 32 is disposed on the first front surface electrode 31 and is connected to the first front surface electrode 31. The first auxiliary electrode 32 is formed of a conductive material including, for example, a binder resin (e.g., an epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin.

[0023] The first back surface electrode 33 is disposed on the back surface 12 of the insulating substrate 10. The first back surface electrode 33 is disposed on a portion of the back surface 12 on the first end face 13 side. The first back surface electrode 33 is disposed on a portion of the back surface 12 closer to the first end face 13. The first back surface electrode 33 may have a two-layer structure. The first back surface electrode 33 includes, for example, a first insulating resin layer 34 and a first conductive layer 35.

[0024] The first insulating resin layer 34 is disposed on the back surface 12 of the insulating substrate 10. The first insulating resin layer 34 is formed of an insulating resin such as, for example, an epoxy resin. The first insulating resin layer 34 improves the adhesive strength of the first back surface electrode 33 to the insulating substrate 10.

[0025] The first conductive layer 35 is disposed on the first insulating resin layer 34. The first conductive layer 35 covers the first insulating resin layer 34. The first conductive layer 35 is formed of a conductive material containing, for example, a binder resin (e.g., an epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin.

[0026] The first end face electrode 36 is disposed on the first end face 13 of the insulating substrate 10. The first end face electrode 36 is connected to the first front face electrode 31 and the first back face electrode 33, and electrically connects the first front face electrode 31 and the first back face electrode 33 to each other. The first end face electrode 36 may also be disposed on the first auxiliary electrode 32. The first end face electrode 36 is formed of, for example, a Ni-Cr alloy. The first end face electrode 36 is formed by a sputtering method.

[0027] The first inner plating film 37 is disposed on the first auxiliary electrode 32, on the first end face electrode 36, and on the first back face electrode 33 (the first conductive layer 35). The first inner plating film 37 covers the first auxiliary electrode 32, the first end face electrode 36, and the first back face electrode 33 (the first conductive layer 35). The first inner plating film 37 protects the first front face electrode 31, the first auxiliary electrode 32, the first end face electrode 36, and the first back face electrode 33 from heat and shock. The first inner plating film 37 is, for example, a nickel plating layer.

[0028] The first outer plating film 38 is disposed on the first inner plating film 37. The first outer plating film 38 covers the first inner plating film 37. The first outer plating film 38 is formed of a material to which a joining member such as solder easily adheres, compared with the first inner plating film 37. The first outer plating film 38 is, for example, a tin plating layer. As shown in FIG. 5, when mounting the chip resistor 1 on the circuit board 50, the first outer plating film 38 is joined to the land pattern 52 of the circuit board 50 via the joining member 54.

[0029] The second electrode 40 includes a second front surface electrode 41, a second back surface electrode 43, and a second end surface electrode 46. The second electrode 40 may further include a second auxiliary electrode 42, a second inner plating film 47, and a second outer plating film 48.

[0030] The second front surface electrode 41 is disposed on the front surface 11 of the insulating substrate 10. The second front surface electrode 41 is disposed on a portion of the front surface 11 on the second end surface 14 side. The second front surface electrode 41 is disposed on a portion of the front surface 11 proximal to the second end surface 14. The second front surface electrode 41 is connected to the resistor layer 20. The second front surface electrode 41 is formed of a conductive material including, for example, metal particles (e.g., silver particles) and glass.

[0031] The second auxiliary electrode 42 is disposed on the second front surface electrode 41 and is connected to the second front surface electrode 41. The second auxiliary electrode 42 is formed of a conductive material including, for example, a binder resin (e.g., an epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin.

[0032] The second back surface electrode 43 is disposed on the back surface 12 of the insulating substrate 10. The second back surface electrode 43 is disposed on a portion of the back surface 12 on the second end surface 14 side. The second back surface electrode 43 is disposed on a portion of the back surface 12 proximal to the second end surface 14. The second back surface electrode 43 may have a two-layer structure. The second back surface electrode 43 includes, for example, a second insulating resin layer 44 and a second conductive layer 45.

[0033] The second insulating resin layer 44 is disposed on the back surface 12 of the insulating substrate 10. The second insulating resin layer 44 is formed of an insulating resin such as, for example, an epoxy resin. The second insulating resin layer 44 improves the adhesive strength of the second back surface electrode 43 to the insulating substrate 10.

[0034] The second conductive layer 45 is disposed on the second insulating resin layer 44. The second conductive layer 45 covers the second insulating resin layer 44. The second conductive layer 45 is formed of a conductive material containing, for example, a binder resin (for example, an epoxy resin) and metal particles (for example, silver particles) dispersed in the binder resin.

[0035] The second end face electrode 46 is disposed on the second end face 14 of the insulating substrate 10. The second end face electrode 46 is connected to the second front face electrode 41 and the second back face electrode 43, and electrically connects the second front face electrode 41 and the second back face electrode 43 to each other. The second end face electrode 46 may also be disposed on the second auxiliary electrode 42. The second end face electrode 46 is formed of, for example, a Ni-Cr alloy. The second end face electrode 46 is formed by a sputtering method.

[0036] The second inner plating film 47 is disposed on the second auxiliary electrode 42, on the second end face electrode 46, and on the second back face electrode 43 (the second conductive layer 45). The second inner plating film 47 covers the second auxiliary electrode 42, the second end face electrode 46, and the second back face electrode 43 (the second conductive layer 45). The second inner plating film 47 protects the second front face electrode 41, the second auxiliary electrode 42, the second end face electrode 46, and the second back face electrode 43 from heat and shock. The second inner plating film 47 is, for example, a nickel plating layer.

[0037] The second outer plating film 48 is disposed on the second inner plating film 47. The second outer plating film 48 covers the second inner plating film 47. The second outer plating film 48 is formed of a material to which a joining member such as solder easily adheres, compared with the second inner plating film 47. The second outer plating film 48 is, for example, a tin plating layer. As shown in FIG. 5, when mounting the chip resistor 1 on the circuit board 50, the second outer plating film 48 is joined to the land pattern 53 of the circuit board 50 via the joining member 55.

[0038] Referring to FIG. 5, the electronic circuit device 2 of the present embodiment will be described. The electronic circuit device 2 includes a chip resistor 1, a circuit board 50, a joining member 54, and a joining member 55. The circuit board 50 includes an insulating circuit board 51, a land pattern 52, and a land pattern 53 spaced apart from the land pattern 52. The first back electrode 33 is joined to the land pattern 52 using a joining member 54 such as solder. The second back electrode 43 is joined to the land pattern 53 using a joining member 55 such as solder.

[0039] A method for manufacturing the chip resistor 1 of the present embodiment will be described.

[0040] The method for manufacturing the chip resistor 1 of the present embodiment includes preparing an insulating substrate 10, forming a resistor layer 20 on the front surface 11 of the insulating substrate 10, and forming a protective layer 24 on the resistor layer 20. Forming the protective layer 24 includes forming a first insulating protective layer 25 on the resistor layer 20 and forming a second insulating protective layer 26 on the first insulating protective layer 25.

[0041] The manufacturing method of the chip resistor according to this embodiment includes forming a first electrode 30 and a second electrode 40. The first electrode 30 and the second electrode 40 are spaced apart from each other in a direction (x direction) in which the first end face 13 and the second end face 14 are spaced apart from each other. Forming the first electrode 30 and the second electrode 40 includes forming a first back surface electrode 33 and a second back surface electrode 43 on the back surface 12, forming a first front surface electrode 31 and a second front surface electrode 41 on the front surface 11, forming a first auxiliary electrode 32 and a second auxiliary electrode 42, forming a first end face electrode 36 and a second end face electrode 46 on the first end face 13 and the second end face 14 respectively, forming a first inner plating film 37 and a second inner plating film 47, and forming a first outer plating film 38 and a second outer plating film 48.

[0042] With reference to FIGS. 2, 3, 6 to 13, an example of the manufacturing method of the chip resistor 1 according to this embodiment will be described.

[0043] With reference to FIG. 6, an insulating substrate 10 is prepared. The insulating substrate 10 is formed of an insulating material such as alumina, for example. The insulating substrate has a front surface 11, a back surface 12 on the side opposite to the front surface 11, a first end face 13, and a second end face 14 on the side opposite to the first end face 13. The first end face 13 and the second end face 14 are each connected to the front surface 11 and the back surface 12.

[0044] The first end face 13 bulges from a connection portion 15b between the back surface 12 and the first end face 13. The second end face 14 bulges from a connection portion 16b between the back surface 12 and the second end face 14. With reference to FIG. 3, a first bulging angle α of the first end face 13 at the connection portion 15b is 20° or more and 40° or less. A second bulging angle β of the second end face 14 at the connection portion 16b is 20° or more and 40° or less. The ratio h 1 of the first bulging height h 1 of the first end face 13 to the thickness t of the insulating substrate is 0.05 or more and 0.17 or less. The ratio h 2 of the second bulging height h 2 / t is 0.05 or more and 0.17 or less. The insulating substrate 10 is formed, for example, by molding alumina powder using a mold and then sintering the molded alumina powder.

[0045] Referring to FIG. 7, a first front surface electrode 31 and a second front surface electrode 41 are formed on the front surface 11 of the insulating substrate 10. The first front surface electrode 31 and the second front surface electrode 41 are formed, for example, by printing a paste containing metal particles (for example, silver particles) and glass frit on the front surface 11 and then baking it.

[0046] Referring to FIG. 8, a first back surface electrode 33 and a second back surface electrode 43 are formed on the back surface 12 of the insulating substrate 10. For example, by printing and curing a resin paste on the back surface 12, a first insulating resin layer 34 and a second insulating resin layer 44 are formed on the back surface 12. Then, a paste (for example, a silver paste) containing a binder resin (for example, an epoxy resin) and metal particles (for example, silver particles) dispersed in the binder resin is printed and cured on the first insulating resin layer 34, the second insulating resin layer 44, and the back surface 12, thereby forming a first conductive layer 35 and a second conductive layer 45. In this way, the first back surface electrode 33 and the second back surface electrode 43 are formed on the back surface 12.

[0047] Referring to FIG. 9, a resistor layer 20 is formed on the front surface 11 of the insulating substrate 10. For example, a paste containing a glass frit in an electrical resistance material such as ruthenium oxide (RuO 2 ) or a silver - palladium alloy is printed and baked on the front surface 11. In this way, the resistor layer 20 is formed. The resistor layer 20 is connected to the first front surface electrode 31 and the second front surface electrode 41.

[0048] Referring to FIGS. 10 and 11, a protective layer 24 is formed on the resistor layer 20. For example, a paste containing glass is printed and fired on the resistor layer 20, the first front surface electrode 31, and the second front surface electrode 41 to form a first insulating protective layer 25 (see FIG. 10). Then, a paste containing an epoxy resin is printed and cured on the first insulating protective layer 25, the first front surface electrode 31, and the second front surface electrode 41 to form a second insulating protective layer 26 (see FIG. 11).

[0049] Referring to FIG. 12, a first auxiliary electrode 32 and a second auxiliary electrode 42 are formed on the first front surface electrode 31 and the second front surface electrode 41, respectively. For example, a paste (e.g., a silver paste) containing a binder resin (e.g., an epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin is applied and cured on the first front surface electrode 31 and the second front surface electrode 41 to form the first auxiliary electrode 32 and the second auxiliary electrode 42.

[0050] Referring to FIG. 13, a first end face electrode 36 and a second end face electrode 46 are formed on the first end face 13 and the second end face 14, respectively, by sputtering. The first end face electrode 36 and the second end face electrode 46 are formed of, for example, a Ni—Cr alloy.

[0051] Then, a first inner plating film 37 and a second inner plating film 47 (see FIG. 2) are formed by plating. The first inner plating film 37 is formed on the first auxiliary electrode 32, the first end face electrode 36, and the first back surface electrode 33 (the first conductive layer 35) and covers the first auxiliary electrode 32, the first end face electrode 36, and the first back surface electrode 33 (the first conductive layer 35). The second inner plating film 47 is formed on the second auxiliary electrode 42, the second end face electrode 46, and the second back surface electrode 43 (the second conductive layer 45) and covers the second auxiliary electrode 42, the second end face electrode 46, and the second back surface electrode 43 (the second conductive layer 45). The first inner plating film 37 and the second inner plating film 47 are, for example, nickel plating layers.

[0052] Then, by means of plating, a first outer plating film 38 and a second outer plating film 48 (see FIG. 2) are formed. The first outer plating film 38 is formed on the first inner plating film 37 and covers the first inner plating film 37. The second outer plating film 48 is formed on the second inner plating film 47 and covers the second inner plating film 47. The first outer plating film 38 and the second outer plating film 48 are, for example, tin plating layers. Thus, the chip resistor 1 shown in FIGS. 1 to 4 is obtained.

[0053] With reference to FIGS. 14 and 15, the operation of the chip resistor 1 of the present embodiment will be described while comparing it with the chip resistor of the first comparative example which is an example of the present embodiment.

[0054] The chip resistor of the first comparative example is configured in the same manner as the chip resistor 1 of the present embodiment, but is different from the chip resistor 1 of the present embodiment in that the first end face 13 and the second end face 14 are not swollen and are flat surfaces. In the example and the first comparative example, the length L of the insulating substrate 10 is 3.2 mm. FIG. 14 shows the stress distribution of the joining member 55 obtained by CAE (Computer Aided Engineering) analysis when the chip resistor of the first comparative example is joined to the circuit board 50 using the joining members 54 and 55 and the temperature of the chip resistor is raised to 155°C. FIG. 15 shows the stress distribution of the joining member 55 obtained by CAE analysis when the chip resistor 1 of the example is joined to the circuit board 50 using the joining members 54 and 55 and the temperature of the chip resistor 1 is raised to 155°C.

[0055] In the first comparative example, the angle between the back surface 12 of the insulating substrate 10 and the second end face 14 is 90°. Therefore, due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50, the thermal stress applied to the joining member 55 near the connection portion 16b between the back surface 12 and the second end face 14 increases. Cracks are likely to occur in the joining member 55 near the connection portion 16b.

[0056] In contrast, in the embodiment, the second end face 14 bulges from the connection portion 16b between the back face 12 and the second end face 14. For example, in the embodiment, the first bulge angle α is 20°, the second bulge angle β is 20°, and the ratio h 1 / t is 0.05, and the ratio h 2 / t is 0.05. The angle between the tangent line of the second end face 14 at the connection portion 16b and the back face 12 increases to form an obtuse angle. Therefore, due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50, the thermal stress applied to the bonding member 55 near the connection portion 16b between the back face 12 and the second end face 14 decreases. The occurrence of cracks in the bonding member 55 near the connection portion 16b can be suppressed. For the same reason, the occurrence of cracks in the bonding member 54 near the connection portion 15b can be suppressed. The chip resistor 1 of the present embodiment can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0057] While comparing with the chip resistor of the first comparative example and the chip resistor of the second comparative example, a further effect of the chip resistor 1 of the present embodiment will be described. The chip resistor of the second comparative example has the same structure as the chip resistor of the first comparative example, but the chip resistor of the second comparative example includes a first end face electrode 36 and a second end face electrode 46 formed by the dip coating method.

[0058] The first end face electrode 36 and the second end face electrode 46 of the chip resistor 1 of the present embodiment are formed by the sputtering method. Therefore, the cost of the chip resistor 1 of the present embodiment can be made lower than the cost of the chip resistor of the second comparative example.

[0059] In the chip resistor of the first comparative example, the first end face electrode 36 and the second end face electrode 46 are formed by a sputtering method, while in the chip resistor of the second comparative example, the first end face electrode 36 and the second end face electrode 46 are formed by a dip coating method. Therefore, in the chip resistor of the first comparative example, cracks are more likely to occur in the bonding member 54 near the connection portion 15b and the bonding member 55 near the connection portion 16b than in the chip resistor of the second comparative example. However, in the chip resistor 1 of the present embodiment, the first end face 13 bulges from the connection portion 15b, and the second end face 14 bulges from the connection portion 16b. Therefore, even though the first end face electrode 36 and the second end face electrode 46 are formed by a sputtering method, the occurrence of cracks in the bonding member 54 near the connection portion 15b and the bonding member 55 near the connection portion 16b can be suppressed. The chip resistor 1 of the present embodiment can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0060] The effects of the chip resistor 1 of the present embodiment will be described.

[0061] The chip resistor 1 of the present embodiment includes an insulating substrate 10, a resistor layer 20, a first electrode 30, and a second electrode 40. The insulating substrate 10 has a front surface 11, a back surface 12 opposite to the front surface 11, a first end face 13, and a second end face 14 opposite to the first end face 13. The first end face 13 and the second end face 14 are each connected to the front surface 11 and the back surface 12. The resistor layer 20 is disposed on the front surface 11. The first electrode 30 and the second electrode 40 are spaced apart from each other in a direction in which the first end face 13 and the second end face 14 are spaced apart from each other. The first electrode 30 includes a first front surface electrode 31, a first end face electrode 36, and a first back surface electrode 33. The first front surface electrode 31 is disposed on the front surface 11 and is connected to the resistor layer 20. The first end face electrode 36 is disposed on the first end face 13 and is connected to the first front surface electrode 31. The first back surface electrode 33 is disposed on the back surface 12 and is connected to the first end face electrode 36. The second electrode 40 includes a second front surface electrode 41, a second end face electrode 46, and a second back surface electrode 43. The second front surface electrode 41 is disposed on the front surface 11 and is connected to the resistor layer 20. The second end face electrode 46 is disposed on the second end face 14 and is connected to the second front surface electrode 41. The second back surface electrode 43 is disposed on the back surface 12 and is connected to the second end face electrode 46. The first end face 13 bulges from a first connection portion (connection portion 15b) between the back surface 12 and the first end face 13. The second end face 14 bulges from a second connection portion (connection portion 16b) between the back surface 12 and the second end face 14.

[0062] Therefore, the thermal stress applied to the bonding member 54 near the first connection portion (connection portion 15b) and the bonding member 55 near the second connection portion (connection portion 16b) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 is reduced. The occurrence of cracks in the bonding member 54 near the first connection portion and the bonding member 55 near the second connection portion can be suppressed. The chip resistor 1 of the present embodiment can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0063] In the chip resistor 1 of the present embodiment, the first bulge angle α of the first end face 13 at the first connection portion (connection portion 15b) is 20° or more. The second bulge angle β of the second end face 14 at the second connection portion (connection portion 16b) is 20° or more.

[0064] Therefore, the thermal stress applied to the bonding member 54 near the first connection portion (connection portion 15b) and the bonding member 55 near the second connection portion (connection portion 16b) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 decreases. The occurrence of cracks in the bonding member 54 near the first connection portion and the bonding member 55 near the second connection portion can be suppressed. The chip resistor 1 of the present embodiment can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0065] In the chip resistor 1 of the present embodiment, the ratio h of the first bulge height h of the first end face 13 to the thickness t of the insulating substrate 10 1 of h 1 / t is 0.05 or more. The ratio h of the second bulge height h of the first end face 13 to the thickness t of the insulating substrate 10 2 of h 2 / t is 0.05 or more. The thickness t of the insulating substrate 10 is the distance between the front surface 11 and the back surface 12. The first bulge height h of the first end face 13 1 is the maximum height of the first end face 13 from the first virtual plane connecting the first connection portion (connection portion 15b), the front surface 11, and the third connection portion (connection portion 15a) of the first end face 13. The second bulge height h of the second end face 14 2 is the maximum height of the second end face 14 from the second virtual plane connecting the second connection portion (connection portion 16b), the front surface 11, and the fourth connection portion (connection portion 16a) of the second end face 14.

[0066] Therefore, due to the difference between the coefficient of thermal expansion of the chip resistor 1 and that of the circuit board 50, the thermal stress applied to the bonding member 54 near the first connection portion (connection portion 15b) and the bonding member 55 near the second connection portion (connection portion 16b) decreases. The occurrence of cracks in the bonding member 54 near the first connection portion and the bonding member 55 near the second connection portion can be suppressed. The chip resistor 1 of the present embodiment can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0067] In the chip resistor 1 of the present embodiment, the distance (length L of the insulating substrate 10) between the first connection portion (connection portion 15b) and the second connection portion (connection portion 16b) is 3.2 mm or more.

[0068] When the distance (length L of the insulating substrate 10) between the first connection portion (connection portion 15b) and the second connection portion (connection portion 16b) increases, the thermal stress applied to the bonding members 54 and 55 due to the difference between the coefficient of thermal expansion of the chip resistor 1 and that of the circuit board 50 increases. However, in the chip resistor 1 of the present embodiment, the first end face 13 bulges from the first connection portion, and the second end face 14 bulges from the second connection portion. Therefore, even when the distance (length L of the insulating substrate 10) between the first connection portion and the second connection portion increases, the thermal stress applied to the bonding member 54 near the first connection portion and the bonding member 55 near the second connection portion due to the difference between the coefficient of thermal expansion of the chip resistor 1 and that of the circuit board 50 decreases. The occurrence of cracks in the bonding member 54 near the first connection portion and the bonding member 55 near the second connection portion can be suppressed. The chip resistor 1 of the present embodiment can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0069] In the chip resistor 1 of the present embodiment, the first back surface electrode 33 and the second back surface electrode 43 each include an insulating resin layer (first insulating resin layer 34, second insulating resin layer 44) and a conductive layer (first conductive layer 35, second conductive layer 45). The insulating resin layer is disposed on the back surface 12. The conductive layer is disposed on the insulating resin layer. The conductive layer is formed of a conductive material including a binder resin and metal particles dispersed in the binder resin.

[0070] The insulating resin layers (the first insulating resin layer 34 and the second insulating resin layer 44) improve the adhesion strength of the first back surface electrode 33 and the second back surface electrode 43 to the insulating substrate 10. The conductive layers (the first conductive layer 35 and the second conductive layer 45) of the present embodiment have a lower Young's modulus than the conductive layers formed of a conductive material containing glass and metal particles. Therefore, the thermal stress applied to the joining members 54 near the first connection portion (connection portion 15b) and the joining members 55 near the second connection portion (connection portion 16b) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 is reduced. Cracks can be suppressed from occurring in the joining members 54 near the first connection portion and the joining members 55 near the second connection portion. The chip resistor 1 of the present embodiment can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0071] The manufacturing method of the chip resistor 1 according to the present embodiment includes preparing an insulating substrate 10. The insulating substrate 10 has a front surface 11, a back surface 12 opposite to the front surface 11, a first end surface 13, and a second end surface 14 opposite to the first end surface 13. The first end surface 13 and the second end surface 14 are each connected to the front surface 11 and the back surface 12. The first end surface 13 bulges from a first connection portion (connection portion 15b) between the back surface 12 and the first end surface 13. The second end surface 14 bulges from a second connection portion (connection portion 16b) between the back surface 12 and the second end surface 14. The manufacturing method of the chip resistor 1 according to the present embodiment includes forming a resistor layer 20 on the front surface 11 and forming a first electrode 30 and a second electrode 40. The first electrode 30 and the second electrode 40 are spaced apart from each other in a direction in which the first end surface 13 and the second end surface 14 are spaced apart from each other. The first electrode 30 includes a first front surface electrode 31, a first end surface electrode 36, and a first back surface electrode 33. The first front surface electrode 31 is disposed on the front surface 11 and is connected to the resistor layer 20. The first end surface electrode 36 is disposed on the first end surface 13 and is connected to the first front surface electrode 31. The first back surface electrode 33 is disposed on the back surface 12 and is connected to the first end surface electrode 36. The second electrode 40 includes a second front surface electrode 41, a second end surface electrode 46, and a second back surface electrode 43. The second front surface electrode 41 is disposed on the front surface 11 and is connected to the resistor layer 20. The second end surface electrode 46 is disposed on the second end surface 14 and is connected to the second front surface electrode 41. The second back surface electrode 43 is disposed on the back surface 12 and is connected to the second end surface electrode 46.

[0072] Therefore, the thermal stress applied to the bonding member 54 near the first connection portion (connection portion 15b) and the bonding member 55 near the second connection portion (connection portion 16b) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 is reduced. The occurrence of cracks in the bonding member 54 near the first connection portion and the bonding member 55 near the second connection portion can be suppressed. According to the manufacturing method of the chip resistor 1 of the present embodiment, it is possible to provide a chip resistor 1 that can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0073] In the manufacturing method of the chip resistor 1 according to the present embodiment, forming the first electrode 30 and the second electrode 40 includes forming the first end face electrode 36 on the first end face 13 and forming the second end face electrode 46 on the second end face 14 by a sputtering method.

[0074] According to the manufacturing method of the chip resistor 1 of the present embodiment, it is possible to provide a chip resistor 1 that can improve the reliability of the electronic circuit device 2 including the chip resistor 1 while reducing the cost of the chip resistor 1.

[0075] In the manufacturing method of the chip resistor 1 of the present embodiment, the first bulging angle α of the first end face 13 at the first connection portion (connection portion 15b) is 20° or more. The second bulging angle β of the second end face 14 at the second connection portion (connection portion 16b) is 20° or more.

[0076] Therefore, the thermal stress applied to the bonding member 54 near the first connection portion (connection portion 15b) and the bonding member 55 near the second connection portion (connection portion 16b) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 decreases. The occurrence of cracks in the bonding member 54 near the first connection portion and the bonding member 55 near the second connection portion can be suppressed. According to the manufacturing method of the chip resistor 1 of the present embodiment, it is possible to provide a chip resistor 1 that can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0077] In the manufacturing method of the chip resistor 1 of the present embodiment, the ratio h of the first bulging height h of the first end face 13 to the thickness t of the insulating substrate 10 1 of h 1 / t is 0.05 or more. The ratio h of the second bulging height h of the first end face 13 to the thickness t of the insulating substrate 10 2 of h 2 / t is 0.05 or more. The thickness t of the insulating substrate 10 is the distance between the front surface 11 and the back surface 12. The first bulging height h of the first end face 13 1is the maximum height of the first end face 13 from the first virtual plane connecting the first connection part (connection part 15b), the front face 11, and the third connection part (connection part 15a) of the first end face 13. The second swelling height h of the second end face 14 2 is the maximum height of the second end face 14 from the second virtual plane connecting the second connection part (connection part 16b), the front face 11, and the fourth connection part (connection part 16a) of the second end face 14.

[0078] Therefore, due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50, the thermal stress applied to the bonding member 54 near the first connection part (connection part 15b) and the bonding member 55 near the second connection part (connection part 16b) decreases. The occurrence of cracks in the bonding member 54 near the first connection part and the bonding member 55 near the second connection part can be suppressed. According to the manufacturing method of the chip resistor 1 of the present embodiment, it is possible to provide a chip resistor 1 that can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0079] In the manufacturing method of the chip resistor 1 of the present embodiment, the distance (the length L of the insulating substrate 10) between the first connection part (connection part 15b) and the second connection part (connection part 16b) is 3.2 mm or more.

[0080] When the distance between the first connection part (connection part 15b) and the second connection part (connection part 16b) (the length L of the insulating substrate 10) increases, the thermal stress applied to the joining members 54 and 55 due to the difference between the coefficient of thermal expansion of the chip resistor 1 and the coefficient of thermal expansion of the circuit board 50 increases. However, in the chip resistor 1 of the present embodiment, the first end face 13 bulges from the first connection part, and the second end face 14 bulges from the second connection part. Therefore, even when the distance between the first connection part and the second connection part (the length L of the insulating substrate 10) increases, the thermal stress applied to the joining member 54 near the first connection part and the joining member 55 near the second connection part due to the difference between the coefficient of thermal expansion of the chip resistor 1 and the coefficient of thermal expansion of the circuit board 50 decreases. The occurrence of cracks in the joining member 54 near the first connection part and the joining member 55 near the second connection part can be suppressed. According to the manufacturing method of the chip resistor 1 of the present embodiment, it is possible to provide a chip resistor 1 that can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0081] In the manufacturing method of the chip resistor 1 of the present embodiment, forming the first electrode 30 and the second electrode 40 includes forming the first back surface electrode 33 and the second back surface electrode 43 on the back surface 12. Forming the first back surface electrode 33 and the second back surface electrode 43 includes forming an insulating resin layer (the first insulating resin layer 34, the second insulating resin layer 44) on the back surface 12 and forming a conductive layer (the first conductive layer 35, the second conductive layer 45) on the insulating resin layer. The conductive layer is formed of a conductive material including a binder resin and metal particles dispersed in the binder resin.

[0082] The insulating resin layers (the first insulating resin layer 34 and the second insulating resin layer 44) improve the adhesive strength of the first back surface electrode 33 and the second back surface electrode 43 with respect to the insulating substrate 10. The conductive layers (the first conductive layer 35 and the second conductive layer 45) of the present embodiment have a lower Young's modulus than the conductive layer formed of a conductive material containing glass and metal particles. Therefore, the thermal stress applied to the joining member 54 near the first connection portion (connection portion 15b) and the joining member 55 near the second connection portion (connection portion 16b) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 is reduced. The occurrence of cracks in the joining member 54 near the first connection portion and the joining member 55 near the second connection portion can be suppressed. According to the manufacturing method of the chip resistor 1 of the present embodiment, it is possible to provide the chip resistor 1 that can improve the reliability of the electronic circuit device 2 including the chip resistor 1.

[0083] The electronic circuit device 2 of the present embodiment includes the chip resistor 1 of the present embodiment, a circuit board 50, a first joining member (joining member 54), and a second joining member (joining member 55). The circuit board 50 includes a first land pattern (land pattern 52) and a second land pattern (land pattern 53) spaced apart from the first land pattern. The first back surface electrode 33 is joined to the first land pattern using the first joining member. The second back surface electrode 43 is joined to the second land pattern using the second joining member.

[0084] Therefore, the thermal stress applied to the first joining member (joining member 54) near the first connection portion (connection portion 15b) and the second joining member (joining member 55) near the second connection portion (connection portion 16b) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 is reduced. The occurrence of cracks in the first joining member near the first connection portion and the second joining member near the second connection portion can be suppressed. The reliability of the electronic circuit device 2 is improved.

[0085] Hereinafter, aspects of the present disclosure will be collectively described as appendices. (Appendix 1) An insulating substrate having a front surface, a back surface opposite to the front surface, a first end surface connected to the front surface and the back surface, and a second end surface opposite to the first end surface, A resistor layer disposed on the front surface, A first electrode, And a second electrode, The first end surface and the second end surface are each connected to the front surface and the back surface, The first electrode and the second electrode are spaced apart from each other in a direction in which the first end surface and the second end surface are spaced apart from each other, The first electrode includes a first front surface electrode disposed on the front surface and connected to the resistor layer, a first end surface electrode disposed on the first end surface and connected to the first front surface electrode, and a first back surface electrode disposed on the back surface and connected to the first end surface electrode, The second electrode includes a second front surface electrode disposed on the front surface and connected to the resistor layer, a second end surface electrode disposed on the second end surface and connected to the second front surface electrode, and a second back surface electrode disposed on the back surface and connected to the second end surface electrode, The first end surface bulges from a first connection portion between the back surface and the first end surface, The second end surface bulges from a second connection portion between the back surface and the second end surface, a chip resistor. (Appendix 2) The first bulging angle of the first end surface at the first connection portion is 20° or more, The second bulging angle of the second end surface at the second connection portion is 20° or more, the chip resistor according to Appendix 1. (Appendix 3) The ratio of the first bulging height of the first end surface to the thickness of the insulating substrate is 0.05 or more, The ratio of the second bulging height of the first end surface to the thickness of the insulating substrate is 0.05 or more, The thickness of the insulating substrate is the distance between the front surface and the back surface, The first swelling height of the first end face is the maximum height of the first end face from a first virtual plane connecting the first connecting portion, the front face, and a third connecting portion of the first end face, The second swelling height of the second end face is the maximum height of the second end face from a second virtual plane connecting the second connecting portion, the front face, and a fourth connecting portion of the second end face. The chip resistor according to Addendum 1 or Addendum 2. (Addendum 4) The distance between the first connecting portion and the second connecting portion is 3.2 mm or more. The chip resistor according to any one of Addenda 1 to 3. (Addendum 5) The first back surface electrode and the second back surface electrode each include an insulating resin layer disposed on the back surface and a conductive layer disposed on the insulating resin layer. The conductive layer is formed of a conductive material including a binder resin and metal particles dispersed in the binder resin. The chip resistor according to any one of Addenda 1 to 4. (Addendum 6) Preparing an insulating substrate, the insulating substrate having a front face, a back surface opposite to the front face, a first end face, and a second end face opposite to the first end face, the first end face and the second end face being connected to the front face and the back surface, respectively, the first end face bulging from a first connecting portion between the back surface and the first end face, and the second end face bulging from a second connecting portion between the back surface and the second end face. Forming a resistor layer on the front face, Forming a first electrode and a second electrode, The first electrode and the second electrode are spaced apart from each other in a direction in which the first end face and the second end face are spaced apart from each other. The first electrode includes a first front face electrode disposed on the front face and connected to the resistor layer, a first end face electrode disposed on the first end face and connected to the first front face electrode, and a first back surface electrode disposed on the back surface and connected to the first end face electrode. The second electrode includes a second front surface electrode disposed on the front surface and connected to the resistor layer, a second end surface electrode disposed on the second end surface and connected to the second front surface electrode, and a second back surface electrode disposed on the back surface and connected to the second end surface electrode, which is a method for manufacturing a chip resistor. (Appendix 7) Forming the first electrode and the second electrode includes forming the first end surface electrode and the second end surface electrode on the first end surface and the second end surface respectively by a sputtering method, which is the method for manufacturing a chip resistor according to Appendix 6. (Appendix 8) The first swelling angle of the first end surface at the first connection portion is 20° or more. The second swelling angle of the second end surface at the second connection portion is 20° or more, which is the method for manufacturing a chip resistor according to Appendix 6 or Appendix 7. (Appendix 9) The ratio of the first swelling height of the first end surface to the thickness of the insulating substrate is 0.05 or more. The ratio of the second swelling height of the first end surface to the thickness of the insulating substrate is 0.05 or more. The thickness of the insulating substrate is the distance between the front surface and the back surface. The first swelling height of the first end surface is the maximum height of the first end surface from the first virtual plane connecting the first connection portion, the front surface, and the third connection portion of the first end surface. The second swelling height of the second end surface is the maximum height of the second end surface from the second virtual plane connecting the second connection portion, the front surface, and the fourth connection portion of the second end surface, which is the method for manufacturing a chip resistor according to any one of Appendix 6 to Appendix 8. (Appendix 10) The distance between the first connection portion and the second connection portion is 3.2 mm or more, which is the method for manufacturing a chip resistor according to any one of Appendix 6 to Appendix 9. (Appendix 11) Forming the first electrode and the second electrode includes forming the first back surface electrode and the second back surface electrode on the back surface. Forming the first back surface electrode and the second back surface electrode includes forming an insulating resin layer on the back surface and forming a conductive layer on the insulating resin layer. The conductive layer is formed of a conductive material including a binder resin and metal particles dispersed in the binder resin. A method for manufacturing a chip resistor according to any one of Appendices 6 to 10. (Appendix 12) The chip resistor according to any one of Appendices 1 to 5, A circuit board including a first land pattern and a second land pattern spaced apart from the first land pattern, A first joining member, And a second joining member, The first back surface electrode is joined to the first land pattern using the first joining member, The second back surface electrode is joined to the second land pattern using the second joining member. An electronic circuit device.

[0086] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Explanation of Reference Numerals

[0087] 1 Chip resistor, 2 Electronic circuit device, 10 Insulating substrate, 11 Front surface, 12 Back surface, 13 First end face, 14 Second end face, 15a, 15b, 16a, 16b Connection parts, 20 Resistor layer, 24 Protection layer, 25 First insulating protection layer, 26 Second insulating protection layer, 30 First electrode, 31 First front surface electrode, 32 First auxiliary electrode, 33 First back surface electrode, 34 First insulating resin layer, 35 First conductive layer, 36 First end face electrode, 37 First inner plating film, 38 First outer plating film, 40 Second electrode, 41 Second front surface electrode, 42 Second auxiliary electrode, 43 Second back surface electrode, 44 Second insulating resin layer, 45 Second conductive layer, 46 Second end face electrode, 47 Second inner plating film, 48 Second outer plating film, 50 Circuit board, 51 Insulating circuit board, 52, 53 Land pattern, 54, 55 Bonding member.

Claims

1. An insulating substrate having a front surface, a back surface opposite to the front surface, a first end surface connected to the front surface and the back surface, and a second end surface opposite to the first end surface; A resistor layer disposed on the front surface; A first electrode; A second electrode, The first end surface and the second end surface are each connected to the front surface and the back surface, The first electrode and the second electrode are spaced apart from each other in a direction in which the first end surface and the second end surface are spaced apart from each other, The first electrode includes a first front surface electrode disposed on the front surface and connected to the resistor layer, a first end surface electrode disposed on the first end surface and connected to the first front surface electrode, and a first back surface electrode disposed on the back surface and connected to the first end surface electrode, The second electrode includes a second front surface electrode disposed on the front surface and connected to the resistor layer, a second end surface electrode disposed on the second end surface and connected to the second front surface electrode, and a second back surface electrode disposed on the back surface and connected to the second end surface electrode, The first end surface bulges from a first connection portion between the back surface and the first end surface, The second end surface bulges from a second connection portion between the back surface and the second end surface, a chip resistor.

2. The first bulging angle of the first end surface at the first connection portion is 20° or more, The second bulging angle of the second end surface at the second connection portion is 20° or more, the chip resistor according to claim 1.

3. The ratio of the first bulging height of the first end surface to the thickness of the insulating substrate is 0.05 or more, The ratio of the second bulging height of the first end surface to the thickness of the insulating substrate is 0.05 or more, The thickness of the insulating substrate is the distance between the front surface and the back surface, The first bulging height of the first end surface is the maximum height of the first end surface from a first virtual plane connecting the first connection portion, the front surface, and a third connection portion of the first end surface, The second bulging height of the second end surface is the maximum height of the second end surface from a second virtual plane connecting the second connection portion, the front surface, and a fourth connection portion of the second end surface, the chip resistor according to claim 1 or claim 2.

4. The chip resistor according to claim 1 or claim 2, wherein the distance between the first connection portion and the second connection portion is 3.2 mm or more.

5. Each of the first back electrode and the second back electrode includes an insulating resin layer disposed on the back surface and a conductive layer disposed on the insulating resin layer. The chip resistor according to claim 1 or claim 2, wherein the conductive layer is formed of a conductive material including a binder resin and metal particles dispersed in the binder resin.

6. Comprising preparing an insulating substrate, the insulating substrate having a front surface, a back surface opposite to the front surface, a first end surface, and a second end surface opposite to the first end surface, wherein the first end surface and the second end surface are each connected to the front surface and the back surface, the first end surface bulging from a first connection portion between the back surface and the first end surface, and the second end surface bulging from a second connection portion between the back surface and the second end surface. Forming a resistor layer on the front surface. Forming a first electrode and a second electrode. The first electrode and the second electrode are spaced apart from each other in a direction in which the first end surface and the second end surface are spaced apart from each other. The first electrode includes a first front surface electrode disposed on the front surface and connected to the resistor layer, a first end surface electrode disposed on the first end surface and connected to the first front surface electrode, and a first back electrode disposed on the back surface and connected to the first end surface electrode. The second electrode includes a second front surface electrode disposed on the front surface and connected to the resistor layer, a second end surface electrode disposed on the second end surface and connected to the second front surface electrode, and a second back electrode disposed on the back surface and connected to the second end surface electrode, a method for manufacturing a chip resistor.

7. The method for manufacturing a chip resistor according to claim 6, wherein forming the first electrode and the second electrode includes forming the first end surface electrode and the second end surface electrode on the first end surface and the second end surface, respectively, by a sputtering method.

8. The first bulging angle of the first end surface at the first connection portion is 20° or more. The method for manufacturing a chip resistor according to claim 6 or claim 7, wherein the second bulging angle of the second end surface at the second connection portion is 20° or more.

9. The ratio of the first bulging height of the first end face to the thickness of the insulating substrate is 0.05 or more. The ratio of the second bulging height of the first end face to the thickness of the insulating substrate is 0.05 or more. The thickness of the insulating substrate is the distance between the front surface and the back surface. The first bulging height of the first end face is the maximum height of the first end face from a first virtual plane connecting the first connecting portion, the front surface, and a third connecting portion of the first end face. The second bulging height of the second end face is the maximum height of the second end face from a second virtual plane connecting the second connecting portion, the front surface, and a fourth connecting portion of the second end face. The method for manufacturing a chip resistor according to claim 6 or claim 7.

10. The distance between the first connecting portion and the second connecting portion is 3.2 mm or more. The method for manufacturing a chip resistor according to claim 6 or claim 7.

11. Forming the first electrode and the second electrode includes forming the first back surface electrode and the second back surface electrode on the back surface. Forming the first back surface electrode and the second back surface electrode includes forming an insulating resin layer on the back surface and forming a conductive layer on the insulating resin layer. The conductive layer is formed of a conductive material including a binder resin and metal particles dispersed in the binder resin. The method for manufacturing a chip resistor according to claim 6 or claim 7.

12. The chip resistor according to claim 1 or claim 2, A circuit board including a first land pattern and a second land pattern spaced apart from the first land pattern, A first joining member, A second joining member, The first back surface electrode is joined to the first land pattern using the first joining member, The second back surface electrode is joined to the second land pattern using the second joining member. An electronic circuit device.

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