Power semiconductor device and manufacturing method thereof
By inclining the first metal wiring member and creating a thickness difference in the insulating sheet, the semiconductor device addresses issues of interfacial peeling and thermal expansion, enhancing insulation and heat dissipation properties.
Patent Information
- Application Number
- JP2023203660
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-12-01
- Publication Date
- 2025-06-12
AI Technical Summary
In semiconductor devices for power applications, the curing shrinkage of molding resin and warping of metal wiring members due to thermal expansion differences lead to interfacial peeling between the insulating sheet and the metal components, reducing insulation and heat dissipation properties.
A semiconductor device design where the lower surface of the first metal wiring member is inclined with respect to the upper surface of the metal plate, creating a thickness difference in the insulating sheet between them, which controls the occurrence of defects that affect insulation and heat dissipation.
This design effectively suppresses the decrease in insulation and heat dissipation properties by directing defects to the side with less influence, thereby improving the overall performance of the semiconductor device.
Smart Images

Figure 2025088876000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device for power and a method for manufacturing the same.
Background Art
[0002] Semiconductor devices for power are used to control and rectify relatively large amounts of power in vehicles such as railway vehicles, hybrid cars, electric vehicles, and industrial machines. Since a high voltage of several hundred volts or more is applied during use of the semiconductor device for power and the semiconductor element for power generates heat, high insulation and heat dissipation are required.
[0003] As a module that achieves both insulation and heat dissipation of a semiconductor device for power and reduces the mounting area and cost, a T-PM (Transfer mold Power Module) is known. In the manufacturing process of the T-PM, an insulating sheet in a semi-cured state having a thermal conductivity of 10 W / m·K or more is disposed between a metal wiring member on which a semiconductor element is mounted and a metal plate, and the insulating sheet is reacted with pressure and heat during transfer molding to bond the metal wiring member and the metal plate.
[0004] Many of the insulating sheets used in T-PMs are composed of ceramic particles and a thermosetting resin, and the molding resin used in transfer molding is also a thermosetting resin. The thermosetting resin has the property of melting by heat and then hardening by a chemical reaction. In order for the insulating sheet to exhibit stable insulation, heat dissipation, and adhesiveness, it is necessary to match the timing of the reaction of the thermosetting resin of the insulating sheet and the timing from resin injection to completion of curing of the molding resin.
[0005] However, particularly in the case of a module with a large overall size, if the resin injection time is shortened in accordance with the timing of the reaction of the insulating sheet, the resin flow resistance applied to the insulating sheet and the metal wiring member and metal plate above and below it increases. As a result, a force is generated that peels the insulating sheet from the metal wiring member and the metal plate, resulting in problems of reduced insulation and heat dissipation.
[0006] In order to solve such problems, for example, in Patent Document 1, the lower mold used in the transfer molding process has a stepped portion provided on the bottom surface of the cavity below the inner lead, and this stepped portion reduces the resin flow resistance against the bent portion connecting the inner lead and the die pad.
Prior Art Documents
Patent Documents
[0007]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0008] In the method of Patent Document 1, the force for peeling off the insulating sheet generated by the resin flow resistance can be suppressed, but in the transfer molding process, other factors, such as the curing shrinkage of the molding resin, also generate a force for peeling off the insulating sheet. Although the amount of curing shrinkage of the molding resin can be adjusted by tuning, it is difficult to make it zero in principle.
[0009] In addition, when a metal wiring member on which a semiconductor element is mounted is die-bonded with a semiconductor element using a metal bonding member, warping occurs due to the difference in the linear expansion coefficient of the materials. When the warped metal wiring member is inserted into the mold in the transfer molding process, a gap is formed between the insulating sheet and the metal wiring member. The air remaining in this gap remains as it is during the transfer molding process and may cause interfacial peeling between the insulating sheet and the metal wiring member.
[0010] Furthermore, the air present between the insulating sheet and the metal wiring member enters the insulating sheet, and due to the force for peeling off the insulating sheet described above, minute voids are generated or move, resulting in problems of reducing the insulation and heat dissipation properties.
[0011] The present disclosure discloses a technology for solving the above problems, and an object thereof is to provide a semiconductor device for power use and a method for manufacturing the same, which can improve insulation and heat dissipation properties.
Means for Solving the Problems
[0012] In the semiconductor device for power use of the present disclosure, when the normal direction of the upper surface of the metal plate is defined as upward and the direction opposite to the normal direction is defined as downward, the metal plate, the insulating sheet whose lower surface is adhered to the upper surface of the metal plate, the first metal wiring member whose lower surface is adhered to the upper surface of the insulating sheet, the semiconductor element whose lower surface is joined to the upper surface of the first metal wiring member, the second metal wiring member joined to the upper surface of the semiconductor element or the upper surface of the first metal wiring member, and a molding resin that seals the metal plate, the insulating sheet, the first metal wiring member, the semiconductor element, and the second metal wiring member in a state where the lower surface of the metal plate is exposed. The lower surface of the first metal wiring member is inclined with respect to the upper surface of the metal plate, and there is a thickness difference in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate.
[0013] The method for manufacturing a semiconductor device for power use of the present disclosure includes a preparation step of preparing a metal plate, a first metal wiring member, a semiconductor element, an insulating sheet, and a second metal wiring member; a semiconductor element joining step of joining the lower surface of the semiconductor element to the upper surface of the first metal wiring member; a second metal wiring member joining step of joining the second metal wiring member to the upper surface of the semiconductor element and the upper surface of the first metal wiring member; and a sealing step of disposing the metal plate, the insulating sheet, the first metal wiring member, the semiconductor element, and the second metal wiring member in a cavity of a mold and sealing them with a molding resin, and adhering the lower surface of the first metal wiring member and the upper surface of the metal plate via the insulating sheet. In a step before the sealing step, the lower surface of the first metal wiring member is inclined with respect to the upper surface of the metal plate, and in the sealing step, a thickness difference is caused in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate.
Effects of the Invention
[0014] According to the semiconductor device for power applications of the present disclosure, due to the thickness difference in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate, it is possible to control the generation of defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet to the side where the thickness of the insulating sheet is large. Therefore, by making the side with less influence on the insulation and heat dissipation properties when the above-mentioned defects occur the side where the thickness of the insulating sheet is large, it is possible to suppress the decrease in the insulation and heat dissipation properties of the insulating sheet.
[0015] According to the manufacturing method of the semiconductor device for power applications of the present disclosure, due to the generation of a thickness difference in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate in the sealing process, it is possible to control the generation of defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet to the side where the thickness of the insulating sheet is large. Therefore, by making the side with less influence on the insulation and heat dissipation properties when the above-mentioned defects occur the side where the thickness of the insulating sheet is large, it is possible to suppress the decrease in the insulation and heat dissipation properties of the insulating sheet.
Brief Description of the Drawings
[0016]
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Embodiments for Carrying Out the Invention
[0017] Embodiment 1. Hereinafter, the semiconductor device for power use according to Embodiment 1 and its manufacturing method will be described with reference to the drawings. FIG. 1 is a perspective view showing the semiconductor device for power use according to Embodiment 1, and FIG. 2 is a cross-sectional view of the portion indicated by A-A in FIG. 1 as viewed from the arrow direction. Further, FIG. 3 is a perspective view showing an example of the semiconductor device for power use according to Embodiment 1, and FIG. 4 is a side view of the semiconductor device for power use shown in FIG. 3. In each figure, the same or corresponding parts are denoted by the same reference numerals, and repeated explanations may be omitted.
[0018] In the following description, the normal direction of the upper surface 51 of the metal plate 5 shown in FIG. 2 is defined as "up", and the direction opposite to the normal direction is defined as "down". Also, using the x, y, and z axes shown in FIGS. 1 and 2, etc., the normal direction of the upper surface 51 of the metal plate 5 is defined as the plus side in the z-axis direction, and the direction opposite to the normal direction is defined as the minus side in the z-axis direction. The plus side refers to the direction of the arrow of the z-axis indicated by the arrow in FIG. 2, etc., and the minus side refers to the direction opposite to the direction of the arrow.
[0019] Furthermore, a specific direction along the upper surface 51 of the metal plate 5 is defined as the x-axis direction, and the directions orthogonal to the x-axis direction along the upper surface 51 of the metal plate 5 are defined as the y-axis positive side and the y-axis negative side. The positive side refers to the direction of the arrow of the y-axis indicated by an arrow in FIG. 2 and the negative side refers to the direction opposite to the direction of the arrow. That is, the upper surface 51 of the metal plate 5 is the surface on the positive side in the z-axis direction, the lower surface 52 is the surface on the negative side in the z-axis direction, and the upper surface 51 and the lower surface 52 are on the xy plane.
[0020] The semiconductor device 101 for power use according to Embodiment 1 is a T-PM. As shown in FIG. 1, it has a main wiring portion 6a and a control wiring portion 6b exposed from the molding resin 7. The main wiring portion 6a through which a large current is passed extends from the molding resin 7 to the positive side and the negative side in the y-axis direction, and is bent to the positive side in the z-axis direction respectively. The control wiring portion 6b which is a wiring portion for controlling the semiconductor element extends from the molding resin 7 to the positive side in the y-axis direction and is bent to the positive side in the z-axis direction.
[0021] Also, as shown in FIG. 2, the semiconductor device 101 for power use includes a metal plate 5, an insulating sheet 4 whose lower surface 42 is adhered to the upper surface 51 of the metal plate 5, a first metal wiring member 3 whose lower surface 32 is adhered to the upper surface 41 of the insulating sheet 4, and semiconductor elements 1a and 1b whose lower surfaces are joined to the upper surface 31 of the first metal wiring member 3.
[0022] The semiconductor device 101 for power use further includes a second metal wiring member 6 joined to the upper surface of the semiconductor elements 1a and 1b or the upper surface 31 of the first metal wiring member 3, and a molding resin 7 that seals the metal plate 5, the insulating sheet 4, the first metal wiring member 3, the semiconductor elements 1a and 1b, and the second metal wiring member 6 with the lower surface 52 of the metal plate 5 exposed. The lower surface 32 of the first metal wiring member 3 is inclined with respect to the upper surface 51 of the metal plate 5, and there is a thickness difference in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5.
[0023] The metal plate 5, which is a heat dissipation plate, is made of a metal with high thermal conductivity such as copper (Cu) or aluminum (Al). The metal plate 5 has at least a flat upper surface 51, and the lower surface 52 is exposed from the molded resin 7. In the example shown in FIG. 2, the metal plate 5 is a rectangular plate-like member, and both the upper surface 51 and the lower surface 52 are flat.
[0024] As shown in FIGS. 3 and 4, the lower surface 52 of the metal plate 5 is joined to the cooler 9 via a heat dissipation joining member 8. The heat dissipation joining member 8 is, for example, a metal joining member such as solder or sintered Ag, or a heat dissipation grease, a heat dissipation sheet, etc. Note that the lower surface 52 of the metal plate 5 may have a heat dissipation fin shape, and in that case, the cooler 9 which is a separate member becomes unnecessary.
[0025] The lower surface 42 of the insulating sheet 4 is adhered to the upper surface 51 of the metal plate 5, and the upper surface 41 of the insulating sheet 4 is adhered to the lower surface 32 of the first metal wiring member 3. That is, the metal plate 5 and the first metal wiring member 3 are adhered via the insulating sheet 4. As shown in FIG. 2, the insulating sheet 4 is arranged up to the end face (periphery) of the metal plate 5 so as to cover the entire upper surface 51 of the metal plate 5, and has substantially the same shape as the metal plate 5 in the xy plane. Since the outer shape (i.e., the outer periphery) of the first metal wiring member 3 in the xy plane is smaller than the outer shape of the metal plate 5, the insulating sheet 4 protrudes to the outer periphery side from the lower surface 32 of the first metal wiring member 3.
[0026] The insulating sheet 4 contains a thermosetting resin. Specifically, it is a mixture of a thermosetting resin such as an epoxy resin and ceramic particles such as boron nitride (BN) and silicon dioxide (SiO 2 ), or a material in which a thermosetting resin is impregnated into a skeleton made of BN, SiO 2 , etc. The insulating sheet 4 is in a semi-cured state in the process before the transfer molding process which is a sealing process, and is cured by the transfer molding process to adhere the first metal wiring member 3 and the metal plate 5. It is desirable that the insulating sheet 4 has a thermal conductivity of 10 W / m·K or more.
[0027] The first metal wiring member 3 is, for example, a plate-shaped heat spreader and has opposing upper surface 31 and lower surface 32. The heat spreader is made of a metal material such as Cu, Al, nickel (Ni), etc. Note that the first metal wiring member 3 may be a lead frame processed into an electrical wiring shape (see Embodiment 7, Figure 13).
[0028] On the upper surface 31 of the first metal wiring member 3, the lower surfaces of the semiconductor elements 1a and 1b are joined via the metal joining member 2a. Further, on the upper surfaces of the semiconductor elements 1a and 1b, the second metal wiring member 6 is joined via the metal joining member 2b. The second metal wiring member 6 is, for example, a lead frame and is made of a metal material with high electrical conductivity such as Cu, Al, etc. Note that the second metal wiring member 6 may be a wire, a ribbon, a bus bar, etc. (see Embodiment 7, Figure 13).
[0029] As shown in Figure 2, the second metal wiring member 6 is joined to the upper surfaces of the semiconductor elements 1a and 1b via the metal joining member 2b. Alternatively, it is joined to the upper surface 31 of the first metal wiring member 3 via the metal joining member 2b.
[0030] Note that in some cases, one end of the second metal wiring member 6 may be joined to the upper surface of the semiconductor element 1a and the other end may be joined to the upper surface 31 of the first metal wiring member 3 (see Embodiment 3, Figure 9). Also, the main wiring portion 6a of the second metal wiring member 6 and the semiconductor elements 1a and 1b may be joined using the metal joining member 2b, and the control wiring portion 6b of the second metal wiring member 6 and the control pads of the semiconductor elements 1a and 1b may be joined by a wire or the like.
[0031] A part of the second metal wiring member 6 is exposed from the molding resin 7 and forms the main wiring portion 6a and the control wiring portion 6b. Also, the second metal wiring member 6 includes an inner lead 61 joined to the upper surface 31 of the first metal wiring member 3 and an outer lead 62 connected to the inner lead 61 and extending in the y-axis direction parallel to the upper surface 51 of the metal plate 5.
[0032] The semiconductor elements 1a and 1b are, for example, power semiconductor elements based on silicon (Si), or power semiconductor elements based on silicon carbide (SiC), gallium nitride (GaN), gallium oxide (GaO), etc., which are attracting attention as next-generation semiconductor elements.
[0033] Here, an example of mounting two semiconductor elements 1a and 1b is shown. However, the number of semiconductor elements mounted on the power semiconductor device may be one or three or more, and the combinations vary depending on the application. For example, when one or two Si-IGBTs (Si-Insulated Gate Biopolar Transistors) are mounted, there are cases such as combining Si-IGBT and Si-FWD (Si-Free Wheeling Diode).
[0034] For the metal bonding member 2a that joins the first metal wiring member 3 and the semiconductor elements 1a and 1b, a die bonding material having high thermal conductivity and high electrical conductivity, such as solder or sintered Ag, is used, for example. For the metal bonding member 2b that joins the semiconductor elements 1a and 1b or the first metal wiring member 3 and the second metal wiring member 6, the same materials as those for the metal bonding member 2a, such as solder or sintered Ag, can be used. Note that the metal bonding member 2b may be different from the metal bonding member 2a, but it is preferably a material having high electrical conductivity for conducting large power.
[0035] The molding resin 7 is a thermosetting resin such as an epoxy resin, for example, and is formed in a transfer molding process. The thermosetting resin has the property of melting by heat and then hardening by a chemical reaction.
[0036] In order to improve the insulation and heat dissipation properties of the semiconductor device 101 for power applications configured as described above, it is important to improve the insulation and heat dissipation properties of the insulating sheet 4. Therefore, it is effective to control the locations where defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4 occur. Although measures to prevent the above-mentioned defects themselves are also important, some of the above-mentioned defects are difficult to avoid in terms of the manufacturing process. In the semiconductor device 101 for power applications, such defects are controlled to occur in locations where their influence on the insulation and heat dissipation properties of the insulating sheet 4 is smaller.
[0037] Specifically, the defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4 will be described. In the transfer molding process, due to the resin flow resistance in the mold and the curing shrinkage of the molded resin, etc., a force is generated to peel the insulating sheet 4 from the first metal wiring member 3 or the metal plate 5. This force may cause interfacial delamination between the first metal wiring member 3 and the insulating sheet 4, or between the metal plate 5 and the insulating sheet 4.
[0038] Also, when the first metal wiring member 3 warps due to the difference in the linear expansion coefficient of the materials when the semiconductor elements 1a and 1b are die-bonded with the metal bonding member 2a, and the warped first metal wiring member 3 is inserted into the mold in the transfer molding process, a gap is formed between the first metal wiring member 3 and the insulating sheet 4. Due to the air present in this gap, interfacial delamination may occur between the first metal wiring member 3 and the insulating sheet 4.
[0039] Furthermore, the air present in the gap between the first metal wiring member 3 and the insulating sheet 4 enters the insulating sheet 4, and when it is subjected to the force to peel the insulating sheet 4 described above, minute voids are generated or move, thereby reducing the insulation and heat dissipation properties. Note that the air present in the above-mentioned gap is usually discharged from the air vent, but when the amount of air is large, it is not discharged and remains at the interface between the first metal wiring member 3 and the insulating sheet 4 or inside the insulating sheet 4. These defects are the defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4, and it is difficult to completely avoid them in terms of the manufacturing process.
[0040] A method for controlling the location where the above-mentioned defect occurs in the semiconductor device 101 for power use will be described with reference to FIG. 2. The lower surface 32 of the first metal wiring member 3 is inclined with respect to the upper surface 51 of the metal plate 5, and there is a thickness difference in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5. The first metal wiring member 3 has a plurality of end faces connecting the upper surface 31 and the lower surface 32, and the plurality of end faces include a first end face 33a and a second end face 33b facing each other.
[0041] In FIG. 2, θ represents the inclination of the lower surface 32 of the first metal wiring member 3 with respect to the upper surface 51 of the metal plate 5, T1 represents the thickness of the insulating sheet 4 on the side of the first end face 33a, and T2 represents the thickness of the insulating sheet 4 on the side of the second end face 33b.
[0042] The insulating sheet 4 protrudes to the outer peripheral side from the lower surface 32 of the first metal wiring member 3. Regarding the gap between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5, the gap on the second end face 33b side is wider than the gap on the first end face 33a side. As a result, the thickness of the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 is such that the thickness T2 on the side of the second end face 33b is larger than the thickness T1 on the side of the first end face 33a (T2>T1). The thickness of the insulating sheet 4 continuously increases from the side of the first end face 33a toward the side of the second end face 33b.
[0043] In the state before the transfer molding process, due to the inclination of the first metal wiring member 3 in the thickness direction of the semiconductor device 101 for power use, that is, in the z-axis direction, the gap between the lower surface 32 of the first metal wiring member 3 and the insulating sheet 4 is wider on the side of the second end face 33b than on the side of the first end face 33a. When the transfer molding process is performed in this state, immediately before the injection of the uncured molding resin into the mold is completed, the above-mentioned gap is filled in order from the side with the narrow gap toward the side with the wide gap.
[0044] Therefore, defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4 are likely to occur on the side where the gap widens due to the inclination of the first metal wiring member 3, in other words, on the side where the thickness of the insulating sheet 4 is large. Accordingly, in the example shown in FIG. 2, the above-mentioned defects tend to gather on the side of the second end face 33b.
[0045] The amount of inclination (inclination θ) of the first metal wiring member 3 with respect to the metal plate 5 is not particularly limited and can be arbitrarily set. The larger the inclination θ and the larger the thickness difference of the insulating sheet 4, the more likely the occurrence location of the above-mentioned defects in the insulating sheet 4 is to be biased. However, since the gap between the lower surface 32 of the first metal wiring member 3, which causes the above-mentioned defects, and the insulating sheet 4 also becomes large, the inclination θ does not mean that the larger it is, the better. In FIG. 2, the difference in the thicknesses T1 and T2 of the insulating sheet 4 is drawn emphasizing it, but actually, it is desirable that the thickness difference of the insulating sheet 4 be about 10% or less (for example, T1 = T2 × 0.9).
[0046] The inclination θ can be set in an arbitrary direction on the xy plane, and can be controlled so that the above-mentioned defects occur on the side of an arbitrary location. The arbitrary location is a location where the influence on the insulation and heat dissipation properties is smaller when the above-mentioned defects occur (see Embodiment 2).
[0047] Note that although the first metal wiring member 3 is inclined in the z-axis direction with respect to the metal plate 5, when viewed as the entire completed power semiconductor device 101, there is no inclination in the z-axis direction. The second metal wiring member 6 exposed from the molding resin 7 is held by a mold in the transfer molding process, and the portion held by the mold does not incline even if the first metal wiring member 3 inclines with respect to the metal plate 5. The inclination of the first metal wiring member 3 with respect to the metal plate 5 is absorbed and offset by deformation of any one or two or more of the metal joining members 2a, 2b, the first metal wiring member 3, and the second metal wiring member 6.
[0048] A method for manufacturing the power semiconductor device 101 will be described with reference to the flowchart of FIG. 5. First, in the preparation step of step S1, a metal plate 5, a first metal wiring member 3, semiconductor elements 1a and 1b, an insulating sheet 4, and a second metal wiring member 6 are prepared. Subsequently, in the semiconductor element bonding step of step S2, the lower surfaces of the semiconductor elements 1a and 1b are bonded to the upper surface 31 of the first metal wiring member 3 using a metal bonding member 2a. Further, in the second metal wiring member bonding step of step S3, the second metal wiring member 6 is bonded to the upper surfaces of the semiconductor elements 1a and 1b and the upper surface 31 of the first metal wiring member 3 using a metal bonding member 2b.
[0049] Subsequently, in the sealing step (transfer molding step) of step S4, the metal plate 5, the insulating sheet 4, the first metal wiring member 3, the semiconductor elements 1a and 1b, and the second metal wiring member 6 are arranged in the cavity of the mold and sealed with a molding resin, and the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 are adhered via the insulating sheet 4.
[0050] In a step before the sealing step of step S4, the lower surface 32 of the first metal wiring member 3 is inclined with respect to the upper surface 51 of the metal plate 5 so that a thickness difference occurs in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 in the sealing step. For example, in the second metal wiring member bonding step of step S3, when integrating the first metal wiring member 3, the semiconductor elements 1a and 1b, and the second metal wiring member 6, a dedicated jig is used to fix them at an arbitrary inclination to incline the first metal wiring member 3.
[0051] A part (outer lead 62) of the second metal wiring member 6 exposed from the molding resin 7 is held by the mold in a state of extending in the y-axis direction parallel to the upper surface 51 of the metal plate 5 during transfer molding. After the transfer molding process is completed, the second metal wiring member 6 exposed from the molding resin 7 is cut and bent to form the power semiconductor device 101 as shown in FIG. 1.
[0052] According to the power semiconductor device 101 according to Embodiment 1, the lower surface 32 of the first metal wiring member 3 is inclined with respect to the upper surface 51 of the metal plate 5, and there is a thickness difference in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5. Therefore, it is possible to control the generation of defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4 to the side where the thickness of the insulating sheet 4 is large.
[0053] Since the inclination θ of the first metal wiring member 3 with respect to the metal plate 5 can be set in an arbitrary direction on the xy plane, it is possible to generate the above defects on the side of an arbitrary location. Therefore, the side where the influence on the insulation and heat dissipation properties is smaller when the above defects occur is set as the side where the thickness of the insulating sheet 4 is large, and by suppressing the generation of the above defects on the side where the influence on the insulation and heat dissipation properties is large, it is possible to suppress a decrease in the insulation and heat dissipation properties of the insulating sheet 4, and it is possible to improve the insulation and heat dissipation properties of the power semiconductor device 101.
[0054] Also, according to the manufacturing method of the power semiconductor device 101 according to Embodiment 1, since a thickness difference occurs in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 in the sealing process, it is possible to control the generation of defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4 to the side where the thickness of the insulating sheet 4 is large. Therefore, by setting the side where the influence on the insulation and heat dissipation properties is smaller when the above defects occur as the side where the thickness of the insulating sheet 4 is large, it is possible to suppress a decrease in the insulation and heat dissipation properties of the insulating sheet 4, and it is possible to improve the insulation and heat dissipation properties of the power semiconductor device 101.
[0055] Embodiment 2. In the above Embodiment 1, the case where the side of the location where the influence on the insulation and heat dissipation properties is smaller when the defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4 occur is set as the side where the thickness of the insulating sheet 4 is large has been described. In this Embodiment 2, a specific example will be given and described for the location where the influence on the insulation and heat dissipation properties is smaller when the above defects occur.
[0056] FIG. 6 is a cross-sectional view showing a power semiconductor device according to Embodiment 2. The power semiconductor device 102 according to Embodiment 2 has a region where the insulation distance along the insulating sheet 4 between the first metal wiring member 3 and the metal plate 5 is L1, and a region where the insulation distance is L2 (L2 > L1). For other configurations, it is the same as the power semiconductor device 101 (see FIG. 2) according to the above Embodiment 1.
[0057] Regarding the gap between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 of the power semiconductor device 102, the gap on the side of the region where the insulation distance is L2 is wider than the gap on the side of the region where the insulation distance is L1. As a result, the thickness of the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 is such that the thickness on the side of the region where the insulation distance is L2 is larger than the thickness on the side of the region where the insulation distance is L1. Since the above defects are likely to occur on the side where the thickness of the insulating sheet 4 is large, that is, on the side of the region with the longer insulation distance L2, it is difficult to cause insulation failure, and a decrease in the insulation performance of the insulating sheet 4 can be suppressed.
[0058] Similarly, regarding the insulation distance between different potentials of the first metal wiring member 3 or the second metal wiring member 6, by making the thickness of the insulating sheet 4 on the side where the insulation distance between different potentials is longer larger than the thickness of the insulating sheet 4 on the side where the insulation distance between different potentials is shorter, a decrease in the insulation performance of the insulating sheet 4 can be suppressed.
[0059] FIGS. 7 and 8 show examples of the thickness distribution of the insulating sheet in the power semiconductor device according to Embodiment 2. In FIGS. 7 and 8, the thickness of the insulating sheet 4 is shown by the darkness of black, and the darker the black, the larger the thickness of the insulating sheet 4. The first metal wiring member 3 of the power semiconductor devices 103 and 104 shown in FIGS. 7 and 8 has a first end face 33a and a second end face 33b, and a third end face 33c and a fourth end face 33d that face each other.
[0060] In the semiconductor device 103 for power use shown in FIG. 7, an air vent for discharging the air inside the mold used in the transfer molding process is disposed on the side of the second end face 33b. In FIG. 7, the air vent location 10 is indicated by a dotted line. Usually, the air vent is provided in a portion clamped to the mold in the transfer molding process (the second metal wiring member 6 in FIG. 7), and is often provided at a position opposite to the gate for injecting the molding resin particularly in the transfer molding process. Further, when positioning pins or the like are provided on the minus side in the z-axis direction of the molding resin, the air vent may be provided on the surface on the minus side in the z-axis direction.
[0061] Regarding the gap between the lower surface 32 of the first metal wiring member 3 of the semiconductor device 103 for power use and the upper surface 51 of the metal plate 5, the gap on the side where the air vent of the molding resin 7 is disposed is wider than the gap on the side opposite to the side where the air vent is disposed. Thereby, the thickness of the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 is larger on the side of the second end face 33b which is the air vent location 10 than the thickness on the side of the first end face 33a where the air vent is not disposed.
[0062] Immediately before the injection of the uncured molding resin into the mold in the transfer molding process is completed, the gap between the lower surface 32 of the first metal wiring member 3 and the insulating sheet 4 is filled in order from the side with the narrow gap toward the side with the wide gap. For this reason, the air existing in the gap between the lower surface 32 of the first metal wiring member 3 and the insulating sheet 4 gathers on the side where the gap becomes wider due to the inclination of the first metal wiring member 3, that is, the side where the thickness of the insulating sheet 4 is large, and is easily discharged from the air vent. Therefore, the occurrence of the above defects due to air can be suppressed, and the deterioration of the insulating property and heat dissipation property of the insulating sheet 4 can be suppressed.
[0063] Further, in the semiconductor device 104 for power use shown in FIG. 8, a control wiring portion 6b is provided as the second metal wiring member 6, and the control wiring portion 6b is disposed near the fourth end face 33d on the side of the second end face 33b. In FIG. 6, the control wiring portion location 11 is indicated by a dotted line.
[0064] Regarding the gap between the lower surface 32 of the first metal wiring member 3 of the semiconductor device 104 for power and the upper surface 51 of the metal plate 5, the gap on the side where the control wiring portion 6b is disposed is wider than the gap on the side opposite to the side where the control wiring portion 6b is disposed. As a result, the thickness of the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 is such that the thickness on the side of the second end surface 33b closer to the fourth end surface 33d, which is the control wiring portion arrangement location 11, is larger than the thickness on the side of the first end surface 33a where the control wiring portion 6b is not disposed. In the example shown in FIG. 8, the thickness of the insulating sheet 4 is maximum in the vicinity of the corner where the second end surface 33b and the fourth end surface 33d intersect.
[0065] Since the control wiring portion 6b is usually at a different potential from the main wiring portion 6a, the insulation distance from the metal plate 5, the first metal wiring member 3, and the main wiring portion 6a is set wide. In particular, when connecting the semiconductor elements 1a and 1b to the control wiring portion 6b with a wire or the like, a jig for wire bonding is required, so the insulation distance is set wide. The example shown in FIG. 8 is common with the example shown in FIG. 6 in that the above-mentioned defect is generated on the side with a longer insulation distance.
[0066] In the example shown in FIG. 8, since the above-mentioned defect is likely to occur on the side where the thickness of the insulating sheet 4 is large, that is, near the control wiring portion arrangement location 11, it is difficult to cause insulation failure, and a decrease in the insulation performance of the insulating sheet 4 can be suppressed. In addition, as a location where the influence on heat dissipation is smaller when the above-mentioned defect occurs, examples include a location farther from the heat-generating semiconductor elements 1a and 1b, a location farther from heat-sensitive electronic components, and the like.
[0067] According to the second embodiment, by setting the side where the thickness of the insulating sheet 4 is large as the side where the insulation distance between the first metal wiring member 3 and the metal plate 5 is longer, the side of the air vent arrangement location 10, or the side of the control wiring portion arrangement location 11, when the above-mentioned defect occurs, the influence on insulation performance and heat dissipation is small, and a decrease in the insulation performance and heat dissipation of the insulating sheet 4 can be suppressed.
[0068] Embodiment 3. FIG. 9 is a cross-sectional view showing a power semiconductor device according to Embodiment 3. In the power semiconductor device 105 according to Embodiment 3, a plurality of first metal wiring members 3A and 3B are provided on the upper surface 41 of the insulating sheet 4 with a space therebetween. The first metal wiring members 3A and 3B have different potentials, are arranged with the intermediate region 13 therebetween, and semiconductor elements 1a and 1b are joined to each of them, respectively. The upper surface of the semiconductor element 1a and the upper surface 31 of the first metal wiring member 3B are connected by a second metal wiring member 6.
[0069] The lower surfaces 32 of the respective first metal wiring members 3A and 3B are inclined with respect to the upper surface 51 of the metal plate 5, and there is a thickness difference in the insulating sheet 4 sandwiched between the lower surfaces 32 of the respective first metal wiring members 3A and 3B and the upper surface 51 of the metal plate 5. Regarding the gaps between the lower surfaces 32 of the respective first metal wiring members 3A and 3B of the power semiconductor device 105 and the upper surface 51 of the metal plate 5, the gap on the side closer to the intermediate region 13 sandwiched between the two first metal wiring members 3A and 3B having different potentials is wider than the gap on the side away from the intermediate region 13.
[0070] More specifically, regarding the gap between the lower surface 32 of the first metal wiring member 3A and the upper surface 51 of the metal plate 5, the gap on the side closer to the intermediate region 13 is wider than the gap on the side away from the intermediate region 13. As a result, in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3A and the upper surface 51 of the metal plate 5, the thickness T4 on the side closer to the intermediate region 13 becomes larger than the thickness T3 of the insulating sheet 4 on the side away from the intermediate region 13 (T4>T3).
[0071] Similarly, regarding the gap between the lower surface 32 of the first metal wiring member 3B and the upper surface 51 of the metal plate 5, the gap on the side closer to the intermediate region 13 is wider than the gap on the side away from the intermediate region 13. As a result, in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3B and the upper surface 51 of the metal plate 5, the thickness T6 on the side closer to the intermediate region 13 becomes larger than the thickness T5 of the insulating sheet 4 on the side away from the intermediate region 13 (T6>T5).
[0072] Thus, in the power semiconductor device 105, in the intermediate region 13 sandwiched between the first metal wiring members 3A and 3B, the sides where the thickness of the insulating sheet 4 is larger face each other. In FIG. 9, the differences between T3 and T4, and between T5 and T6, which are the thicknesses of the insulating sheet 4, are emphasized in the drawing, but actually, it is desirable that the thickness difference of the insulating sheet 4 be 10% or less (for example, T3 = T4 × 0.9).
[0073] The plurality of first metal wiring members 3A and 3B have different potentials. In many cases, however, the potential difference between them is smaller than the potential difference between the metal plate 5 and the first metal wiring members 3A and 3B. Therefore, by aligning the locations where defects that cause a reduction in the insulation and heat dissipation properties of the insulating sheet 4 occur closer to the intermediate region 13, the insulation and heat dissipation properties are less likely to be affected by a reduction when the above-mentioned defects occur on the side farther from the intermediate region 13.
[0074] In addition, when there are a plurality of first metal wiring members 3A and 3B, the direction of the inclination of each of the first metal wiring members 3A and 3B with respect to the metal plate 5 is not limited to the example shown in FIG. 9, and various combinations are possible. For example, when an air vent is arranged on the plus side in the y direction of the first metal wiring member 3A, in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3A and the upper surface 51 of the metal plate 5, the thickness T3 on the side farther from the intermediate region 13 may be made larger than the thickness T4 on the side closer to the intermediate region 13.
[0075] According to Embodiment 3, in addition to the same effects as those of Embodiment 1 described above, by mounting the semiconductor elements 1a and 1b on each of the plurality of first metal wiring members 3A and 3B, the area in the xy plane can be reduced and miniaturization can be achieved compared to the case where two semiconductor elements 1a and 1b are mounted on one first metal wiring member 3 as in Embodiments 1 and 2. In addition, by increasing the options for the combination of the inclinations of the plurality of first metal wiring members 3A and 3B with respect to the metal plate 5, it is possible to improve the insulation and heat dissipation properties while preventing the device from becoming larger.
[0076] Embodiment 4. FIG. 10 is a cross-sectional view showing a power semiconductor device according to Embodiment 4. In the power semiconductor device 106 according to Embodiment 4, a step portion 14 surrounding the outer periphery of the first metal wiring member 3 is provided at an end face connecting the upper surface 31 and the lower surface 32 of the first metal wiring member 3, and the area of the lower surface 32 of the first metal wiring member 3 is smaller than the area of the upper surface 31. Other configurations are the same as those of the power semiconductor device 101 (see FIG. 2) according to the above Embodiment 1.
[0077] As shown in FIG. 10, the lower surface 32 of the first metal wiring member 3 is inclined with respect to the upper surface 51 of the metal plate 5, and there is a thickness difference in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5. The thickness of the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5 is such that the thickness on the side of the second end face 33b is larger than the thickness on the side of the first end face 33a. Thus, it is possible to control the generation of defects that cause a decrease in the insulation and heat dissipation properties of the insulating sheet 4 to the side of the second end face 33b where the thickness of the insulating sheet 4 is large.
[0078] Furthermore, by providing the step portion 14 at the end face of the first metal wiring member 3 and making the area of the lower surface 32 of the first metal wiring member 3 smaller than the area of the upper surface 31, the insulation distance along the insulating sheet 4 between the first metal wiring member 3 and the metal plate 5 becomes longer compared to the case where the step portion 14 is not provided. Therefore, when the above-mentioned defects occur, it is difficult to cause insulation failure, and a decrease in the insulation property of the insulating sheet 4 can be suppressed.
[0079] In the example shown in FIG. 10, a single step portion 14 surrounding the outer periphery of the first metal wiring member 3 is provided, but a plurality of step portions may be provided. Also, the step portion 14 may be provided only at the first end face 33a and the second end face 33b, or may be provided only at the second end face 33b. Further, the dimension of the step portion 14 of the second end face 33b in the y-axis direction may be made larger than the dimension of the step portion 14 of the first end face 33a in the y-axis direction. Thereby, the insulation distance on the side of the second end face 33b where the above-mentioned defects are likely to occur becomes even longer, and a decrease in the insulation property of the insulating sheet 4 can be further suppressed.
[0080] According to Embodiment 4, in addition to the same effects as those of Embodiment 1, by providing the stepped portion 14 on the end face connecting the upper surface 31 and the lower surface 32 of the first metal wiring member 3, the insulation distance along the insulating sheet 4 between the first metal wiring member 3 and the metal plate 5 becomes longer, so that a further decrease in the insulation property of the insulating sheet 4 can be suppressed. By increasing the dimension in the y-axis direction of the stepped portion 14 on the side of the second end face 33b having a large thickness of the insulating sheet 4, it is possible to further improve the insulation property and the heat dissipation property.
[0081] Embodiment 5. FIG. 11 is a cross-sectional view showing a power semiconductor device according to Embodiment 5. In the power semiconductor device 107 according to Embodiment 5, the second metal wiring member 6 includes an inner lead 61 joined to the upper surface 31 of the first metal wiring member 3 and an outer lead 62 connected to the inner lead 61 and extending in the y-axis direction parallel to the upper surface 51 of the metal plate 5. The inner lead 61 is inside the molding resin 7, and the outer lead 62 is outside the molding resin 7.
[0082] As shown in FIG. 11, the inner lead 61 of the power semiconductor device 107 has a curved portion 63 that curves in a direction away from the upper surface 31 of the first metal wiring member 3, that is, in the positive z-axis direction. The height H2 from the upper surface 31 of the first metal wiring member 3 to the top of the curved portion 63 is higher than the height H1 from the upper surface 31 of the first metal wiring member 3 to the upper surface of the outer lead 62. For other configurations, it is the same as the power semiconductor device 101 (see FIG. 2) according to Embodiment 1 above.
[0083] According to such a configuration, at the time of mold clamping in the transfer molding process, the curved portion 63 of the second metal wiring member 6 (inner lead 61) is deformed so as to be parallel to the upper surface 51 of the metal plate 5. In other words, the height H2 of the curved portion 63 of the inner lead 61 is deformed to be the same height as the height of the upper surface of the outer lead 62.
[0084] As a result, a force is applied to press the first metal wiring member 3 joined to the inner lead 61 toward the minus side in the z-axis direction, reducing the gap between the first metal wiring member 3 and the insulating sheet 4. By reducing the initial gap between the first metal wiring member 3 and the insulating sheet 4, the occurrence of defects caused by the air present in the gap can be suppressed.
[0085] According to Embodiment 5, in addition to the same effects as those of Embodiment 1, since the inner lead 61 has a curved portion 63 that is curved toward the plus side in the z-axis direction, the initial gap between the insulating sheet 4 and the first metal wiring member 3 can be reduced, and the occurrence of defects caused by the gap can be suppressed. Therefore, it is possible to further improve the insulation and heat dissipation properties.
[0086] Embodiment 6. FIG. 12 is a cross-sectional view showing a power semiconductor device according to Embodiment 6. In the power semiconductor device 108 according to Embodiment 6, the second metal wiring member 6 is provided with three protrusions 15a, 15b, and 15c (collectively referred to as protrusions 15) on the surface joined to the semiconductor elements 1a and 1b and the surface joined to the first metal wiring member 3. The amount of inclination of the first metal wiring member 3 with respect to the metal plate 5 is controlled by these protrusions 15. Other configurations are the same as those of the power semiconductor device 101 (see FIG. 2) according to Embodiment 1.
[0087] In the example shown in FIG. 12, the second metal wiring member 6 to which the main wiring portion 6a extending toward the plus side in the y-axis direction is connected is provided with a protrusion 15a on the joint surface with the first metal wiring member 3. Further, the second metal wiring member 6 to which the main wiring portion 6a extending toward the minus side in the y-axis direction is connected is provided with a protrusion 15b on the joint surface with the semiconductor element 1a and a protrusion 15c on the joint surface with the semiconductor element 1b.
[0088] At least some of these protrusions 15 are in contact with the first metal wiring member 3 or the semiconductor elements 1a, 1b, and when the mold is clamped in the transfer molding process, a force is applied to press the first metal wiring member 3 or the semiconductor elements 1a, 1b joined to the second metal wiring member 6 in the negative z-axis direction. Therefore, by adjusting the height of each protrusion 15, the amount of inclination of the first metal wiring member 3 with respect to the metal plate 5 can be adjusted. Also, the direction of inclination of the first metal wiring member 3 on the xy plane can be controlled by the position where the protrusions 15 are provided.
[0089] For example, when the height of the protrusion 15c in the z-axis direction is higher than the height of the protrusion 15b in the z-axis direction, the second metal wiring member 6 joined to the semiconductor elements 1a, 1b is not parallel to the upper surface 51 of the metal plate 5. When placed in the mold in the transfer molding process in such a state, the second metal wiring member 6 is deformed to be parallel to the upper surface 51 of the metal plate 5 during mold clamping. As a result, the first metal wiring member 3 joined to the second metal wiring member 6 is pressed in the negative z-axis direction and inclined with respect to the metal plate 5.
[0090] Note that the number of the protrusions 15 is not particularly limited, and any number may be used as long as the amount of inclination of the first metal wiring member 3 with respect to the metal plate 5 can be controlled. Also, the protrusions 15 may be provided on either one of the surface joined to the semiconductor elements 1a, 1b of the second metal wiring member 6 and the surface joined to the first metal wiring member 3.
[0091] In the above-described Embodiment 1, when integrating the first metal wiring member 3, the semiconductor elements 1a, 1b, and the second metal wiring member 6, the first metal wiring member 3 was inclined using a dedicated jig. However, such a jig has a complex structure, and there is a problem that the initial investment and management costs are high when preparing jigs for mass production. In contrast, with the method of providing the protrusions 15 on the second metal wiring member 6, it is possible to control the amount of inclination of the first metal wiring member 3 with respect to the metal plate 5 without complicating the jig.
[0092] According to Embodiment 6, in addition to the same effects as those of Embodiment 1, projections 15 are provided on either one or both of the surfaces of the second metal wiring member 6 joined to the semiconductor elements 1a and 1b and the surface joined to the first metal wiring member 3. By controlling the amount of inclination of the first metal wiring member 3 with respect to the metal plate 5 by these projections 15, a complicated jig for inclining the first metal wiring member 3 becomes unnecessary, and it is possible to improve the insulation and heat dissipation while suppressing the manufacturing cost.
[0093] Embodiment 7. FIG. 13 is a cross-sectional view showing a power semiconductor device according to Embodiment 7. In Embodiments 1 to 6, the case where the first metal wiring member 3 is a heat spreader and the second metal wiring member 6 is a lead frame has been described. However, the first metal wiring member and the second metal wiring member are not limited to these. In Embodiment 7, the case where the first metal wiring member is a lead frame and the second metal wiring member is a wire will be described.
[0094] As shown in FIG. 13, the power semiconductor device 109 according to Embodiment 7 includes a metal plate 5, an insulating sheet 4, a first metal wiring member 3 which is a lead frame, a metal bonding member 2a, semiconductor elements 1a and 1b, wires 12a and 12b as the second metal wiring member, and a molding resin 7. Further, it includes a main wiring portion 3a and a control wiring portion 3b formed by a part of the first metal wiring member 3 exposed from the molding resin 7.
[0095] The lead frame constituting the first metal wiring member 3 is made of a metal material having a high electrical conductivity such as Cu or Al. Since the metal plate 5, the insulating sheet 4, the semiconductor elements 1a and 1b, the metal bonding member 2a, and the molding resin 7 are the same as those of the power semiconductor device 101 according to Embodiment 1, the description thereof will be omitted here.
[0096] Wire 12a connects the semiconductor element 1a and the first metal wiring member 3, and wire 12b connects the semiconductor element 1a and the semiconductor element 1b. As the wires 12a and 12b, Al wires, Au wires, Cu wires, etc. are used. Note that as the second metal wiring member, a ribbon or a bus bar may be used instead of a wire. When the second metal wiring member 6 is a wire or a ribbon, it is directly joined to the semiconductor elements 1a and 1b using a wire bonder and a ribbon bonder, respectively.
[0097] Also in the power semiconductor device 109, the lower surface 32 of the first metal wiring member 3 is inclined with an inclination θ with respect to the upper surface 51 of the metal plate 5, and there is a thickness difference in the insulating sheet 4 sandwiched between the lower surface 32 of the first metal wiring member 3 and the upper surface 51 of the metal plate 5. Thereby, the same effect as that of the power semiconductor device 101 according to the first embodiment is obtained.
[0098] Although various exemplary embodiments and examples are described in the present disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a specific embodiment, but are applicable to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are assumed within the scope of the technology disclosed in this specification. For example, it includes the case where at least one component is deformed, added, or omitted, and further, the case where at least one component is extracted and combined with the components of other embodiments.
[0099] Hereinafter, aspects of the present disclosure will be collectively described as appendices.
[0100] (Appendix 1) When the normal direction of the upper surface of the metal plate is defined as up and the direction opposite to the normal direction is defined as down, the metal plate, an insulating sheet whose lower surface is adhered to the upper surface of the metal plate, a first metal wiring member whose lower surface is adhered to the upper surface of the insulating sheet, a semiconductor element whose lower surface is joined to the upper surface of the first metal wiring member, A second metal wiring member joined to the upper surface of the semiconductor element or the upper surface of the first metal wiring member; A molded resin that seals the metal plate, the insulating sheet, the first metal wiring member, the semiconductor element, and the second metal wiring member with the lower surface of the metal plate exposed; A semiconductor device for power use, characterized in that the lower surface of the first metal wiring member is inclined with respect to the upper surface of the metal plate, and there is a thickness difference in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate. (Appendix 2) The insulating sheet protrudes to the outer peripheral side beyond the lower surface of the first metal wiring member; The insulating sheet between the first metal wiring member and the metal plate has a region where the insulation distance is L1 and a region where the insulation distance is L2 (L2 > L1); Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the side where the insulation distance is L2 is wider than the gap on the side where the insulation distance is L1, for the semiconductor device for power use according to Appendix 1. (Appendix 3) Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the side where the air vent of the molded resin is arranged is wider than the gap on the side opposite to the side where the air vent is arranged, for the semiconductor device for power use according to Appendix 1 or Appendix 2. (Appendix 4) A wiring portion for controlling the semiconductor element is provided as the first metal wiring member or the second metal wiring member; Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the side where the wiring portion for control is arranged is wider than the gap on the side opposite to the side where the wiring portion for control is arranged, for the semiconductor device for power use according to any one of Appendix 1 to Appendix 3. (Appendix 5) A plurality of the first metal wiring members arranged side by side on the upper surface of the insulating sheet with a space therebetween; The lower surface of each of the first metal wiring members is inclined with respect to the upper surface of the metal plate, and the insulating sheet sandwiched between the lower surface of each of the first metal wiring members and the upper surface of the metal plate has a thickness difference. The semiconductor device for power use according to any one of Appendices 1 to 4, characterized in that. (Appendix 6) Regarding the gap between the lower surface of each of the first metal wiring members and the upper surface of the metal plate, the gap on the side closer to the intermediate region sandwiched between two of the first metal wiring members having different potentials from each other is wider than the gap on the side away from the intermediate region. The semiconductor device for power use according to Appendix 5, characterized in that. (Appendix 7) A stepped portion surrounding the outer periphery of the first metal wiring member is provided at the end face connecting the upper surface and the lower surface of the first metal wiring member. The semiconductor device for power use according to any one of Appendices 1 to 6, characterized in that the area of the lower surface of the first metal wiring member is smaller than the area of the upper surface. (Appendix 8) The second metal wiring member includes an inner lead joined to the upper surface of the first metal wiring member and an outer lead connected to the inner lead and extending in a direction parallel to the upper surface of the metal plate. The inner lead has a curved portion that curves in a direction away from the upper surface of the first metal wiring member, and the height from the upper surface of the first metal wiring member to the top of the curved portion is higher than the height from the upper surface of the first metal wiring member to the upper surface of the outer lead. The semiconductor device for power use according to any one of Appendices 1 to 7, characterized in that. (Appendix 9) The second metal wiring member is provided with protrusions on either one or both of the surface joined to the semiconductor element and the surface joined to the first metal wiring member. The semiconductor device for power use according to any one of Appendices 1 to 8, characterized in that the inclination amount of the first metal wiring member with respect to the metal plate is controlled by the protrusions. (Appendix 10) A preparation step of preparing a metal plate, a first metal wiring member, a semiconductor element, an insulating sheet, and a second metal wiring member. A semiconductor element bonding step of bonding the lower surface of the semiconductor element to the upper surface of the first metal wiring member; A second metal wiring member bonding step of bonding the second metal wiring member to the upper surface of the semiconductor element and the upper surface of the first metal wiring member; A sealing step of disposing the metal plate, the insulating sheet, the first metal wiring member, the semiconductor element, and the second metal wiring member in a cavity of a mold and sealing them with a molding resin, and bonding the lower surface of the first metal wiring member and the upper surface of the metal plate via the insulating sheet; In a step prior to the sealing step, the lower surface of the first metal wiring member is inclined with respect to the upper surface of the metal plate; A method for manufacturing a power semiconductor device, characterized in that, in the sealing step, a thickness difference is caused in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate. (Appendix 11) The mold used in the sealing step has an air vent for discharging internal air; Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the side where the air vent is disposed is made wider than the gap on the side opposite to the side where the air vent is disposed. A method for manufacturing a power semiconductor device according to Appendix 10.
Industrial Applicability
[0101] The present disclosure can be used as a power semiconductor device and a method for manufacturing the same.
Explanation of Reference Numerals
[0102] 1a, 1b semiconductor elements, 2a, 2b metal bonding members, 3, 3A, 3B first metal wiring members, 3a main wiring portion, 3b control wiring portion, 4 insulating sheet, 5 metal plate, 6 second metal wiring member, 6a main wiring portion, 6b control wiring portion, 7 molding resin, 8 heat dissipation bonding member, 9 cooler, 10 air vent location, 11 control wiring portion location, 12a, 12b wires, 13 intermediate region, 14 step portion, 15, 15a, 15b, 15c protrusions, 31 upper surface, 32 lower surface, 33a first end face, 33b second end face, 33c third end face, 33d fourth end face, 41 upper surface, 42 lower surface, 51 upper surface, 52 lower surface, 61 inner lead, 62 outer lead, 63 curved portion, 101, 102, 103, 104, 105, 106, 107, 108, 109 power semiconductor devices
Claims
1. When defining the normal direction of the upper surface of the metal plate as upward and the direction opposite to the normal direction as downward, the metal plate, an insulating sheet whose lower surface is adhered to the upper surface of the metal plate, a first metal wiring member whose lower surface is adhered to the upper surface of the insulating sheet, a semiconductor element whose lower surface is joined to the upper surface of the first metal wiring member, a second metal wiring member joined to the upper surface of the semiconductor element or the upper surface of the first metal wiring member, a molding resin that seals the metal plate, the insulating sheet, the first metal wiring member, the semiconductor element, and the second metal wiring member with the lower surface of the metal plate exposed, A semiconductor device for power use, wherein the lower surface of the first metal wiring member is inclined with respect to the upper surface of the metal plate, and there is a thickness difference in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate.
2. The insulating sheet protrudes to the outer peripheral side beyond the lower surface of the first metal wiring member, having a region where the insulation distance along the insulating sheet between the first metal wiring member and the metal plate is L1 and a region where the insulation distance is L2 (L2 > L1), Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the region side where the insulation distance is L2 is wider than the gap on the region side where the insulation distance is L1. The semiconductor device for power use according to Claim 1.
3. Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the side where the air vent of the molding resin is arranged is wider than the gap on the side opposite to the side where the air vent is arranged. The semiconductor device for power use according to Claim 1.
4. As the first metal wiring member or the second metal wiring member, a wiring portion for controlling the semiconductor element is provided, Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the side where the wiring portion for control is arranged is wider than the gap on the side opposite to the side where the wiring portion for control is arranged. The semiconductor device for power use according to Claim 1.
5. A plurality of the first metal wiring members arranged side by side on the upper surface of the insulating sheet with a space therebetween are provided, The lower surface of each of the first metal wiring members is inclined with respect to the upper surface of the metal plate, and the insulating sheet sandwiched between the lower surface of each of the first metal wiring members and the upper surface of the metal plate has a thickness difference. The semiconductor device for power use according to claim 1, characterized in that.
6. Regarding the gap between the lower surface of each of the first metal wiring members and the upper surface of the metal plate, the gap on the side closer to the intermediate region sandwiched between two of the first metal wiring members having different potentials from each other is wider than the gap on the side away from the intermediate region. The semiconductor device for power use according to claim 5, characterized in that.
7. On the end face connecting the upper surface and the lower surface of the first metal wiring member, a stepped portion surrounding the outer periphery of the first metal wiring member is provided. The semiconductor device for power use according to any one of claims 1 to 6, characterized in that the area of the lower surface of the first metal wiring member is smaller than the area of the upper surface.
8. The second metal wiring member includes an inner lead joined to the upper surface of the first metal wiring member and an outer lead connected to the inner lead and extending in a direction parallel to the upper surface of the metal plate. The inner lead has a curved portion that curves in a direction away from the upper surface of the first metal wiring member, and the height from the upper surface of the first metal wiring member to the top of the curved portion is higher than the height from the upper surface of the first metal wiring member to the upper surface of the outer lead. The semiconductor device for power use according to any one of claims 1 to 6, characterized in that.
9. The second metal wiring member is provided with protrusions on either one or both of the surface joined to the semiconductor element and the surface joined to the first metal wiring member. The semiconductor device for power use according to any one of claims 1 to 6, characterized in that the inclination amount of the first metal wiring member with respect to the metal plate is controlled by the protrusion.
10. A preparation step of preparing a metal plate, a first metal wiring member, a semiconductor element, an insulating sheet, and a second metal wiring member; A semiconductor element bonding step of bonding the lower surface of the semiconductor element to the upper surface of the first metal wiring member; A second metal wiring member bonding step of bonding the second metal wiring member to the upper surface of the semiconductor element and the upper surface of the first metal wiring member; Place the metal plate, the insulating sheet, the first metal wiring member, the semiconductor element, and the second metal wiring member in the cavity of the mold and seal them with a molding resin, and bond the lower surface of the first metal wiring member and the upper surface of the metal plate via the insulating sheet. A sealing step is provided. In a step prior to the sealing step, the lower surface of the first metal wiring member is inclined with respect to the upper surface of the metal plate. A method for manufacturing a power semiconductor device, characterized in that a thickness difference is caused in the insulating sheet sandwiched between the lower surface of the first metal wiring member and the upper surface of the metal plate in the sealing step.
11. The mold used in the sealing step has an air vent for discharging internal air. Regarding the gap between the lower surface of the first metal wiring member and the upper surface of the metal plate, the gap on the side where the air vent is disposed is made wider than the gap on the side opposite to the side where the air vent is disposed. The method for manufacturing a power semiconductor device according to claim 10, characterized in that.
Citation Information
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