Power semiconductor device and power conversion device including the same

Abstract

To provide a power semiconductor device and a power conversion device including the same, which prevents electric field concentration in the lower edge region of a trench gate.SOLUTION: A power semiconductor device includes a substrate 110, a first conductive type epitaxial layer 117 disposed on the substrate, a plurality of second conductive type wells 130 spaced apart from one another on the epitaxial layer, a gate 160 disposed between the plurality of wells, a gate insulating layer 155 disposed to cover the gate, and a first conductive type doped region 140 disposed on a side of the gate insulating layer. The doped region includes a first conductive type first doped region 140a having a first horizontal width and a first conductive type second doped region 140b having a second horizontal width smaller than the first horizontal width and disposed below the first conductive type first doped region.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The embodiments relate to a power semiconductor device and a power conversion device including the same.

Background Art

[0002] A power semiconductor is one of the core elements that determine the efficiency, speed, durability, and reliability of a power electronics system.

[0003] Recently, with the development of the power electronics industry, the conventionally used silicon (Si) power semiconductors have reached their physical limits, and active research has been conducted on wide bandgap (WBG) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace them.

[0004] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, thereby having characteristics such as a low intrinsic carrier concentration, a high breakdown electric field (about 4 to 20 times), a high thermal conductivity (about 3 to 13 times), and a high electron saturation velocity (about 2 to 2.5 times).

[0005] Due to such characteristics, they can operate in high-temperature and high-voltage environments and have a high switching speed and low switching losses. Among them, GaN (gallium nitride) power semiconductor devices can be used in low-voltage systems, and SiC (silicon carbide) power semiconductor devices are suitable for high-voltage systems.

[0006] Conventional SiC MOSFETs can be classified into MOSFETs with a trench structure, MOSFETs with a vertical doubly implanted structure (DIMOSFET), or MOSFETs with a lateral diffused structure, etc., depending on the structure. DIMOSFETs are sometimes called Planar MOSFETs or VDMOSFETs.

[0007] On the other hand, MOSFETs with a trench structure have a problem that the electric field concentrates in the edge region due to the shape of the trench gate. Even if a P-shield process or the like is performed to solve this problem, there are problems such as the addition of a mask layer, an increase in the process difficulty, and an increase in the cell pitch, and a new solution is required.

[0008] Also, conventionally, MOSFETs with a trench structure have a problem that the reliability of the element decreases because it is difficult to precisely control the channel region and the short circuit characteristics.

Summary of the Invention

Problems to be Solved by the Invention

[0009] One of the technical problems of the embodiment is to prevent the electric field concentration in the lower edge region of the trench gate.

[0010] Also, one of the technical problems of the embodiment is to control the length of the channel.

[0011] Also, one of the technical problems of the embodiment is to prevent the damage generated when forming the doping region.

[0012] Also, one of the technical problems of the embodiment is to improve the reliability of the element during high-speed switching.

[0013] The technical problems of the embodiments are not limited to those described in this section and include those that can be understood from the description of the invention.

Means for Solving the Problems

[0014] The power semiconductor device according to the embodiment and the power conversion device including the same include a substrate 110, a first conductivity type epi-layer 117 disposed on the substrate 110, a plurality of second conductivity type wells 130 disposed separately from each other on the epi-layer 117, a gate 160 disposed between the plurality of wells 130, and a gate insulating layer 155 disposed so as to cover at least a part of the gate 160, and may include a first conductivity type doping region 140 disposed on a side portion of the gate insulating layer 155.

[0015] Also, in the embodiment, the lower surface of the doping region 140 can be positioned higher than the lower surface of the gate 160.

[0016] Also, in the embodiment, the lower end edge region of the gate insulating layer 155 can be in contact with the well 130.

[0017] Also, in the embodiment, the bottom surface of the well 130 can be positioned lower than the bottom surface of the gate insulating layer 155.

[0018] Also, in the embodiment, the doping region 140 and the epi-layer 117 do not contact each other, and a well 130 is positioned between the doping region 140 and the epi-layer 117.

[0019] Also, in the embodiment, the doping region 140 can include a first conductivity type first doping region 140a in contact with a source electrode and a first conductivity type second doping region 140b in contact with a side surface of the gate insulating layer 155.

[0020] Also, in the embodiment, the doping concentration of the second doping region 140b may be substantially the same as the doping concentration of the first doping region 140a.

[0021] The lower surface of the second doping region 140b can be positioned higher than the lower surface of the gate 160.

[0022] Also, in the embodiment, the second doping region 140b may be formed by an epitaxial regrowth process.

[0023] Also, in the embodiment, the second doping region 140b may not overlap vertically with the source contact layer 145.

[0024] Also, in the embodiment, the thickness of the second doping region in the vertical direction may be 1 / 2 or more of the thickness of the gate 160 in the vertical direction.

[0025] Also, in the embodiment, it further includes a JFET region 150 disposed on the lower surface of the gate insulating layer 155, and the JFET region 150 can be in contact with the plurality of wells 130.

[0026] The deviation of the doping concentration in the second doping region 140b is controlled within 10%.

[0027] The first length L1 of the second doping region 140b in contact with the gate insulating layer 155 may be longer than the second length L2 of the well 130 in contact with the gate insulating layer.

[0028] The region of the second conductivity type well 130 in contact with the gate insulating layer 155 is disposed under the second doping region 140b.

[0029] Also, the power semiconductor device according to the embodiment can include a substrate, a first conductivity type epi-layer 117 disposed on the substrate, a plurality of second conductivity type wells 130 disposed separately from each other on the epi-layer 117, a gate disposed between the plurality of wells 130, and a gate insulating layer disposed to cover the gate.

[0030] It includes a first-conductivity-type doping region 140 disposed on a side portion of the gate insulating layer, and the doping region 140 may include a first-conductivity-type first doping region 140a having a first horizontal width and a first-conductivity-type third doping region 140c having a second horizontal width smaller than the first horizontal width and disposed below the first doping region 140a.

[0031] The doping concentration of the third doping region 140c may be lower than the doping concentration of the first doping region.

[0032] The lower surface of the third doping region 140c may be positioned higher than the lower surface of the gate 160.

[0033] The region of the well 130 in contact with the gate insulating layer 155 is disposed below the third doping region 140c.

[0034] The lower end edge region of the gate insulating layer 155 is surrounded by the well 130.

[0035] The bottom surface of the well 130 may be positioned lower than the bottom surface of the gate insulating layer 155.

[0036] The third doping region 140c is formed by an epitaxial regrowth process, and the first doping region 140a may be formed by ion implantation.

[0037] Also, the second doping region is disposed inside the first doping region.

[0038] Also, the upper surface of the second doping region is positioned at the same height as the upper surface of the first doping region.

[0039] Also, the thickness of the second doping region may be larger than the vertical thickness of the first doping region.

[0040] In addition, the power semiconductor device according to the embodiment can include a substrate, a first conductivity type epitaxial layer disposed on the substrate, a plurality of second conductivity type wells disposed separately from each other on the epitaxial layer, a gate disposed within the plurality of wells, and a gate insulating layer disposed to cover at least a part of the gate. The first conductivity type doping region disposed at a side portion of the gate insulating layer is included, and the doping region can include a first conductivity type first doping region having a first horizontal width and a first conductivity type third doping region having a second horizontal width smaller than the first horizontal width and disposed inside the first doping region.

[0041] The doping concentration of the third doping region may be lower than the doping concentration of the first doping region.

[0042] The lower surface of the third doping region can be positioned higher than the lower surface of the gate.

[0043] The bottom surface of the well can be positioned lower than the bottom surface of the gate insulating layer.

[0044] The upper surface of the third doping region is positioned at the same height as the upper surface of the first doping region, and the thickness of the third doping region may be larger than the vertical thickness of the first doping region.

Advantages of the Invention

[0045] The power semiconductor device according to the embodiment has a technical effect of preventing electric field concentration in the lower edge region of the trench gate.

[0046] For example, in the embodiment, the second conductivity type well is disposed to cover the lower edge region of the trench gate, thereby preventing electric field concentration in the lower edge region of the trench gate.

[0047] In addition, the embodiments have a technical effect of being able to control the channel length. For example, in the embodiments, the second doping region of the first conductivity type is formed by an epitaxial regrowth process instead of an implant process, so that the doping concentration is more uniformly controlled compared to the ion implantation process. As a result, the depth of the doping region can be accurately controlled, and the channel length can be precisely controlled.

[0048] For example, there is a special technical effect that the channel length can be precisely controlled by uniformly controlling the deviation of the doping concentration within about 5 - 10% in the second doping region of the first conductivity type.

[0049] In addition, the embodiments have a technical effect of being able to prevent damage generated when forming the doping region. For example, in the embodiments, the second doping region of the first conductivity type is formed by an epitaxial regrowth process instead of an implant process without a separate P - shield process, thereby preventing damage that may occur in the implant process.

[0050] In addition, the embodiments have a technical effect of being able to improve the reliability of the device during high - speed switching.

[0051] For example, in the embodiments, the doping concentration of the second doping region of the first conductivity type disposed on the side of the trench gate is formed lower than the doping concentration of the first doping region of the first conductivity type, so that the saturation current decreases and the SCWT (Short Circuit Withstand Time) increases, improving the reliability of the device during high - speed switching.

[0052] The technical effects of the embodiments are not limited to those described in this item and include those that can be understood from the description of the invention.

Brief Description of the Drawings

[0053]

Figure 1

Figure 2

Figure 3

Figure 4a

Figure 4b

Figure 4c

Figure 4d

Figure 4e

Figure 4f

Figure 4g

Figure 5

Mode for Carrying Out the Invention

[0054] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings. The suffixes "module" and "section" for the components used in the following description are given or mixed for the purpose of facilitating the preparation of the specification, and do not have meanings or roles that are distinguished from each other by themselves. Also, the accompanying drawings are for the purpose of facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawings. Also, when an element such as a layer, region, or substrate is referred to as being "on" another component, this includes cases where it is directly on another element or where another intermediate element may be present therebetween.

[0055] In the specification or claims, the meaning of "Component A includes at least one of a, b, and / or c" can include (1) when Component A includes a, (2) when Component A includes b, (3) when Component A includes c, (4) when Component A includes a and b, (5) when Component A includes b and c, (6) when Component A includes a and c, and (7) when Component A includes all of a, b, and c.

[0056] Singular expressions include not only singular but also plural expressions unless the context clearly indicates otherwise. For example, the meaning of "Component A includes a structure" can include the meaning of "Component A includes one or more structures".

[0057] FIG. 1 is an exemplary configuration diagram of a power conversion device 1000 according to an embodiment.

[0058] The power conversion device 1000 according to the embodiment can receive a DC power supply from a battery or a fuel cell and convert it into an AC power supply, and supply the AC power supply to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive a DC power supply from a battery, convert it into a three-phase AC power supply, and supply it to a motor M, and the motor M can provide power for an electric vehicle, a fuel cell vehicle, etc.

[0059] The power conversion device 1000 according to the embodiment can include a power semiconductor element 100. The power semiconductor element 100 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and can include an IGBT (Insulated Gate Bipolar Transistor).

[0060] For example, the power conversion device 1000 can include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, 100f, and can include a plurality of diodes (not shown). Each of the plurality of diodes may be inherently present in the form of an internal diode in each of the power semiconductor devices 100a, 100b, 100c, 100d, 100e, 100f, but is not limited thereto and may be separately arranged.

[0061] In the embodiment, a DC power supply can be converted into an AC power supply by on / off control of a plurality of power semiconductor devices 100a to 100f. For example, the power conversion device 1000 according to the embodiment can turn on the first power semiconductor device 100a and turn off the second power semiconductor device 100b in the first time interval of one cycle to supply a positive-polarity power supply to the motor M, and turn off the first power semiconductor device 100a and turn on the second power semiconductor device 100b in the second time interval of one cycle to supply a negative-polarity power supply to the motor M.

[0062] In the embodiment, a group of power semiconductor devices arranged in series between the high-voltage line and the low-voltage line on the input side can be called an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b can constitute the first arm, the third power semiconductor device 100c and the fourth power semiconductor device 100d can constitute the second arm, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f can constitute the third arm.

[0063] The upper-side power semiconductor device and the lower-side power semiconductor device in the arm are controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b do not turn on simultaneously but turn on and off alternately.

[0064] Each of the power semiconductor devices 100a to 100f has a high power applied in the off state. For example, when the first power semiconductor device 100a is on and the second power semiconductor device 100b is off, the input voltage is directly applied to the second power semiconductor device 100b. The voltage input to the second power semiconductor device 100b is a relatively high voltage. To withstand such a high voltage, the breakdown voltage of each of the power semiconductor devices 100a to 100f can be designed to be at a high level.

[0065] Each of the power semiconductor devices 100a to 100f can conduct a high current in the on state. The motor M is driven by a relatively high current, and such a high current is supplied to the motor M through the on - state power semiconductor.

[0066] The high voltage applied to each of the power semiconductor devices 100a to 100f can induce a high switching loss. The high current flowing through the power semiconductor devices 100a to 100f can induce a high conduction loss. To dissipate the heat generated by such losses, the power semiconductor devices 100a to 100f can be packaged in a power semiconductor module including a heat dissipation means.

[0067] The power semiconductor device 100 of the embodiment may be a SiC (Silicon Carbide) power semiconductor device, which can operate in a high - temperature and high - voltage environment and can have a high switching speed and a low switching loss.

[0068] On the other hand, the power conversion device 1000 according to the embodiment can include a plurality of power semiconductor modules.

[0069] For example, the plurality of power semiconductor devices 100a to 100f illustrated in FIG. 1 are packaged in one power semiconductor module, or the power semiconductor devices constituting each arm are packaged in one power semiconductor module.

[0070] For example, the first power semiconductor element 100a, the second power semiconductor element 100b, the third power semiconductor element 100c, the fourth power semiconductor element 100d, the fifth power semiconductor element 100e, and the sixth power semiconductor element 100f illustrated in FIG. 1 are packaged in one power semiconductor module.

[0071] In addition, additional power semiconductor elements arranged in parallel with each of the power semiconductor elements 100a to 100f can be further included to increase the current capacity. In such a case, the number of power semiconductor elements included in the power semiconductor module is more than six.

[0072] The power conversion device 1000 according to the embodiment may also include power semiconductor elements in the form of diodes in addition to the power semiconductor elements 100a to 100f in the form of transistors. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor element 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor element 100b. And such diodes may also be packaged together in one power semiconductor module. Further, the diodes may be arranged in the form of internal diodes in each power semiconductor element.

[0073] Next, the power semiconductor elements constituting each arm are packaged in one power semiconductor module.

[0074] For example, the first power semiconductor element 100a and the second power semiconductor element 100b constituting the first arm are packaged in the first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d constituting the second arm are packaged in the second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f constituting the third arm are packaged in the third power semiconductor module.

[0075] In addition, additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a to 100f can be further included to increase the current capacity. In this case, the number of power semiconductor devices included in each power semiconductor module will be more than two. And each arm includes, in addition to the power semiconductor devices 100a to 100f in transistor form, power semiconductor devices in diode form (not shown), and such diodes may also be packaged together in one power semiconductor module. Further, the diode may be arranged in the form of an internal diode in each power semiconductor device.

[0076] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor devices 100 according to the embodiment.

[0077] The power semiconductor device 100 according to the embodiment can include a source electrode 190 disposed above a predetermined semiconductor epi-layer 120, a gate electrode 175, and a drain electrode 105 disposed below the semiconductor epi-layer 120.

[0078] In the form of a MOSFET, the source electrode 190 or the gate electrode 175 can include an Al-based metal, and the drain electrode 105 can include a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, or NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0079] Next, FIG. 3 is a cross-sectional view of the power semiconductor device according to the first embodiment. Referring to FIG. 3, the power semiconductor device according to the first embodiment can include at least one of a substrate 110, a drain electrode 115, a first-conductivity-type epi-layer 117, a second-conductivity-type well 130, a first-conductivity-type doping region 140, a source contact layer 145, a gate 160, and a gate insulating layer 155. The "first-conductivity-type epi-layer" can be referred to as the "epi-layer", and the "second-conductivity-type well" can be referred to as the "well". Also, in other configurations, the expressions of "first-conductivity type" or "second-conductivity type" may be omitted.

[0080] Specifically, in the first embodiment, a drain electrode 115 is disposed under a substrate 110. Also, the epi-layer 117 is disposed on the substrate 110. The epi-layer 117 may be an N-type drift region, but is not limited thereto.

[0081] Also, a well 130 is disposed on the epi-layer 117. The second-conductivity-type wells 130 can include a plurality of wells that are spaced apart from each other. A gate 160 and a gate insulating layer 155 are disposed between the plurality of wells 130. The gate insulating layer 155 is disposed to cover side surfaces and a bottom surface of the gate 160. The gate 160 can be positioned inside the gate insulating layer 155. Also, a JFET region 150 is disposed under the gate 160 and the gate insulating layer 155 to protect the gate insulating layer 155, but is not limited thereto.

[0082] On the other hand, in the case of a trench MOSFET studied internally, a problem has been studied in which an electric field concentrates in a lower edge region of a trench gate and the gate insulating layer is damaged. Accordingly, a separate ion implantation region such as a P-shield process is formed to prevent electric field concentration, but there has been a difficulty in the separate ion implantation region formation process.

[0083] Also, in the case of a MOSFET having a trench structure, there has been a problem in that the reliability of the device is reduced because it is difficult to precisely control a channel region and short circuit characteristics.

[0084] To solve the above problems, in the embodiment, the well 130 is formed deeper than the gate 160 and the gate insulating layer 155. Specifically, a bottom surface of the well 130 can be positioned lower than bottom surfaces of the gate 160 and the gate insulating layer 155. Also, the well 130 can be in contact with the gate insulating layer 155. Thus, the embodiment has a technical effect of preventing electric field concentration by disposing the well 130 to cover a lower edge region of the trench gate.

[0085] Also, in the embodiment, a first conductivity type doping region 140, a second ion implantation region 135, and a source contact layer 145 are disposed on the second conductivity type well 130. On the other hand, the doping region 140 is disposed on the side surface of the gate insulating layer 155. The doping region 140 is disposed so as to extend to the source contact layer 145 along the gate insulating layer 155.

[0086] Further, the lower surface of the doping region 140 can be positioned higher than the lower surfaces of the gate 160 and the gate insulating layer 155. Also, the depth of the doping region 140 is formed shallower than the depth of the gate 160. Also, the vertical thickness of the doping region 140 may be 1 / 2 or more of the vertical thickness of the gate 160, but is not limited thereto. According to the embodiment, by forming the channel region such that the vertical depth of the doping region 140 is 1 / 2 or more of the vertical depth of the gate 160, there is an effect that the electric field can be surely controlled as compared with the existing trench structure.

[0087] Thereby, a channel is formed between the lower surface of the doping region 140 and the lower surface of the well 130 in the embodiment. For example, a channel region is formed in the well 130 region in contact with the gate insulating layer 155.

[0088] On the other hand, the region formed at the side portion of the gate 160 in the doping region 140 is formed by an epitaxial regrowth process instead of an implant process. Thereby, the embodiment can accurately control the depth of the doping region 140. By accurately controlling the depth of the doping region 140, the embodiment has a special technical effect that the length of the channel can be accurately controlled.

[0089] Also, the embodiment has a technical effect of preventing damage generated when forming the doping region. For example, the embodiment can prevent damage that may occur in the implant process by forming the second doping region by an epitaxial regrowth process instead of an implant process without a separate P-shield process.

[0090] In addition, the embodiment has a technical effect of preventing electric field concentration in the lower edge region of the trench gate. For example, in the embodiment, the well is arranged to cover the lower edge region of the trench gate, thereby preventing electric field concentration in the lower edge region of the trench gate.

[0091] Hereinafter, with reference to FIGS. 4a to 4g, the manufacturing process of the power semiconductor device according to the first embodiment will be described, and the technical features of the embodiment will be described in detail.

[0092] Referring to FIG. 4a, a first conductivity type epitaxial layer 117 can be formed on a substrate 110.

[0093] The substrate 110 and the epitaxial layer 117 can include, but are not limited to, SiC (Silicon Carbide).

[0094] For example, the substrate 110 and the epitaxial layer 117 can include a 4H-SiC material, but are not limited thereto. For example, the substrate 110 and the epitaxial layer 117 can include 3C-SiC or 6H-SiC.

[0095] In addition, the epitaxial layer 117 can include a plurality of layers having different concentrations and can have the function of a current spreading layer (CSL).

[0096] For example, the epitaxial layer 117 can include a first conductivity type buffer layer (not shown) and a first conductivity type drift layer (not shown).

[0097] In addition, the first conductivity type may be N type, and the second conductivity type may be P type, but is not limited thereto.

[0098] Also, a first conductivity type first doping region 140a and a second conductivity type ion implantation region 135 are formed on the epi-layer 117 by an implantation process. The first doping region 140a can be located between the second conductivity type ion implantation regions 135. The length direction of the first conductivity type first doping region 140a may be a horizontal direction.

[0099] For example, the first doping region 140a can function as a source region of the first conductivity type, and an N-type dopant such as nitrogen or phosphorus is about 1×10 19 cm -3 ~ about 3×10 20 cm -3 It can be formed by ion implantation at a concentration of.

[0100] Also, the ion implantation region 135 can be in contact with the source electrode hereafter. Also, the ion implantation region 135 can function to maintain the potential of the second conductivity type well 130 and can function as a body diode.

[0101] Next, referring to FIG. 4b, after arranging a first mask 180a on the first doping region 140a, a second conductivity type well 130 can be formed by an implantation process. The first mask 180a may be a hard mask such as oxide, but is not limited thereto. The well 130 has a P-type dopant of about 1×1016 cm -3 ~ about 2×10 19 cm -3 It may be ion implanted at a concentration of. For example, Al (aluminum), boron, etc. may be implanted, but is not limited thereto. The well 130 can include a plurality of regions arranged separately with the epi-layer 117 interposed therebetween by the first mask 180a.

[0102] Next, referring to FIG. 4c, after the second mask 180b is disposed on the well 130, the first trench 170 can be formed by etching. The second mask 180b may be a hard mask such as an oxide, but is not limited thereto.

[0103] For example, a part of the first doping region 140a, the well 130, and the epitaxial layer 117 can be removed to form the first trench 170. The depth of the first trench 170 may be shallower than the depth of the well 130.

[0104] Next, referring to FIG. 4d, a second doping region 140b of the first conductivity type can be formed in the first trench 170. The second doping region 140b is formed by epitaxial regrowth in the first trench 170. Thereafter, a planarization process can be performed to make the heights of the upper surfaces of the second doping region 140b and the first doping region 140a the same. The doping concentration of the second doping region 140b may be substantially the same as the doping concentration of the first doping region 140a, but is not limited thereto.

[0105] For example, the second doping region 140b is formed by epitaxial regrowth so as to contain an N-type dopant such as nitrogen or phosphorus at a concentration of about 1×10 19 cm -3 ~about 3×10 20 cm -3 However, it is not limited thereto.

[0106] In an embodiment, since the second doping region 140b is formed by an epitaxial regrowth process instead of an implant process, the depth of the second doping region 140b can be controlled.

[0107] Referring to FIG. 3, a channel is formed between the well 130 in contact with the gate insulating layer 155. By being able to control the depth of the second doping region 140b, there is a technical effect that the length of the channel can be precisely controlled.

[0108] On the one hand, when the doping region is formed by an implant process, damage accumulates due to high energy. In the case of SiC (Silicon Carbide), in order to recover this, a high-temperature annealing process of about 1700°C to 1800°C is inevitable, but it is impossible to completely recover even with this. On the other hand, in the embodiment, since the second doping region 140b is formed by an epitaxial regrowth process instead of an implant process, there is a technical effect of preventing irreparable damage generated by the implant process.

[0109] Next, referring to FIG. 4e, after the third mask 180c is disposed on the doping region 140, a part of the second doping region 140b can be etched to form the second trench 172. A part of the epitaxial layer 117 is removed when the second trench 172 is formed. The third mask 180c may be a hard mask such as an oxide, but is not limited thereto.

[0110] The bottom surface of the second trench 172 can be positioned higher than the bottom surface of the well 130. Also, the bottom surface of the second trench 172 can be positioned lower than the lower surface of the second doping region 140b.

[0111] The third mask 180c can have an inverted form of the first mask 180a used above. Thereby, the side surface of the third mask 180c is aligned vertically with one side surface of the well 130, but is not limited thereto. Thereby, the well 130 is removed and a part of the side surface is exposed when the second trench 172 is formed, but is not limited thereto.

[0112] In an embodiment, the first length L1 of the first conductivity type second doping region 140b exposed by the second trench 172 may be longer than the second length L2 of the second conductivity type well 130 exposed by the second trench 172. For example, the second length L2 of the second conductivity type well 130 exposed by the second trench 172 may have about 40% to 70% of the overall depth of the second trench 172, but is not limited thereto.

[0113] The second length L2 region of the second conductivity type well 130 exposed by the second trench 172 can function as a channel region.

[0114] According to the embodiment, there is a technical effect that the second conductivity type well 130 is arranged to cover the lower edge region of the trench gate, and thus electric field concentration is prevented in the lower edge region of the trench gate.

[0115] Thereby, in the embodiment, the second conductivity type well 130 can be formed to cover the lower edge region of the trench gate without a separate P-shield process. Thus, since a large energy ion implantation process is unnecessary, there is a technical effect that damage to the element can be prevented and the reliability of the element can be improved.

[0116] Next, referring to FIG. 4f, a JFET region 150 can be formed under the second trench 172 by an implant process, but is not limited thereto. The JFET region 150 can be located between a plurality of second conductivity type wells 130. Also, the lower surface of the JFET region 150 can be located lower than the lower surface of the second conductivity type well 130.

[0117] Next, referring to FIG. 4g, after forming the gate insulating layer 155 on the second trench, the gate 160 can be formed inside the gate insulating layer 155. The gate insulating layer 155 may be a thermal oxide film or a deposited oxide film, but is not limited thereto. Also, the lower surfaces of the gate 160 and the gate insulating layer 155 can be positioned lower than the lower surface of the second doping region 140b. Also, the lower surfaces of the gate 160 and the gate insulating layer 155 can be positioned higher than the lower surface of the well 130. Also, an insulating layer 165 is formed on the gate 160.

[0118] Also, a source contact layer 145 is formed on the ion implantation region 135 of the second conductivity type, and a source electrode (not shown) is formed on the source contact layer 145 in a later process.

[0119] Next, an insulating layer 165 is formed on the gate 160 and the gate insulating layer 155. The insulating layer 165 can be made of an oxide film, a nitride film, or the like, but is not limited thereto.

[0120] Also, a source electrode (not shown) can be formed on the source contact layer 145. The source electrode is formed so as to cover the insulating layer 165. The source electrode can be made of Al or the like, but is not limited thereto. Also, the source electrode can further include a barrier metal layer.

[0121] Also, a drain electrode 115 is formed on the lower side of the substrate 110. The drain electrode 115 can include a Ti layer, a Ni layer, a Ti / Ni / Ag metal including an Ag layer, or NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0122] Thereby, in the embodiment, current can flow through the drain electrode 115, the substrate 110, the epitaxial layer 117 of the first conductivity type, the well 130 of the second conductivity type, the doping region 140 of the first conductivity type, and the source electrode (not shown).

[0123] Next, FIG. 5 is a cross-sectional view of a power semiconductor device according to the second embodiment. The second embodiment can adopt the technical features of the first embodiment. For example, in the second embodiment, the second conductivity type well 130 surrounds the lower edge region of the gate 160 and the gate insulating layer 155, thereby having a technical effect of preventing electric field concentration in the lower edge region of the gate.

[0124] Subsequently, referring to FIG. 5, in the second embodiment, the first conductivity type doping region 140 may include a first conductivity type first doping region 140a and a first conductivity type third doping region 140c.

[0125] At this time, the doping concentration of the first doping region 140a may be different from the doping concentration of the third doping region 140c. Specifically, the doping concentration of the third doping region 140c may be lower than the doping concentration of the first doping region 140a. The first doping region 140a is disposed under the source contact layer 145. Also, one side surface of the third doping region 140c can overlap perpendicularly with one side surface of the insulating layer 165. The third doping region 140c does not have to overlap perpendicularly with the source contact layer 145.

[0126] In the second embodiment, the third doping region 140c is formed by epitaxial regrowth in the first trench 170 (see FIG. 4d). Subsequently, a planarization process can be performed to form the third doping region 140c and the upper surface of the first doping region 140a to have the same height.

[0127] At this time, the doping concentration of the third doping region 140c may be lower than the doping concentration of the first doping region 140a.

[0128] For example, the first doping region 140a has an N-type dopant such as nitrogen or phosphorus of about 1×10 19 cm -3 ~ about 3×10 20 cm -3It may be formed by ion implantation at the concentration of

[0129] On the other hand, the third doping region 140c is formed by epitaxial regrowth so as to contain an N-type dopant such as nitrogen or phosphorus at a concentration of about 1×10 17 cm -3 ~ about 3×10 19 cm -3 , but is not limited thereto.

[0130] According to the second embodiment, the third doping region 140c is disposed on the side portion of the gate 160, and is formed to have a doping concentration lower than that of the first doping region 140a in contact with the source contact layer 145, so that the saturation current is reduced.

[0131] Specifically, in the second embodiment, the current passes through the doping region 140 in which the doping concentration changes in the vertical direction from the side surface of the trench gate, so that the saturation current is reduced.

[0132] Specifically, by controlling the sheet resistance in the third doping region 140c doped lower than the first doping region 140a to relatively increase, the on-resistance (Ron) in the third doping region 140c is controlled to relatively increase, and the saturation current is reduced.

[0133] Therefore, the second embodiment has a technical effect that the SCWT (Short Circuit Withstand Time) is increased by reducing the saturation current, and the reliability is improved during high-speed switching.

[0134] The power semiconductor device according to the embodiment has a technical effect of preventing electric field concentration in the lower edge region of the trench gate.

[0135] For example, in the embodiment, by arranging the p-well to cover the lower edge region of the trench gate, electric field concentration is prevented in the lower edge region of the trench gate.

[0136] In addition, the embodiment has a technical effect of being able to control the channel length. For example, in the embodiment, by forming the first conductivity type second doping region by an epitaxial regrowth process instead of an implant process, the doping concentration is more uniformly controlled compared to the ion implantation process, thereby enabling accurate control of the depth of the doping region and precise control of the channel length.

[0137] For example, there is a special technical effect that the channel length can be precisely controlled by uniformly controlling the deviation of the doping concentration within about 5 to 10% in the first conductivity type second doping region.

[0138] In addition, the embodiment has a technical effect of being able to prevent damage generated when forming the doping region. For example, in the embodiment, by forming the first conductivity type second doping region by an epitaxial regrowth process instead of an implant process without a separate P-shield process, damage that may occur in the implant process can be prevented.

[0139] In addition, the embodiment has a technical effect of being able to improve the reliability of the element during high-speed switching.

[0140] For example, in the embodiment, by forming the doping concentration of the first conductivity type second doping region arranged on the side of the trench gate to be lower than the doping concentration of the first conductivity type first doping region, the saturation current decreases, the SCWT (Short Circuit Withstand Time) increases, and the reliability of the element during high-speed switching is improved.

[0141] Although the embodiments of the present invention have been described above with reference to the embodiments, those having ordinary knowledge in the art should easily understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the following claims.

Explanation of Reference Numerals

[0142] 110: Substrate 115: Drain electrode 117: Epitaxial layer of the first conductivity type 130: Well of the second conductivity type 135: Ion implantation region of the second conductivity type 140: Doping region of the first conductivity type 140a: First doping region of the first conductivity type 140b: Second doping region of the first conductivity type 145: Source contact layer 150: JFET region 155: Gate insulating layer 160: Gate 165: Insulating layer 170: First trench 172: Second trench 180a, 180b, 180c: First, second, and third masks

Claims

1. A substrate; a first conductivity type epitaxial layer disposed on the substrate; a plurality of second conductivity type wells spaced apart from one another on the epitaxial layer; a gate disposed between the plurality of second conductivity type wells and a gate insulating layer disposed to cover at least a portion of the gate; a first conductive type doped region disposed on a side of the gate insulating layer; The first conductive type doped region is a first doped region of a first conductivity type having a first horizontal width; a second doped region of the first conductivity type disposed below the first doped region of the first conductivity type and having a second horizontal width smaller than the first horizontal width.

2. The power semiconductor device according to claim 1 , wherein a bottom surface of the first conductive type second doping region is located higher than a bottom surface of the gate.

3. The power semiconductor device according to claim 1 , wherein a lower edge region of the gate insulating layer contacts the plurality of second conductive type wells.

4. The power semiconductor device according to claim 1 , wherein bottom surfaces of the plurality of second conductive type wells are located lower than a bottom surface of the gate insulating layer.

5. the first conductive type doping region and the first conductive type epitaxial layer are spaced apart from each other; The power semiconductor device according to claim 1 , wherein the plurality of second conductivity type wells are located between the first conductivity type doping region and the first conductivity type epitaxial layer.

6. The power semiconductor device of claim 1 , wherein a doping concentration of the first conductive type second doped region is substantially the same as a doping concentration of the first conductive type first doped region.

7. The power semiconductor device of claim 1 , wherein a doping concentration of the first conductive type second doped region is lower than a doping concentration of the first conductive type first doped region.

8. The power semiconductor device according to claim 1 , wherein the first conductivity type second doping region is formed by an epitaxial regrowth process.

9. The power semiconductor device of claim 1 , wherein the first conductivity type second doping region does not vertically overlap a source contact layer.

10. A power conversion device comprising the power semiconductor device according to claim 1 .

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