Detector

Abstract

To provide a detector capable of achieving a high numerical aperture while suppressing degradation in location accuracy of detection.SOLUTION: A detector comprises a substrate, a plurality of photoelectric converters mounted on the substrate and each including semiconductor layers, a plurality of transistors provided for the respective photoelectric converters, and a plurality of signal lines. Each detection device includes the plurality of transistors. A first signal line of the plurality of signal lines is arranged between the photoelectric converter of a first detection device and the photoelectric converter of a second detection device adjacent to a first side of the first detection device in a first direction, and connected to the first detection device and the second detection device. A second signal line of the plurality of signal lines is arranged between the photoelectric converter of the first detection device and the photoelectric converter of a third detection device adjacent to the other side of the first detection device in the first direction, and connected to the first detection device and the third detection device.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a detection device.

Background Art

[0002] An optical detection device in which a plurality of photoelectric conversion elements such as PIN photodiodes are arranged on a substrate is known. Such an optical detection device is used as a biological sensor for detecting biological information, such as a fingerprint sensor or a vein sensor. The plurality of photoelectric conversion elements are arranged at intervals with an arrangement pitch corresponding to the detection resolution.

[0003] Patent Document 1 describes a solid-state imaging device including a photodiode and a plurality of transistors for each pixel. In the solid-state imaging device described in Patent Document 1, amplification transistors formed in each pixel are provided symmetrically with respect to a signal line connected to the amplification transistors. That is, in Patent Document 1, the signal line is shared between adjacent pixels.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] An optical detection device is required to increase the aperture ratio. When the configuration described in Patent Document 1 is applied to an optical detection device, although the aperture ratio increases, the photoelectric conversion elements and the plurality of transistors are arranged symmetrically with respect to the signal line. For this reason, the arrangement pitch of the photoelectric conversion elements may not be constant. As a result, the detection position accuracy may decrease.

[0006] An object of the present invention is to provide a detection device capable of improving the aperture ratio while suppressing a decrease in detection position accuracy.

Means for Solving the Problem

[0007] The detection device according to one aspect of the present invention includes a substrate, a plurality of photoelectric conversion elements provided on the substrate and including a semiconductor layer having a photovoltaic effect, a plurality of transistors provided corresponding to each of the plurality of photoelectric conversion elements, and a plurality of photoelectric conversion elements provided between the plurality of photoelectric conversion elements adjacent to each other in a first direction and extending in a second direction intersecting the first direction, and supplying signals to any one of the photoelectric conversion elements or the plurality of transistors. One detection element is configured to include the photoelectric conversion element and a plurality of the transistors arranged adjacent to the photoelectric conversion element in the second direction. Among the plurality of signal lines, a first signal line is disposed between the photoelectric conversion element of the first detection element and the photoelectric conversion element of the second detection element adjacent to one side of the first detection element in the first direction, and is connected to the first detection element and the second detection element. Among the plurality of signal lines, a second signal line is disposed between the photoelectric conversion element of the first detection element and the photoelectric conversion element of the third detection element adjacent to the other side of the first detection element in the first direction, and is connected to the first detection element and the third detection element.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

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Figure 9

DETAILED DESCRIPTION OF THE INVENTION

[0009] The mode (embodiment) for carrying out the invention will be described in detail with reference to the drawings. The present invention is not limited by the content described in the following embodiments. Further, the constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the constituent elements described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each figure, elements that are the same as those described above with respect to the previously shown figures may be given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In this specification and the claims, when expressing the mode of arranging another structure on a certain structure, when simply described as "on", unless otherwise specified, it includes both the case of arranging another structure directly on a certain structure in contact with it and the case of arranging another structure above a certain structure through yet another structure.

[0011] (Embodiment) FIG. 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device-equipped lighting device having a detection device according to the first embodiment. As shown in FIG. 1, the detection device-equipped lighting device 120 includes a detection device 1, a lighting device 121, and a cover glass 122. In the direction perpendicular to the surface of the detection device 1, the lighting device 121, the detection device 1, and the cover glass 122 are laminated in this order.

[0012] The lighting device 121 has a light irradiation surface 121a that irradiates light, and irradiates the light L1 from the light irradiation surface 121a toward the detection device 1. The lighting device 121 is a backlight. The lighting device 121 may be, for example, a so-called side-light type backlight having a light guide plate provided at a position corresponding to the detection area AA and a plurality of light sources arranged at one end or both ends of the light guide plate. As the light source, for example, a light emitting diode (LED: Light Emitting Diode) that emits light of a predetermined color is used. Further, the lighting device 121 may be a so-called direct-lit type backlight having a light source (for example, an LED) provided directly below the detection area AA. Further, the lighting device 121 is not limited to a backlight, and may be provided on the side or above the detection device 1, and may irradiate the light L1 from the side or above the finger Fg.

[0013] The detection device 1 is provided to face the light irradiation surface 121a of the lighting device 121. The light L1 irradiated from the lighting device 121 passes through the detection device 1 and the cover glass 122. The detection device 1 is, for example, a light reflection type biosensor, and can detect the unevenness (for example, fingerprints) on the surface of the finger Fg by detecting the light L2 reflected on the surface of the finger Fg. Alternatively, in addition to detecting fingerprints, the detection device 1 may detect information related to the living body by detecting the light L2 reflected inside the finger Fg. Information related to the living body is, for example, a blood vessel image such as a vein, a pulse, a pulse wave, or the like. The color of the light L1 from the lighting device 121 may be varied according to the detection target.

[0014] The cover glass 122 is a member for protecting the detection device 1 and the lighting device 121, and covers the detection device 1 and the lighting device 121. The cover glass 122 is, for example, a glass substrate. Note that the cover glass 122 is not limited to a glass substrate, and may be a resin substrate or the like. Further, the cover glass 122 may not be provided. In this case, a protective layer is provided on the surface of the detection device 1, and the finger Fg is in contact with the protective layer of the detection device 1.

[0015] The detection device 120 with a lighting device may be provided with a display panel instead of the lighting device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode) or an inorganic EL display (micro LED, mini LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using a liquid crystal element as a display element, or an electrophoretic display panel (EPD: Electrophoretic Display) using an electrophoretic element as a display element. Even in this case, based on the display light irradiated from the display panel passing through the detection device 1 and the light L2 reflected by the finger Fg, information regarding the fingerprint or living body of the finger Fg can be detected.

[0016] FIG. 2 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device according to a modified example. As shown in FIG. 2, in the detection device 120 with a lighting device, in a direction perpendicular to the surface of the detection device 1, the detection device 1, the lighting device 121, and the cover glass 122 are laminated in this order. Also in this modified example, a display panel such as an organic EL display panel can be adopted as the lighting device 121.

[0017] The light L1 irradiated from the lighting device 121 passes through the cover glass 122 and is then reflected by the finger Fg. The light L2 reflected by the finger Fg passes through the cover glass 122 and further passes through the lighting device 121. The detection device 1 can detect information regarding a living body such as fingerprint detection by receiving the light L2 that has passed through the lighting device 121.

[0018] FIG. 3 is a plan view showing a detection device according to the first embodiment. As shown in FIG. 3, the detection device 1 includes a substrate 21, a sensor unit 10, a first gate line driving circuit 15A, a second gate line driving circuit 15B, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

[0019] The control board 101 is electrically connected to the substrate 21 via the wiring board 110. The wiring board 110 is, for example, a flexible printed circuit board or a rigid board. A detection circuit 48 is provided on the wiring board 110. A control circuit 102 and a power supply circuit 103 are provided on the control board 101. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 supplies voltage signals such as the power supply potential Vsf and the reference potential Vcom (see FIG. 5) to the sensor unit 10, the first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16.

[0020] The substrate 21 has a detection region AA and a peripheral region GA. The detection region AA is a region that overlaps with the plurality of detection elements 3 included in the sensor unit 10. The peripheral region GA is a region outside the detection region AA and does not overlap with the detection elements 3. That is, the peripheral region GA is a region between the outer periphery of the detection region AA and the end of the substrate 21. The first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 are provided in the peripheral region GA.

[0021] The plurality of detection elements 3 of the sensor unit 10 are each an optical sensor having a photoelectric conversion element 30. The photoelectric conversion element 30 is a photodiode and outputs an electrical signal corresponding to the light irradiated thereto. More specifically, the photoelectric conversion element 30 is a PIN (Positive Intrinsic Negative) photodiode. The detection elements 3 are arranged in a matrix in the detection region AA. The photoelectric conversion elements 30 included in the plurality of detection elements 3 perform detection according to gate drive signals (for example, a reset control signal RST and a read control signal RD) supplied from the first gate line drive circuit 15A and the second gate line drive circuit 15B. The plurality of photoelectric conversion elements 30 output electrical signals corresponding to the light irradiated thereto to the signal line selection circuit 16 as detection signals Vdet. The detection device 1 detects information regarding a living body based on the detection signals Vdet from the plurality of photoelectric conversion elements 30.

[0022] The first gate line drive circuit 15A, the second gate line drive circuit 15B, and the signal line selection circuit 16 are provided in the peripheral region GA. Specifically, the first gate line drive circuit 15A and the second gate line drive circuit 15B are provided in a region extending along the second direction Dy in the peripheral region GA. The signal line selection circuit 16 is provided in a region extending along the first direction Dx in the peripheral region GA and is provided between the sensor unit 10 and the detection circuit 48. The first gate line drive circuit 15A and the second gate line drive circuit 15B are arranged with the detection region AA sandwiched therebetween in the first direction Dx. However, it is not limited thereto, and the first gate line drive circuit 15A and the second gate line drive circuit 15B may be formed as one circuit and arranged along one side of the detection region AA.

[0023] Note that the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21 and is a direction orthogonal to the first direction Dx. Note that the second direction Dy may intersect without being orthogonal to the first direction Dx. Further, the third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy and is the normal direction of the substrate 21.

[0024] FIG. 4 is a block diagram showing a configuration example of the detection device according to the first embodiment. As shown in FIG. 4, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Part or all of the functions of the detection control circuit 11 are included in the control circuit 102. Also, part or all of the functions other than the detection circuit 48 in the detection unit 40 are included in the control circuit 102.

[0025] The detection control circuit 11 is a circuit that supplies control signals to the first gate line driving circuit 15A, the second gate line driving circuit 15B, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals such as a start signal STV and a clock signal CK to the first gate line driving circuit 15A and the second gate line driving circuit 15B. Also, the detection control circuit 11 supplies various control signals such as a selection signal ASW to the signal line selection circuit 16.

[0026] The first gate line driving circuit 15A and the second gate line driving circuit 15B are circuits that drive a plurality of gate lines (read control scanning line GLrd, reset control scanning line GLrst (see FIG. 5)) based on various control signals. The first gate line driving circuit 15A and the second gate line driving circuit 15B sequentially or simultaneously select a plurality of gate lines, and supply a gate drive signal (for example, a reset control signal RST, a read control signal RD) to the selected gate line. Thereby, the first gate line driving circuit 15A and the second gate line driving circuit 15B select a plurality of photoelectric conversion elements 30 connected to the gate line.

[0027] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal lines SL (see FIG. 5). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL and the detection circuit 48 based on the selection signal ASW supplied from the detection control circuit 11. Thereby, the signal line selection circuit 16 outputs the detection signal Vdet of the photoelectric conversion element 30 to the detection unit 40. Note that the signal line selection circuit 16 may be omitted. In this case, the output signal line SL may be directly connected to the detection circuit 48.

[0028] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a memory circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 to operate synchronously based on the control signal supplied from the detection control circuit 11.

[0029] The detection circuit 48 is, for example, an analog front end circuit (AFE, Analog Front End). The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplification circuit 42 and an A / D conversion circuit 43. The detection signal amplification circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplification circuit 42 into a digital signal.

[0030] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg contacts or approaches the detection surface, the signal processing circuit 44 can detect the unevenness of the surface of the finger Fg and the palm based on the signal from the detection circuit 48. Also, the signal processing circuit 44 may detect information about the living body based on the signal from the detection circuit 48. Information about the living body is, for example, the blood vessel image, pulse wave, pulse, blood oxygen saturation, etc. of the finger Fg and the palm.

[0031] The memory circuit 46 temporarily stores the signal calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0032] The coordinate extraction circuit 45 is a logic circuit that obtains detection coordinates of unevenness on the surface of the finger Fg or the like when contact or proximity of the finger Fg is detected in the signal processing circuit 44. Further, the coordinate extraction circuit 45 is a logic circuit that obtains detection coordinates of blood vessels of the finger Fg or the palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from each detection element 3 of the sensor unit 10 to generate two-dimensional information indicating the shape of the unevenness on the surface of the finger Fg or the like. Note that the coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0033] Next, a circuit configuration example and an operation example of the detection device 1 will be described. FIG. 5 is a circuit diagram showing a plurality of detection elements. As shown in FIG. 5, the detection element 3 includes a photoelectric conversion element 30, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. Further, the detection element 3 is provided with a reset control scan line GLrst and a readout control scan line GLrd as detection drive lines (gate lines), and an output signal line SL as a wiring for signal readout.

[0034] The reset control scan line GLrst, the readout control scan line GLrd, and the output signal line SL are each connected to a plurality of detection elements 3. Specifically, the reset control scan line GLrst and the readout control scan line GLrd extend in the first direction Dx (see FIG. 3) and are connected to a plurality of detection elements 3 arranged in the first direction Dx. Further, the output signal line SL extends in the second direction Dy and is connected to a plurality of detection elements 3 arranged in the second direction Dy. The output signal line SL is a wiring to which signals from a plurality of transistors (readout transistor Mrd and source follower transistor Msf) are output.

[0035] The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are provided corresponding to one photoelectric conversion element 30. The plurality of transistors included in the detection element 3 are each composed of an n-type TFT (Thin Film Transistor). However, the present invention is not limited to this, and each transistor may be composed of a p-type TFT.

[0036] A reference potential Vcom is applied to the anode of the photoelectric conversion element 30. The cathode of the photoelectric conversion element 30 is connected to the node N1. The node N1 is connected to one of the source or drain of the reset transistor Mrst and the gate of the source follower transistor Msf. When the photoelectric conversion element 30 is irradiated with light, the signal (charge) output from the photoelectric conversion element 30 is accumulated in the capacitive element formed at the node N1.

[0037] The gate of the reset transistor Mrst is connected to the reset control scan line GLrst. A reset potential Vrst is supplied to the other of the source or drain of the reset transistor Mrst. When the reset transistor Mrst is turned on (conductive state) in response to the reset control signal RST supplied from the first gate line drive circuit 15A, the potential of the node N1 is reset to the reset potential Vrst. The reference potential Vcom has a potential lower than the reset potential Vrst, and the photoelectric conversion element 30 is driven in reverse bias.

[0038] The source follower transistor Msf is connected between the terminal to which the power supply potential Vsf is supplied and the readout transistor Mrd (node N2). The gate of the source follower transistor Msf is connected to the node N1. A signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30 is supplied to the gate of the source follower transistor Msf. Thereby, the source follower transistor Msf outputs a signal voltage corresponding to the signal (charge) generated in the photoelectric conversion element 30 to the readout transistor Mrd.

[0039] The readout transistor Mrd is connected between the source (node N2) of the source follower transistor Msf and the output signal line SL. The gate of the readout transistor Mrd is connected to the readout control scan line GLrd. When the readout transistor Mrd is turned on in response to the readout control signal RD supplied from the second gate line drive circuit 15B, the signal output from the source follower transistor Msf, that is, the signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30 is output to the output signal line SL as the detection signal Vdet.

[0040] Note that the circuit of one detection element 3 is not limited to a configuration having three transistors, namely, the reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd. The detection element 3 may have two transistors or may have four or more transistors.

[0041] FIG. 6 is a timing waveform diagram showing an operation example of the detection element. As shown in FIG. 6, the detection element 3 executes detection in the order of the reset period Prst, the accumulation period Pch, and the readout period Pdet. The power supply circuit 103 supplies the reference potential Vcom to the anode of the photoelectric conversion element 30 over the reset period Prst, the accumulation period Pch, and the readout period Pdet.

[0042] The control circuit 102 sets the reset control signal RST supplied to the reset control scan line GLrst to high (high-level voltage) at time t0, and the reset period Prst starts. In the reset period Prst, the reset transistor Mrst is turned on (conducting state), and the potential of node N1 rises to the potential of the reset potential Vrst. Also, since the readout transistor Mrd is off (non-conducting state), the source of the source follower transistor Msf is charged by the power supply potential Vsf, and the potential of node N2 rises.

[0043] At time t1, the control circuit 102 sets the read control signal RD supplied to the read control scan line GLrd to high (high-level voltage). As a result, the read transistor Mrd turns on (conducting state), and the potential of node N2 becomes (Vrst - Vthsf). Here, Vthsf is the threshold voltage Vthsf of the source follower transistor Msf.

[0044] At time t2, the control circuit 102 sets the reset control signal RST to low (low-level voltage), the reset period Prst ends, and the accumulation period Pch starts. During the accumulation period Pch, the reset transistor Mrst turns off (non-conducting state). The potential of node N1 is accumulated with a signal corresponding to the light irradiated on the photoelectric conversion element 30 and decreases to (Vrst - Vphoto). Here, Vphoto is a signal (voltage fluctuation component) corresponding to the light irradiated on the photoelectric conversion element 30.

[0045] The potential of the detection signal Vdet1 output from the output signal line SL at time t3 is (Vrst - Vthsf - Vrdon). Vrdon is the voltage drop caused by the on-resistance of the read transistor Mrd.

[0046] At time t3, the control circuit 102 sets the read control signal RD to low (low-level voltage). As a result, the read transistor Mrd turns off (non-conducting state), and the potential of node N2 remains constant at (Vrst - Vthsf). Also, a load is applied so that the potential of the detection signal Vdet output from the output signal line SL becomes low (low-level voltage).

[0047] At time t4, the control circuit 102 sets the read control signal RD to high (high-level voltage). As a result, the read transistor Mrd turns on (conducting state), the accumulation period Pch ends, and the read period Pdet starts. The potential of node N2 changes to (Vrst - Vthsf - Vphoto) according to the signal Vphoto. The potential of the detection signal Vdet2 output during the read period Pdet decreases by the amount of the signal Vphoto from the potential of the detection signal Vdet1 acquired at time t3 and becomes (Vrst - Vthsf - Vrdon - Vphoto).

[0048] The detection unit 40 can detect the light irradiated on the photoelectric conversion element 30 based on the difference signal (Vphoto) between the detection signal Vdet1 at time t3 and the detection signal Vdet2 at time t5. In FIG. 6, an operation example of one detection element 3 is shown. However, the first gate line driving circuit 15A and the second gate line driving circuit 15B can detect with the detection elements 3 in the entire detection region AA by sequentially scanning the reset control scanning line GLrst and the read control scanning line GLrd in a time-division manner, respectively.

[0049] Next, the planar configuration and cross-sectional configuration of the detection element 3 will be described. FIG. 7 is a plan view showing a plurality of detection elements. As shown in FIG. 7, the plurality of detection elements 3 are arranged in the first direction Dx and the second direction Dy. The plurality of detection elements 3 arranged in the first direction Dx are represented as detection elements 3(m), 3(m + 1), 3(m + 2), 3(m + 3). However, when there is no need to distinguish and describe the detection elements 3(m), 3(m + 1), 3(m + 2), 3(m + 3), they are simply represented as detection element 3. Note that the output signal line SL, the read control scanning line GLrd, and the reset control scanning line GLrst are also represented in the same way.

[0050] One detection element 3 is connected to two gate lines (read control scanning line GLrd, reset control scanning line GLrst) and four signal lines (output signal line SL, power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom), and includes a part thereof. The read control scanning line GLrd and the reset control scanning line GLrst extend in the first direction Dx and are arranged side by side in the second direction Dy. The plurality of signal lines (output signal line SL, power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom) extend in the second direction Dy and are arranged side by side in the first direction Dx.

[0051] In the example shown in FIG. 7, the detection element 3 is an area surrounded by two gate lines (reset control scanning lines GLrst(N), GLrst(N + 1)) and two signal lines (power supply signal line SLsf, reference signal line SLcom).

[0052] Further, one detection element 3 includes a photoelectric conversion element 30 and a plurality of transistors (reset transistor Mrst, readout transistor Mrd, and source follower transistor Msf) arranged adjacent to the photoelectric conversion element 30 in the second direction Dy.

[0053] The photoelectric conversion element 30 is provided in a region surrounded by a readout control scan line GLrd, a reset control scan line GLrst, a reset signal line SLrst, and an output signal line SL. The plurality of transistors are arranged between the readout control scan line GLrd and the reset control scan line GLrst adjacent to each other in the second direction Dy. In FIG. 7, the region where the plurality of transistors are formed is indicated by a dotted line as region MA.

[0054] Here, three signal lines (power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom) excluding the output signal line SL are respectively provided between two adjacent photoelectric conversion elements 30 in the first direction Dx, extend in the second direction Dy intersecting the first direction Dx, and are wirings for supplying signals to either the photoelectric conversion element 30 or the plurality of transistors. For example, the output signal line SL(m), the reference signal line SLcom, and the output signal line SL(m + 1) are arranged between two adjacent photoelectric conversion elements 30 in the first direction Dx. Also, the reset signal line SLrst, the power supply signal line SLsf, and the reset signal line SLrst are arranged between two adjacent photoelectric conversion elements 30 in the first direction Dx. Specifically, the reference signal line SLcom is a wiring for supplying a reference potential Vcom to the photoelectric conversion element 30. The power supply signal line SLsf is a wiring for supplying a power supply potential Vsf to the source follower transistor Msf. The reset signal line SLrst is a wiring for supplying a reset potential Vrst to the reset transistor Mrst.

[0055] The output signal lines SL(m), SL(m + 1), SL(m + 2), and SL(m + 3) are provided corresponding to the detection elements 3(m), 3(m + 1), 3(m + 2), and 3(m + 3), respectively. Among the three signal lines excluding the output signal line SL, two signal lines (for example, the power supply signal line SLsf and the reference signal line SLcom) are connected to the two adjacent detection elements 3 on both sides.

[0056] For example, taking the detection elements 3(m + 1) and 3(m + 2) as an example, among the three signal lines described above, the power supply signal line SLsf (the first signal line) is arranged between the photoelectric conversion element 30 of the detection element 3(m + 1) (the first detection element) and the photoelectric conversion element 30 of the detection element 3(m + 2) (the second detection element) adjacent to the detection element 3(m + 1) in one direction Dx. And the power supply signal line SLsf is connected to the two detection elements 3(m + 1) and 3(m + 2).

[0057] Also, among the three signal lines described above, the reference signal line SLcom (the second signal line) is arranged between the photoelectric conversion element 30 of the detection element 3(m + 1) and the photoelectric conversion element 30 of the detection element 3(m) (the third detection element) adjacent to the detection element 3(m + 1) in the other direction Dx. And the reference signal line SLcom is connected to the two detection elements 3(m) and 3(m + 1).

[0058] Two adjacent detection elements 3 are configured to be inverted with a virtual line parallel to the second direction Dy as the axis of symmetry. For example, the two detection elements 3(m) and 3(m + 1) are symmetric with respect to the reference signal line SLcom. The two detection elements 3(m + 1) and 3(m + 2) are symmetric with respect to the power supply signal line SLsf. The two detection elements 3(m + 2) and 3(m + 3) are symmetric with respect to the reference signal line SLcom.

[0059] More specifically, in the detection element 3(m), in the first direction Dx, the power supply signal line SLsf, the reset signal line SLrst, the photoelectric conversion element 30 (and a plurality of transistors), the output signal line SL(m), and the reference signal line SLcom are arranged in this order. In the detection element 3(m + 1), in the first direction Dx, the reference signal line SLcom, the output signal line SL(m + 1), the photoelectric conversion element 30 (and a plurality of transistors), the reset signal line SLrst, and the power supply signal line SLsf are arranged in this order. Similarly, in the detection elements 3(m + 1) and 3(m + 2), the arrangement order of each signal line is reversed. The reference signal line SLcom is arranged between two adjacent output signal lines SL(m) and SL(m + 1) in the first direction Dx. Also, the power supply signal line SLsf is provided between two adjacent reset signal lines SLrst in the first direction Dx.

[0060] Also, in the detection elements 3 arranged in the first direction Dx, the plurality of photoelectric conversion elements 30 are arranged in the first direction Dx at an equal arrangement pitch Px. The arrangement pitch Px is the interval between virtual lines CL parallel to the second direction Dy passing through the midpoints of the first direction Dx of each photoelectric conversion element 30. Also, the plurality of photoelectric conversion elements 30 each have an outer shape that is symmetric with the virtual line CL as the axis of symmetry. In this specification, when expressed as "equal", it also includes being substantially equal.

[0061] Furthermore, in each detection element 3, the photoelectric conversion element 30 is arranged between two signal lines (for example, the power supply signal line SLsf and the reset signal line SLrst) in the first direction Dx and between two signal lines (for example, the output signal line SL and the reference signal line SLcom). Thereby, in each detection element 3, the region occupied by the four signal lines is symmetric with the virtual line CL as the axis of symmetry.

[0062] As described above, the detection device 1 of the present embodiment can improve the aperture ratio of the detection element 3 by sharing two signal lines among a plurality of signal lines with two adjacent detection elements 3. For example, the aperture ratio increases by about 15% compared to a configuration in which four signal lines (output signal line SL, power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom) are provided for each detection element 3. In the present specification, the aperture ratio refers to the ratio of the area that does not overlap with the wiring and transistors among the areas surrounded by two gate lines (reset control scan lines GLrst(N), GLrst(N+1)) and two signal lines (for example, power supply signal line SLsf, reference signal line SLcom).

[0063] Further, the arrangement pitch Px of the plurality of photoelectric conversion elements 30 is equal, and in each detection element 3, the photoelectric conversion element 30 and the plurality of signal lines are symmetrically configured with the virtual line CL as the axis of symmetry. Thereby, compared with the case where the arrangement pitch Px is formed unevenly, for example, when the photoelectric conversion element 30 and the plurality of transistors are arranged adjacent to each other in the first direction Dx and share the signal line, the detection device 1 can suppress a decrease in the position accuracy of detection.

[0064] FIG. 8 is a plan view showing an enlarged adjacent detection element. FIG. 8 shows an enlarged view of a part of adjacent detection elements 3(m), 3(m+1), and detection element 3(m+2). As shown in FIG. 8, the photoelectric conversion element 30 is configured to include a semiconductor layer having a photovoltaic effect. Specifically, the semiconductor layer of the photoelectric conversion element 30 includes an i-type semiconductor layer 31, an n-type semiconductor layer 32, and a p-type semiconductor layer 33. The i-type semiconductor layer 31, the n-type semiconductor layer 32, and the p-type semiconductor layer 33 are, for example, amorphous silicon (a-Si). Note that the material of the semiconductor layer is not limited to this, and may be polysilicon, microcrystalline silicon, or the like.

[0065] The n-type semiconductor layer 32 is doped with impurities in a-Si to form an n+ region. The p-type semiconductor layer 33 is doped with impurities in polysilicon to form a p+ region. The i-type semiconductor layer 31 is, for example, an undoped intrinsic semiconductor and has lower conductivity than the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

[0066] In adjacent detection elements 3(m) and 3(m + 1), the two p-type semiconductor layers 33 are connected by a connection wiring 33s. The connection wiring 33s is provided to cross a reference signal line SLcom and is connected to the reference signal line SLcom via a contact hole H11. Thereby, two photoelectric conversion elements 30 adjacent to each other in the first direction Dx are electrically connected to one reference signal line SLcom disposed between the two photoelectric conversion elements 30. A reference potential Vcom is supplied to the p-type semiconductor layers 33 of the two photoelectric conversion elements 30 via a common reference signal line SLcom. Also, two photoelectric conversion elements 30 adjacent to each other in the first direction Dx are arranged symmetrically with the reference signal line SLcom interposed therebetween.

[0067] The lower conductive layer 35 is provided in a region overlapping with the semiconductor layer of the photoelectric conversion element 30. In adjacent detection elements 3(m) and 3(m + 1), the two lower conductive layers 35 are connected by a connection wiring 35s. The connection wiring 35s overlaps with the connection wiring 33s, is provided to cross the reference signal line SLcom, and is connected to the reference signal line SLcom via the contact hole H11. Thereby, two lower conductive layers 35 adjacent to each other in the first direction Dx are electrically connected to one reference signal line SLcom. The same reference potential Vcom as that of the p-type semiconductor layer 33 is supplied to the lower conductive layer 35, and the parasitic capacitance between the lower conductive layer 35 and the p-type semiconductor layer 33 can be suppressed. Note that the p-type semiconductor layer 33 (connection wiring 33s) and the lower conductive layer 35 (connection wiring 35s) may be connected to the common reference signal line SLcom at different positions in the second direction Dy.

[0068] The outer shape of the photoelectric conversion element 30 in plan view is symmetrically formed with a virtual line CL as an axis of symmetry. In the detection element 3(m + 1), a recess LA is formed at the lower left corner of the photoelectric conversion element 30. The recess LA is provided so that the output signal line SL(m + 1) and the photoelectric conversion element 30 do not interfere with each other, for example, according to the routing configuration of the output signal line SL(m + 1). A recess RA is formed at a position symmetric to the recess LA at the lower right corner of the photoelectric conversion element 30. Thereby, the symmetry of the photoelectric conversion element 30 is improved, and the detection position accuracy can be improved.

[0069] Further, the upper electrode 34 provided on the photoelectric conversion element 30 is connected to the n-type semiconductor layer 32 via the contact hole H1. The connection wiring 34a is connected to the upper electrode 34 and extends in the second direction Dy. The connection wiring 34a is connected to the node N1 via a contact hole. Thereby, the cathode (n-type semiconductor layer 32) of the photoelectric conversion element 30 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the connection wiring 34a and the node N1. The connection wiring 34a can adopt, for example, a laminated structure of molybdenum (Mo) and aluminum (Al). However, it is not limited thereto, and the connection wiring 34a may be made of other metal materials or may be a translucent conductive material such as ITO.

[0070] The reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd are adjacent to the photoelectric conversion element 30 in the second direction Dy with the readout control scanning line GLrd interposed therebetween. Also, the three transistors are arranged side by side in the first direction Dx.

[0071] The reset transistor Mrst includes a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. One end of the semiconductor layer 61 is connected to the reset signal line SLrst. The other end of the semiconductor layer 61 is connected to the node N1 via the contact hole H3. The portion of the reset signal line SLrst connected to the semiconductor layer 61 functions as the source electrode 62, and the portion of the node N1 connected to the semiconductor layer 61 functions as the drain electrode 63. The gate electrode 64 is formed by branching from the reset control scanning line GLrst in the second direction Dy and intersects the semiconductor layer 61. A channel region is formed in the portion of the semiconductor layer 61 overlapping the gate electrode 64.

[0072] The source follower transistor Msf has a semiconductor layer 65, a source electrode 67, and a gate electrode 68. One end of the semiconductor layer 65 is connected to a connection wiring SLcn via a contact hole. The connection wiring SLcn is electrically connected to a power supply signal line SLsf via a bridge wiring BG and a contact hole H12. The bridge wiring BG is provided in the same layer as, for example, a gate line (such as a read control scanning line GLrd), and intersects a reset signal line SLrst in a plan view. The other end of the semiconductor layer 65 is connected to a semiconductor layer 71 of a read transistor Mrd via a connection wiring CN (node N2).

[0073] The read transistor Mrd has a semiconductor layer 71, a drain electrode 72, and a gate electrode 74. In FIG. 8, the semiconductor layer 71 is shown separately from the connection wiring CN and the semiconductor layer 65, but the semiconductor layer 65, the semiconductor layer 71, and the connection wiring CN are formed from one continuous semiconductor layer. The other end of the semiconductor layer 71 is connected to an output signal line SL. In other words, the portion of the connection wiring CN (node N2) connected to the semiconductor layer 71 functions as a source electrode, and the portion of the output signal line SL connected to the semiconductor layer 71 functions as a drain electrode 72. The two gate electrodes 74 are portions branched from a read control scanning line GLrd. The semiconductor layer 71 intersects the two gate electrodes 74 branched from the read control scanning line GLrd. With such a configuration, the source follower transistor Msf and the read transistor Mrd are connected to the output signal line SL.

[0074] Focusing on adjacent detection elements 3(m) and 3(m + 1), the reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd are arranged symmetrically with the reference signal line SLcom interposed therebetween.

[0075] Focusing on the adjacent detection elements 3(m + 1) and 3(m + 2), two connection wirings SLcn adjacent to each other in the first direction Dx are connected to a common bridge wiring BG and connected to one power supply signal line SLsf via a contact hole H12. That is, two source follower transistors Msf adjacent to each other in the first direction Dx are connected to one power supply signal line SLsf arranged between the two source follower transistors Msf. The two source follower transistors Msf are arranged symmetrically with the power supply signal line SLsf interposed therebetween.

[0076] Note that the planar configuration of the photoelectric conversion element 30 and each transistor shown in FIG. 8 is merely an example and can be changed as appropriate. For example, the configuration is not limited to a configuration in which a plurality of transistors are arranged side by side in the first direction Dx, and some transistors may be provided at different positions such as being adjacent to other transistors in the second direction Dy.

[0077] FIG. 9 is a cross-sectional view taken along line IX-IX' of FIG. 8. Note that in FIG. 9, among the three transistors included in the detection element 3, the cross-sectional configuration of the reset transistor Mrst is shown, but the cross-sectional configurations of the source follower transistor Msf and the readout transistor Mrd are the same as that of the reset transistor Mrst.

[0078] The substrate 21 is an insulating substrate, and for example, a glass substrate such as quartz or non-alkali glass, or a resin substrate such as polyimide is used. The gate electrode 64 is provided on the substrate 21. The insulating films 22 and 23 are provided on the substrate 21 so as to cover the gate electrode 64. The insulating films 22, 23, 24, 25, and 26 are inorganic insulating films, for example, silicon oxide (SiO2), silicon nitride (SiN), or the like.

[0079] The semiconductor layer 61 is provided on the insulating film 23. For the semiconductor layer 61, polysilicon is used, for example. However, the semiconductor layer 61 is not limited thereto, and may be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, a low temperature polysilicon (LTPS), or the like. The reset transistor Mrst has a bottom gate structure in which the gate electrode 64 is provided below the semiconductor layer 61, but may also have a top gate structure in which the gate electrode 64 is provided above the semiconductor layer 61, or a dual gate structure in which the gate electrode 64 is provided above and below the semiconductor layer 61.

[0080] The semiconductor layer 61 includes a channel region 61a, high-concentration impurity regions 61b and 61c, and low-concentration impurity regions 61d and 61e. The channel region 61a is, for example, an undoped intrinsic semiconductor or a low-impurity region, and has lower conductivity than the high-concentration impurity regions 61b and 61c and the low-concentration impurity regions 61d and 61e. The channel region 61a is provided in a region overlapping with the gate electrode 64.

[0081] The high-concentration impurity region 61b is provided in a region connected to the source electrode 62, that is, a region overlapping with the bottom surface of the contact hole H5. The high-concentration impurity region 61c is provided in a region connected to the drain electrode 63, that is, a region overlapping with the bottom surface of the contact hole H3. The low-concentration impurity regions 61d and 61e are respectively provided between the channel region 61a and the high-concentration impurity regions 61b and 61c.

[0082] The insulating films 24 and 25 are provided on the insulating film 23 so as to cover the semiconductor layer 61. The source electrode 62 and the drain electrode 63 are connected to the semiconductor layer 61 through the contact holes H3 and H5 penetrating the insulating films 24 and 25. The source electrode 62 and the drain electrode 63 are made of, for example, a laminated film of TiAlTi or TiAl having a laminated structure of titanium and aluminum.

[0083] The gate electrode 68 of the source follower transistor Msf is provided on the same layer as the gate electrode 64. The drain electrode 63 (node N1) is connected to the gate electrode 68 through a contact hole penetrating through the insulating film 22 to the insulating film 25.

[0084] Also, the connection wiring SLcn is provided on the same layer as the source electrode 62 (reset signal line SLrst) and the drain electrode 63 (node N1).

[0085] Next, the cross-sectional structure of the photoelectric conversion element 30 will be described. The lower conductive layer 35 is provided on the substrate 21 on the same layer as the gate electrode 64. The insulating films 22 and 23 are provided on the lower conductive layer 35. The photoelectric conversion element 30 is provided on the insulating film 23. In other words, the lower conductive layer 35 is provided between the substrate 21 and the p-type semiconductor layer 33. By forming the lower conductive layer 35 of the same material as the gate electrode 64, it functions as a light-shielding layer, and the lower conductive layer 35 can suppress the intrusion of light from the substrate 21 side into the photoelectric conversion element 30.

[0086] In the direction perpendicular to the surface of the substrate 21 (the third direction Dz), the i-type semiconductor layer 31 is provided between the p-type semiconductor layer 33 and the n-type semiconductor layer 32. In this embodiment, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are laminated in this order on the insulating film 23.

[0087] Specifically, the p-type semiconductor layer 33 is provided on the insulating film 23 on the same layer as the semiconductor layer 61. The insulating films 24, 25, and 26 are provided to cover the p-type semiconductor layer 33. Contact holes H13 are provided at positions where the insulating films 24 and 25 overlap the p-type semiconductor layer 33. The insulating film 26 is provided on the insulating film 25 to cover a plurality of transistors including the reset transistor Mrst. The insulating film 26 covers the side surfaces of the insulating films 24 and 25 that form the inner wall of the contact hole H13. Also, a contact hole H14 is provided in the insulating film 26 at a position overlapping the p-type semiconductor layer 33.

[0088] The connection wiring 33s connected to the p-type semiconductor layer 33 and the connection wiring 35s connected to the lower conductive layer 35 each extend to positions overlapping the output signal line SL and the reference signal line SLcom. The contact hole H11 is provided so as to penetrate from the insulating film 22 to the insulating film 25, and the connection wiring 33s and the connection wiring 35s are connected to the reference signal line SLcom via the contact hole H11.

[0089] The i-type semiconductor layer 31 is provided on the insulating film 26 and is connected to the p-type semiconductor layer 33 via a contact hole H14 penetrating the insulating film 24 to the insulating film 26. The n-type semiconductor layer 32 is provided on the i-type semiconductor layer 31.

[0090] The insulating film 27 is provided on the insulating film 26 so as to cover the photoelectric conversion element 30. The insulating film 27 is provided in direct contact with the photoelectric conversion element 30 and the insulating film 26. The insulating film 27 is made of an organic material such as photosensitive acrylic. The insulating film 27 is thicker than the insulating film 26. The insulating film 27 has better step coverage than an inorganic insulating material and is provided so as to cover the side surfaces of the i-type semiconductor layer 31 and the n-type semiconductor layer 32. Note that the insulating film 27 may be an inorganic insulating film.

[0091] The upper electrode 34 is provided on the insulating film 27. The upper electrode 34 is a conductive material having translucency such as ITO (Indium Tin Oxide), for example. The upper electrode 34 is provided following the surface of the insulating film 27 and is connected to the n-type semiconductor layer 32 via a contact hole H1 provided in the insulating film 27. Further, the upper electrode 34 is provided so as to straddle the upper sides of the read control scanning line GLrd and the connection wiring SLcn, and is electrically connected to the drain electrode 63 and the gate electrode 68 of the reset transistor Mrst via a contact hole H2 provided in the insulating film 27.

[0092] The insulating films 28 and 29 are provided on the insulating film 27 covering the upper electrode 34. The insulating film 28 is an inorganic insulating film. The insulating film 28 is provided as a protective layer that suppresses the intrusion of moisture into the photoelectric conversion element 30. The insulating film 29 is an organic protective film. The insulating film 29 is formed so as to flatten the surface of the detection device 1.

[0093] In the detection device 1 of the present embodiment, among the three signal lines (power supply signal line SLsf, reset signal line SLrst, and reference signal line SLcom) excluding the output signal line SL, the power supply signal line SLsf and the reference signal line SLcom are shared by two adjacent detection elements 3. Although the configuration has been shown, it is not limited thereto.

[0094] For example, among the three signal lines excluding the output signal line SL, the power supply signal line SLsf and the reset signal line SLrst may be connected to two adjacent detection elements 3. In this case, the power supply signal line SLsf and the reset signal line SLrst are arranged with the photoelectric conversion element 30 sandwiched in the first direction Dx. Also, the reference signal line SLcom is provided for each photoelectric conversion element 30 arranged in the first direction Dx. Also, two adjacent reset transistors Mrst in the first direction Dx are electrically connected to one reset signal line SLrst arranged between the two reset transistors Mrst, and are arranged symmetrically with the reset signal line SLrst interposed therebetween.

[0095] Alternatively, among the three signal lines excluding the output signal line SL, the reference signal line SLcom and the reset signal line SLrst may be connected to two adjacent detection elements 3. In this case, the reference signal line SLcom and the reset signal line SLrst are arranged with the photoelectric conversion element 30 sandwiched in the first direction Dx. Also, the power supply signal line SLsf is provided for each detection element 3 arranged in the first direction Dx.

[0096] Note that the planar configuration and cross-sectional configuration of the detection element 3 are merely examples and can be changed as appropriate. For example, the photoelectric conversion element 30 is not limited to the configuration having the concave portion LA, and may be rectangular, or may have other shapes such as a polygonal shape. Further, the stacking order of the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 of the photoelectric conversion element 30 may be reversed. The photoelectric conversion element 30 may be provided in a layer different from the semiconductor layer of each transistor. For example, the photoelectric conversion element 30 may be provided on the insulating film 26.

[0097] As described above, the preferred embodiments of the present invention have been described, but the present invention is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention also naturally belong to the technical scope of the present invention.

Explanation of Reference Numerals

[0098] 1 Detection device 3 Detection element 10 Sensor unit 15A First gate line drive circuit 15B Second gate line drive circuit 16 Signal line selection circuit 21 Substrate 22, 23, 24, 25, 26, 27, 28, 29 Insulating film 30 Photoelectric conversion element 31 i-type semiconductor layer 32 n-type semiconductor layer 33 p-type semiconductor layer 34 Upper electrode 34a Connection wiring 48 Detection circuit AA Detection region GA Peripheral region GLrst Reset control scanning line GLrd Readout control scanning line SL Output signal line SLsf Power supply signal line SLrst Reset signal line SLcom Reference signal line Vsf power supply potential Vcom reference potential Vrst reset potential RST reset control signal RD read control signal Mrst reset transistor Mrd read transistor Msf source follower transistor

Claims

1. A substrate; a plurality of diode elements provided on the substrate and having optical characteristics; a plurality of transistors provided corresponding to the plurality of diode elements each having an optical characteristic; a plurality of signal lines that are provided between a plurality of the diode elements having optical characteristics adjacent to each other in a first direction, extend in a second direction intersecting the first direction, and supply signals to any of the plurality of the diode elements having optical characteristics or the plurality of the transistors; One detection element includes a plurality of the transistors, a first signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of a first detection element and the diode element having the optical characteristics of a second detection element adjacent to the first detection element on one side in the first direction, and is connected to the first detection element and the second detection element; a second signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of the first detection element and the diode element having the optical characteristics of a third detection element adjacent to the first detection element on the other side in the first direction, and is connected to the first detection element and the third detection element; a first reset signal line disposed between the first detection element and the first signal line for resetting the potential of the diode element having the optical characteristics of the first detection element to a predetermined potential; a first output signal line disposed between the first detection element and the second signal line, for outputting a signal corresponding to a potential of the diode element having an optical characteristic of the first detection element; a second output signal line disposed between the third detection element and the second signal line for outputting a signal corresponding to a potential of the diode element having an optical characteristic of the third detection element; the second signal line is a reference signal line that supplies a reference potential to the diode element having optical characteristics; The reference signal line is provided between two of the first output signal lines and the second output signal line adjacent to each other in the first direction. Detection device.

2. The two diode elements having optical characteristics adjacent to each other in the first direction are electrically connected to one of the reference signal lines arranged between the two diode elements having optical characteristics, and are arranged symmetrically with respect to the reference signal line. The detection device according to claim 1 .

3. The plurality of diode elements having optical characteristics are arranged at equal arrangement pitches in the first direction.

3. The detection device according to claim 1 or 2.

4. The outer shapes of the plurality of diode elements having optical characteristics are symmetrical with respect to a virtual line that passes through a midpoint of the diode element having optical characteristics in the first direction and is parallel to the second direction as a symmetry axis. The detection device according to any one of claims 1 to 3.

5. The detection elements each include a plurality of gate lines extending in the first direction and adjacent to each other in the second direction, The plurality of transistors are disposed between the plurality of gate lines adjacent to each other in the second direction. The detection device according to any one of claims 1 to 4.

6. The first signal line and the first reset signal line, and the second signal line and the first output signal line, which are arranged to sandwich the diode element having the optical characteristics of the first detection element, are symmetrical with respect to a virtual line that passes through a midpoint of the diode element having the optical characteristics in the first direction and is parallel to the second direction. A detection device according to any one of claims 1 to 5.

7. A substrate; a plurality of diode elements provided on the substrate and having optical characteristics; a plurality of transistors provided corresponding to the plurality of diode elements each having an optical characteristic; a plurality of signal lines that are provided between a plurality of the diode elements having optical characteristics adjacent to each other in a first direction, extend in a second direction intersecting the first direction, and supply signals to any of the plurality of the diode elements having optical characteristics or the plurality of the transistors; One detection element includes a plurality of the transistors, a first signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of a first detection element and the diode element having the optical characteristics of a second detection element adjacent to the first detection element on one side in the first direction, and is connected to the first detection element and the second detection element; a second signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of the first detection element and the diode element having the optical characteristics of a third detection element adjacent to the first detection element on the other side in the first direction, and is connected to the first detection element and the third detection element; a first reset signal line disposed between the first detection element and the first signal line for resetting the potential of the diode element having the optical characteristics of the first detection element to a predetermined potential; a first output signal line disposed between the first detection element and the second signal line, for outputting a signal corresponding to a potential of the diode element having an optical characteristic of the first detection element; The region occupied by the first signal line and the first reset signal line, and the second signal line and the first output signal line, which are arranged to sandwich the diode element having the optical characteristics of the first detection element, is symmetrical with respect to a virtual line that passes through a midpoint of the diode element having the optical characteristics in the first direction and is parallel to the second direction. Detection device.

8. the transistors include a source follower transistor, a reset transistor and a read transistor; the signal lines include a reset signal line that supplies a reset signal to the reset transistor and a power supply signal line that supplies a power supply potential to the source follower transistor; Two of the source follower transistors adjacent to each other in the first direction are electrically connected to one of the power supply signal lines disposed between the two source follower transistors, and are disposed symmetrically with respect to the power supply signal line. A detection device according to any one of claims 1 to 7.

9. A substrate; a plurality of diode elements provided on the substrate and having optical characteristics; a plurality of transistors provided corresponding to the plurality of diode elements each having an optical characteristic; a plurality of signal lines that are provided between a plurality of the diode elements having optical characteristics adjacent to each other in a first direction, extend in a second direction intersecting the first direction, and supply signals to any of the plurality of the diode elements having optical characteristics or the plurality of the transistors; One detection element includes a plurality of the transistors, a first signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of a first detection element and the diode element having the optical characteristics of a second detection element adjacent to the first detection element on one side in the first direction, and is connected to the first detection element and the second detection element; a second signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of the first detection element and the diode element having the optical characteristics of a third detection element adjacent to the first detection element on the other side in the first direction, and is connected to the first detection element and the third detection element; the transistors include a first transistor that transmits a signal of the diode element having an optical characteristic, and a second transistor that resets an applied voltage of the diode element having an optical characteristic to a predetermined potential; the signal lines include a reset signal line that supplies a reset signal to the second transistor and a power supply signal line that supplies a power supply potential to the first transistor; The two first transistors are electrically connected to one of the power supply signal lines disposed between the two first transistors, and are disposed symmetrically with respect to the two reset signal lines and the power supply signal lines. Detection device.

10. The power supply signal line is provided between two of the reset signal lines adjacent to each other in the first direction.

10. A detection device according to claim 8 or claim 9.

11. A substrate; a plurality of diode elements provided on the substrate and having optical characteristics; a plurality of transistors provided corresponding to the plurality of diode elements each having an optical characteristic; a plurality of signal lines that are provided between a plurality of the diode elements having optical characteristics adjacent to each other in a first direction, extend in a second direction intersecting the first direction, and supply signals to any of the plurality of the diode elements having optical characteristics or the plurality of the transistors; One detection element includes a plurality of the transistors, a first signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of a first detection element and the diode element having the optical characteristics of a second detection element adjacent to the first detection element on one side in the first direction, and is connected to the first detection element and the second detection element; a second signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of the first detection element and the diode element having the optical characteristics of a third detection element adjacent to the first detection element on the other side in the first direction, and is connected to the first detection element and the third detection element; a first reset signal line disposed between the first detection element and the first signal line for resetting the potential of the diode element having the optical characteristics of the first detection element to a predetermined potential; a first output signal line disposed between the first detection element and the second signal line, for outputting a signal corresponding to a potential of the diode element having an optical characteristic of the first detection element; the transistors include a source follower transistor, a reset transistor and a read transistor; the signal lines include a reset signal line that supplies a reset signal to the reset transistor and a power supply signal line that supplies a power supply potential to the source follower transistor; two of the source follower transistors adjacent to each other in the first direction are electrically connected to one of the power supply signal lines disposed between the two source follower transistors, and are disposed symmetrically with respect to the power supply signal line; The power supply signal line is provided between two of the reset signal lines adjacent to each other in the first direction. Detection device.

12. A substrate; a plurality of diode elements provided on the substrate and having optical characteristics; a plurality of transistors provided corresponding to the plurality of diode elements each having an optical characteristic; a plurality of signal lines that are provided between a plurality of the diode elements having optical characteristics adjacent to each other in a first direction, extend in a second direction intersecting the first direction, and supply signals to any of the plurality of the diode elements having optical characteristics or the plurality of the transistors; one detection element includes the diode element having optical characteristics and a plurality of the transistors arranged adjacent to the diode element having optical characteristics in the second direction, a first signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of a first detection element and the diode element having the optical characteristics of a second detection element adjacent to the first detection element on one side in the first direction, and is connected to the first detection element and the second detection element; a second signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of the first detection element and the diode element having the optical characteristics of a third detection element adjacent to the first detection element on the other side in the first direction, and is connected to the first detection element and the third detection element; a first reset signal line disposed between the first detection element and the first signal line for resetting the potential of the diode element having the optical characteristics of the first detection element to a predetermined potential; a second reset signal line disposed between the second detection element and the first signal line for resetting the potential of the diode element having the optical characteristics of the second detection element to a predetermined potential; a first output signal line disposed between the first detection element and the second signal line, for outputting a signal corresponding to a potential of the diode element having an optical characteristic of the first detection element; a second output signal line disposed between the third detection element and the second signal line, for outputting a signal corresponding to a potential of the diode element having an optical characteristic of the third detection element; Detection device.

13. the plurality of signal lines include a reference signal line that supplies a reference potential to the plurality of diode elements having optical characteristics; The two diode elements having optical characteristics adjacent to each other in the first direction are electrically connected to one of the reference signal lines arranged between the two diode elements having optical characteristics, and are arranged symmetrically with respect to the reference signal line.

13. The detection device of claim 12.

14. the second signal line is the reference signal line, The reference signal line is provided between two of the first output signal lines and the second output signal line adjacent to each other in the first direction.

14. The detection device according to claim 13.

15. The plurality of diode elements having optical characteristics are arranged at equal arrangement pitches in the first direction. Detecting device according to any one of claims 12 to 14.

16. The outer shapes of the plurality of diode elements having optical characteristics are symmetrical with respect to a virtual line that passes through a midpoint of the diode element having optical characteristics in the first direction and is parallel to the second direction as a symmetry axis. Detecting device according to any one of claims 12 to 15.

17. The detection elements each include a plurality of gate lines extending in the first direction and adjacent to each other in the second direction, The plurality of transistors are disposed between the plurality of gate lines adjacent to each other in the second direction. Detecting device according to any one of claims 12 to 16.

18. The region occupied by the first signal line and the first reset signal line, and the second signal line and the first output signal line, which are arranged to sandwich the diode element having the optical characteristics of the first detection element, is symmetrical with respect to a virtual line that passes through a midpoint of the diode element having the optical characteristics in the first direction and is parallel to the second direction. Detecting device according to any one of claims 12 to 17.

19. the transistors include a source follower transistor, a reset transistor and a read transistor; the signal lines include a reset signal line that supplies a reset signal to the reset transistor and a power supply signal line that supplies a power supply potential to the source follower transistor; Two of the source follower transistors adjacent to each other in the first direction are electrically connected to one of the power supply signal lines disposed between the two source follower transistors, and are disposed symmetrically with respect to the power supply signal line. Detecting device according to any one of claims 12 to 18.

20. A substrate; a plurality of diode elements provided on the substrate and having optical characteristics; a plurality of transistors provided corresponding to the plurality of diode elements each having an optical characteristic; a plurality of signal lines that are provided between a plurality of the diode elements having optical characteristics adjacent to each other in a first direction, extend in a second direction intersecting the first direction, and supply signals to any of the plurality of the diode elements having optical characteristics or the plurality of the transistors; one detection element includes the diode element having optical characteristics and a plurality of the transistors arranged adjacent to the diode element having optical characteristics in the second direction, a first signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of a first detection element and the diode element having the optical characteristics of a second detection element adjacent to the first detection element on one side in the first direction, and is connected to the first detection element and the second detection element; a second signal line among the plurality of signal lines is disposed between the diode element having the optical characteristics of the first detection element and the diode element having the optical characteristics of a third detection element adjacent to the first detection element on the other side in the first direction, and is connected to the first detection element and the third detection element; the transistors include a source follower transistor, a reset transistor and a read transistor; the signal lines include a reset signal line that supplies a reset signal to the reset transistor and a power supply signal line that supplies a power supply potential to the source follower transistor; Two of the source follower transistors adjacent to each other in the first direction are electrically connected to one of the power supply signal lines disposed between the two source follower transistors, and are disposed symmetrically with respect to the two reset signal lines and the power supply signal lines. Detection device.

21. The power supply signal line is provided between two of the reset signal lines adjacent to each other in the first direction.

21. A detection device according to claim 19 or claim 20.

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