Electronic component

Abstract

To provide a technique capable of efficiently radiating a heat from a chip in an upper stage in an electronic component in which two or more chips to which a semiconductor element is provided is integrated to a vertical direction.SOLUTION: An electronic component comprises: a first chip having a first semiconductor element; a second chip having a second semiconductor element; and a circuit board. Both of the first chip and the second chip, are integrated so that a surface of the first chip on the side where the first semiconductor element is formed and a surface of the second chip on the side where the second semiconductor element is formed are fixed to an opposite direction. The first chip, the second chip, and the circuit board are integrated so that the second chip is positioned to between the first chip and the circuit board. At least one part of the first chip and the second chip and the circuit board are electrically connected via the connection member, and a heat transmission conductive material contacted to both of the first chip and the circuit board is arranged at a position where the second chip does not exist in a view of a direction that is vertical to a main surface of the first chip.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an electronic component in which a plurality of chips each having a semiconductor element are integrated.

Background Art

[0002] In recent years, in order to reduce the size and improve the performance of electronic components, a plurality of chips provided with semiconductor elements have been laminated. In an electronic component in which two or more chips provided with semiconductor elements are laminated in the vertical direction, heat is generated in each of the upper chip and the lower chip during driving, and the heat can be propagated in one direction or in both directions. Then, due to the heat generation of one chip, the other chip may not operate normally or its characteristics may deteriorate. Patent Document 1 discloses covering a chip stack in which eight chips are stacked with a sealing resin and providing a heat radiating member on the upper surface of the sealing resin.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the structure described in Patent Document 1, since a sealing resin is interposed between the chip stack and the heat radiating member, the heat conduction from the chip stack to the heat radiating member is restricted and a sufficient heat dissipation effect cannot be achieved, and for example, the problem that the temperature of the uppermost chip rises excessively may occur.

[0005] Further, for example, in the case of an electronic component in which the uppermost chip is an imaging element or a display element, it is necessary to prevent the optical path of the imaging light or the display light from being obstructed. Therefore, it is not practical to arrange the heat radiating member as in Patent Document 1. Therefore, the problem that the temperature of the uppermost chip rises excessively may occur.

[0006] Therefore, in an electronic component in which two or more chips provided with semiconductor elements are vertically integrated, a technique capable of efficiently dissipating heat from the upper chip has been demanded.

Means for Solving the Problem

[0007] One aspect of the present invention includes a first chip having a first semiconductor element, a second chip having a second semiconductor element, and a circuit board. The first chip and the second chip are fixed in a facing direction such that the surface of the first chip on the side where the first semiconductor element is formed and the surface of the second chip on the side where the second semiconductor element is formed face each other. The first chip, the second chip, and the circuit board are integrated such that the second chip is positioned between the first chip and the circuit board. At least one of the first chip and the second chip and the circuit board are electrically connected via a connection member. A heat conduction member that abuts both the first chip and the circuit board is disposed at a position where the second chip does not exist when viewed through in a direction perpendicular to the main surface of the first chip. The electronic component is characterized by this.

Effect of the Invention

[0008] According to the present invention, in an electronic component in which two or more chips provided with semiconductor elements are vertically integrated, a technique capable of efficiently dissipating heat from the upper chip can be provided.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0010] With reference to the drawings, an electronic component (semiconductor device) and the like according to an embodiment of the present invention will be described. Note that the embodiments described below are examples, and for example, those skilled in the art can appropriately change and implement the detailed configurations without departing from the spirit of the present invention.

[0011] In the drawings referred to in the following description of the embodiments, unless otherwise specified, elements denoted by the same reference numerals have the same functions. In the drawings, when a plurality of the same elements are arranged, the assignment of reference numerals and their descriptions may be omitted.

[0012] Also, for the sake of convenience of illustration and description, the drawings may be schematically represented. Therefore, the shapes, sizes, arrangements, etc. of the elements shown in the drawings may not necessarily exactly match the actual objects.

[0013] [Embodiment 1] (Configuration) FIG. 1(a) is a schematic plan view showing an electronic component 800 as an electronic component (semiconductor device) according to the present embodiment. It is a view of the electronic component 800 seen from a direction perpendicular to its main surface (the normal direction of the main surface), and not only the appearance but also the positions of the second chip 200, the heat conduction member 400, and the effective region AA in which semiconductor elements are provided in the first chip are schematically shown. FIG. 1(b) is a schematic cross-sectional view of the electronic component 800 cut along the X - Y line shown in FIG. 1(a).

[0014] As shown, the electronic component 800 has a structure in which the first chip 100, the second chip 200, the heat conduction member 400, and the circuit board 500 are integrated. In this specification, being integrated means not only being simply connected but also a state in which the relative positional relationship between them is fixed.

[0015] The first chip 100 includes a first substrate 110 which is, for example, a semiconductor substrate. On the side of the first main surface FS1 of the first substrate 110, a semiconductor element 120 is formed. Although schematically shown in the figure, the semiconductor element 120 may include, for example, a large number of transistors and diodes. A part of the semiconductor element 120 may be provided in the first substrate 110.

[0016] On the side of the first main surface FS1 of the first substrate 110, a first insulating layer 130, a first wiring layer 140, and a first connection electrode 150 are further provided. The first wiring layer 140 and the first connection electrode 150 are formed using, for example, aluminum or copper.

[0017] The first wiring layer 140 is schematically shown as a single layer in the figure, but may be a multilayer wiring structure in which a plurality of wiring layers are stacked. For the first insulating layer 130, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used, and it can also function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure may be configured to include vias and plugs for connecting wirings of different layers.

[0018] The semiconductor element 120, the first wiring layer 140, and the first connection electrode 150 are electrically connected to form an electronic circuit. The first connection electrode 150 is formed in a layer different from the first wiring layer 140, is located on the lowermost surface of the first chip 100, and is electrically connected to a second connection electrode 250 provided on the second chip 200.

[0019] The second chip 200 includes a second substrate 210 which is, for example, a semiconductor substrate. On the side of the second main surface FS2 of the second substrate 210, a semiconductor element 220 is formed. Although schematically shown in the figure, the semiconductor element 220 may include, for example, a large number of transistors and diodes. A part of the semiconductor element 220 may be provided in the second substrate 210.

[0020] On the side of the second main surface FS2 of the second substrate 210, a second insulating layer 230, a second wiring layer 240, and a second connection electrode 250 are further provided. The second wiring layer 240 and the second connection electrode 250 are formed using, for example, aluminum or copper. Although the second wiring layer 240 is schematically shown as a single layer in the figure, it may have a multilayer wiring structure in which a plurality of wiring layers are stacked. For the second insulating layer 230, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used, and it can also function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure may include vias and plugs that connect wirings of different layers.

[0021] The semiconductor element 220, the second wiring layer 240, and the second connection electrode 250 are electrically connected to form an electronic circuit. The second connection electrode 250 is formed in a layer different from the second wiring layer 240, is located on the uppermost surface of the second chip 200, and is electrically connected to the first connection electrode 150 provided on the first chip 100.

[0022] In the second chip 200, a through electrode TE extending from the back surface side (the side opposite to the second main surface FS2) of the second substrate 210 to the second wiring layer 240 is provided, and an external connection member BP is provided between the through electrode TE and the circuit board 500. Through the through electrode TE and the external connection member BP, the second wiring layer 240 of the second chip 200 and an electrode (not shown) on the circuit board 500 are electrically connected. The material of the through electrode TE is copper or gold, and it is formed by filling, for example, copper or gold into a through via formed to extend from the back surface of the second substrate 210 to the second wiring layer 240 by plating.

[0023] The external connection member BP is, for example, a solder ball, and can be formed by forming a solder resist (not shown) having an opening on the through electrode TE on the back surface of the second substrate 210, mounting a solder ball in the opening, and then performing reflow.

[0024] The circuit board 500 can be any of a rigid board such as a glass epoxy board or a ceramic board, a flexible board such as a flexible printed circuit board, or a rigid-flexible board combining them. An electric circuit for transmitting and receiving signals, supplying power, etc. is provided on the circuit board 500 for an electronic device composed of the first chip 100 and the second chip.

[0025] As shown in FIG. 1(b), in the electronic component 800, the semiconductor element 120 of the first chip 100 and the semiconductor element 220 of the second chip 200 face each other with an insulating layer or a wiring layer interposed therebetween, and the first chip 100 and the second chip 200 are integrated. With the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode interposed therebetween, the first main surface FS1 and the second main surface FS2 face each other, and the first chip and the second chip are fixed so that the first connection electrode and the second connection electrode are electrically connected.

[0026] The first connection electrode 150 and the second connection electrode 250 are preferably made of the same material, specifically, for example, copper or gold. When the first chip and the second chip are fixed, the first connection electrode 150 and the second connection electrode 250 can be mechanically and electrically joined by thermocompression bonding without using an adhesive or the like.

[0027] In addition, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used for the first insulating layer 130 and the second insulating layer 230. By forming the first insulating layer 130 and the second insulating layer 230 of the same material and activating their respective surfaces by a technique such as plasma irradiation, the first insulating layer 130 and the second insulating layer 230 can be directly joined at a low temperature.

[0028] In the electronic component 800 according to the present embodiment, as shown in FIG. 1(a), in a plan view, the projected area of the second chip 200 can be made smaller than the projected area of the first chip 100, and the cost of the substrate can be suppressed. Moreover, in a plan view, the second chip 200 is included in the first chip 100, and the two chips are laid out so that the second chip 200 does not protrude from the outer edge of the first chip 100. Note that the plan view means viewing from a direction perpendicular to the main surface of the first chip 100 (the normal direction of the main surface).

[0029] Then, in a position where the second chip 200 and the first chip 100 do not overlap in a perspective view in a plan view, a heat conduction member 400 that connects the first chip 100 and the circuit board 500 is provided. The first chip 100 is provided with an effective region AA where a semiconductor element is provided and a peripheral region PA arranged on the outer periphery of the effective region AA. As shown in FIG. 1(a), in the peripheral region PA of the first chip 100, the heat conduction member 400 is arranged around the second chip 200. As shown in FIG. 1(b), the heat conduction member 400 is in contact with both the first chip 100 and the circuit board 500.

[0030] For the heat conduction member 400, for example, a thermally conductive adhesive or a thermally conductive grease can be used. Alternatively, a resin containing a metal member or a thermally conductive filler such as graphite having thermal conductivity can be used. A form in which an adhesive or an adhesive is provided on both surfaces of a resin sheet containing a thermally conductive filler and fixed to both the first chip 100 and the circuit board 500 may also be used.

[0031] In this embodiment, the heat conduction member 400 is arranged to contact the peripheral region of the first chip 100 and the circuit board 500. Therefore, heat can be efficiently dissipated from the peripheral region PA of the first chip 100 to the circuit board 500 through the heat conduction member 400. In the configuration illustrated in FIG. 1(b), a gap is provided between the heat conduction member 400 and the second chip 200 in order to enhance the heat dissipation performance of the first chip 100. However, by bringing the side surface of the heat conduction member 400 into contact with the second chip 200, heat dissipation from not only the first chip 100 but also the second chip 200 to the circuit board 500 may be promoted. Further, although not shown, it is preferable from the viewpoint of heat dissipation to provide a heat conduction member 400 also between the back surface of the second chip 200 (the main surface on the side opposite to the second main surface FS2 of the substrate 210) and the circuit board 500.

[0032] If the components of the electronic component 800 according to this embodiment are exemplified, the first chip 100 is an image sensor, and the second chip 200 is a chip including at least one of a memory circuit or a logic circuit. The heat conduction member 400 can efficiently dissipate the heat of the first chip 100 to the circuit board 500 without obstructing the optical path of the imaging light of the image sensor.

[0033] Further, for example, the first chip 100 may be a memory chip, and the second chip 200 may be a logic chip. The heat conduction member 400 can efficiently dissipate the heat of the first chip 100 to the circuit board 500. The above combinations of chips are examples, and the electronic component (semiconductor device) of the embodiment may be configured by combining other types of chips without any problem.

[0034] In the example shown in FIG. 1(a), in a plan view, heat conduction members 400 shorter than each side of the second chip 200 are arranged outside each of the four sides of the second chip 200, but this embodiment is not limited to this example. FIGS. 2(a) to 2(c) are schematic plan views showing an electronic component 800 according to a modified example of this embodiment.

[0035] As shown in Fig. 2(a), by arranging a heat conduction member 400 that is longer than and substantially parallel to at least one side of the second chip 200, the heat conduction efficiency can be improved, and the mechanical strength of the peripheral region PA of the first chip 100 can be enhanced.

[0036] As shown in Fig. 2(b), by surrounding the outer periphery of the second chip 200 with the heat conduction member 400, the heat conduction efficiency can be further improved, and the mechanical strength of the peripheral region PA of the first chip 100 can be enhanced.

[0037] As shown in Fig. 2(c), a support member 450 different from the heat conduction member 400 may be arranged along, for example, two sides of the second chip 200. By providing a support member with a higher elastic modulus and less likely to deform than the heat conduction member 400, the mechanical strength of the electronic component 800 can be improved. Incidentally, both the heat conduction member 400 and the support member 450 may be arranged along the same side of the second chip 200.

[0038] When using thermal grease as the heat conduction member 400, the heat conduction member 400 can be easily formed at an arbitrary position. When using a thermally conductive adhesive as the heat conduction member 400, various arrangement patterns as exemplified in Figs. 2(a) to 2(c) can be easily formed, and moreover, since the rigidity is higher than that of thermal grease, the mechanical strength of the electronic component 800 can be increased. When using a thermally conductive adhesive as the heat conduction member 400, a support member may be appropriately formed around the heat conduction member 400 as an embankment structure for suppressing overhang.

[0039] As described above, in the present embodiment, by providing the heat conduction member 400 that contacts both the peripheral region of the first chip 100 and the circuit board 500, the heat of the first chip 100 can be efficiently released to the circuit board 500. Therefore, inconveniences such as abnormal operation of the first chip 100 and deterioration of the characteristics of the semiconductor element due to heat generation and heat accumulation can be suppressed.

[0040] (Manufacturing Method) A method for manufacturing an electronic component (semiconductor device) according to this embodiment will be described with reference to FIGS. 3(a) to 4(c). Each figure schematically shows a cross-section at each stage of the manufacturing process.

[0041] As shown in FIG. 3(a), a first chip 100 is prepared. In FIG. 3(a), only a single first chip 100 is illustrated, but it is also possible to form a plurality of first chips 100 on the same wafer and then cut them into individual chips. On the main surface FS1 (first main surface) of the first substrate 110, a semiconductor element 120, a first insulating layer 130, a first wiring layer 140, and a first connection electrode 150 are sequentially formed. For the first substrate 110, a single-crystal semiconductor substrate such as silicon can be used, for example.

[0042] On the main surface FS1, which is one of the main surfaces of the first substrate 110, a first semiconductor element 120 such as a transistor or a diode is provided. When an insulator substrate such as glass or resin is used instead of a semiconductor substrate for the first substrate 110, a TFT (thin film transistor) may be provided as the first semiconductor element 120 on the main surface FS1 of the insulator substrate.

[0043] A first insulating layer 130 is provided on the main surface FS1 where the first semiconductor element 120 is not provided and on the first semiconductor element 120. As the first insulating layer 130, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, etc. is used. In the first insulating layer 130, a contact plug (not shown) electrically connected to the first semiconductor element 120 is arranged. A conductive material such as tungsten is embedded in the contact plug. Inside the first insulating layer 130, a first wiring layer 140 electrically connected to the first semiconductor element 120 via the contact plug is provided.

[0044] Although the first wiring layer 140 is schematically shown as a single layer in the figure, it can be a multilayer wiring structure in which a plurality of wiring layers are stacked. The first insulating layer 130 can also function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure can be configured to include vias and plugs that connect wirings in different layers. A metal material such as aluminum or copper is used for the first wiring layer 140, and a barrier metal such as Ti, Ta, TiN, or TaN may be provided at the interface between the first wiring layer 140 and the first insulating layer 130 to suppress the diffusion of the metal into the first insulating layer 130.

[0045] On the first wiring layer 140, the first insulating layer 130, the first connection electrode 150, and the first insulating layer 130 are sequentially stacked and provided. Note that at least three insulating layers are arranged between the first semiconductor element 120 and the first wiring layer 140, between the first wiring layer 140 and the first connection electrode 150, and around the first connection electrode 150. For the sake of illustration, these are all shown as the first insulating layer 130 without distinction.

[0046] The semiconductor element 120, the first wiring layer 140, and the first connection electrode 150 are electrically connected to form an electronic circuit. Note that a dummy pattern that is not electrically connected to the circuit may be formed in the same layer as the first connection electrode 150 and used as an anchor to increase the bonding strength when bonding the first chip 100 and the second chip 200.

[0047] The surface of the first substrate 110 opposite to the main surface FS1 is polished by backgrinding or CMP, and the first substrate 110 can be thinned to a thickness of about 50 μm to 200 μm. By polishing by CMP so that the step between the first connection electrode 150 and the first insulating layer 130 is minimized on the outermost surface of the first chip 100, the yield of the process of bonding the first chip 100 and the second chip 200 can be improved.

[0048] As shown in FIG. 3(b), a second chip 200 is prepared. In FIG. 3(b), only a single second chip 200 is illustrated, but it is also possible to form a plurality of second chips 200 on the same wafer and then cut them into individual chips. For the second substrate 210, a single crystal semiconductor substrate such as silicon can be used, for example.

[0049] On a second main surface FS2, which is one of the main surfaces of the second substrate 210, semiconductor elements 220 such as transistors and diodes are provided. When an insulator substrate such as glass or resin is used instead of a semiconductor substrate for the second substrate 210, a TFT (thin film transistor) may be arranged as the second semiconductor element 220 on the second main surface FS2 of the insulator substrate.

[0050] A second insulating layer 230 is provided on the second main surface FS2 where the second semiconductor element 120 is not provided and on the second semiconductor element 220. As the second insulating layer 230, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used. If the same type of insulating material as the first insulating layer 130 provided on the outermost surface of the first chip 100 is used as the second insulating layer 230 of the second chip 200, it is preferable because the first insulating layer 130 and the second insulating layer 230 can be easily directly bonded. For example, when silicon oxide is used as the first insulating layer 130, it is preferable to use silicon oxide with the same composition for the second insulating layer 230.

[0051] Contact plugs (not shown) electrically connected to the second semiconductor element 220 are arranged in the second insulating layer 230. A conductive material such as tungsten is embedded in the contact plugs. Inside the second insulating layer 130, a second wiring layer 240 electrically connected to the semiconductor element 220 through the contact plugs is provided.

[0052] The second wiring layer 240 is schematically shown as a single layer in the figure, but it can be a multilayer wiring structure in which a plurality of wiring layers are stacked. The second insulating layer 230 can also function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure can be configured to include vias and plugs that connect wirings of different layers. A metal material such as aluminum or copper is used for the second wiring layer 240, and a barrier metal such as Ti, Ta, TiN, or TaN may be provided at the interface between the second wiring layer 240 and the second insulating layer 230 to suppress the diffusion of the metal into the second insulating layer 230.

[0053] On the second wiring layer 240, the second insulating layer 230, the second connection electrode 250, and the second insulating layer 230 are sequentially stacked and provided. Note that at least three insulating layers are arranged between the second semiconductor element 220 and the second wiring layer 240, between the second wiring layer 240 and the second connection electrode 250, and around the second connection electrode 250. For the sake of illustration convenience in the figure, these are all shown as the second insulating layer 230 without distinction.

[0054] The semiconductor element 220, the second wiring layer 240, and the second connection electrode 250 are electrically connected to form an electronic circuit. Note that a dummy pattern that is not electrically connected to the circuit may be formed in the same layer as the second connection electrode 250 and used as an anchor to increase the bonding strength when bonding the first chip 100 and the second chip 200.

[0055] At the outermost surface of the second chip 200, by polishing by CMP so that the step difference between the second connection electrode 250 and the second insulating layer 230 becomes as small as possible, the yield of the process of bonding the first chip 100 and the second chip 200 can be improved.

[0056] Next, as shown in FIG. 3(c), the first chip 100 and the second chip 200 are bonded and integrated. Here, an example of the direct bonding method is shown, but bonding may be performed using bumps such as solder bumps or micro bumps. In that case, a bump member (not shown) may be separately formed on the surface of either the first connection electrode 150 or the second connection electrode 250, and then the bump member may be melted and bonded.

[0057] When directly bonding the first chip 100 and the second chip 200, first, the outermost surface of the first chip 100 is cleaned by two-fluid cleaning or spin cleaning using pure water to remove foreign substances adhering to the surface. Then, the main surface of the first chip 100 on the side where the first connection electrode 150 is exposed is irradiated with plasma to activate the surface.

[0058] Similarly, the outermost surface of the second chip 200 is cleaned by two-fluid cleaning or spin cleaning using pure water to remove foreign substances adhering to the surface. Then, the main surface of the second chip 100 on the side where the second connection electrode 250 is exposed is irradiated with plasma to activate the surface.

[0059] After cleaning and activating the surfaces of both chips, quickly oppose the main surface of the first chip 100 (the main surface on the side where the first connection electrode 150 is located) and the main surface of the second chip 200 (the main surface on the side where the second connection electrode 250 is located), and align the first connection electrode 150 and the second connection electrode 250. Then, apply a predetermined load from the back surface BS2 in a state where the first connection electrode 150 and the second connection electrode 250, and the first insulating layer 130 and the second insulating layer 230 are in contact with each other. Thereby, the first insulating layer 130 and the second insulating layer 230 are pressure-bonded at room temperature. Then, while heating to about 250°C to 400°C, apply a load from the back surface BS2 for a predetermined time. Thereby, the first connection electrode 150 and the second connection electrode 250 are joined by thermal diffusion, and the direct bonding (thermal compression bonding) is completed.

[0060] Next, as shown in FIG. 3(d), the back surface BS2 side of the second chip 200 is polished by back grinding or CMP to thin the second substrate 210 to a thickness of about 50 μm to 200 μm. Then, an opening TV extending from the back surface BS2 of the second chip 200 to a part of the second wiring layer 240 is formed. When the second substrate 210 is a silicon substrate, an opening can be formed in the silicon substrate by dry etching using the Bosch process.

[0061] After an opening is formed in the second substrate 210, the second insulating layer 230 between the second main surface FS2 of the second substrate 210 and the second wiring layer 240 is removed by reactive ion etching (RIE) to extend the opening TV and expose the surface of the second wiring layer 240.

[0062] Thereafter, although not shown in FIG. 3(d), an insulating film (not shown) such as silicon oxide or silicon nitride is formed on the side surface of the opening TV and the back surface BS2 of the second substrate 210. Then, a barrier metal such as Ti, TiN, Ta, TaN and a plating seed layer such as Cu or Au are sequentially formed by sputtering in the opening TV covered with the insulating film. Next, after a resist having an opening is formed on the opening TV, Cu or Au is grown and filled in the opening TV by plating. Thereafter, the barrier metal and the plating seed layer in the unnecessary regions are removed by etching to form the through electrode TE.

[0063] Next, as shown in FIG. 4(a), a solder resist SR is applied on the back surface BS2 of the second substrate 210 and the through electrode TE, and the solder resist is removed only on the through electrode TE by exposure and development. Next, a flux (not shown) is applied on the through electrode TE provided with the opening of the solder resist SR. Solder balls are mounted on the flux and heated to 250° C. in a nitrogen atmosphere to melt the solder balls, thereby forming the external connection member BP.

[0064] On the other hand, as shown in FIG. 4(b), a circuit board 500 on which a heat conduction member 400 is disposed is prepared. That is, a thermally conductive resin is applied on the circuit board 500 by, for example, a dispenser to form the heat conduction member 400.

[0065] Then, as shown in FIG. 4(c), the electrode (not shown) of the circuit board 500 and the second chip 200 are aligned and joined. Thus, the electronic component 800 in which the second chip 200 and the circuit board 500 are electrically connected by the external connection member BP and the first chip 100 and the circuit board 500 are connected by the heat conduction member 400 is completed.

[0066] [Embodiment 2] Referring to the drawings, the electronic component (semiconductor device) according to Embodiment 2 will be described. For matters common to Embodiment 1, the description will be simplified or omitted.

[0067] FIG. 5(a) is a schematic plan view showing an electronic component 800 as an electronic component (semiconductor device) according to Embodiment 2. FIG. 5(b) is a schematic cross-sectional view of the electronic component 800 cut along the X-Y line shown in FIG. 5(a).

[0068] In Embodiment 1, the first chip 100 and the second chip 200 were integrated, and a heat conduction member was disposed around the second chip in a plan view. In this embodiment, the second chip 200 and the third chip 300 are integrated with respect to the first chip 100, and a heat conduction member is disposed between the second chip and the third chip 300 in a plan view. In FIG. 5(a), not only the appearance in a plan view but also the positions of the second chip 200, the third chip 300, the heat conduction member 400, and the effective region AA in which the semiconductor element 120 is provided in the first chip are schematically shown. The electronic component 800 has a structure in which the first chip 100, the second chip 200, the third chip 300, the heat conduction member 400, and the circuit board 500 are integrated.

[0069] The first chip 100 includes a first substrate 110 which is, for example, a semiconductor substrate. A semiconductor element 120 is formed on the side of the first main surface FS1 of the first substrate 110. Although schematically shown in the figure, the semiconductor element 120 may include, for example, a large number of transistors and diodes. A part of the semiconductor element 120 may be provided in the first substrate 110.

[0070] On the side of the first main surface FS1 of the first substrate 110, a first insulating layer 130, a first wiring layer 140, and a first connection electrode 150 are further provided. The first wiring layer 140 and the first connection electrode 150 are formed using, for example, aluminum or copper.

[0071] Although the first wiring layer 140 is schematically shown as a single layer in the figure, it can be a multilayer wiring structure in which a plurality of wiring layers are stacked. For the first insulating layer 130, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used, and it can also function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure can be configured to include vias and plugs that connect wirings of different layers.

[0072] The semiconductor element 120, the first wiring layer 140, and the first connection electrode 150 are electrically connected to form an electronic circuit. The first connection electrode 150 is formed in a layer different from the first wiring layer 140, is located on the lowermost surface of the first chip 100, and is electrically connected to the second connection electrode 250 provided on the second chip 200.

[0073] The second chip 200 includes, for example, a second substrate 210 that is a semiconductor substrate. On the side of the second main surface FS2 of the second substrate 210, a semiconductor element 220 is formed. Although schematically shown in the figure, the semiconductor element 220 can include, for example, a large number of transistors and diodes. A part of the semiconductor element 220 can be provided in the second substrate 210.

[0074] On the side of the second main surface FS2 of the second substrate 210, further, a second insulating layer 230, a second wiring layer 240, and a second connection electrode 250 are provided. The second wiring layer 240 and the second connection electrode 250 are formed using, for example, aluminum or copper. Although the second wiring layer 240 is schematically shown as a single layer in the figure, it can be a multilayer wiring structure in which a plurality of wiring layers are stacked. For the second insulating layer 230, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used, and it can also function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure can be configured to include vias and plugs that connect wirings of different layers.

[0075] The semiconductor element 220, the second wiring layer 240, and the second connection electrode 250 are electrically connected to form an electronic circuit. The second connection electrode 250 is formed in a layer different from the second wiring layer 240, is located on the uppermost surface of the second chip 200, and is electrically connected to the first connection electrode 150 provided on the first chip 100.

[0076] A through electrode TE extending from the back side of the second substrate 210 (the side opposite to the second main surface FS2) to the second connection electrode 250 is arranged on the second chip 200, and an external connection member BP is arranged on the through electrode TE. Through the through electrode TE and the external connection member BP, the second connection electrode 250 of the second chip 200 and an electrode (not shown) on the circuit board 500 are electrically connected. The material of the through electrode TE is copper or gold, and is formed by filling, for example, copper or gold by plating into a through via formed so as to extend from the back surface of the second substrate 210 to the second connection electrode 250. The external connection member BP is, for example, a solder ball, and can be formed by forming a solder resist (not shown) having an opening on the through electrode TE on the back surface of the second substrate 210, mounting the solder ball in the opening, and then performing reflow.

[0077] The third chip 300 includes a third substrate 310 which is, for example, a semiconductor substrate. A semiconductor element 320 is formed on the side of the third main surface FS3 of the third substrate 310. Although schematically shown in the figure, the semiconductor element 320 can include, for example, a large number of transistors and diodes. A part of the semiconductor element 320 can be provided in the third substrate 310.

[0078] On the side of the third main surface FS3 of the third substrate 310, a third insulating layer 330, a third wiring layer 340, and a third connection electrode 350 are further provided. The third wiring layer 340 and the third connection electrode 350 are formed using, for example, aluminum or copper. Although the third wiring layer 340 is schematically shown as a single layer in the figure, it may have a multilayer wiring structure in which a plurality of wiring layers are stacked. For the third insulating layer 330, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used, and it can also function as an interlayer insulating layer in the multilayer wiring structure. The multilayer wiring structure may include vias and plugs for connecting wirings of different layers.

[0079] The semiconductor element 320, the third wiring layer 340, and the third connection electrode 350 are electrically connected to form an electronic circuit. The third connection electrode 350 is formed in a layer different from the third wiring layer 340, is located on the uppermost surface of the third chip 300, and is electrically connected to the first connection electrode 150 provided on the first chip 100.

[0080] In the third chip 300, a through electrode TE extending from the back surface side of the third substrate 310 (the side opposite to the third main surface FS3) to the third connection electrode 350 is arranged, and an external connection member BP is arranged on the through electrode TE. Through the through electrode TE and the external connection member BP, the third connection electrode 350 of the third chip 300 and an electrode (not shown) on the circuit board 500 are electrically connected. The material of the through electrode TE is copper or gold, and it is formed by filling, for example, copper or gold by plating into a through via formed so as to extend from the back surface of the third substrate 310 to the third connection electrode 350. The external connection member BP is, for example, a solder ball, and it can be formed by forming a solder resist (not shown) having an opening on the through electrode TE on the back surface of the third substrate 310 and mounting a solder ball in the opening and then performing reflow.

[0081] The circuit board 500 can be any of a rigid board such as a glass epoxy board or a ceramic board, a flexible board such as a flexible printed circuit board, or a rigid-flexible board combining them. The circuit board 500 is provided with an electric circuit for transmitting and receiving signals and supplying power to an electronic device configured by integrating the first chip 100, the second chip 200, and the third chip 300.

[0082] As shown in FIG. 5(b), in the electronic component 800, the semiconductor element 120 of the first chip 100 and the semiconductor element 220 of the second chip 200 are in a direction facing each other with an insulating layer or a wiring layer interposed therebetween, and the first chip 100 and the second chip 200 are integrated. Also, the semiconductor element 120 of the first chip 100 and the semiconductor element 320 of the third chip 300 are in a direction facing each other with an insulating layer or a wiring layer interposed therebetween, and the first chip 100 and the third chip 300 are integrated.

[0083] The first connection electrode 150, the second connection electrode 250, and the third connection electrode 350 are preferably made of the same material, specifically, for example, copper or gold. When the first chip and the second chip are fixed, the first connection electrode 150 and the second connection electrode 250 can be mechanically and electrically joined by thermocompression bonding without using an adhesive or the like. Similarly, when the first chip and the third chip are fixed, the first connection electrode 150 and the third connection electrode 350 can be mechanically and electrically joined by thermocompression bonding without using an adhesive or the like.

[0084] Also, for the first insulating layer 130, the second insulating layer 230, and the third insulating layer 330, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide is used. By forming the first insulating layer 130 and the second insulating layer 230 of the same material and activating their respective surfaces by a technique such as plasma irradiation, the first insulating layer 130 and the second insulating layer 230 can be directly joined at a low temperature. Similarly, by forming the first insulating layer 130 and the third insulating layer 330 of the same material and activating their respective surfaces by a technique such as plasma irradiation, the first insulating layer 130 and the third insulating layer 330 can be directly joined at a low temperature.

[0085] In the electronic component 800 according to this embodiment, as shown in FIG. 5(a), in a plan view, the first chip 100 is provided with an effective region AA where semiconductor elements are provided and a peripheral region PA arranged on the outer periphery of the effective region AA. As shown in FIG. 5(a), in a plan view, the second chip 200 and the third chip 300 are arranged so as to overlap the peripheral region PA while sandwiching the effective region AA of the first chip 100.

[0086] Then, in a position where the second chip 200 and the first chip 100 do not overlap and a position where the third chip 200 and the first chip 100 do not overlap in a plan view perspective, a heat conduction member 400 for connecting the first chip 100 and the circuit board 500 is provided. As shown in FIG. 5(a), the heat conduction member 400 is arranged so as to include the effective region AA of the first chip 100 in a plan view. As shown in FIG. 5(b), the heat conduction member 400 is in contact with both the first chip 100 and the circuit board 500.

[0087] For the heat conduction member 400, for example, a thermally conductive adhesive or thermally conductive grease can be used. Alternatively, an adhesive or adhesive can be provided on both sides of a resin sheet containing a filler such as a metal member or graphite having thermal conductivity, and it may be fixed to both the first chip 100 and the circuit board 500.

[0088] In this embodiment, the heat conduction member 400 is arranged to contact the effective area AA of the first chip 100 and the circuit board 500. Therefore, heat can be efficiently dissipated from the effective area AA of the first chip 100 to the circuit board 500 through the heat conduction member 400. In the configuration illustrated in FIG. 5(b), in order to enhance the heat dissipation performance of the first chip 100, gaps are provided between the heat conduction member 400 and the second chip 200, and between the heat conduction member 400 and the third chip 300. However, by bringing the side surface of the heat conduction member 400 into contact with the side surface of the second chip 200 or the third chip 300, a structure that promotes heat dissipation from not only the first chip 100 but also the second chip 200 or the third chip 300 to the circuit board 500 may be adopted. Further, from the viewpoint of heat dissipation, although not shown in the drawings, it is preferable to provide the heat conduction member 400 between the back surface of the second chip 200 and the circuit board 500, or between the back surface of the third chip 300 and the circuit board 500.

[0089] If the components of the electronic component 800 according to this embodiment are exemplified, the first chip 100 is an image sensor, and the second chip 200 and the third chip 300 are chips including at least one of a memory circuit or a logic circuit. The heat conduction member 400 can efficiently dissipate the heat of the first chip 100 to the circuit board 500 without obstructing the optical path of the imaging light of the image sensor. The heat conduction member 400 can be arranged so as to overlap with the light receiving area of the image sensor when viewed from a direction perpendicular to the main surface of the first chip.

[0090] Further, for example, the first chip 100 may be a memory chip, and the second chip 200 and the third chip 300 may be logic chips. The heat conduction member 400 can efficiently dissipate the heat of the first chip 100 to the circuit board 500. The above combinations are examples, and the electronic component (semiconductor device) of the embodiment may be configured by combining other types of chips without any problem.

[0091] In the example shown in Fig. 5(a), in a plan view, the heat conduction member 400 is arranged so as to include the effective region AA of the first chip 100, but the length in the longitudinal direction is shorter than the length in the longitudinal direction of the second chip 200 or the third chip 300. However, the present embodiment is not limited to this example. Figs. 6(a) to 6(c) are schematic plan views showing an electronic component 800 according to a modified example of the present embodiment.

[0092] As shown in Fig. 6(a), the longitudinal direction of the heat conduction member 400 in a plan view may be arranged substantially parallel to the longitudinal directions of the second chip 200 and the third chip 300, and the length of the heat conduction member 400 in this direction may be made larger than the lengths of the second chip 200 and the third chip 300. By arranging in this way, in addition to enhancing the cooling efficiency, the mechanical strength of the portion of the peripheral region PA of the first chip 100 that is not supported by the second chip 200 and the third chip 300 can be improved.

[0093] As shown in Fig. 6(b), the heat conduction member 400 may be arranged along three sides of the second chip 200 and / or three sides of the third chip 300. By arranging in this way, in addition to enhancing the cooling efficiency, the mechanical strength of the portion of the peripheral region PA of the first chip 100 that is not supported by the second chip 200 and the third chip 300 can be further improved.

[0094] As shown in Fig. 6(c), separately from the heat conduction member 400, a support member 450 may be provided in the peripheral region PA of the first chip 100 in a portion that is not supported by the second chip 200 and the third chip 300. By providing a member having a higher elastic modulus and being less likely to deform than the heat conduction member 400 as the support member 450, the mechanical strength of the electronic component 800 can be improved. Also, if the support member 450 is formed in advance before forming the heat conduction member 400, the support member 450 can function as an embankment structure for suppressing overhang when forming the heat conduction member 400.

[0095] (Manufacturing method) The manufacturing procedure of the electronic component according to this embodiment is the same as or similar to the manufacturing procedure of the electronic component according to Embodiment 1 described with reference to FIGS. 3(a) to 4(c), and thus the description thereof is omitted.

[0096] As described above, in Embodiment 2, the heat conductive member 400 that abuts on both the effective region AA of the first chip 100 and the circuit board 500 is provided. Thereby, heat generated from the effective region of the first chip 100 and heat propagated from the peripheral circuit to the effective region can be efficiently released to the circuit board 500. For this reason, inconveniences such as the first chip 100 operating abnormally or the characteristics of the semiconductor element deteriorating due to heat generation and heat accumulation can be suppressed.

[0097] [Embodiment 3] The electronic component (semiconductor device) according to Embodiment 3 will be described with reference to the drawings. Regarding matters common to Embodiment 1 or Embodiment 2, the description will be simplified or omitted. The first chip included in the electronic component according to this embodiment is a back-illuminated image sensor, and the second chip is a chip including at least one of a memory circuit or a logic circuit.

[0098] (Manufacturing Method) When manufacturing the electronic component according to this embodiment, the first chip 100 and the second chip 200 are joined in the same manner as in Embodiment 1 described with reference to FIGS. 3(a) to 3(c). Subsequent steps will be described with reference to FIGS. 7(a) to 7(e). Each figure schematically shows a cross section at each stage of the manufacturing process.

[0099] As shown in FIG. 7(a), a member FIL is formed on the side surface and the back surface BS2 of the second chip 200. The upper surface of the edge portion of the first chip 100 that was not in contact with the second chip 200 is also covered with the member FIL.

[0100] When, for example, silicon oxide is used as the material of the member FIL, the member FIL can be formed by methods such as SOG (spin-on glass) or CVD. When, for example, a resin such as an epoxy resin or an acrylic resin is used as the material of the member FIL, the member FIL can be formed by methods such as resin molding or dispenser.

[0101] Next, as shown in FIG. 7(b), the member FIL is polished by back grinding to expose and thin the back surface BS2 of the second chip 200. At this time, the upper surface of the member FIL and the back surface BS2 of the second chip 200 are flattened so that as little step as possible is generated.

[0102] Next, as shown in FIG. 7(c), holes are drilled from above in the member FIL on both sides of the second chip 200, and the heat conduction member 400 is filled inside the holes. The depth of the holes is set to a depth that reaches the outermost surface of the first insulating layer 130 provided on the first chip 100, and the filled heat conduction member 400 is configured to contact the first chip 100.

[0103] As the material of the heat conduction member 400, for example, a thermally conductive adhesive is used, and is filled inside the holes by methods such as dispenser or screen printing to form the heat conduction member 400. By using methods such as CMP or back grinding to flatten the step between the upper surface of the member FIL and the upper surface of the heat conduction member 400, the manufacturing yield in subsequent processes can be improved.

[0104] Next, as shown in FIG. 7(d), after the back surface BS1 side of the first chip 100 is polished and thinned, a color filter layer CF is formed. Note that FIG. 7(d) is shown with the top and bottom reversed from FIG. 7(c). Micro lenses (not shown) may be formed on the color filter layer CF. Further, an opening TV is formed that extends from the back surface BS1 of the first chip 100 to the external connection terminal 140P formed in the same layer as the first wiring layer 140.

[0105] Next, as shown in FIG. 7(e), the back surface BS2 of the second chip 200 is placed on the circuit board 500. As a result, the heat conduction member 400 abuts on both the first chip 100 and the circuit board 500. Also, using a wire such as gold, copper, or aluminum as the external connection member BP, the external connection terminal 140P and an electrode (not shown) on the circuit board 500 are connected, and the electronic component 800 is completed.

[0106] As described above, in the electronic component according to this embodiment, the first chip including the back-illuminated image sensor and the second chip including at least one of the memory circuit and the logic circuit are integrated. The heat conduction member 400 can be arranged so as not to overlap with the light receiving region of the image sensor when viewed through in a direction perpendicular to the main surface of the first chip. The heat conduction member 400 can efficiently dissipate the heat of the first chip to the circuit board without obstructing the optical path of the imaging light of the back-illuminated image sensor. Therefore, the operation of the back-illuminated image sensor is not adversely affected by heat generation or heat accumulation, and a stable and good image can be captured.

[0107] [Embodiment 4] As Embodiment 4, a system including an electronic component in which the first chip 100 is an image sensor and the second chip 200 is a chip including at least one of a memory circuit and a logic circuit will be described. FIG. 8(a) is a schematic diagram for explaining a device 9191 including a semiconductor device 930 including the electronic device according to the above-described embodiment. The device 9191 including the semiconductor device 930 will be described in detail.

[0108] The semiconductor device 930 includes a semiconductor device 910 in which a first chip as a photoelectric conversion device and a second chip including at least one of a memory circuit or a logic circuit are integrated. Further, in addition to the semiconductor device 910, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910. The package 920 can include a substrate to which the semiconductor device 910 is fixed and a lid such as glass facing the semiconductor device 910. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the substrate and a terminal provided on the semiconductor device 910.

[0109] The device 9191 can include at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror provided corresponding to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is a semiconductor device such as an ASIC.

[0110] The processing device 960 processes a signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or an ASIC for constituting an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0111] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970 or transmitted externally by a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960 separately from the storage circuit and the arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0112] Also, the device 9191 is suitable for electronic devices such as an information terminal having a photographing function (e.g., a smartphone or a wearable terminal) and a camera (e.g., an interchangeable-lens camera, a compact camera, a video camera, a surveillance camera). The mechanical device 990 in the camera can drive the components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for anti-vibration operation.

[0113] Also, the device 9191 can be a transportation device such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation device can be used as a moving device. The device 9191 as a transportation device is suitable for those that transport the semiconductor device 930 or those that assist and / or automate driving (operation) by means of a photographing function. The processing device 960 for assisting and / or automating driving (operation) can perform processing for operating the mechanical device 990 as a moving device based on the information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office device such as a copier, or an industrial device such as a robot. According to the above-described embodiment, since heat is efficiently dissipated from the chip of the image sensor to the circuit board, it is possible to stably acquire an image with good characteristics.

[0114] Therefore, if the semiconductor device 930 according to this embodiment is used in the device 9191, the value of the device can also be improved. For example, when the semiconductor device 930 is mounted on a transportation device to perform external shooting or measurement of the external environment of the transportation device, excellent performance can be obtained. Therefore, in manufacturing and selling the transportation device, deciding to mount the semiconductor device according to this embodiment on the transportation device is advantageous for enhancing the performance of the transportation device itself. In particular, the semiconductor device 930 is suitable for a transportation device that performs driving support and / or autonomous driving of the transportation device using the information obtained by the semiconductor device. Note that the implementation in vehicles, ships, aircraft, etc. is not limited to the application to devices that are practically used for transportation purposes. For example, it can also be suitably implemented in drones that perform aerial photography for various purposes such as inspection of buildings and agricultural facilities and monitoring of natural phenomena.

[0115] The photoelectric conversion system and the moving body according to this embodiment will be described with reference to FIGS. 8(b) and 8(c). FIG. 8(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device as the electronic component described in the above embodiment. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of a parallax image) from the plurality of pieces of image data acquired by the photoelectric conversion system 8. Further, the photoelectric conversion system 8 has a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means for acquiring distance information to an object. That is, the distance information is information related to parallax, defocus amount, distance to an object, and the like. The collision determination unit 804 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicatedly designed hardware, may be realized by a software module, or may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like.

[0116] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the photoelectric conversion system 8 is connected to a control ECU 820 which is a control device that outputs a control signal for generating a braking force for the vehicle based on the determination result of a collision determination unit 804. Also, the photoelectric conversion system 8 is connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, when the determination result of the collision determination unit 804 indicates a high possibility of collision, the control ECU 820 performs vehicle control to avoid the collision and reduce damage, such as applying the brakes, returning the accelerator, and suppressing the engine output. The alarm device 830 warns the user by sounding an alarm such as a sound, displaying alarm information on a screen of a car navigation system, or applying vibration to the seat belt or steering wheel.

[0117] In the present embodiment, the photoelectric conversion system 8 images the surroundings of the vehicle, for example, the front or the rear. FIG. 8(c) shows the photoelectric conversion system when imaging the front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 80. With such a configuration, the accuracy of distance measurement can be further improved.

[0118] In the above, an example of controlling so as not to collide with other vehicles has been described, but it is also applicable to control for automatically driving while following other vehicles and control for automatically driving so as not to deviate from the lane. Further, the photoelectric conversion system is not limited to vehicles such as the host vehicle, and can be applied to, for example, moving bodies (moving devices) such as ships, airplanes, or industrial robots. In addition, it can be applied not only to moving bodies but also to devices that widely utilize object recognition, such as an advanced road traffic system (ITS). According to the above-described embodiment, since heat is efficiently radiated from the chip of the image sensor to the circuit board, it is possible to stably acquire an image with good characteristics.

[0119] [Other Embodiments] Note that the present invention is not limited to the embodiments described above, and many modifications are possible within the technical idea of the present invention. For example, it is possible to implement by combining all or part of the different embodiments described above.

[0120] For example, in the above-described embodiment, in the first chip having a large projected area in plan view, one or two chips having a small projected area are integrated so as to be included, but three or more chips may be integrated with respect to the first chip. If the first chip and the circuit board are connected by a heat conduction member to form a heat dissipation path, the same effects as those of the above-described embodiment can be obtained.

[0121] Also, in an electronic component in which an electronic device integrating a plurality of chips and a circuit board are integrated, the circuit board is not necessarily electrically connected to only one chip. For example, the electrical connection method shown in FIG. 1(b) and the electrical connection method shown in FIG. 7(e) may be used in combination so that the circuit board is electrically connected to a plurality of chips.

[0122] Also, the arrangement of the support member 450 is not limited to the examples of FIGS. 2(c) and 6(c). For example, the heat conduction member and the support member may be alternately arranged in a columnar shape.

[0123] The photoelectric conversion device to which the present invention is applied is not limited to a specific form. For example, regarding the light receiving portion, it may be either a surface irradiation type or a back surface irradiation type. The image signal output from the photoelectric conversion device may be an analog signal or a digital signal. Further, the use of the photoelectric conversion device according to the embodiment is not limited to imaging. For example, it can also be applied to a distance measuring device (a device for distance measurement using focus detection or TOF (Time Of Flight)), a photometric device (a device for measuring the incident light amount), and the like.

[0124] This specification discloses at least the following matters. [Matter 1] A first chip having a first semiconductor element, A second chip having a second semiconductor element, A circuit board, and the first chip and the second chip are fixed in a facing orientation such that the surface of the first chip on which the first semiconductor element is formed faces the surface of the second chip on which the second semiconductor element is formed, the first chip, the second chip, and the circuit board are integrated such that the second chip is positioned between the first chip and the circuit board, at least one of the first chip and the second chip and the circuit board are electrically connected via a connecting member, a heat conduction member that abuts both the first chip and the circuit board is disposed at a position where the second chip does not exist when viewed through from a direction perpendicular to the main surface of the first chip, An electronic component characterized by the above. [Item 2] When the electronic component is viewed through from a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed along at least a part of the outer edge of the second chip. The electronic component according to Item 1, characterized by the above. [Item 3] When the electronic component is viewed through from a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed surrounding the second chip. The electronic component according to Item 1, characterized by the above. [Item 4] When the electronic component is viewed through from a direction perpendicular to the main surface of the first chip, a plurality of the heat conduction members are disposed sandwiching the second chip therebetween. The electronic component according to Item 1, characterized by the above. [Item 5] When the electronic component is viewed through from a direction perpendicular to the main surface of the first chip, a support member that supports between the first chip and the circuit board is provided at a position where the second chip and the heat conduction member do not exist. The electronic component according to any one of Items 1 to 4, characterized by the above. [Item 6] Further comprising a third chip having a third semiconductor element. The first chip and the third chip are fixed in a facing direction in which the surface of the first chip on the side where the first semiconductor element is formed and the surface of the third chip on the side where the third semiconductor element is formed face each other. They are integrated so that the third chip is positioned between the first chip and the circuit board. When viewed through from a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed at a position where the second chip and the third chip do not exist. The electronic component according to item 1, characterized in that. [Item 7] When the electronic component is viewed through from a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed between the second chip and the third chip. The electronic component according to item 6, characterized in that. [Item 8] When the electronic component is viewed through from a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed at a position overlapping the first semiconductor element. The electronic component according to item 6 or 7, characterized in that. [Item 9] When the electronic component is viewed through from a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed along at least a part of the outer edge of the third chip. The electronic component according to any one of items 6 to 8, characterized in that. [Item 10] When viewed through from a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed along three sides of the third chip. The electronic component according to any one of items 6 to 9, characterized in that. [Item 11] When viewed through from a direction perpendicular to the main surface of the first chip, a support member for supporting between the first chip and the circuit board is provided at a position where the third chip does not exist. The electronic component according to any one of items 6 to 10, characterized in that. [Item 12] The first chip includes a first substrate, and the first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode that is different in layer from the first wiring layer are provided on a first main surface of the first substrate. The second chip includes a second substrate, and the second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode that is different in layer from the second wiring layer are provided on a second main surface of the second substrate. With the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode interposed therebetween, the first main surface and the second main surface face each other, and the first chip and the second chip are fixed so that the first connection electrode and the second connection electrode are electrically connected. The electronic component according to any one of Matters 1 to 11, characterized in that. [Matter 13] The connection member electrically connects the second wiring layer and the circuit board. The electronic component according to Matter 12, characterized in that. [Matter 14] The connection member electrically connects the first wiring layer and the circuit board. The electronic component according to Matter 12, characterized in that. [Matter 15] The first insulating layer and the second insulating layer are joined. The electronic component according to any one of Matters 12 to 14, characterized in that. [Matter 16] The first insulating layer and the second insulating layer are made of the same type of insulating material. The electronic component according to any one of Matters 12 to 15, characterized in that. [Matter 17] The first connection electrode and the second connection electrode are joined. The electronic component according to any one of Matters 12 to 16, characterized in that. [Matter 18] The first chip is a chip including an image sensor, and the second chip is a chip including at least one of a memory circuit and a logic circuit. The electronic component according to any one of Items 1 to 17, characterized in that... [Item 19] At least one of a color filter or a microlens is provided in the image sensor. The electronic component according to Item 18, characterized in that... [Item 20] The heat conduction member is made of any one of a thermally conductive adhesive, a thermally conductive grease, and a resin containing a thermally conductive filler. The electronic component according to any one of Items 1 to 19, characterized in that...

Explanation of Reference Numerals

[0125] 100... First chip / 110... First substrate / 120... Semiconductor element / 130... First insulating layer / 140... First wiring layer / 150... First connection electrode / 200... Second chip / 210... Second substrate / 220... Semiconductor element / 230... Second insulating layer / 240... Second wiring layer / 250... Second connection electrode / 300... Third chip / 310... Third substrate / 320... Semiconductor element / 330... Third insulating layer / 340... Third wiring layer / 350... Third connection electrode / 400... Heat conduction member / 450... Support member / 500... Circuit board / 800... Electronic component / AA... Effective area / BP... External connection member / BS1... Rear surface / BS2... Rear surface / FS1... First main surface / FS2... Second main surface / FS3... Third main surface / PA... Peripheral area / SR... Solder resist / TE... Through electrode / TV... Opening

Claims

1. a first chip having a first semiconductor element; a second chip having a second semiconductor element; and a circuit board, the first chip and the second chip are fixed in a facing orientation such that the surface of the first chip on the side where the first semiconductor element is formed faces the surface of the second chip on the side where the second semiconductor element is formed; the first chip, the second chip, and the circuit board are integrated such that the second chip is positioned between the first chip and the circuit board; at least one of the first chip and the second chip is electrically connected to the circuit board via a connection member; a heat conduction member that abuts both the first chip and the circuit board is disposed at a position where the second chip does not exist when viewed through in a direction perpendicular to the main surface of the first chip; An electronic component characterized by the above.

2. When the electronic component is viewed through in a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed along at least a part of the outer edge of the second chip. The electronic component according to claim 1, characterized by the above.

3. When the electronic component is viewed through in a direction perpendicular to the main surface of the first chip, the heat conduction member is disposed surrounding the second chip. The electronic component according to claim 1, characterized by the above.

4. When the electronic component is viewed through in a direction perpendicular to the main surface of the first chip, a plurality of the heat conduction members are disposed sandwiching the second chip therebetween. The electronic component according to claim 1, characterized by the above.

5. When the electronic component is viewed through in a direction perpendicular to the main surface of the first chip, a support member that supports between the first chip and the circuit board is provided at a position where the second chip and the heat conduction member do not exist. The electronic component according to claim 1, characterized in that...

6. further comprising a third chip having a third semiconductor element, the first chip and the third chip are fixed in a facing orientation such that the surface of the first chip on the side where the first semiconductor element is formed faces the surface of the third chip on the side where the third semiconductor element is formed, integrated such that the third chip is positioned between the first chip and the circuit board, the heat conductive member is disposed at a position where the second chip and the third chip do not exist when viewed through in a direction perpendicular to the main surface of the first chip. The electronic component according to claim 1, characterized in that...

7. When the electronic component is viewed through in a direction perpendicular to the main surface of the first chip, the heat conductive member is disposed between the second chip and the third chip. The electronic component according to claim 6, characterized in that...

8. When the electronic component is viewed through in a direction perpendicular to the main surface of the first chip, the heat conductive member is disposed at a position overlapping with the first semiconductor element. The electronic component according to claim 6, characterized in that...

9. When the electronic component is viewed through in a direction perpendicular to the main surface of the first chip, the heat conductive member is disposed along at least a part of the outer edge of the third chip. The electronic component according to claim 6, characterized in that...

10. When viewed through in a direction perpendicular to the main surface of the first chip, the heat conductive member is disposed along three sides of the third chip. The electronic component according to claim 6, characterized in that...

11. When viewed through in a direction perpendicular to the main surface of the first chip, a support member for supporting between the first chip and the circuit board is provided at a position where the third chip does not exist. The electronic component according to claim 6, characterized in that...

12. The first chip includes a first substrate, and the first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode different in layer from the first wiring layer are provided on a first main surface of the first substrate. The second chip includes a second substrate, and the second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode different in layer from the second wiring layer are provided on a second main surface of the second substrate. With the first insulating layer, the first wiring layer, the first connection electrode, the second insulating layer, the second wiring layer, and the second connection electrode interposed therebetween, the first main surface and the second main surface face each other, and the first chip and the second chip are fixed so that the first connection electrode and the second connection electrode are electrically connected. The electronic component according to any one of claims 1 to 11, characterized in that...

13. The connection member electrically connects the second wiring layer and the circuit board. The electronic component according to claim 12, characterized in that...

14. The connection member electrically connects the first wiring layer and the circuit board. The electronic component according to claim 12, characterized in that...

15. The first insulating layer and the second insulating layer are joined. The electronic component according to claim 12, characterized in that...

16. The first insulating layer and the second insulating layer are made of the same type of insulating material. The electronic component according to claim 12, characterized in that...

17. The first connection electrode and the second connection electrode are joined. The electronic component according to claim 12, characterized in that...

18. The first chip is a chip equipped with an image sensor, and the second chip is a chip equipped with at least one of a memory circuit or a logic circuit. The electronic component according to any one of claims 1 to 11, characterized in that.

19. At least one of a color filter or a microlens is provided in the image sensor. The electronic component according to claim 18, characterized in that.

20. The heat conductive member is made of any one of a thermally conductive adhesive, a thermally conductive grease, and a resin containing a thermally conductive filler. The electronic component according to any one of claims 1 to 11, characterized in that.

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