Three-dimensional memory devices

Abstract

To provide three-dimensional memory devices and methods for forming the same.SOLUTION: A 3D memory device includes: a substrate; a peripheral circuit on the substrate; a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit; an N-type doped semiconductor layer above the memory stack; a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer; and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of fabricating the same.

Background Art

[0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of the memory cells approaches a lower limit, planar processes and fabrication techniques become difficult and costs increase. As such, the memory density of planar memory cells is approaching an upper limit.

[0003] 3D memory architectures can address this density limit of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0004] Embodiments of 3D memory devices and methods of forming the same are disclosed herein.

[0005] In one example, a 3D memory device includes a substrate, peripheral circuitry on the substrate, a memory stack including alternating conductor and dielectric layers on the peripheral circuitry, an N-type doped semiconductor layer on the memory stack, a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer, and a source contact on the memory stack and in contact with the N-type doped semiconductor layer. An upper end portion of each of the plurality of channel structures is coplanar with or below a top surface of the N-type doped semiconductor layer.

[0006] In another example, a 3D memory device includes a substrate, a memory stack including alternating conductor layers and dielectric layers on the substrate, an N-type doped semiconductor layer on the memory stack, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer. Each of the plurality of channel structures includes a memory film and a semiconductor channel. An upper end of the memory film is below an upper end of the semiconductor channel. The N-type doped semiconductor layer surrounds a portion of the semiconductor channel and includes a semiconductor plug in contact therewith. A doping concentration of the semiconductor plug is different from a doping concentration of the remaining portion of the N-type doped semiconductor layer.

[0007] In yet another example, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes peripheral circuitry. The second semiconductor structure includes a memory stack including alternating conductor layers and dielectric layers, an N-type doped semiconductor layer, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuitry. The N-type doped semiconductor layer includes a semiconductor plug surrounding a portion of each of the plurality of channel structures penetrating into the N-type doped semiconductor layer. A doping concentration of the semiconductor plug is different from a doping concentration of the remaining portion of the N-type doped semiconductor layer.

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure and further to enable one skilled in the art to make and use the disclosure.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0011] Although specific configurations and arrangements are described, it will be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may be employed in various other applications.

[0012] Note that references in the specification such as "one embodiment", "embodiment", "exemplary one embodiment", "some embodiments", etc. indicate that the described embodiments may have certain features, structures, or characteristics, but not all embodiments necessarily include such features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in relation to one embodiment, it will be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in relation to other embodiments, whether explicitly described or not.

[0013] Generally, terms can be understood at least in part from their usage in context. For example, at least in part depending on the context, phrases such as "one or more" as used herein can be used to describe a feature, structure, or characteristic in the singular sense or to describe a combination of features, structures, or characteristics in the plural sense. Similarly, here too, articles such as "a", "an", or "the" in the English language can be understood at least in part depending on the context as conveying either singular or plural usage. In addition, the phrase "based on" can be understood not necessarily to convey an exclusive set of elements, but rather, here too at least in part depending on the context, to allow for the presence of additional elements not necessarily explicitly described.

[0014] As used in this disclosure, the meanings of "above", "higher than", and "directly above" not only mean that "above" means "directly above something", but also include the meaning of "above something" with intermediate features or layers in between. It should be immediately understood that "higher than" or "directly above" should be interpreted in the broadest sense such that it can include not only the meaning of "higher than" or "directly above something", but also the meaning of being "higher than" or "directly above something" (i.e., directly above something) without any intermediate features or layers in between.

[0015] Spatial relative terms such as "below", "lower than", "bottom", "top", "upper side", and similar terms may be used herein to facilitate the description when describing the relationship between one element or feature and another element or feature, as illustrated in the figures. The spatial relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures or in operation. The device may be oriented in some other way (rotated 90 degrees or in some other orientation), and the spatial relative descriptors used herein may, likewise, be interpreted accordingly.

[0016] As used herein, the term "substrate" refers to the material to which subsequent material layers are added. Patterns can be formed on the substrate itself. The materials added on the substrate can be patterned or left unpatterned. Further, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from electrically non-conductive materials such as glass, plastic, or sapphire wafers.

[0017] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend across the entire underlying or overlying structure, or can have an extent smaller than the extent of the underlying or overlying structure. Further, a layer can be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer can be disposed between the top and bottom surfaces of a continuous structure, or between a pair of horizontal planes at the top and bottom surfaces. A layer can extend along a horizontal, vertical, and / or tapered surface. A substrate can be a layer, can contain one or more layers therein, and / or can have one or more layers thereon, above it, and / or below it. A layer can also contain a plurality of layers. For example, an interconnect layer can include one or more conductor layers and contact layers (wherein interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0018] As used herein, the phrase "nominal / nominally" refers to a desired or target value of a characteristic or parameter for a component or process operation that is set at the design stage of a product or process, along with a range of values above and / or below the desired value. The range of values can be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a particular technology node associated with the semiconductor device of the subject matter. Based on the particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10 - 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, the term "3D memory device" refers to a semiconductor device having a vertical orientation string of memory cell transistors (referred to herein as a "memory string", such as a NAND memory string) on a horizontally oriented substrate such that the memory string extends in a direction perpendicular to the substrate. As used herein, the phrase "vertical / perpendicularly" means nominally perpendicular to the outer surface of the substrate.

[0020] In some 3D memory devices, such as 3D NAND memory devices, a slit structure (e.g., a gate line slit (GLS)) is used to make electrical contact to a source of a memory array, such as an array common source (ACS), from the front side of the device. However, a front side source contact can affect the electrical performance of a 3D memory device by introducing both leakage current and parasitic capacitance between the word line and the source contact, even when a spacer is present therebetween. The formation of the spacer also complicates the manufacturing process. In addition to affecting electrical performance, the slit structure typically includes wall-shaped polysilicon and / or overgrowth, which can introduce local stress, causing wafer warping or bowing, thereby reducing production yield.

[0021] Furthermore, in some 3D NAND memory devices, semiconductor plugs are selectively grown, for example, to surround the sidewalls of a channel structure, which is referred to as sidewall selective epitaxial growth (SEG). Compared to another type of semiconductor plug formed at the lower end of the channel structure, e.g., bottom SEG, the formation of sidewall SEG avoids etching of the memory film and semiconductor channel at the bottom of the channel hole (also referred to as “SONO” punch), thereby enlarging the process window, particularly when fabricating 3D NAND memory devices with advanced technologies such as having 96 or more levels in a multi - deck architecture. Sidewall SEG is typically formed by replacing a sacrificial layer between the substrate and the stack structure with sidewall SEG, which involves multiple deposition and etching processes through slit openings. However, as the levels of 3D NAND memory devices continue to increase, the aspect ratio of the slit openings through the stack structure becomes large, making the deposition and etching processes through the slit openings more difficult, and it is not desirable to form sidewall SEG using known approaches due to increased cost and reduced yield.

[0022] Various embodiments according to the present disclosure provide 3D memory devices having backside source contacts. By moving the source contacts from the front side to the back side, the effective memory cell array area is increased and the spacer formation process can be skipped, so that the cost per memory cell can be reduced. Moreover, the device performance can be improved by avoiding leakage current and parasitic capacitance between the word line and the source contact, and by reducing local stress caused by the front side slit structure (as the source contact). Sidewall SEGs (e.g., semiconductor plugs) are formed from the back side of the substrate, thereby avoiding deposition or etching processes through openings that penetrate the stack structure on the front side of the substrate. As a result, the complexity and cost of the manufacturing process can be reduced, and the product yield can be increased. Also, the manufacturing process of the sidewall SEGs is no longer affected by the aspect ratio of the openings that penetrate the stack structure, i.e., is not limited by the level of the memory stack, so that the scalability of the 3D memory device can also be improved.

[0023] In some embodiments, the substrate on which the memory stack is formed is removed from the back side to expose the channel structure prior to the formation of the sidewall SEGs. Thus, the choice of substrate can be extended to, for example, a dummy wafer for cost reduction or a silicon-on-insulator (SOI) wafer for simplifying the manufacturing process. Removal of the substrate can also avoid the difficult problem of thickness uniformity control in known methods using a backside thinning process.

[0024] For example, various 3D memory device architectures and methods of fabricating the same having different erase operation mechanisms are disclosed in the present disclosure so as to be able to accommodate different requirements and applications. In some embodiments, the sidewall SEG is part of an N-type doped semiconductor layer to enable gate-induced drain leakage (GIDL) erasure by the 3D memory device. In some embodiments, the sidewall SEG is part of a P-type doped semiconductor layer to enable P-well bulk erasure by the 3D memory device.

[0025] FIG. 1 is a side view illustrating a cross-section of an exemplary 3D memory device 100 according to some embodiments of the present disclosure. In some embodiments, the 3D memory device 100 is a bonded chip comprising a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 are connected at a bonding interface 106 therebetween according to some embodiments. As shown in FIG. 1, the first semiconductor structure 102 may include a substrate 101 that can include silicon (e.g., single-crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI, or any other suitable material.

[0026] The first semiconductor structure 102 of the 3D memory device 100 can include peripheral circuits 108 on a substrate 101. Note that the x-axis and y-axis are included in FIG. 1 to further illustrate the spatial relationship of the components within the 3D memory device 100 having the substrate 101. The substrate 101 includes two outer surfaces (e.g., a top surface and a bottom surface) that extend laterally (i.e., horizontally) in the x-direction. As used herein, whether one component (e.g., a layer or a device) is "above", "higher than", or "lower than" another component (e.g., a layer or a device) of a semiconductor device (e.g., the 3D memory device 100) is determined with respect to the substrate (e.g., the substrate 101) of the semiconductor device in the y-direction (i.e., the vertical direction) when the substrate is positioned at the bottommost plane of the semiconductor device in the y-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0027] In some embodiments, the peripheral circuit 108 is configured to control and sense the 3D memory device 100. The peripheral circuit 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuit used to facilitate the operation of the 3D memory device 100, including, but not limited to, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 108 may well include transistors formed “on” the substrate 101, with all or part of the transistors being formed within the substrate 101 (e.g., below the top surface of the substrate 101) and / or directly on top of the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) may also be formed within the substrate 101. The transistors are fast according to some embodiments, using advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). In some embodiments, it is understood that the peripheral circuit 108 may further include any other circuit compatible with an advanced logic process, including logic circuits such as processors and programmable logic devices (PLDs), or memory circuits such as static random access memory (SRAM) and dynamic RAM (DRAM).

[0028] In some embodiments, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuit 108 for communicating electrical signals with the peripheral circuit 108. The interconnect layer can include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term "interconnect" can broadly include any suitable type of interconnect, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also referred to as "inter-metal dielectric (IMD) layers") in which the interconnect lines and VIA contacts can be formed. That is, the interconnect layer can include interconnect lines and VIA contacts within the plurality of ILD layers. The interconnect lines and VIA contacts within the interconnect layer can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers within the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0029] As shown in FIG. 1, the first semiconductor structure 102 of the 3D memory device 100 can further include a bonding layer 110 at the bonding interface 106 and above the interconnect layer and the peripheral circuit 108. The bonding layer 110 can include a plurality of bonding contacts 111 and a dielectric that electrically insulates the bonding contacts 111. The bonding contacts 111 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of the bonding layer 110 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 111 and the surrounding dielectric within the bonding layer 110 can be used for hybrid bonding.

[0030] Similarly, as shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can also include a bonding layer 112 at the bonding interface 106 and also above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 can include a plurality of bonding contacts 113 and a dielectric that electrically insulates the bonding contacts 113. The bonding contacts 113 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of the bonding layer 112 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 113 and the surrounding dielectric within the bonding layer 112 can be used for hybrid bonding. The bonding contacts 113 are in contact with the bonding contacts 111 at the bonding interface 106 in some embodiments.

[0031] As described in detail below, the second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 facing each other at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 110 and 112 as a result of a hybrid bonding (also referred to as a "metal / dielectric hybrid bonding"), which is a direct bonding technique (i.e., forming a bond between surfaces without using an intermediate layer such as solder or an adhesive) and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface 106 is the location where the bonding layers 112 and 110 contact and bond. In practice, the bonding interface 106 can be a layer having a specific thickness including the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0032] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 for transferring electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which interconnect lines and VIA contacts can be formed. The interconnect lines and VIA contacts in the interconnect layer can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0033] In some embodiments, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can include an array of channel structures 124 that function as an array of NAND memory strings. As shown in FIG. 1, each channel structure 124 can have a plurality of pairs each including a conductor layer 116 and a dielectric layer 118 penetrating vertically therethrough. The alternately arranged conductor layers 116 and dielectric layers 118 are part of the memory stack 114. The number of pairs of conductor layers 116 and dielectric layers 118 in the memory stack 114 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D memory device 100. It is understood that in some embodiments, the memory stack 114 can have a multi-deck architecture (not shown) including a plurality of memory decks stacked on top of each other. The number of pairs of conductor layers 116 and dielectric layers 118 in each memory deck can be the same or different.

[0034] The memory stack 114 can include a plurality of conductor layers 116 and dielectric layers 118 arranged alternately. The conductor layers 116 and dielectric layers 118 within the memory stack 114 may be alternately arranged in the vertical direction. In other words, except for those at the top or bottom of the memory stack 114, each conductor layer 116 can be adjacent to two dielectric layers 118 on both sides, and each dielectric layer 118 can be adjacent to two conductor layers 116 on both sides. The conductor layer 116 can include a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductor layer 116 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductor layer 116 extends horizontally as a word line and can end in one or more staircase structures of the memory stack 114. The dielectric layer 118 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0035] As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can also include an N-type doped semiconductor layer 120 above the memory stack 114. The N-type doped semiconductor layer 120 can be an example of the "sidewall SEG" described above. The N-type doped semiconductor layer 120 can include a semiconductor material such as silicon. In some embodiments, the N-type doped semiconductor layer 120 includes polysilicon formed by a deposition technique, as will be described in detail below. In some embodiments, the N-type doped semiconductor layer 120 includes single crystal silicon, such as a device layer of an SOI wafer, as will be described in detail below. The N-type doped semiconductor layer 120 is preferably doped with any suitable N-type dopant such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contributes to providing free electrons and enhancing the conductivity of the intrinsic semiconductor. For example, the N-type doped semiconductor layer 120 can be a polysilicon layer doped with an N-type dopant such as P, Ar, or Sb. In some embodiments, the N-type doped semiconductor layer 120 is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having a plurality of polysilicon sub-layers with a non-uniform doping concentration at its interface (e.g., a sharp change in doping concentration at the interface between two sub-layers). It is understood that the doping concentration of the N-type dopant in the N-type doped semiconductor layer 120 can still change gradually in the vertical direction as long as there is no sharp doping concentration change that can distinguish two or more sub-layers due to the change in doping concentration.

[0036] In some embodiments, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., as semiconductor channel 128) and a composite dielectric layer (e.g., as memory film 126). In some embodiments, semiconductor channel 128 includes silicon such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, memory film 126 is a composite layer including a tunnel layer, a storage layer (also referred to as a "charge trap layer"), and a blocking layer. The remaining space of channel structure 124 may be partially or completely filled with a capping layer including a dielectric material such as silicon oxide and / or voids. Channel structure 124 can have a cylindrical shape (e.g., pillar shape). The capping layer of memory film 126, semiconductor channel 128, tunnel layer, storage layer, and blocking layer are radially arranged and configured in this order from the center towards the outer surface of the pillar in some embodiments. The tunnel layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, memory film 126 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0037] In some embodiments, channel structure 124 further includes a channel plug 129 at the bottom (e.g., lower end) of channel structure 124. As used herein, the "upper end" of a component (e.g., channel structure 124) is the end far from substrate 101 in the y direction, and the "lower end" of a component (e.g., channel structure 124) is the end close to substrate 101 in the y direction when substrate 101 is positioned within the bottom plane of 3D memory device 100. Channel plug 129 can include a semiconductor material (e.g., polysilicon). In some embodiments, channel plug 129 functions as the drain of a NAND memory string.

[0038] As shown in FIG. 1, each channel structure 124 can penetrate into the N-type doped semiconductor layer 120 through the alternately arranged conductor layers 116 and dielectric layers 118 of the memory stack 114 in the vertical direction. The upper end of each channel structure 124 may be flush with or below the top surface of the N-type doped semiconductor layer 120. That is, in some embodiments, the channel structure 124 does not extend beyond the top surface of the N-type doped semiconductor layer 120. In some embodiments, as shown in FIG. 1, the upper end of the memory film 126 is below the upper end of the semiconductor channel 128 of the channel structure 124. In some embodiments, the upper end of the memory film 126 is below the top surface of the N-type doped semiconductor layer 120, and the upper end of the semiconductor channel 128 is flush with or below the top surface of the N-type doped semiconductor layer 120. For example, as shown in FIG. 1, the memory film 126 ends at the bottom surface of the N-type doped semiconductor layer 120, and the semiconductor channel 128 extends above the bottom surface of the N-type doped semiconductor layer 120, whereby the N-type doped semiconductor layer 120 can surround and contact the top 127 of the semiconductor channel 128 penetrating into the N-type doped semiconductor layer 120. In some embodiments, the doping concentration of the top 127 of the semiconductor channel 128 penetrating into the N-type doped semiconductor layer 120 is different from the doping concentration of the remaining portion of the semiconductor channel 128. For example, the semiconductor channel 128 may include undoped polysilicon excluding the top 127, which may include doped polysilicon to enhance conductivity when forming an electrical connection with the surrounding N-type doped semiconductor layer 120.

[0039] In some embodiments, the N-type doped semiconductor layer 120 includes semiconductor plugs 122 that each surround and contact the top 127 of each semiconductor channel 128 of the channel structure 124 that penetrates into the N-type doped semiconductor layer 120. The semiconductor plugs 122 include, according to some embodiments, doped polysilicon, for example, N-type doped polysilicon. Since the semiconductor plugs 122 can be formed in a post-process after the formation of the remaining portion of the N-type doped semiconductor layer 120, as will be described in detail below, the doping concentration of the semiconductor plugs 122 can be different from the doping concentration of the remaining portion of the N-type doped semiconductor layer 120. In some embodiments, the semiconductor plugs 122 include polysilicon (e.g., N-type doped polysilicon), and the remaining portion of the N-type doped semiconductor layer 120 includes single-crystalline silicon (e.g., N-type doped single-crystalline silicon). In some embodiments, the semiconductor plugs 122 include polysilicon (e.g., N-type doped polysilicon), and the remaining portion of the N-type doped semiconductor layer 120 includes polysilicon (e.g., N-type doped polysilicon), but having a different doping concentration from that of the semiconductor plugs 122.

[0040] Each semiconductor plug 122 can surround and contact the sidewalls of the top 127 of each semiconductor channel 128. As a result, the semiconductor plug 122 of the N-type doped semiconductor layer 120 can act as a "sidewall SEG (e.g., semiconductor plug)" of the channel structure 124 and can replace the "bottom SEG (e.g., semiconductor plug)". Further, as will be described in detail below, the formation of the semiconductor plug 122 is performed on the opposite side of the memory stack 114, thereby avoiding any deposition or etching process through the opening penetrating the memory stack 114, thereby reducing the manufacturing complexity and cost and improving the yield and vertical scalability. Depending on the relative position of the upper end of the semiconductor channel 128 of each channel structure 124 with respect to the top surface of the N-type doped semiconductor layer 120, the semiconductor plug 122 can be formed in contact with the upper end above the semiconductor channel 128 as well when the upper end of the semiconductor channel 128 is below the top surface of the N-type doped semiconductor layer 120, as shown in FIG. 1 for example. In other examples where the upper end of the semiconductor channel 128 is on the same plane as the top surface of the N-type doped semiconductor layer 120, it is understood that the semiconductor plug 122 can be formed by surrounding and contacting only the sidewalls of the top 127 of the semiconductor channel 128.

[0041] Nevertheless, the N-type doped semiconductor layer 120 surrounding the top 127 of the semiconductor channel 128 of the channel structure 124 together with the semiconductor plug 122 (e.g., as a sidewall SEG) can enable GIDL-assisted body biasing for the erase operation of the 3D memory device 100. GIDL around the source select gate of the NAND memory string can generate a hole current in the NAND memory string and can raise the body potential for the erase operation.

[0042] As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can further include an insulating structure 130 that vertically penetrates the alternately arranged conductor layers 116 and dielectric layers 118 of each memory stack 114. Unlike the channel structure 124 that further penetrates into the N-type doped semiconductor layer 120, the insulating structure 130, in some embodiments, stops at the bottom surface of the N-type doped semiconductor layer 120, that is, it does not extend vertically into the N-type doped semiconductor layer 120. That is, the top surface of the insulating structure 130 may be coplanar with the bottom surface of the N-type doped semiconductor layer 120. Each insulating structure 130 can extend laterally and also separate the channel structure 124 into a plurality of blocks. That is, the memory stack 114 is divided into a plurality of memory blocks by the insulating structures 130, and thereby, the array of channel structures 124 can be separated into each memory block. Different from the slit structure of the existing 3D NAND memory device described above that includes a front-side ACS contact, the insulating structure 130 does not include a contact therein (that is, it does not function as a source contact), and thus, in some embodiments, it does not introduce parasitic capacitance and leakage current due to the conductor layer 116 (including the word line). In some embodiments, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 can be filled with silicon oxide.

[0043] Furthermore, as will be described in detail below, since the openings for forming the insulating structure 130 are not used to form the N-type doped semiconductor layer 120 and the semiconductor plug 122 therein (e.g., as sidewall SEGs), even as the number of alternately arranged conductor layers 116 and dielectric layers 118 increases and the aspect ratio of the openings increases, it has no effect on the formation of the N-type doped semiconductor layer 120 and the semiconductor plug 122 therein.

[0044] Instead of a front-side source contact, the 3D memory device 100 can include a back-side source contact 132 that is above the memory stack 114 and in contact with the N-type doped semiconductor layer 120, as shown in FIG. 1. The source contact 132 and the memory stack 114 (and the insulating structure 130 therethrough) may be disposed on the opposite side of the N-type doped semiconductor layer 120 and can thus be regarded as a "back-side" source contact. In some embodiments, the source contact 132 is electrically connected to the semiconductor channel 128 of the channel structure 124 through the semiconductor plug 122 of the N-type doped semiconductor layer 120. In some embodiments, the source contact 132 is not laterally aligned with the insulating structure 130 but is adjacent to the channel structure 124 to reduce the resistance of the electrical connection therebetween. For example, the source contact 132 may be in the lateral direction (e.g., the x direction in FIG. 1) between the insulating structure 130 and the channel structure 124. The source contact 132 can include any suitable type of contact. In some embodiments, the source contact 132 includes a VIA contact. In some embodiments, the source contact 132 includes a laterally extending wall-shaped contact. The source contact 132 can include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., titanium nitride (TiN)).

[0045] As shown in FIG. 1, the 3D memory device 100 can further include a BEOL interconnect layer 133 that is on and electrically connected to a source contact 132 for pad out, e.g., for transferring electrical signals between the 3D memory device 100 and an external circuit. In some embodiments, the interconnect layer 133 includes one or more ILD layers 134 on the N-type doped semiconductor layer 120 and a redistribution layer 136 on the ILD layer 134. The upper end portion of the source contact 132 is, in some embodiments, coplanar with the top surface of the ILD layer 134 and the bottom surface of the redistribution layer 136, and the source contact 132 penetrates vertically through the ILD layer 134 into the N-type doped semiconductor layer 120. The ILD layer 134 in the interconnect layer 133 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The redistribution layer 136 in the interconnect layer 133 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the redistribution layer 136 includes Al. In some embodiments, the interconnect layer 133 further includes a passivation layer 138 as an outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 can be exposed from the passivation layer 138 as a contact pad 140. That is, the interconnect layer 133 of the 3D memory device 100 can also include a contact pad 140 for wire bonding and / or bonding with an interposer.

[0046] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 that pass through the N-type doped semiconductor layer 120. Since the N-type doped semiconductor layer 120 may be a thinned substrate, such as the device layer of a SOI wafer, in some embodiments, the contacts 142 and 144 are through-silicon contacts (TSCs). In some embodiments, contact 142 penetrates the N-type doped semiconductor layer 120 and the ILD layer 134 to contact the redistribution layer 136, whereby the N-type doped semiconductor layer 120 is electrically connected to contact 142 through the source contact 132 of the interconnect layer 133 and the redistribution layer 136. In some embodiments, contact 144 penetrates the N-type doped semiconductor layer 120 and the ILD layer 134 to contact the contact pad 140. Each of contacts 142 and 144 can include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN). In some embodiments, at least contact 144 further includes a spacer (e.g., a dielectric layer) for electrically isolating contact 144 from the N-type doped semiconductor layer 120.

[0047] In some embodiments, the 3D memory device 100 further includes peripheral contacts 146 and 148 that each extend vertically outside of the memory stack 114. Each peripheral contact 146 or 148 can have a depth greater than the depth of the memory stack 114 such that it extends vertically from the bonding layer 112 to the N-type doped semiconductor layer 120 within the peripheral region outside of the memory stack 114. In some embodiments, the peripheral contact 146 is below the contact 142 and in contact with the contact 142, whereby the N-type doped semiconductor layer 120 is electrically connected to the peripheral circuit 108 within the first semiconductor structure 102 through at least the source contact 132, the interconnect layer 133, the contact 142, and the peripheral contact 146. In some embodiments, the peripheral contact 148 is below the contact 144 and in contact with the contact 144, whereby the peripheral circuit 108 within the first semiconductor structure 102 is electrically connected to the contact pad 140 for pad out through at least the contact 144 and the peripheral contact 148. Each of the peripheral contacts 146 and 148 can include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0048] As shown in FIG. 1, 3D memory device 100 includes various local contacts (also referred to as "C1") as part of the interconnect structure and is in direct contact with the structures within memory stack 114. In some embodiments, the local contacts include channel local contacts 150 that are each below and in contact with the lower end of each respective channel structure 124. Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fanout. In some embodiments, the local contacts further include word line local contacts 152 that are each below and in contact with each respective conductor layer 116 (including word lines) in the staircase structure of memory stack 114 for word line fanout. Local contacts such as channel local contacts 150 and word line local contacts 152 can be electrically connected to the peripheral circuit 108 of the first semiconductor structure 102 through at least bonding layers 112 and 110. Local contacts such as channel local contacts 150 and word line local contacts 152 can each include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0049] FIG. 2 is a side view illustrating a cross-section of another exemplary 3D memory device 200 according to some embodiments of the present disclosure. In some embodiments, 3D memory device 200 is a bonded chip that includes a first semiconductor structure 202 and a second semiconductor structure 204 stacked on the first semiconductor structure 202. The first semiconductor structure 202 and the second semiconductor structure 204 are coupled at a bonding interface 206 therebetween in some embodiments. As shown in FIG. 2, the first semiconductor structure 202 can include a substrate 201 that can include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0050] The first semiconductor structure 202 of the 3D memory device 200 can include peripheral circuits 208 on a substrate 201. In some embodiments, the peripheral circuits 208 are configured to control and sense the 3D memory device 200. The peripheral circuits 208 can be any suitable digital, analog, and / or mixed-signal control and sensing circuits used to facilitate the operation of the 3D memory device 200, including, but not limited to, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits 208 may well include transistors formed "on" the substrate 201, with all or part of the transistors being formed within the substrate 201 (e.g., below the top surface of the substrate 201) and / or directly on top of the substrate 201. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of transistors) may also be formed within the substrate 201. The transistors are fast according to some embodiments using advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). It is understood that in some embodiments, the peripheral circuits 208 may further include any other circuits compatible with an advanced logic process, including logic circuits such as processors and PLDs, or memory circuits such as SRAM and DRAM.

[0051] In some embodiments, the first semiconductor structure 202 of the 3D memory device 200 further includes an interconnect layer (not shown) above the peripheral circuit 208 for communicating electrical signals with the peripheral circuit 208. The interconnect layer can include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and VIA contacts. As used herein, the term "interconnect" can, in a broad sense, include any suitable type of interconnect, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers (also referred to as "IMD layers") in which the interconnect lines and VIA contacts can be formed. That is, the interconnect layer can include interconnect lines and VIA contacts within the plurality of ILD layers. The interconnect lines and VIA contacts within the interconnect layer can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers within the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0052] As shown in FIG. 2, the first semiconductor structure 202 of the 3D memory device 200 can further include a bonding layer 210 at the bonding interface 206 and above the interconnect layer and the peripheral circuit 208. The bonding layer 210 can include a plurality of bonding contacts 211 and a dielectric that electrically insulates the bonding contacts 211. The bonding contacts 211 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of the bonding layer 210 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 211 and the surrounding dielectric within the bonding layer 210 can be used for hybrid bonding.

[0053] Similarly, as shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 can also include a bonding layer 212 at the bonding interface 206 and also above the bonding layer 210 of the first semiconductor structure 202. The bonding layer 212 can include a plurality of bonding contacts 213 and a dielectric that electrically insulates the bonding contacts 213. The bonding contacts 213 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of the bonding layer 212 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 213 and the surrounding dielectric within the bonding layer 212 can be used for hybrid bonding. The bonding contacts 213 are in contact with the bonding contacts 211 at the bonding interface 206 in some embodiments.

[0054] As described in detail below, the second semiconductor structure 204 can be bonded on top of the first semiconductor structure 202 face-to-face at the bonding interface 206. In some embodiments, the bonding interface 206 is disposed between the bonding layers 210 and 212 as a result of a hybrid bonding (also referred to as a "metal / dielectric hybrid bonding"), which is a direct bonding technique (i.e., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 206 is the location where the bonding layers 212 and 210 contact and are bonded. In practice, the bonding interface 206 can be a layer having a specific thickness including the top surface of the bonding layer 210 of the first semiconductor structure 202 and the bottom surface of the bonding layer 212 of the second semiconductor structure 204.

[0055] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes an interconnect layer (not shown) above the bonding layer 212 for transferring electrical signals. The interconnect layer can include a plurality of interconnects such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which interconnect lines and VIA contacts can be formed. The interconnect lines and VIA contacts in the interconnect layer can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0056] In some embodiments, the 3D memory device 200 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 can include an array of channel structures 224 that function as an array of NAND memory strings. As shown in FIG. 2, each channel structure 224 can penetrate vertically through a plurality of pairs each including a conductor layer 216 and a dielectric layer 218. The alternately arranged conductor layers 216 and dielectric layers 218 are part of the memory stack 214. The number of pairs of conductor layers 216 and dielectric layers 218 in the memory stack 214 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D memory device 200. It is understood that in some embodiments, the memory stack 214 can have a multi-deck architecture (not shown) including a plurality of memory decks stacked on top of each other. The number of pairs of conductor layers 216 and dielectric layers 218 in each memory deck may be the same or different.

[0057] The memory stack 214 can include a plurality of conductor layers 216 and dielectric layers 218 arranged alternately. The conductor layers 216 and dielectric layers 218 within the memory stack 214 may be alternately arranged in the vertical direction. In other words, except for those at the top or bottom of the memory stack 214, each conductor layer 216 can be adjacent to two dielectric layers 218 on both sides, and each dielectric layer 218 can be adjacent to two conductor layers 216 on both sides. The conductor layer 216 can include a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductor layer 216 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductor layer 216 extends horizontally as a word line and can end at one or more staircase structures of the memory stack 214. The dielectric layer 218 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0058] As shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 can also include a P-type doped semiconductor layer 220 above the memory stack 114. The P-type doped semiconductor layer 220 can be an example of the "sidewall SEG" described above. The P-type doped semiconductor layer 220 can include a semiconductor material such as silicon. In some embodiments, the P-type doped semiconductor layer 220 includes polysilicon formed by a deposition technique, as will be described in detail below. In some embodiments, the P-type doped semiconductor layer 220 includes single-crystalline silicon, such as a device layer of an SOI wafer, as will be described in detail below. The P-type doped semiconductor layer 220 is doped with any suitable P-type dopant, such as boron (B), gallium (Ga), or aluminum (Al), and the intrinsic semiconductor creates a deficiency of valence electrons called "holes". For example, the P-type doped semiconductor layer 220 can be a polysilicon layer doped with a P-type dopant such as P, Ar, or Sb. In some embodiments, the P-type doped semiconductor layer 220 is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having a plurality of polysilicon sub-layers with a non-uniform doping concentration at its interface (e.g., a sharp change in doping concentration at the interface between two sub-layers). It is understood that the doping concentration of the P-type dopant in the P-type doped semiconductor layer 220 can still change gradually in the vertical direction as long as there is no sharp change in doping concentration that can distinguish two or more sub-layers due to the change in doping concentration.

[0059] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes an N-well 221 within the P-type doped semiconductor layer 220. The N-well 221 may be doped with any suitable N-type dopant such as P, Ar, or Sb, which contributes to providing free electrons and enhancing the conductivity of the intrinsic semiconductor. In some embodiments, the N-well 221 is doped from the bottom surface of the P-type doped semiconductor layer 220. It is understood that the N-well 221 may extend vertically through the entire thickness of the P-type doped semiconductor layer 220, i.e., up to the top surface of the P-type doped semiconductor layer 220, or through a portion of the entire thickness of the P-type doped semiconductor layer 220.

[0060] In some embodiments, each channel structure 224 includes a channel hole filled with a semiconductor layer (e.g., as semiconductor channel 228) and a composite dielectric layer (e.g., as memory film 226). In some embodiments, the semiconductor channel 228 includes silicon such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, the memory film 226 is a composite layer including a tunnel layer, a storage layer (also referred to as a "charge trap layer"), and a blocking layer. The remaining space of the channel structure 224 may be partially or fully filled with a capping layer including a dielectric material such as silicon oxide and / or voids. The channel structure 224 can have a cylindrical shape (e.g., pillar shape). The capping layer, semiconductor channel 228, tunnel layer, storage layer, and blocking layer of the memory film 226 are radially arranged and configured in this order from the center towards the outer surface of the pillar in some embodiments. The tunnel layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 226 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] In some embodiments, the channel structure 224 further includes a channel plug 227 at the bottom (e.g., the lower end) of the channel structure 224. As used herein, the “upper end” of a component (e.g., the channel structure 224) is the end that is far from the substrate 201 in the y direction, and the “lower end” of a component (e.g., the channel structure 224) is the end that is close to the substrate 201 in the y direction when the substrate 201 is positioned within the bottommost plane of the 3D memory device 200. The channel plug 227 can include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 227 functions as the drain of a NAND memory string.

[0062] As shown in FIG. 2, each channel structure 224 can penetrate vertically through the alternating conductor layers 216 and dielectric layers 218 of the memory stack 214 into the P-type doped semiconductor layer 220. The upper end of each channel structure 224 may be in the same plane as or below the top surface of the P-type doped semiconductor layer 220. That is, in some embodiments, the channel structure 224 does not extend beyond the top surface of the P-type doped semiconductor layer 220. In some embodiments, as shown in FIG. 2, the upper end of the memory film 226 is below the upper end of the semiconductor channel 228 of the channel structure 224. In some embodiments, the upper end of the memory film 226 is below the top surface of the P-type doped semiconductor layer 220, and the upper end of the semiconductor channel 228 is in the same plane as or below the top surface of the P-type doped semiconductor layer 220. For example, as shown in FIG. 2, the memory film 226 ends at the bottom surface of the P-type doped semiconductor layer 220, and the semiconductor channel 228 extends above the bottom surface of the P-type doped semiconductor layer 220, whereby the P-type doped semiconductor layer 220 can surround and contact the top 229 of the semiconductor channel 228 penetrating into the P-type doped semiconductor layer 220. In some embodiments, the doping concentration of the top 229 of the semiconductor channel 228 penetrating into the P-type doped semiconductor layer 220 is different from the doping concentration of the remaining portion of the semiconductor channel 228. For example, the semiconductor channel 228 may include undoped polysilicon excluding the top 229, which may include doped polysilicon to enhance conductivity when forming an electrical connection with the surrounding P-type doped semiconductor layer 220.

[0063] In some embodiments, the P-type doped semiconductor layer 220 includes semiconductor plugs 222 that each surround and contact the top 229 of each semiconductor channel 228 of the channel structure 224 penetrating into the P-type doped semiconductor layer 220. The semiconductor plugs 222 include doped polysilicon, e.g., P-type doped polysilicon, according to some embodiments. Since the semiconductor plugs 222 can be formed in a post-process after the formation of the remaining portion of the P-type doped semiconductor layer 220, as will be described in detail below, the doping concentration of the semiconductor plugs 222 can be different from the doping concentration of the remaining portion of the P-type doped semiconductor layer 220. In some embodiments, the semiconductor plugs 222 include polysilicon (e.g., P-type doped polysilicon), and the remaining portion of the P-type doped semiconductor layer 220 includes single crystal silicon (e.g., P-type doped single crystal silicon). In some embodiments, the semiconductor plugs 222 include polysilicon (e.g., P-type doped polysilicon), and the remaining portion of the P-type doped semiconductor layer 220 includes polysilicon (e.g., P-type doped polysilicon), but with a doping concentration different from that of the semiconductor plugs 222.

[0064] Each semiconductor plug 222 can surround and contact the sidewalls of the top 229 of each semiconductor channel 228. As a result, the semiconductor plug 222 of the P-type doped semiconductor layer 220 acts as a "sidewall SEG (e.g., semiconductor plug)" of the channel structure 224 and can replace the "bottom SEG (e.g., semiconductor plug)". Further, as will be described in detail below, the formation of the semiconductor plug 222 is performed on the opposite side of the memory stack 214, thereby avoiding any deposition or etching process through the opening penetrating the memory stack 214, thereby reducing manufacturing complexity and cost and improving yield and vertical scalability. Depending on the relative position of the upper end of the semiconductor channel 228 of each channel structure 224 with respect to the top surface of the P-type doped semiconductor layer 220, the semiconductor plug 222 can be formed in contact with the upper end, above the semiconductor channel 228 as well, for example, as shown in FIG. 2, when the upper end of the semiconductor channel 228 is below the top surface of the P-type doped semiconductor layer 220. In other examples where the upper end of the semiconductor channel 228 is coplanar with the top surface of the P-type doped semiconductor layer 220, it is understood that the semiconductor plug 222 can be formed in contact with only the sidewalls of the top 229 of the semiconductor channel 228.

[0065] Nevertheless, the P-type doped semiconductor layer 220 surrounding the top 229 of the semiconductor channel 228 of the channel structure 224 together with the semiconductor plug 222 (e.g., as the sidewall SEG) can enable the use of the P-well bulk erase operation for the 3D memory device 200. The design of the 3D memory device 200 disclosed herein can achieve the separation of the hole current path and the electron current path for forming the erase operation and the read operation, respectively. In some embodiments, the 3D memory device 200 is configured to form an electron current path between an electron source (e.g., the N-well 221) and the semiconductor channel 228 of the channel structure 224 to supply electrons to the NAND memory string when performing a read operation, according to some embodiments. Conversely, the 3D memory device 200 is configured to form a hole current path between a hole source (e.g., the P-type doped semiconductor layer 220) and the semiconductor channel 228 of the channel structure 224 to supply holes to the NAND memory string when performing a P-well bulk erase operation, according to some embodiments.

[0066] As shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 may further include insulating structures 230 that each penetrate vertically through the interleaved conductive layers 216 and dielectric layers 218 of the memory stack 214. Unlike the channel structures 224 that penetrate further into the P-type doped semiconductor layer 220, the insulating structures 230 may stop at the bottom surface of the P-type doped semiconductor layer 220, i.e., not extend vertically into the P-type doped semiconductor layer 220, according to some embodiments. That is, the top surface of the insulating structures 230 may be flush with the bottom surface of the P-type doped semiconductor layer 220. Each insulating structure 230 may also extend laterally to separate the channel structures 224 into multiple blocks. That is, the memory stack 214 may be divided into multiple memory blocks by the insulating structures 230, thereby separating the array of channel structures 224 into each memory block. Unlike the slit structures of existing 3D NAND memory devices described above that include front-side ACS contacts, the insulating structures 230 do not include contacts therein (i.e., do not function as source contacts) and therefore do not introduce parasitic capacitance and leakage current due to the conductive layers 216 (including wordlines) according to some embodiments. In some embodiments, each insulating structure 230 comprises an opening (e.g., a slit) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 230 can be filled with silicon oxide.

[0067] Furthermore, as described in more detail below, because the openings for forming the insulating structures 230 are not used (e.g., as sidewall SEGs) for forming the P-type doped semiconductor layers 220 and semiconductor plugs 222 therein, the increased aspect ratio of the openings as well as the increased number of interleaved conductive layers 216 and dielectric layers 218 do not affect the formation of the P-type doped semiconductor layers 220 and semiconductor plugs 222 therein.

[0068] Instead of a front-side source contact, the 3D memory device 100 may include back-side source contacts 231 and 232 above the memory stack 214 and in contact with the N-well 221 and the P-type doped semiconductor layer 220, as shown in FIG. 1. The source contacts 231 and 232 and the memory stack 214 (and the insulating structure 230 therethrough) may be disposed on opposite sides of the P-type doped semiconductor layer 220 and may therefore be considered "back-side" source contacts. In some embodiments, the source contact 220 in contact with the P-type doped semiconductor layer 220 is electrically connected to the semiconductor channel 228 of the channel structure 224 through the semiconductor plug 222 of the P-type doped semiconductor layer 220. In some embodiments, the source contact 231 in contact with the N-well 221 is electrically connected to the semiconductor channel 228 of the channel structure 224 through the semiconductor plug 222 of the P-type doped semiconductor layer 220. In some embodiments, the source contact 232 is not laterally aligned with the insulating structure 230 but is adjacent to the channel structure 224 to reduce the resistance of the electrical connection therebetween. As shown in FIG. 2, the source contact 231 is laterally aligned with the insulating structure 230, but it is understood that in some examples, the source contact 231 may not be laterally aligned with the insulating structure 230 but may be adjacent to the channel structure 224 (e.g., laterally between the insulating structure 230 and the channel structure 224) to reduce the resistance of the electrical connection therebetween as well. As described above, the source contacts 231 and 232 may be used to separately control the electron current and the hole current, respectively, during read and erase operations. The source contacts 231 and 232 may include any suitable type of contact. In some embodiments, the source contacts 231 and 232 include VIA contacts. In some embodiments, the source contacts 231 and 232 include laterally extending wall-shaped contacts.The source contacts 231 and 232 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0069] As shown in FIG. 2, the 3D memory device 100 can further include a BEOL interconnect layer 233 overlying and electrically connecting the source contacts 231 and 232 for pad-out, e.g., for transferring electrical signals between the 3D memory device 200 and an external circuit. In some embodiments, the interconnect layer 233 includes one or more ILD layers 234 over the P-type doped semiconductor layer 220 and a redistribution layer 236 over the ILD layer 234. The upper ends of the source contacts 231 or 232 are flush with the top surface of the ILD layer 234 and the bottom surface of the redistribution layer 236. The source contacts 231 and 232 can be electrically isolated over the ILD layer 234. In some embodiments, the source contact 232 penetrates vertically through the ILD layer 234 into the P-type doped semiconductor layer 220 and makes an electrical connection with the P-type doped semiconductor layer 220. In some embodiments, the source contact 231 penetrates vertically through the ILD layer 234 and the P-type doped semiconductor layer 220 into the N-well 221 to make an electrical connection to the N-well. The source contact 231 may include a spacer (e.g., a dielectric layer) surrounding its sidewalls such that it is electrically isolated from the P-type doped semiconductor layer 220. The redistribution layer 236 may include two electrically isolated interconnects: a first interconnect 236-1 in contact with the source contact 232 and a second interconnect 236-2 in contact with the source contact 231.

[0070] The ILD layer 234 in the interconnect layer 233 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The redistribution layer 236 in the interconnect layer 233 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the redistribution layer 236 includes Al. In some embodiments, the interconnect layer 233 further includes a passivation layer 238 as an outermost layer for passivation and protection of the 3D memory device 200. A portion of the redistribution layer 236 may be exposed from the passivation layer 238 as a contact pad 240. That is, the interconnect layer 233 of the 3D memory device 200 may also include a contact pad 240 for wire bonding and / or bonding with an interposer.

[0071] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes contacts 242, 243, and 244 through the P-type doped semiconductor layer 220. Since the P-type doped semiconductor layer 220 may be a device layer of a thinned substrate, e.g., an SOI wafer, the contacts 242, 243, and 244 are TSCs according to some embodiments. In some embodiments, the contact 242 penetrates the P-type doped semiconductor layer 220 and the ILD layer 234 to contact the first interconnect 236-1 of the redistribution layer 236, thereby electrically connecting the P-type doped semiconductor layer 220 to the contact 242 through the source contact 232 and the first interconnect 236-1 of the interconnect layer 233. In some embodiments, the contact 243 penetrates the P-type doped semiconductor layer 220 and the ILD layer 234 to contact the second interconnect 236-2 of the redistribution layer 236, such that the N-well 221 is electrically connected to the contact 243 through the source contact 231 and the second interconnect 236-2 of the interconnect layer 233. In some embodiments, the contact 244 penetrates the P-type doped semiconductor layer 220 and the ILD layer 234 to contact the contact pad 240. The contacts 242, 243, and 244 may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least the contacts 243 and 244 each further include a spacer (e.g., a dielectric layer) to electrically isolate the contacts 243 and 244 from the P-type doped semiconductor layer 220.

[0072] In some embodiments, the 3D memory device 200 further includes peripheral contacts 246, 247, and 248 that each extend vertically outside of each memory stack 214. Each peripheral contact 246, 247, or 248 can have a depth greater than the depth of the memory stack 214 such that it extends vertically from the bonding layer 212 to the P-type doped semiconductor layer 220 within the peripheral region outside of the memory stack 214. In some embodiments, peripheral contact 246 is below contact 242 and in contact with contact 242, whereby the P-type doped semiconductor layer 220 is electrically connected to the peripheral circuit 208 within the first semiconductor structure 202 through at least source contact 232, the first interconnect 236-1 of the interconnect layer 233, contact 242, and peripheral contact 246. In some embodiments, peripheral contact 247 is below contact 243 and in contact with contact 243, whereby the N-well 221 is electrically connected to the peripheral circuit 208 within the first semiconductor structure 202 through at least source contact 231, the second interconnect 236-2 of the interconnect layer 233, contact 243, and peripheral contact 247. That is, the electron current and hole current for read and erase operations can be separately controlled by the peripheral circuit 208 through different electrical connections. In some embodiments, peripheral contact 248 is below contact 244 and in contact with contact 244, whereby the peripheral circuit 208 within the first semiconductor structure 202 is electrically connected to the contact pad 240 for pad out through at least contact 244 and peripheral contact 248. Each of the peripheral contacts 246, 247, and 248 can include one or more conductor layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0073] As shown in FIG. 2, 3D memory device 200 also includes various local contacts (also referred to as "C1") as part of the interconnect structure and is in direct contact with the structures within memory stack 214. In some embodiments, the local contacts include channel local contacts 250 that are each below and in contact with the lower end of each respective channel structure 224. Each channel local contact 250 can be electrically connected to a bit line contact (not shown) for bit line fanout. In some embodiments, the local contacts further include word line local contacts 252 that are each below and in contact with each respective conductor layer 216 (including word lines) in the staircase structure of memory stack 214 for word line fanout. Local contacts such as channel local contacts 250 and word line local contacts 252 can be electrically connected to the peripheral circuit 208 of the first semiconductor structure 202 through at least bonding layers 212 and 210. Local contacts such as channel local contacts 250 and word line local contacts 252 can each include one or more conductor layers such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0074] Figures 3A - 3N illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 5A illustrates a flowchart of a method 500 for forming an exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 5B illustrates a flowchart of another method 501 for forming an exemplary 3D memory device according to some embodiments of the present disclosure. The examples of 3D memory devices shown in FIGS. 3A - 3N, FIG. 5A, and FIG. 5B include the 3D memory device 100 shown in FIG. 1. FIGS. 3A - 3N, FIG. 5A, and FIG. 5B will be described together. It is understood that the operations shown in methods 500 and 501 are not exhaustive, and other operations may be similarly performed before, after, or between any of the illustrated operations. Further, some of these operations may be performed simultaneously or in an order different from that shown in FIGS. 5A and 5B.

[0075] Referring to FIG. 5A, method 500 begins with operation 502 where a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate. As illustrated in FIG. 3G, a plurality of transistors are formed on the silicon substrate 350 using a plurality of processes including, but not limited to, photolithography, etching, thin - film deposition, thermal growth, implantation, chemical - mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed within the silicon substrate 350 by ion implantation and / or thermal diffusion, which function, for example, as source regions and / or drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed within the silicon substrate 350 by wet etching and / or dry etching and thin - film deposition. The transistors can form a peripheral circuit 352 on the silicon substrate 350.

[0076] As illustrated in FIG. 3G, the bonding layer 348 is formed above the peripheral circuit 352. The bonding layer 348 includes bonding contacts that are electrically connected to the peripheral circuit 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and the bonding contacts through the ILD layer are formed using wet etching and / or dry etching, such as reactive ion etching (RIE), and then formed using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0077] The memory stack and the channel structure penetrating the N-type doped semiconductor layer in the vertical direction may be formed above the second substrate. As illustrated in FIG. 5A, method 500 proceeds to operation 504, where a sacrificial layer on the second substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. The second substrate may be a silicon substrate. Since the second substrate is removed from the final product, to reduce the cost of the second substrate, it is understood that it may be a dummy wafer made of any suitable material, such as glass, sapphire, plastic, silicon, etc., for example, a part of a carrier substrate. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the N-type doped semiconductor layer includes polysilicon, and the dielectric stack includes alternately arranged stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and the stack sacrificial layers are alternately deposited on the N-type doped semiconductor layer to form the dielectric stack.

[0078] As shown in FIG. 3A, the sacrificial layer 304 is formed on the carrier substrate 302, and the N-type doped semiconductor layer 306 is formed on the sacrificial layer 304. The N-type doped semiconductor layer 306 can include polysilicon doped with an N-type dopant such as P, As, or Sb. The sacrificial layer 304 can include any suitable sacrificial material that can be selectively removed later and is different from the material of the N-type doped semiconductor layer 306. In some embodiments, the sacrificial layer 304 includes a dielectric material such as silicon oxide or silicon nitride. To form the sacrificial layer 304, silicon oxide or silicon nitride is deposited on the carrier substrate 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form the N-type doped semiconductor layer 306, polysilicon is deposited on the sacrificial layer 304 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, and then the deposited polysilicon is doped with an N-type dopant such as P, As, or Sb using ion implantation and / or thermal diffusion. In some embodiments, in-situ doping of an N-type dopant such as P, As, or Sb is performed when depositing polysilicon on the sacrificial layer 304 to form the N-type doped semiconductor layer 306.

[0079] As illustrated in FIG. 3B, a dielectric stack 308 including a plurality of pairs of a first dielectric layer (referred to herein as “stack sacrificial layer” 312) and a second dielectric layer (referred to herein as “stack dielectric layer” 310, and collectively referred to herein as “dielectric layer pair”) is formed on an N-type doped semiconductor layer 306. The dielectric stack 308 includes, in some embodiments, alternately arranged stack sacrificial layers 312 and stack dielectric layers 310. The stack dielectric layer 310 and the stack sacrificial layer 312 can be alternately deposited on the N-type doped semiconductor layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some embodiments, each stack dielectric layer 310 includes a layer of silicon oxide, and each stack sacrificial layer 312 includes a layer of silicon nitride. The dielectric stack 308 can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in FIG. 3B, a staircase structure can be formed at the edge of the dielectric stack 308. The staircase structure can be formed by performing a plurality of so-called “trim etch” cycles on the dielectric layer pair of the dielectric stack 308 toward the carrier substrate 302. By applying repeated trim etch cycles to the dielectric layer pair of the dielectric stack 308, the dielectric stack 308 can have one or more inclined edges and a top dielectric layer pair that is shorter than the bottom dielectric layer pair, as shown in FIG. 3B.

[0080] As illustrated in FIG. 5A, method 500 proceeds to operation 506, where a channel structure is formed that vertically penetrates the dielectric stack and the N-type doped semiconductor layer. In some embodiments, to form the channel structure, a channel hole that vertically penetrates the dielectric stack and the N-type doped semiconductor layer and stops at the sacrificial layer is etched, and then a memory film and a semiconductor channel are deposited along the sidewalls of the channel hole.

[0081] As illustrated in FIG. 3B, the channel hole is an opening that vertically penetrates the dielectric stack 308 and the N-type doped semiconductor layer 306. In some embodiments, a plurality of openings are formed, and each opening serves as a location for growing an individual channel structure 314 in a later process. In some embodiments, the fabrication process for forming the channel hole of the channel structure 314 includes wet etching and / or dry etching such as deep reactive ion etching (DRIE). The sacrificial layer 304 can function as an etch stop layer to control the through-hole variation between different channel holes. For example, the etching of the channel hole can be stopped by the sacrificial layer 304 without further penetrating into the carrier substrate 302. That is, in some embodiments, the lower end of each channel hole (and the corresponding channel structure 314) is between the top and bottom surfaces of the sacrificial layer 304.

[0082] As illustrated in FIG. 3B, a memory film including a blocking layer 317, a storage layer 316, and a tunnel layer 315, and a semiconductor channel 318 are then formed in this order along the sidewalls and bottom surface of the channel hole. In some embodiments, first, the blocking layer 317, the storage layer 316, and the tunnel layer 315 are deposited in this order along the sidewalls and bottom surface of the channel hole using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to form the memory film. Then, the semiconductor channel 318 can be formed by depositing a semiconductor material such as polysilicon (e.g., undoped polysilicon) on the tunnel layer 315 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are then deposited to form the blocking layer 317, the storage layer 316, and the tunnel layer 315 of the memory film and the semiconductor channel 318.

[0083] As illustrated in FIG. 3B, the capping layer is formed within the channel hole and on the semiconductor channel 318 and fills the channel hole completely or partially (e.g., without voids or with voids). The capping layer can be formed by depositing a dielectric material such as silicon oxide using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Then, a channel plug can be formed on top of the channel hole. In some embodiments, the memory film on the top surface of the dielectric stack 308, the semiconductor channel 318, and a portion of the capping layer are removed and planarized by CMP, wet etching, and / or dry etching. Then, a recess can be formed at the top of the channel hole by wet etching and / or dry etching a portion of the semiconductor channel 318 and the capping layer at the top of the channel hole. Then, the channel plug can be formed by depositing a semiconductor material such as polysilicon within the recess by one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Thereby, the channel structure 314 is formed through the dielectric stack 308 and the N-type doped semiconductor layer 306. Depending on the depth at which the etching of each channel hole is stopped by the sacrificial layer 304, the channel structure 314 can penetrate further into the sacrificial layer 304 or stop at the interface between the sacrificial layer 304 and the N-type doped semiconductor layer 306. Nevertheless, the channel structure 314 cannot penetrate further into the carrier substrate 302.

[0084] As illustrated in FIG. 5A, method 500 proceeds to operation 508, where the dielectric stack is replaced with a memory stack, for example, using a so-called “gate replacement” process, whereby the channel structure vertically penetrates the memory stack and the N-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with a memory stack, an opening is etched that vertically penetrates the dielectric stack and terminates at the N-type doped semiconductor layer, and the stack sacrificial layer is replaced with a stack conductor layer through the opening to form a memory stack including an alternating arrangement of a stack dielectric layer and a stack conductor layer.

[0085] As illustrated in FIG. 3C, slit 320 is an opening that vertically penetrates dielectric stack 308 and terminates at N-type doped semiconductor layer 306. In some embodiments, the fabrication process for forming slit 320 includes wet etching and / or dry etching, such as DRIE. Then, gate replacement can be performed through slit 320 to replace dielectric stack 308 with memory stack 330 (shown in FIG. 3E).

[0086] As illustrated in FIG. 3D, outer recess 322 is first formed by removing stack sacrificial layer 312 (shown in FIG. 3C) through slit 320. In some embodiments, stack sacrificial layer 312 is removed by applying an etchant through slit 320 to form outer recesses 322 alternating between stack dielectric layers 310. The etchant can include any suitable etchant that selectively etches stack sacrificial layer 312 with respect to stack dielectric layer 310.

[0087] As illustrated in FIG. 3E, the stack conductive layer 328 (including the gate electrode and the adhesive layer) is deposited into the outer recess 322 (shown in FIG. 3D) through the slit 320. In some embodiments, the gate dielectric layer 332 is deposited in the outer recess 322 before the stack conductor layer 328, and the stack conductive layer 328 is deposited on the gate dielectric layer 332. The stack conductor layer 328, such as a metal layer, can be deposited using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the gate dielectric layer 332, such as a high-k dielectric layer, is formed along the sidewalls and also at the bottom of the slit 320. The memory stack 330 including the alternately arranged stack conductive layers 328 and stack dielectric layers 310 thereby forms, in some embodiments, by replacing the dielectric stack 308 (shown in FIG. 3D).

[0088] As illustrated in FIG. 5A, method 500 proceeds to operation 510 where an insulating structure is formed that vertically penetrates the memory stack. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the openings to fill the openings. As illustrated in FIG. 3E, an insulating structure 336 is formed that vertically penetrates the memory stack 330 and terminates on the top surface of the N-type doped semiconductor layer 306. The insulating structure 336 can be formed by depositing one or more dielectric materials, such as silicon oxide, into the slit 320 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to completely or partially fill the slit 320 (with or without voids). In some embodiments, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide).

[0089] As illustrated in FIG. 3F, after the formation of the insulating structure 336, local contacts including the channel local contact 344 and the word line local contact 342, and the peripheral contacts 338 and 340 are formed. The local dielectric layer can be formed on the memory stack 330 by depositing a dielectric material such as silicon oxide or silicon nitride on the memory stack 330 using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340 can be formed by etching contact openings through the local dielectric layer (and any other ILD layer) using wet etching and / or dry etching, such as RIE, and then filling the contact openings with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0090] As illustrated in FIG. 3F, the bonding layer 346 is formed above the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes bonding contacts that are electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and / or dry etching, such as RIE, and then one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0091] As illustrated in FIG. 5A, method 500 proceeds to operation 512, where the first and second substrates are joined face-to-face, and the memory stack is above the peripheral circuitry. The joining can include a hybrid join. As illustrated in FIG. 3G, the carrier substrate 302 and the components formed thereon (e.g., the memory stack 330 and the channel structure 314 formed therethrough) are flipped upside down. The downward facing joining layer 346 is joined to the upward facing joining layer 348, i.e., joined face-to-face, thereby forming a joining interface 354 between the carrier substrate 302 and the silicon substrate 350 in some embodiments. In some embodiments, a processing process, e.g., plasma processing, wet processing, and / or heat treatment, is applied to the joining surfaces prior to joining. After joining, the joining contacts in the joining layer 346 and the joining contacts in the joining layer 348 are aligned and in contact with each other, such that the memory stack 330 and the channel structure 314 formed therethrough may be electrically connected to the peripheral circuitry 352 and is above the peripheral circuitry 352.

[0092] As illustrated in FIG. 5A, method 500 proceeds to operation 514, where the second substrate and the sacrificial layer are removed to expose the ends of the channel structure. The removal can be performed from the backside of the second substrate. As illustrated in FIG. 3H, the carrier substrate 302 and the sacrificial layer 304 (shown in FIG. 3G) are removed from the backside to expose the upper ends of the channel structure 314. The carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some embodiments, the carrier substrate 302 is peeled off. The removal of the carrier substrate 302 can be stopped by the underlying sacrificial layer 304 due to its different material to ensure thickness uniformity. In some embodiments where the carrier substrate 302 includes silicon and the sacrificial layer 304 includes silicon oxide, the carrier substrate 302 can be removed using CMP and automatically stop at the interface between the carrier substrate 302 and the sacrificial layer 304.

[0093] Next, the sacrificial layer 304 can be similarly selectively removed using wet etching with a suitable etchant such as hydrofluoric acid without etching the underlying N-type doped semiconductor layer 306. As described above, since the channel structure 314 does not penetrate into the carrier substrate 302 beyond the sacrificial layer 304, the removal of the carrier substrate 302 does not affect the channel structure 314. Removal of the sacrificial layer 304 can expose the upper end portion of the channel structure 314. In some embodiments where the channel structure 314 penetrates into the sacrificial layer 304, selective etching of the sacrificial layer 304 containing silicon oxide also removes a portion of the blocking layer 317 containing silicon oxide that is above the top surface of the N-type doped semiconductor layer 306, but the storage layer 316 containing silicon nitride and other layers (e.g., the tunnel layer 315) surrounded by the storage layer 316 remain intact.

[0094] As illustrated in FIG. 5A, method 500 proceeds to operation 516 where a portion of the channel structure in contact with the N-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure in contact with the N-type doped semiconductor layer with a semiconductor plug, a portion of the memory film in contact with the N-type doped semiconductor layer is removed, thereby forming a recess surrounding a portion of the semiconductor channel, a portion of the semiconductor channel is doped, and polysilicon is deposited within the recess to surround and contact the portion of the doped semiconductor channel to form a contacting semiconductor plug.

[0095] As shown in FIG. 3I, a part of the storage layer 316 (shown in FIG. 3H) in contact with the N-type doped semiconductor layer 306 is removed. In some embodiments, the storage layer 316 containing silicon nitride is selectively removed using wet etching with a suitable etchant such as phosphoric acid without etching the N-type doped semiconductor layer 306 containing polysilicon. The etching of the storage layer 316 is controlled by controlling the etching time and / or the etching rate, so that the etching does not continue to affect the remaining portion of the storage layer 316 surrounded by the memory stack 330.

[0096] As shown in FIG. 3J, a portion of the blocking layer 317 and the tunnel layer 315 that are in contact with the N-type doped semiconductor layer 306 is removed, thereby forming a recessed portion 357 that surrounds the top of the semiconductor channel 318 in contact with the N-type doped semiconductor layer 306. In some embodiments, the blocking layer 317 and the tunnel layer 315 containing silicon oxide are selectively removed using wet etching with a suitable etchant such as hydrofluoric acid without etching the N-type doped semiconductor layer 306 and the semiconductor channel 318 containing polysilicon. The etching of the blocking layer 317 and the tunnel layer 315 is controlled by controlling the etching time and / or the etching rate, so that the etching does not continue to affect the remaining portions of the blocking layer 317 and the tunnel layer 315 surrounded by the memory stack 330. As a result, according to some embodiments, the top of the memory film (including the blocking layer 317, the storage layer 316, and the tunnel layer 315) of the channel structure 314 in contact with the N-type doped semiconductor layer 306 is removed, thereby forming a recessed portion 357 and exposing the top of the semiconductor channel 318. In some embodiments, the top of the semiconductor channel 318 exposed by the recessed portion 357 is doped to increase its conductivity. For example, an inclined ion implantation process may be performed to dope the top of the semiconductor channel 318 (e.g., containing polysilicon) exposed by the recessed portion 357 with any suitable dopant to the desired doping concentration.

[0097] As illustrated in FIG. 3K, the semiconductor plug 359 is formed within the recess 357 (shown in FIG. 3J) and surrounds and contacts the doped top of the semiconductor channel 318. As a result, in some embodiments, the top of the channel structure 314 (shown in FIG. 3H) that abuts the N-type doped semiconductor layer 306 is thereby replaced by the semiconductor plug 359. In some embodiments, to form the semiconductor plug 359, one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof are used to deposit polysilicon within the recess 357 to fill the recess 357, and subsequently, any excess polysilicon above the top surface of the N-type doped semiconductor layer 306 is removed by a CMP process. In some embodiments, in-situ doping of an N-type dopant such as P, As, or Sb is performed when depositing polysilicon within the recess 357 to dope the semiconductor plug 359. Since the semiconductor plug 359 and the N-type doped semiconductor layer 306 may include the same material such as polysilicon and may have the same thickness (after the CMP process), the semiconductor plug 359 may be regarded as a part of the N-type doped semiconductor layer 306. Nevertheless, since the semiconductor plug 359 is formed in a process after the formation of the remaining portion of the N-type doped semiconductor layer 306 (e.g., shown in FIG. 3A), in some embodiments, the doping concentration of the semiconductor plug 359 is different from the doping concentration of the remaining portion of the N-type doped semiconductor layer 306, regardless of whether the semiconductor plug 359 is doped in-situ.

[0098] As described above, the semiconductor plug 359 within the N-type doped semiconductor layer 306 can function as a sidewall SEG of the channel structure 314. Unlike known methods of forming sidewall SEGs by etching and deposition processes through a slit 320 (e.g., as shown in FIG. 3D) that penetrates the dielectric stack 308 from end to end with a high aspect ratio, the semiconductor plug 359 may be formed from the opposite side of the dielectric stack 308 / memory stack 330 after the carrier substrate 302 has been removed, which is not affected by the level of the dielectric stack 308 / memory stack 330 and the aspect ratio of the slit 320. By avoiding problems also introduced by the high aspect ratio of the slit 320, fabrication complexity and cost can be reduced and yield can be increased. Furthermore, vertical scalability (e.g., higher levels of the dielectric stack 308 / memory stack 330) can be improved as well.

[0099] As illustrated in FIG. 5A, method 500 proceeds to operation 518 where a source contact is formed above the memory stack and contacts the N-type doped semiconductor layer. As illustrated in FIG. 3L, one or more ILD layers 356 are formed on the N-type doped semiconductor layer 306. The ILD layer 356 can be formed by depositing a dielectric material on top of the N-type doped semiconductor layer 306 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The source contact opening 358 can be formed into the N-type doped semiconductor layer 306 through the ILD layer 356. In some embodiments, the source contact opening 358 is formed using wet etching and / or dry etching such as RIE. In some embodiments, the source contact opening 358 further penetrates into the top of the N-type doped semiconductor layer 306. The etching process through the ILD layer 356 can continue to etch a portion of the N-type doped semiconductor layer 306. In some embodiments, a separate etching process is used to etch a portion of the N-type doped semiconductor layer 306 after etching through the ILD layer 356.

[0100] As illustrated in FIG. 3M, a source contact 364 is formed within the source contact opening 358 (shown in FIG. 3L) on the back side of the N-type doped semiconductor layer 306. The source contact 364 is, in some embodiments, above the memory stack 330 and in contact with the N-type doped semiconductor layer 306. In some embodiments, one or more conductive materials are deposited within the source contact opening 358 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, filling the source contact opening 358 with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process such as CMP is then performed, thereby removing excess conductive material and making the top surface of the source contact 364 coplanar with the top surface of the ILD layer 356.

[0101] As illustrated in FIG. 5A, method 500 proceeds to operation 520 where an interconnect layer is formed over the source contact and contacts the source contact. In some embodiments, the contact is formed through the N-type doped semiconductor layer to contact the interconnect layer, whereby the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnect layer.

[0102] As illustrated in FIG. 3N, the rewiring layer 370 is formed over the source contact 364 and contacts the source contact 364. In some embodiments, the rewiring layer 370 is formed by depositing a conductive material such as Al on the top surfaces of the ILD layer 356 and the source contact 364 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A passivation layer 372 may be formed over the rewiring layer 370. In some embodiments, the passivation layer 372 is formed by depositing a dielectric material such as silicon nitride using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Thereby, an interconnect layer 376 including the ILD layer 356, the rewiring layer 370, and the passivation layer 372 is formed in some embodiments.

[0103] As illustrated in FIG. 3L, contact openings 360 and 361 are formed through the ILD layer 356 and the N-type doped semiconductor layer 306, respectively. In some embodiments, the contact openings 360 and 361 are formed using wet etching and / or dry etching, such as RIE, through the ILD layer 356 and the N-type doped semiconductor layer 306. In some embodiments, the contact openings 360 and 361 are patterned using lithography to be aligned with the peripheral contacts 338 and 340, respectively. The etching of the contact openings 360 and 361 stops at the upper ends of the peripheral contacts 338 and 340, exposing the peripheral contacts 338 and 340. As illustrated in FIG. 3L, spacers 362 are formed along the sidewalls of the contact openings 360 and 361 to electrically isolate the N-type doped semiconductor layer 306 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the etching of the source contact opening 358 is performed after the formation of the spacers 362, whereby the spacers 362 are not formed along the sidewalls of the source contact opening 358, increasing the contact area between the source contact 364 and the N-type doped semiconductor layer 306.

[0104] As illustrated in FIG. 3M, contacts 366 and 368 are respectively formed in contact openings 360 and 361 (shown in FIG. 3L) on the back side of the N-type doped semiconductor layer 306. In some embodiments, contacts 366 and 368 penetrate the ILD layer 356 and the N-type doped semiconductor layer 306 in the vertical direction. Contacts 366 and 368 and source contact 364 are formed using the same deposition process, thereby reducing the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings 360 and 361 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, filling the contact openings 360 and 361 with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). Then, a planarization process such as CMP is performed, thereby removing excess conductive material and making the top surfaces of contacts 366 and 368 (and the top surface of source contact 364) coplanar with the top surface of the ILD layer 356. In some embodiments, since contact openings 360 and 361 are respectively aligned with peripheral contacts 338 and 340, contacts 366 and 368 are similarly above and in contact with peripheral contacts 338 and 340, respectively.

[0105] As illustrated in FIG. 3N, the redistribution layer 370 is also formed above and in contact with contact 366. As a result, the N-type doped semiconductor layer 306 can be electrically connected to the peripheral contact 338 through the source contact 364, the redistribution layer 370 of the interconnect layer 376, and the contact 366. In some embodiments, the N-type doped semiconductor layer 306 is electrically connected to the peripheral circuit 352 through the source contact 364, the interconnect layer 376, the contact 366, the peripheral contact 338, and the bonding layers 346 and 348.

[0106] As illustrated in FIG. 3N, contact pad 374 is formed above contact 368 and is in contact with contact 368. In some embodiments, a portion of passivation layer 372 covering contact 368 is removed by wet etching and / or dry etching, thereby exposing a portion of underlying redistribution layer 370 to form contact pad 374. As a result, contact pad 374 for pad out can be electrically connected to contact 368, peripheral contacts 340, and peripheral circuit 352 through bonding layers 346 and 348.

[0107] It is understood that the second substrate, the sacrificial layer, and the N-type doped semiconductor layer described above in method 500 can be replaced with a handling layer, a buried oxide layer (also referred to as a "BOX" layer), and a device layer in an SOI wafer as described below with respect to method 501. Details of similar operations between methods 500 and 501 may not be repeated for ease of explanation. Referring to FIG. 5B, method 501 begins with operation 502 in which a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate.

[0108] As illustrated in FIG. 5B, method 501 proceeds to operation 503 where the device layer of the SOI wafer is doped with an N-type dopant. The SOI wafer can include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide and the device layer includes single crystal silicon. As illustrated in FIG. 3A, SOI wafer 301 includes a handling layer 302 (corresponding to carrier substrate 302 in the description of method 500 above), a buried oxide layer 304 (corresponding to sacrificial layer 304), and a device layer 306 (corresponding to N-type doped semiconductor layer 306). The device layer 306 can be doped with an N-type dopant such as P, As, or Sb using ion implantation and / or thermal diffusion, thereby becoming an N-type doped device layer 306. It is understood that the above description regarding carrier substrate 302, sacrificial layer 304, and N-type doped semiconductor layer 306 can similarly apply to handling layer 302, buried oxide layer 304, and doped device layer 306 of SOI wafer 301, respectively, to better understand method 501 below, and thus will not be repeated for simplicity of explanation.

[0109] As illustrated in FIG. 5B, method 501 proceeds to operation 505 where a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include stacked dielectric layers and stacked sacrificial layers arranged alternately. As illustrated in FIG. 5B, method 501 proceeds to operation 507 where a channel structure is formed that vertically penetrates the dielectric stack and the doped device layer. In some embodiments, to form the channel structure, a channel hole is formed that vertically penetrates the dielectric stack and the doped device layer and stops at the buried oxide layer, and then a memory film and a semiconductor channel are deposited along the sidewalls of the channel hole. As illustrated in FIG. 5B, method 501 proceeds to operation 508 where the dielectric stack is replaced with a memory stack, whereby the channel structure vertically penetrates the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with a memory stack, an opening is etched that vertically penetrates the dielectric stack and stops at the doped device layer, the stacked sacrificial layer is replaced with a stacked conductor layer through the opening, and a memory stack is formed that includes an alternating arrangement of stacked dielectric layers and stacked conductor layers. As illustrated in FIG. 5B, method 501 proceeds to operation 510 where an insulating structure is formed that vertically penetrates the memory stack. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited in the opening to fill the opening.

[0110] As illustrated in FIG. 5B, method 501 proceeds to operation 513, where the first substrate and the SOI wafer are bonded face-to-face, and the memory stack is above the peripheral circuit. The bonding can include a hybrid bonding. As illustrated in FIG. 5B, method 501 proceeds to operation 515, where the handle layer and the buried oxide layer of the SOI wafer are removed to expose the ends of the channel structure. As illustrated in FIG. 5B, method 501 proceeds to operation 517, where a portion of the channel structure that is in contact with the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure that is in contact with the doped device layer with a semiconductor plug, a portion of the memory film that is in contact with the doped device layer is etched, thereby forming a recess surrounding a portion of the semiconductor channel, a portion of the semiconductor channel is doped, and polysilicon is deposited within the recess to surround and contact the portion of the doped semiconductor channel to form a contacting semiconductor plug.

[0111] As illustrated in FIG. 5B, method 501 proceeds to operation 519, where a source contact is formed above the memory stack and in contact with the doped device layer. As illustrated in FIG. 5B, method 501 proceeds to operation 520, where an interconnect layer is formed above the source contact and in contact with the source contact. In some embodiments, the contact is formed through the doped device layer and in contact with the interconnect layer, whereby the doped device layer is electrically connected to the contact through the source contact and the interconnect layer.

[0112] Figures 4A - 4O illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 6A illustrates a flowchart of a method 600 for forming another exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 6B illustrates a flowchart of another method 601 for forming another exemplary 3D memory device according to some embodiments of the present disclosure. The examples of 3D memory devices shown in FIGS. 4A - 4O, FIG. 6A, and FIG. 6B include the 3D memory device 200 shown in FIG. 2. FIGS. 4A - 4O, FIG. 6A, and FIG. 6B will be described together. It is understood that the operations shown in methods 600 and 601 are not exhaustive and that other operations may be similarly performed before, after, or between any of the illustrated operations. Further, some of these operations may be performed simultaneously or in an order different from that shown in FIGS. 6A and 6B.

[0113] Referring to FIG. 6A, method 600 begins with operation 602 where peripheral circuitry is formed on a first substrate. The first substrate may be a silicon substrate. As illustrated in FIG. 4G, a plurality of transistors are formed on silicon substrate 450 using a plurality of processes including, but not limited to, photolithography, etching, thin - film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions (not shown) are formed within silicon substrate 450 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed within silicon substrate 450 by wet etching and / or dry etching as well as thin - film deposition. The transistors can form peripheral circuitry 452 on silicon substrate 450.

[0114] As illustrated in FIG. 4G, the bonding layer 448 is formed above the peripheral circuit 452. The bonding layer 448 includes bonding contacts that are electrically connected to the peripheral circuit 452. To form the bonding layer 448, an ILD layer is deposited using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and / or dry etching, such as RIE, and then using one or more thin film deposition processes such as ALD, CVD, PVD, or any other suitable process, or any combination thereof.

[0115] A channel structure that vertically penetrates a memory stack and a P-type doped semiconductor layer having an N-well can be formed above the second substrate. As illustrated in FIG. 6A, method 600 proceeds to operation 604, where a sacrificial layer on the second substrate, a P-type doped semiconductor layer having an N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are subsequently formed. The second substrate may be a silicon substrate. Since the second substrate is removed from the final product, in order to reduce the cost of the second substrate, it is understood that it may be a dummy wafer made of any suitable material, such as glass, sapphire, plastic, silicon, etc., for example, a part of a carrier substrate. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the P-type doped semiconductor layer includes polysilicon, and the dielectric stack includes alternately arranged stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and the stack sacrificial layers are alternately deposited on the P-type doped semiconductor layer to form the dielectric stack. In some embodiments, before forming the dielectric stack, a part of the P-type doped semiconductor layer is doped with an N-type dopant to form an N-well.

[0116] As illustrated in FIG. 4A, a sacrificial layer 404 is formed on a carrier substrate 402, and a P-type doped semiconductor layer 406 is formed on the sacrificial layer 404. The P-type doped semiconductor layer 406 can include polysilicon doped with a P-type dopant such as B, Ga, or Al. The sacrificial layer 404 can include any suitable sacrificial material that can be selectively removed later and is different from the material of the P-type doped semiconductor layer 406. In some embodiments, the sacrificial layer 404 includes a dielectric material such as silicon oxide or silicon nitride. To form the sacrificial layer 404, silicon oxide or silicon nitride is deposited on the carrier substrate 402 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form the P-type doped semiconductor layer 406, polysilicon is deposited on the sacrificial layer 404 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof, and then the deposited polysilicon is doped with a P-type dopant such as B, Ga, or Al using ion implantation and / or thermal diffusion. In some embodiments, in-situ doping of a P-type dopant such as B, Ga, or Al is performed when depositing polysilicon on the sacrificial layer 404 to form the P-type doped semiconductor layer 406.

[0117] As illustrated in FIG. 4A, a portion of the P-type doped semiconductor layer 406 is doped with an N-type dopant such as P, As, or Sb to form an N-well 407 within the P-type doped semiconductor layer 406. In some embodiments, the N-well 407 is formed using ion implantation and / or thermal diffusion. The ion implantation and / or thermal diffusion process can be controlled to control the thickness of the N-well 407 through either the entire thickness or a portion of the thickness of the P-type doped semiconductor layer 406.

[0118] As illustrated in FIG. 4B, a dielectric stack 410 including a plurality of pairs of a first dielectric layer (referred to herein as “stack sacrificial layer” 412) and a second dielectric layer (referred to herein as “stack dielectric layer” 410, and collectively referred to herein as “dielectric layer pair”) is formed on a P-type doped semiconductor layer 406. The dielectric stack 408 includes, in some embodiments, alternately arranged stack sacrificial layers 412 and stack dielectric layers 410. The stack dielectric layer 410 and the stack sacrificial layer 412 can be alternately deposited on the P-type doped semiconductor layer 406 above the carrier substrate 402 to form the dielectric stack 408. In some embodiments, each stack dielectric layer 410 includes a layer of silicon oxide, and each stack sacrificial layer 412 includes a layer of silicon nitride. The dielectric stack 408 can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in FIG. 4B, a staircase structure can be formed at the edge of the dielectric stack 408. The staircase structure can be formed by performing a plurality of so-called “trim etch” cycles on the dielectric layer pair of the dielectric stack 408 towards the carrier substrate 402. By applying repeated trim etch cycles to the dielectric layer pair of the dielectric stack 408, the dielectric stack 408 can have one or more inclined edges and a top dielectric layer pair shorter than the bottom dielectric layer pair, as shown in FIG. 4B.

[0119] As illustrated in FIG. 6A, method 600 proceeds to operation 606 where a channel structure is formed that vertically penetrates the dielectric stack and the P-type doped semiconductor layer. In some embodiments, to form the channel structure, a channel hole that vertically penetrates the dielectric stack and the P-type doped semiconductor layer and stops at the sacrificial layer is etched, and then a memory film and a semiconductor channel are deposited along the sidewalls of the channel hole.

[0120] As illustrated in FIG. 4B, the channel hole is an opening that vertically penetrates the dielectric stack 408 and the P-type doped semiconductor layer 406. In some embodiments, a plurality of openings are formed, and each opening serves as a location for growing an individual channel structure 414 in a later process. In some embodiments, the fabrication process for forming the channel hole of the channel structure 414 includes wet etching and / or dry etching such as DRIE. The sacrificial layer 404 can function as an etch stop layer to control the variation in the through-holes between different channel holes. For example, the etching of the channel hole can be stopped by the sacrificial layer 404 without further penetrating into the carrier substrate 402. That is, in some embodiments, the lower end of each channel hole (and the corresponding channel structure 414) is between the top and bottom surfaces of the sacrificial layer 404.

[0121] As illustrated in FIG. 4B, a memory film including a blocking layer 417, a storage layer 416, and a tunnel layer 415, and a semiconductor channel 418 are then formed in this order along the sidewalls and bottom surface of the channel hole. In some embodiments, first, the blocking layer 417, the storage layer 416, and the tunnel layer 415 are deposited in this order along the sidewalls and bottom surface of the channel hole using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to form the memory film. Then, the semiconductor channel 418 can be formed by depositing a semiconductor material such as polysilicon (e.g., undoped polysilicon) on top of the tunnel layer 415 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (the "SONO" structure) are then deposited to form the blocking layer 417, the storage layer 416, and the tunnel layer 415 of the memory film and the semiconductor channel 418.

[0122] As illustrated in FIG. 4B, the capping layer is formed within the channel hole and on the semiconductor channel 418 and fills the channel hole completely or partially (e.g., without voids or with voids). The capping layer can be formed by depositing a dielectric material such as silicon oxide using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Next, a channel plug can be formed at the top of the channel hole. In some embodiments, the memory film on the top surface of the dielectric stack 408, the semiconductor channel 418, and a portion of the capping layer are removed and planarized by CMP, wet etching, and / or dry etching. Next, a recess can be formed at the top of the channel hole by wet etching and / or dry etching a portion of the semiconductor channel 418 and the capping layer at the top of the channel hole. Next, the channel plug can be formed by depositing a semiconductor material such as polysilicon within the recess by one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Thereby, the channel structure 414 is formed through the dielectric stack 408 and the P-type doped semiconductor layer 406. Depending on the depth at which the etching of each channel hole is stopped by the sacrificial layer 404, the channel structure 414 can penetrate further into the sacrificial layer 404 or stop at the interface between the sacrificial layer 404 and the P-type doped semiconductor layer 406. Nevertheless, the channel structure 414 cannot penetrate further into the carrier substrate 402.

[0123] As illustrated in FIG. 6A, method 600 proceeds to operation 608 where the dielectric stack is replaced with a memory stack, for example, using a so-called “gate replacement” process, whereby the channel structure penetrates vertically through the memory stack and the P-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with a memory stack, an opening is etched that penetrates the dielectric stack vertically and terminates at the P-type doped semiconductor layer, and the stack sacrificial layer is replaced with a stack conductor layer through the opening to form a memory stack including an alternating arrangement of a stack dielectric layer and a stack conductor layer.

[0124] As illustrated in FIG. 4C, slit 420 is an opening that penetrates the dielectric stack 408 vertically and terminates at the P-type doped semiconductor layer 406. In some embodiments, the fabrication process for forming slit 420 includes wet etching and / or dry etching, such as DRIE. Although slit 420 is laterally aligned with N-well 407 as shown in FIG. 4C, it is understood that in other examples, slit 420 may not be laterally aligned with N-well 407. Gate exchange can then be performed through slit 420 to replace dielectric stack 408 with memory stack 430 (shown in FIG. 4E).

[0125] As illustrated in FIG. 4D, outer recess 422 is first formed by removing stack sacrificial layer 412 (shown in FIG. 4C) through slit 420. In some embodiments, stack sacrificial layer 412 is removed by applying an etchant through slit 420 to form outer recesses 422 alternating between stack dielectric layers 410. The etchant can include any suitable etchant that selectively etches stack sacrificial layer 412 with respect to stack dielectric layer 410.

[0126] As illustrated in FIG. 4E, the stack conductor layer 428 (including the gate electrode and the adhesive layer) is deposited into the outer recess 422 (shown in FIG. 4D) through the slit 420. In some embodiments, the gate dielectric layer 432 is deposited into the outer recess 422 in front of the stack conductor layer 428, and the stack conductor layer 428 is deposited on the gate dielectric layer 432. The stack conductor layer 428, such as a metal layer, can be deposited using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the gate dielectric layer 432, such as a high-k dielectric layer, is formed along the sidewalls and also at the bottom of the slit 420. The memory stack 430 including the alternately arranged stack conductor layers 428 and stack dielectric layers 410 thereby forms, in some embodiments, by replacing the dielectric stack 408 (shown in FIG. 4D).

[0127] As illustrated in FIG. 6A, method 600 proceeds to operation 610 where an insulating structure is formed that penetrates the memory stack in a vertical direction. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the openings to fill the openings. As illustrated in FIG. 4E, an insulating structure 436 is formed that penetrates the memory stack 430 in a vertical direction and terminates on the top surface of the P-type doped semiconductor layer 406. The insulating structure 436 can be formed by depositing one or more dielectric materials such as silicon oxide into the slit 420 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to completely or partially fill the slit 420 (with or without voids). In some embodiments, the insulating structure 436 includes the gate dielectric layer 432 (e.g., including a high-k dielectric) and a dielectric capping layer 434 (e.g., including silicon oxide).

[0128] As illustrated in FIG. 4F, after the formation of the insulating structure 436, local contacts including channel local contact 444 and word line local contact 442, and peripheral contacts 438, 439, and 440 are formed. The local dielectric layer can be formed on the memory stack 430 by depositing a dielectric material such as silicon oxide or silicon nitride on the memory stack 430 using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The channel local contact 444, word line local contact 442, and peripheral contacts 438, 439, and 440 are formed by etching contact openings through the local dielectric layer (and any other ILD layer) using wet etching and / or dry etching, such as RIE, and then filling the contact openings with a conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0129] As illustrated in FIG. 4F, the bonding layer 446 is formed above the channel local contact 444, word line local contact 442, and peripheral contacts 438, 439, and 440. The bonding layer 446 includes bonding contacts that are electrically connected to the channel local contact 444, word line local contact 442, and peripheral contacts 438, 439, and 440. To form the bonding layer 446, an ILD layer is deposited using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and / or dry etching, such as RIE, and then using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0130] As illustrated in FIG. 6A, method 600 proceeds to operation 612, where the first substrate and the second substrate are bonded face-to-face, with the memory stack above the peripheral circuitry. The bonding can include hybrid bonding. As illustrated in FIG. 4G, a carrier substrate 402 and components formed thereon (e.g., a memory stack 430 and a channel structure 414 formed therein) are flipped upside down. A downward bonding layer 446 is bonded to an upward bonding layer 448, i.e., bonded face-to-face, thereby forming a bonding interface 454 between the carrier substrate 402 and the silicon substrate 450 in some embodiments. In some embodiments, a processing process, such as plasma processing, wet processing, and / or heat treatment, is applied to the bonding surfaces prior to bonding. After bonding, the bonding contacts in the bonding layer 446 and the bonding contacts in the bonding layer 448 are aligned and in contact with each other, such that the memory stack 430 and the channel structure 414 formed therethrough are electrically connected to the peripheral circuitry 452, which is above the peripheral circuitry 452.

[0131] As illustrated in FIG. 6A, method 600 proceeds to operation 614, where the second substrate and the sacrificial layer are removed to expose the ends of the channel structure. The removal can be performed from the back side of the second substrate. As illustrated in FIG. 4H, the carrier substrate 402 and the sacrificial layer 404 (shown in FIG. 4G) are removed from the back side to expose the upper ends of the channel structure 414. The carrier substrate 402 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some embodiments, the carrier substrate 402 is peeled off. The removal of the carrier substrate 402 can be stopped by the underlying sacrificial layer 404 due to its different material to ensure thickness uniformity. In some embodiments where the carrier substrate 402 includes silicon and the sacrificial layer 304 includes silicon oxide, the carrier substrate 402 can be removed using CMP and automatically stop at the interface between the carrier substrate 402 and the sacrificial layer 404.

[0132] Next, the sacrificial layer 404 can be similarly selectively removed using wet etching with a suitable etchant such as hydrofluoric acid without etching the underlying P-type doped semiconductor layer 406. As explained above, since the channel structure 414 does not penetrate into the carrier substrate 402 beyond the sacrificial layer 404, the removal of the carrier substrate 402 does not affect the channel structure 414. Removal of the sacrificial layer 404 can expose the upper end portion of the channel structure 414. In some embodiments where the channel structure 414 penetrates into the sacrificial layer 404, selective etching of the sacrificial layer 404 containing silicon oxide also removes a portion of the blocking layer 417 containing silicon oxide that is above the top surface of the P-type doped semiconductor layer 406, but the storage layer 416 containing silicon nitride and other layers (e.g., the tunnel layer 415) surrounded by the storage layer 416 remain intact.

[0133] As illustrated in FIG. 6A, method 600 proceeds to operation 616 where a portion of the channel structure in contact with the P-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure in contact with the P-type doped semiconductor layer with a semiconductor plug, a portion of the memory film in contact with the P-type doped semiconductor layer is removed, thereby forming a recess surrounding a portion of the semiconductor channel, a portion of the semiconductor channel is doped, and polysilicon is deposited within the recess to surround and contact the portion of the doped semiconductor channel to form the contacting semiconductor plug.

[0134] As illustrated in FIG. 4I, a portion of the storage layer 416 (shown in FIG. 4H) that is in contact with the P-type doped semiconductor layer 406 is removed. In some embodiments, the storage layer 416, which includes silicon nitride, is selectively removed using wet etching with a suitable etchant, such as phosphoric acid, without etching the P-type doped semiconductor layer 406, which includes polysilicon. The etching of the storage layer 416 is controlled by controlling the etching time and / or the etching rate, such that the etching does not continue to affect the remaining portion of the storage layer 416 surrounded by the memory stack 430.

[0135] As shown in FIG. 4J, a portion of the blocking layer 417 and the tunnel layer 415 that are in contact with the P-type doped semiconductor layer 406 is removed, thereby forming a recess 457 that surrounds the top of the semiconductor channel 418 in contact with the P-type doped semiconductor layer 406. In some embodiments, the blocking layer 417 and the tunnel layer 415 containing silicon oxide are selectively removed using wet etching with a suitable etchant such as hydrofluoric acid without etching the P-type doped semiconductor layer 406 and the semiconductor channel 418 containing polysilicon. The etching of the blocking layer 417 and the tunnel layer 415 is controlled by controlling the etching time and / or the etching rate, so that the etching does not continue to affect the remaining portions of the blocking layer 417 and the tunnel layer 415 surrounded by the memory stack 430. As a result, according to some embodiments, the top of the memory film (including the blocking layer 417, the storage layer 416, and the tunnel layer 415) of the channel structure 414 in contact with the P-type doped semiconductor layer 406 is removed, thereby forming a recess 457 and exposing the top of the semiconductor channel 418. In some embodiments, the top of the semiconductor channel 418 exposed by the recess 457 is doped to increase its conductivity. For example, an inclined ion implantation process may be performed to dope any suitable dopant to the desired doping concentration on the top of the semiconductor channel 418 (e.g., containing polysilicon) exposed by the recess 457.

[0136] As illustrated in FIG. 4K, the semiconductor plug 459 is formed within the recess 457 (shown in FIG. 4J) and surrounds and contacts the doped top of the semiconductor channel 418. As a result, in some embodiments, the top of the channel structure 414 (shown in FIG. 4H) that abuts the P-type doped semiconductor layer 406 is thereby replaced by the semiconductor plug 459. In some embodiments, to form the semiconductor plug 459, one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof are used to deposit polysilicon within the recess 457 to fill the recess 457, and subsequently, any excess polysilicon above the top surface of the P-type doped semiconductor layer 406 is removed by a CMP process. In some embodiments, in-situ doping of a P-type dopant such as B, Ga, or Al is performed when depositing polysilicon within the recess 457 to dope the semiconductor plug 459. Since the semiconductor plug 459 and the P-type doped semiconductor layer 406 can include the same material such as polysilicon and have the same thickness (after the CMP process), the semiconductor plug 459 may be regarded as a part of the P-type doped semiconductor layer 406. Nevertheless, since the semiconductor plug 459 is formed in a process after the formation of the remaining portion of the P-type doped semiconductor layer 406 (e.g., shown in FIG. 4A), in some embodiments, the doping concentration of the semiconductor plug 459 is different from the doping concentration of the remaining portion of the P-type doped semiconductor layer 406, regardless of whether the semiconductor plug 459 is doped in-situ.

[0137] As described above, the semiconductor plug 459 within the P-type doped semiconductor layer 406 can function as a sidewall SEG of the channel structure 414. Unlike known methods of forming a sidewall SEG by etching and deposition processes through a slit 420 (e.g., as shown in FIG. 4D) that penetrates the dielectric stack 408 from end to end with a high aspect ratio, the semiconductor plug 459 may be formed from the opposite side of the dielectric stack 408 / memory stack 430 after the carrier substrate 402 has been removed, which is not affected by the level of the dielectric stack 408 / memory stack 430 and the aspect ratio of the slit 420. By avoiding problems also introduced by the high aspect ratio of the slit 420, fabrication complexity and cost can be reduced and yield can be increased. Further, vertical scalability (e.g., higher levels of the dielectric stack 408 / memory stack 430) can be improved as well.

[0138] As illustrated in FIG. 6A, method 600 proceeds to operation 618 where a first source contact is formed above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact is formed above the memory stack and in contact with the N-well. As illustrated in FIG. 4L, one or more ILD layers 456 are formed over the P-type doped semiconductor layer 406. The ILD layer 456 can be formed by depositing a dielectric material on top of the P-type doped semiconductor layer 406 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0139] As illustrated in FIG. 4M, the source contact opening 458 can be formed within the P-type doped semiconductor layer 406 through the ILD layer 456. In some embodiments, the source contact opening 458 is formed using wet etching and / or dry etching, such as RIE. In some embodiments, the source contact opening 458 further penetrates into the top of the P-type doped semiconductor layer 406. The etching process through the ILD layer 456 can continue to etch a portion of the P-type doped semiconductor layer 406. In some embodiments, a separate etching process is used to etch a portion of the P-type doped semiconductor layer 406 after the etching through the ILD layer 456.

[0140] As illustrated in FIG. 4M, the source contact opening 465 can be formed within the N-well 407 through the ILD layer 456. In some embodiments, the source contact opening 465 is formed using wet etching and / or dry etching, such as RIE. In some embodiments, the source contact opening 465 further penetrates into the top of the N-well 407. The etching process through the ILD layer 456 can continue to etch a portion of the N-well 407. In some embodiments, a separate etching process is used to etch a portion of the N-well 407 after the etching through the ILD layer 456. The etching of the source contact opening 458 can be performed after the etching of the source contact opening 465, or vice versa. In some examples, the source contact openings 458 and 465 are etched by the same etching process, thereby reducing the number of etching processes.

[0141] As illustrated in FIG. 4N, source contacts 464 and 478 are formed in source contact openings 458 and 465 (shown in FIG. 4M) on the back side of the P-type doped semiconductor layer 406, respectively. Source contact 464 is, in some embodiments, above the memory stack 430 and in contact with the P-type doped semiconductor layer 406. Source contact 478 is, in some embodiments, above the memory stack 430 and in contact with the N-well 407. In some embodiments, one or more conductive materials are deposited in source contact openings 458 and 465 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, filling the source contact openings 458 and 465 with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). Then, a planarization process such as CMP is performed, thereby removing excess conductive material and enabling the top surfaces of source contacts 464 and 478 to be coplanar with each other and further coplanar with the top surface of the ILD layer 456. In some examples, source contacts 464 and 478 are formed by the same deposition and CMP processes, thereby reducing the number of fabrication processes.

[0142] As illustrated in FIG. 6A, method 600 proceeds to operation 620 where an interconnect layer is formed over and in contact with the first and second source contacts. In some embodiments, the interconnect layer includes a first interconnect and a second interconnect that are above and in contact with the first and second source contacts, respectively.

[0143] As illustrated in FIG. 4O, the redistribution layer 470 is formed above the source contacts 464 and 478 and is in contact with the source contacts 464 and 478. In some embodiments, the redistribution layer 470 is formed by depositing a conductive material such as Al on the top surface of the ILD layer 456 and the source contact 364 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the redistribution layer 470 is patterned by a lithography and etching process, and includes a first interconnect 470-1 that is above the source contact 464 and in contact with the source contact 464, and a second interconnect 470-2 that is above the source contact 478 and in contact with the source contact 478. The first and second interconnects 470-1 and 470-2 can be electrically isolated from each other. The passivation layer 472 can be formed on the redistribution layer 470. In some embodiments, the passivation layer 472 is formed by depositing a dielectric material such as silicon nitride using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Thereby, an interconnect layer 476 including the ILD layer 456, the redistribution layer 470, and the passivation layer 472 is formed in some embodiments.

[0144] As illustrated in FIG. 4L, contact openings 460, 461, and 463 are formed that each penetrate the ILD layer 456 and the P-type doped semiconductor layer 406. In some embodiments, the contact openings 460, 461, and 463 are formed using wet etching and / or dry etching, such as RIE, through the ILD layer 456 and the P-type doped semiconductor layer 406. In some embodiments, the contact openings 460, 461, and 463 are patterned using lithography to be aligned with the peripheral contacts 438, 440, and 439, respectively. The etching of the contact openings 460, 461, and 463 stops at the upper ends of the peripheral contacts 438, 439, and 440, and can expose the peripheral contacts 438, 439, and 440. The etching of the contact openings 460, 461, and 463 is performed by the same etching process, thereby reducing the number of etching processes. Due to different etching depths, the etching of the contact openings 460, 461, and 463 may be performed before the etching of the source contact opening 465, or vice versa, but it is understood that they are not performed simultaneously.

[0145] As illustrated in FIG. 4M, the spacer 462 is formed along the sidewalls of the contact openings 460, 461, and 463 and further the source contact opening 465 to electrically isolate the P-type doped semiconductor layer 406 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the spacer 462 is formed along the sidewalls of the contact openings 460, 461, and 463 and further the source contact opening 465 by the same deposition process, thereby reducing the number of fabrication processes. In some embodiments, the etching of the source contact opening 458 is performed after the formation of the spacer 362, whereby the spacer 362 is not formed along the sidewall of the source contact opening 358, increasing the contact area between the source contact 364 and the N-type doped semiconductor layer 306.

[0146] As illustrated in FIG. 4N, contacts 466, 468, and 469 are respectively formed within contact openings 460, 461, and 463 (shown in FIG. 4M) on the back side of the P-type doped semiconductor layer 406. Contacts 466, 468, and 469 penetrate the ILD layer 456 and the P-type doped semiconductor layer 406 in the vertical direction in some embodiments. Contacts 466, 468, and 469 as well as source contacts 464 and 478 are formed using the same deposition process, thereby reducing the number of deposition processes. In some embodiments, one or more conductive materials are deposited within contact openings 460, 461, and 463 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, filling the contact openings 460, 461, and 463 with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). Then, a planarization process such as CMP is performed, thereby removing excess conductive material and enabling the top surfaces of contacts 466, 468, and 469 (and the top surfaces of source contacts 464 and 478) to be flush with the top surface of the ILD layer 456. In some embodiments, since contact openings 460, 461, and 463 are respectively aligned with peripheral contacts 438, 440, and 439, contacts 466, 468, and 469 are similarly each above and in contact with peripheral contacts 438, 440, and 439.

[0147] As illustrated in FIG. 4O, the first interconnect 470-1 of the rewiring layer 470 is formed above the contact 466 and in contact with the contact 466. As a result, the P-type doped semiconductor layer 406 can be electrically connected to the peripheral contact 438 through the source contact 464, the first interconnect 470-1 of the interconnect layer 476, and the contact 466. In some embodiments, the P-type doped semiconductor layer 406 is electrically connected to the peripheral circuit 452 through the source contact 464, the first interconnect 470-1 of the interconnect layer 476, the contact 466, the peripheral contact 438, and the bonding layers 446 and 448. Similarly, the second interconnect 470-2 of the rewiring layer 470 is formed above the contact 469 and in contact with the contact 469. As a result, the N-well 407 can be electrically connected to the peripheral contact 438 through the source contact 478, the second interconnect 470-2 of the interconnect layer 476, and the contact 469. In some embodiments, the N-well 407 is electrically connected to the peripheral circuit 452 through the source contact 478, the second interconnect 470-2 of the interconnect layer 476, the contact 469, the peripheral contact 439, and the bonding layers 446 and 448.

[0148] As illustrated in FIG. 4O, the contact pad 474 is formed above the contact 468 and in contact with the contact 468. In some embodiments, a portion of the passivation layer 472 covering the contact 468 is removed by wet etching and / or dry etching, thereby exposing a portion of the underlying rewiring layer 470 to form the contact pad 474 for pad out. As a result, the contact pad 474 for pad out can be electrically connected to the peripheral circuit 452 through the contact 468, the peripheral contact 440, and the bonding layers 446 and 448.

[0149] The second substrate, sacrificial layer, and P-type doped semiconductor layer described above in method 600 can be replaced with a SOI wafer including a handling layer, a buried oxide layer (also referred to as a "BOX" layer), and a device layer, as described below with respect to method 601. Details of similar operations between methods 600 and 601 may not be repeated for ease of explanation. Referring to FIG. 6B, method 601 begins with operation 602 where a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate.

[0150] As illustrated in FIG. 6B, method 601 proceeds to operation 603 where the device layer of the SOI wafer is doped with a P-type dopant. The SOI wafer can include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide and the device layer includes single-crystalline silicon. As illustrated in FIG. 6B, method 601 proceeds to operation 605 where a portion of the doped device layer is doped with an N-type dopant to form an N-well within the doped device layer.

[0151] As illustrated in FIG. 4A, the SOI wafer 401 includes a handling layer 402 (corresponding to the carrier substrate 402 in the above description when explaining method 600), a buried oxide layer 404 (corresponding to the sacrificial layer 404), and a device layer 406 (corresponding to the P-type doped semiconductor layer 406). The device layer 406 can be doped with a P-type dopant such as P, As, or Sb using ion implantation and / or thermal diffusion, thereby becoming the P-type doped device layer 406. A portion of the doped device layer 406 can be further doped with an N-type dopant such as B, Ga, or Al using ion implantation and / or thermal diffusion, thereby forming the N well 407. It is understood that the above descriptions related to the carrier substrate 402, the sacrificial layer 404, and the P-type doped semiconductor layer 406 can similarly apply to the handling layer 402, the buried oxide layer 404, and the doped device layer 406 of the SOI wafer 401, respectively, to better understand the following method 601, and thus will not be repeated for ease of explanation.

[0152] As illustrated in FIG. 6B, method 601 proceeds to operation 607 where a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include stacked dielectric layers and stacked sacrificial layers arranged alternately. As illustrated in FIG. 6B, method 601 proceeds to operation 609 where a channel structure is formed that vertically penetrates the dielectric stack and the doped device layer. In some embodiments, to form the channel structure, a channel hole is formed that vertically penetrates the dielectric stack and the doped device layer and stops at the buried oxide layer, and then a memory film and a semiconductor channel are deposited along the sidewalls of the channel hole. As illustrated in FIG. 6B, method 601 proceeds to operation 608 where the dielectric stack is replaced with a memory stack, whereby the channel structure vertically penetrates the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with a memory stack, an opening is etched that vertically penetrates the dielectric stack and stops at the doped device layer, the stacked sacrificial layer is replaced with a stacked conductor layer through the opening, and a memory stack is formed that includes an alternating arrangement of stacked dielectric layers and stacked conductor layers. As illustrated in FIG. 6B, method 601 proceeds to operation 610 where an insulating structure method is formed that vertically penetrates the memory stack. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited in the opening to fill the opening.

[0153] As illustrated in FIG. 6B, method 601 proceeds to operation 613 where the first substrate and the SOI wafer are bonded face-to-face with the memory stack above the peripheral circuits. The bonding can include hybrid bonding. As illustrated in FIG. 6B, method 601 proceeds to operation 615 where the handle layer and the buried oxide layer of the SOI wafer are removed to expose the ends of the channel structure. As illustrated in FIG. 6B, method 601 proceeds to operation 617 where a portion of the channel structure in contact with the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure in contact with the doped device layer with a semiconductor plug, a portion of the memory film in contact with the doped device layer is etched, thereby forming a recess surrounding a portion of the semiconductor channel. A portion of the semiconductor channel is doped and polysilicon is deposited within the recess to surround and contact the portion of the doped semiconductor channel to form a contacting semiconductor plug.

[0154] As illustrated in FIG. 6B, method 601 proceeds to operation 619 where a first source contact above the memory stack and in contact with the doped device layer is formed, and a second source contact above the memory stack and in contact with the N-well is formed. As illustrated in FIG. 6B, method 601 proceeds to operation 621 where an interconnect layer above and in contact with the first and second source contacts is formed. In some embodiments, the interconnect layer includes a first interconnect above and in contact with the first source contact and a second interconnect above and in contact with the second source contact. In some embodiments, the first contact is formed through the doped device layer to contact the first interconnect layer, whereby the doped device layer is electrically connected to the first contact through the first source contact and the first interconnect layer. In some embodiments, the second contact is formed through the doped device layer to contact the second interconnect layer, whereby the doped device layer is electrically connected to the second contact through the second source contact and the second interconnect layer.

[0155] According to one aspect of the present disclosure, a 3D memory device includes a substrate, peripheral circuits on the substrate, a memory stack including alternating conductor layers and dielectric layers on the peripheral circuits, an N-type doped semiconductor layer on the memory stack, a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer, and a source contact on the memory stack and in contact with the N-type doped semiconductor layer. The upper end of each of the plurality of channel structures is in the same plane as the top surface of the N-type doped semiconductor layer or below it.

[0156] In some embodiments, the N-type doped semiconductor layer includes polysilicon.

[0157] In some embodiments, the N-type doped semiconductor layer includes single-crystalline silicon.

[0158] In some embodiments, each of the channel structures includes a memory film and a semiconductor channel, and the upper end of the memory film is below the upper end of the semiconductor channel.

[0159] In some embodiments, the upper end of the memory film is below the top surface of the N-type doped semiconductor layer, and the upper end of the semiconductor channel is in the same plane as the top surface of the N-type doped semiconductor layer or below it.

[0160] In some embodiments, a portion of the semiconductor channel penetrating into the N-type doped semiconductor layer includes doped polysilicon.

[0161] In some embodiments, the N-type doped semiconductor layer includes a semiconductor plug surrounding and in contact with a portion of the semiconductor channel, and the doping concentration of the semiconductor plug is different from the doping concentration of the remaining portion of the N-type doped semiconductor layer.

[0162] In some embodiments, the 3D memory device further includes an interconnect layer that is above the source contact and electrically connected to the source contact.

[0163] In some embodiments, the 3D memory device further includes a first contact through the N-type doped semiconductor layer. According to some embodiments, the N-type doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact, the interconnect layer, and the first contact.

[0164] In some embodiments, the 3D memory device further includes a second contact through the N-type doped semiconductor layer. The interconnect layer includes, according to some embodiments, a contact pad that is electrically connected to the second contact.

[0165] In some embodiments, the 3D memory device further includes an insulating structure that extends laterally to separate a plurality of channel structures into a plurality of blocks through the memory stack in the vertical direction.

[0166] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0167] In some embodiments, the top surface of the insulating structure is in the same plane as the bottom surface of the N-type doped semiconductor layer.

[0168] In some embodiments, the 3D memory device further includes a bonding interface between the peripheral circuit and the memory stack.

[0169] According to another aspect of the present disclosure, a 3D memory device includes a substrate, a memory stack including alternating conductor layers and dielectric layers on the substrate, an N-type doped semiconductor layer on the memory stack, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer. Each of the plurality of channel structures includes a memory film and a semiconductor channel. An upper end of the memory film is below an upper end of the semiconductor channel. The N-type doped semiconductor layer surrounds a portion of the semiconductor channel and includes a semiconductor plug in contact therewith. A doping concentration of the semiconductor plug is different from a doping concentration of the remaining portion of the N-type doped semiconductor layer.

[0170] In some embodiments, the semiconductor plug includes polysilicon and the remaining portion of the N-type doped semiconductor layer includes polysilicon.

[0171] In some embodiments, the semiconductor plug includes polysilicon and the remaining portion of the N-type doped semiconductor layer includes single crystal silicon.

[0172] In some embodiments, the 3D memory device further includes an insulating structure that penetrates vertically through the memory stack and extends laterally to separate the plurality of channel structures into a plurality of blocks.

[0173] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0174] In some embodiments, a top surface of the insulating structure is in the same plane as a bottom surface of the N-type doped semiconductor layer.

[0175] In some embodiments, the 3D memory device further includes a source contact that is above the memory stack and in contact with the N-type doped semiconductor layer.

[0176] In some embodiments, the 3D memory device further includes peripheral circuitry above the substrate and a bonding interface between the peripheral circuitry and the memory stack.

[0177] In some embodiments, the 3D memory device further includes an interconnect layer that is above the source contact and electrically connected to the source contact.

[0178] In some embodiments, the N-type doped semiconductor layer is electrically connected to the peripheral circuit at least through the source contact and the interconnect layer.

[0179] According to yet another aspect of the present disclosure, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory stack including alternating conductor layers and dielectric layers, an N-type doped semiconductor layer, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit. The N-type doped semiconductor layer includes a semiconductor plug surrounding a part of each of the plurality of channel structures penetrating into the N-type doped semiconductor layer. The doping concentration of the semiconductor plug is different from the doping concentration of the remaining portion of the N-type doped semiconductor layer.

[0180] In some embodiments, the second semiconductor structure further includes an insulating structure that extends horizontally in a vertical direction through the memory stack to separate the plurality of channel structures into a plurality of blocks.

[0181] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0182] In some embodiments, the insulating structure does not penetrate vertically into the N-type doped semiconductor layer.

[0183] In some embodiments, the second semiconductor structure further includes a source contact in contact with the N-type doped semiconductor layer.

[0184] In some embodiments, the second semiconductor structure further includes an interconnect layer, and each of the channel structures does not extend beyond the N-type doped semiconductor layer.

[0185] In some embodiments, the semiconductor plug includes polysilicon, and the remaining portion of the N-type doped semiconductor layer includes polysilicon.

[0186] In some embodiments, the semiconductor plug includes polysilicon, and the remaining portion of the N-type doped semiconductor layer includes single-crystalline silicon.

[0187] The foregoing description of specific embodiments will clarify the general nature of the present disclosure so that, within the knowledge of the art, without departing from the general concept of the present disclosure and without undue experimentation, such specific embodiments can be readily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein. It will be understood that the language or terminology herein is for the purpose of description and thus should be interpreted by those skilled in the art in light of the teachings and guidance.

[0188] Embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation forms of the specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for the convenience of explanation. Alternative boundaries can be defined as long as the specified functions and their relationships are properly executed.

[0189] The summary and abstract sections of the invention may define one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventor, and thus are not intended to limit the present disclosure and the appended claims in any way.

[0190] The scope and range of the present disclosure should not be limited by the above exemplary embodiments, but should be defined only by the claims and their equivalents.

Explanation of Reference Numerals

[0191] 100 3D memory device 101 Substrate 102 First semiconductor structure 104 Second semiconductor structure 106 Bonding interface 108 Peripheral circuit 110 Bonding layer 111 Bonding contact 112 Bonding layer 113 Bonding contact 114 Memory stack 116 Conductor layer 118 Dielectric layer 120 N-type doped semiconductor layer 122 Semiconductor plug 124 Channel structure 126 Memory film 127 Top 128 Semiconductor channel 129 Channel plug 130 Insulating structure 132 Backside source contact 133 BEOL interconnect layer 134 ILD layer 136 Rewiring layer 138 Passivation layer 140 Contact pad 142, 144 Contacts 146, 148 Peripheral contacts 150 Channel local contact 152 Word line local contact 200 3D memory device 201 Substrate 202 First semiconductor structure 204 Second semiconductor structure 206 Bonding interface 208 Peripheral circuit 210 Bonding layer 211 Bonding contact 212 Bonding layer 213 Bonding contact 216 Conductor layer 218 Dielectric layer 220 P-type doped semiconductor layer 221 N-well 222 Semiconductor plug 224 Channel structure 226 Memory film 227 Channel plug 228 Semiconductor channel 229 Top 230 Insulation structure 231, 232 Backside source contact 233 BEOL interconnect layer 234 ILD layer 236 Rewiring layer 236-1 First interconnect 236-2 Second interconnect 238 Passivation layer 240 Contact pad 242, 243, 244 Contact 246, 247, 248 Peripheral contact 250 Channel local contact 252 Word line local contact 302 Carrier substrate 304 Sacrificial layer 306 N-type doped semiconductor layer 308 Dielectric stack 310 Stacked dielectric layer 312 Stacked sacrificial layer 314 Channel structure 315 Tunnel layer 316 Storage layer 317 Blocking layer 318 Semiconductor channel 320 Slit 322 Outer recess 328 Stacked conductor layer 330 Memory stack 332 Gate dielectric layer 334 Dielectric capping layer 336 Insulation structure 338, 340 Peripheral contact 342 Word line local contact 344 Channel local contact 346 Bonding layer 348 Bonding layer 350 Silicon substrate 352 Peripheral circuit 354 Bonding interface 356 ILD layer 357 Concave portion 358 Source contact opening 359 Semiconductor plug 360, 361 Contact opening 362 Spacer 364 Source contact 366, 368 Contact 370 Rewiring layer 372 Passivation layer 374 Contact pad 376 Interconnection layer 402 Carrier substrate 404 Sacrificial layer 406 P-type doped semiconductor layer 407 N-well 408 Dielectric stack 410 Stacked dielectric layer 412 Stacked sacrificial layer 414 Channel structure 415 Tunnel layer 416 Storage layer 417 Blocking layer 418 Semiconductor channel 420 Slit 422 Outer concave portion 428 Stacked conductor layer 430 Memory stack 432 Gate dielectric layer 434 Dielectric capping layer 436 Insulation Structure 438, 439, 440 Peripheral Contact 442 Word Line Local Contact 444 Channel Local Contact 446 Bonding Layer 448 Bonding Layer 450 Silicon Substrate 452 Peripheral Circuit 454 Bonding Interface 456 ILD Layer 457 Concave Portion 458 Source Contact Opening 459 Semiconductor Plug 460, 461, and 463 Contact Opening 464 and 478 Source Contact 465 Source Contact Opening 466, 468, and 469 Contact 470 Redistribution Layer 470-1 First Interconnection 470-2 Second Interconnection 472 Passivation Layer 474 Contact Pad 476 Interconnection Layer

Claims

1. 1. A three-dimensional (3D) memory device, comprising: A substrate; peripheral circuits on the substrate; a memory stack including alternating conductive and dielectric layers above the peripheral circuitry; an N-type doped semiconductor layer above the memory stack; a plurality of channel structures, each penetrating vertically through the memory stack into the N-type doped semiconductor layer, an upper end of each of the plurality of channel structures being flush with or below a top surface of the N-type doped semiconductor layer; a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

2. 10. The 3D memory device of claim 1, wherein the N-type doped semiconductor layer comprises polysilicon.

3. 10. The 3D memory device of claim 1, wherein the N-type doped semiconductor layer comprises single crystal silicon.

4. 4. The 3D memory device of claim 1, wherein each of the channel structures includes a memory film and a semiconductor channel, and an upper end of the memory film is below an upper end of the semiconductor channel.

5. 5. The 3D memory device of claim 4, wherein the upper end of the memory film is below the top surface of the N-type doped semiconductor layer and the upper end of the semiconductor channel is coplanar with or below the top surface of the N-type doped semiconductor layer.

6. 6. The 3D memory device of claim 4 or 5, wherein the portion of the semiconductor channel that penetrates into the N-type doped semiconductor layer comprises doped polysilicon.

7. 7. The 3D memory device of claim 6, wherein the N-type doped semiconductor layer includes a semiconductor plug surrounding and contacting a portion of the semiconductor channel, the doping concentration of the semiconductor plug being different from the doping concentration of a remainder of the N-type doped semiconductor layer.

8. 8. The 3D memory device of claim 1, further comprising an interconnect layer above and electrically connected to said source contacts.

9. 10. The 3D memory device of claim 8, further comprising a first contact through said N-type doped semiconductor layer, said N-type doped semiconductor layer being electrically connected to said peripheral circuitry through at least said source contact, said interconnect layer, and said first contact.

10. 10. The 3D memory device of claim 8 or 9, further comprising a second contact through the N-type doped semiconductor layer, the interconnect layer including a contact pad electrically connected to the second contact.

11. 11. The 3D memory device of claim 1, further comprising an insulating structure that penetrates the memory stack vertically and extends laterally to separate the plurality of channel structures into a plurality of blocks.

12. The 3D memory device of claim 11 , wherein the insulating structures are filled with one or more dielectric materials.

13. 13. The 3D memory device of claim 11 or 12, wherein a top surface of the insulating structure is coplanar with a bottom surface of the N-type doped semiconductor layer.

14. The 3D memory device according to any one of claims 1 to 13, further comprising a bonding interface between the peripheral circuitry and the memory stack.

15. 1. A three-dimensional (3D) memory device, comprising: A substrate; a memory stack including alternating conductive and dielectric layers overlying the substrate; an N-type doped semiconductor layer above the memory stack; a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer; a plurality of channel structures, each of the plurality of channel structures including a memory film and a semiconductor channel, an upper end of the memory film being below an upper end of the semiconductor channel; 1. A three-dimensional (3D) memory device, wherein the N-type doped semiconductor layer includes a semiconductor plug surrounding and contacting a portion of a semiconductor channel, the semiconductor plug having a doping concentration different from a doping concentration of a remainder of the N-type doped semiconductor layer.

16. 16. The 3D memory device of claim 15, wherein the semiconductor plug comprises polysilicon and the remaining portion of the N-type doped semiconductor layer comprises polysilicon.

17. 16. The 3D memory device of claim 15, wherein the semiconductor plug comprises polysilicon and the remainder of the N-type doped semiconductor layer comprises single crystal silicon.

18. 18. The 3D memory device of claim 15, further comprising an insulating structure that penetrates the memory stack vertically and extends laterally to separate the channel structures into blocks.

19. 20. The 3D memory device of claim 18, wherein the isolation structures are filled with one or more dielectric materials.

20. 20. The 3D memory device of claim 18 or 19, wherein a top surface of the insulating structure is coplanar with a bottom surface of the N-type doped semiconductor layer.

21. 21. The 3D memory device of any one of claims 15 to 20, further comprising a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

22. peripheral circuitry above the substrate; 22. The 3D memory device of claim 21, further comprising a bonding interface between the peripheral circuitry and the memory stack.

23. 23. The 3D memory device of claim 22, further comprising an interconnect layer above and electrically connected to said source contacts.

24. 24. The 3D memory device of claim 23, wherein the N-type doped semiconductor layer is electrically connected to the peripheral circuitry through at least the source contact and the interconnect layer.

25. 1. A three-dimensional (3D) memory device, comprising: a first semiconductor structure including peripheral circuitry; A second semiconductor structure, a memory stack including alternating conductive and dielectric layers; an N-type doped semiconductor layer; a second semiconductor structure comprising: a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuitry, the N-type doped semiconductor layer including a semiconductor plug surrounding a portion of each of the plurality of channel structures that penetrate into the N-type doped semiconductor layer, the doping concentration of the semiconductor plug being different from the doping concentration of a remainder of the N-type doped semiconductor layer; a bonding interface between the first semiconductor structure and the second semiconductor structure.

26. 26. The 3D memory device of claim 25, wherein the second semiconductor structure further comprises an insulating structure that extends vertically through the memory stack and laterally to separate the plurality of channel structures into a plurality of blocks.

27. 30. The 3D memory device of claim 26, wherein the insulating structures are filled with one or more dielectric materials.

28. 30. The 3D memory device of claim 26 or 27, wherein the insulating structures do not penetrate vertically into the N-type doped semiconductor layer.

29. 30. The 3D memory device of any one of claims 25 to 28, wherein the second semiconductor structure further comprises a source contact in contact with the N-type doped semiconductor layer.

30. the second semiconductor structure further comprises an interconnect layer; 30. The 3D memory device of claim 29, wherein the N-type doped semiconductor layer is electrically connected to the peripheral circuitry through at least the source contact and the interconnect layer.

31. 31. The 3D memory device of any one of claims 25 to 30, wherein each of the channel structures does not extend beyond the N-type doped semiconductor layer.

32. 32. The 3D memory device of any one of claims 25 to 31, wherein the semiconductor plug comprises polysilicon and the remaining portion of the N-type doped semiconductor layer comprises polysilicon.

33. 32. The 3D memory device of any one of claims 25 to 31, wherein the semiconductor plug comprises polysilicon and the remainder of the N-type doped semiconductor layer comprises single crystal silicon.

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