Switching control circuit and power supply circuit

Abstract

To provide a switching control circuit that suppresses an over-voltage of an output voltage when making a transition from a normal mode to a burst mode.SOLUTION: A switching control circuit 10 comprises: a transformer 26 including a primary coil L1, secondary coils L2 and L3, and an assistance coil La; transistors 24, 25 that control a current in the primary coil; a resonance circuit including the primary coil and a capacitor 21; and a control IC that outputs, based on a resonance current flowing in the resonance circuit, a driving signal that causes a load detection circuit that detects a load state of a power supply circuit and the power supply circuit in the case where the it is under light load to operate in a burst mode, and outputs a driving signal that causes the power supply circuit to operate in a normal mode in the case where it is under heavy load. A driving signal output circuit stops an output of a driving signal without going through a state where a driving signal for gradually reducing an ON period of the transistor is output from a state where the driving signal is output on the basis of predetermined conditions immediately after the power supply circuit starts operation in the burst mode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a switching control circuit and a power supply circuit.

Background Art

[0002] A current resonant type DC-DC converter generally operates in an operation mode (normal mode) of continuously driving a switching element when the load state is a heavy load, and shifts to a burst mode when the load state becomes a light load. When such a DC-DC converter operates in the burst mode, in order to prevent the ringing of the transformer included in the DC-DC converter, so-called soft start and soft end may be performed (for example, Patent Documents 1 to 3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when the DC-DC converter shifts to the burst mode and performs a soft end operation, the output voltage may become an overvoltage depending on the load state.

[0005] The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a switching control circuit capable of suppressing an overvoltage of an output voltage when shifting from a normal mode to a burst mode.

Means for Solving the Problems

[0006] A first aspect of the switching control circuit according to the present invention that solves the above-described problems is a switching control circuit that controls the switching of the first and second transistors of a power supply circuit that includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, the first and second transistors that control the current of the primary coil, and a resonance circuit that includes the primary coil and a first capacitor, and generates an output voltage of a target level from an input voltage on the secondary side. The switching control circuit includes a load detection circuit that detects a state of a load of the power supply circuit based on a resonance current flowing through the resonance circuit, and a drive signal output circuit that outputs a drive signal for operating the power supply circuit in a burst mode when the state of the load is a light load, and outputs the drive signal for operating the power supply circuit in a normal mode when the state of the load is a heavy load. The drive signal output circuit changes from a first state in which the drive signal is output based on a predetermined condition immediately after the power supply circuit starts operating in the burst mode, to a third state in which the output of the drive signal is stopped, without passing through a second state in which the drive signal is output and the on-periods of the first and second transistors are gradually shortened.

[0007] An aspect of the power supply circuit according to the present invention for solving the above-described problems is a power supply circuit that generates an output voltage at a target level on the secondary side from an input voltage, including a transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors that control the current of the primary coil, a resonance circuit including the primary coil and a first capacitor, and a switching control circuit that controls the switching of the first and second transistors. The switching control circuit includes a load detection circuit that detects the state of the load of the power supply circuit based on the resonance current flowing through the resonance circuit, and a drive signal output circuit that outputs a drive signal for operating the power supply circuit in burst mode when the state of the load is a light load, and outputs the drive signal for operating the power supply circuit in normal mode when the state of the load is a heavy load. The drive signal output circuit changes from a first state in which the drive signal is output based on a predetermined condition immediately after the power supply circuit starts operating in burst mode, to a third state in which the output of the drive signal is stopped without passing through a second state in which the drive signal is output to gradually shorten the on-periods of the first and second transistors.

[0008] A second aspect of the switching control circuit according to the present invention for solving the above-described problems includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors for controlling the current of the primary coil, and a resonance circuit including the primary coil and a first capacitor, and is a switching control circuit for controlling the switching of the first and second transistors of a power supply circuit that generates an output voltage of a target level on the secondary side from an input voltage, and includes a drive signal output circuit that outputs a plurality of types of drive signals for driving the first and second transistors. The plurality of types of drive signals include a first drive signal output based on the polarity of the resonance current of the resonance circuit and a feedback voltage corresponding to the output voltage, a second drive signal output based on the timing at which the voltage of the auxiliary coil becomes any of a plurality of predetermined levels and a dead time, a third drive signal output so as to gradually shorten the on-periods of the first and second transistors, and a fourth drive signal output so as to stop driving the first and second transistors. The drive signal output circuit operates in a first pattern in which, after outputting the first drive signal, after outputting the second drive signal, without outputting the third drive signal, outputs the fourth drive signal, and then operates in a second pattern in which the second drive signal, the third drive signal, and the fourth drive signal are output in this order.

Advantages of the Invention

[0009] According to the present invention, it is possible to provide a switching control circuit capable of suppressing an overvoltage of the output voltage when shifting from the "normal mode" to the "burst mode".

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Embodiments for Carrying Out the Invention

[0011] From the description of this specification and the accompanying drawings, at least the following matters become clear. =====This Embodiment===== <<<Overview of the Switching Power Supply Circuit 10>>> FIG. 1 is a diagram showing an example of the configuration of a switching power supply circuit 10 according to an embodiment of the present invention. The switching power supply circuit 10 is an LLC current resonance type power supply circuit that generates an output voltage Vout at a target level for a load 11 from a predetermined input voltage Vin.

[0012] The switching power supply circuit 10 includes capacitors 20, 21, 22, 32, resistor 23, NMOS transistors 24, 25, transformer 26, control block 27, diodes 30, 31, constant voltage circuit 33, light emitting diode 34, and resistors 35, 36.

[0013] Capacitor 20 stabilizes the voltage between the power line to which the input voltage Vin is applied and the ground line on the ground side, and removes noise and the like. The input voltage Vin is a DC voltage of a predetermined level. Capacitor 21 is a so-called resonance capacitor that forms a resonance circuit with the leakage inductance (leakage inductance) between the primary coil L1 and the secondary coils L2, L3. Capacitor 21 corresponds to the "first capacitor".

[0014] Capacitor 22 and resistor 23 form a detection circuit that shunts and detects the resonance current Icr flowing through capacitor 21, and the serially connected capacitor 22 and resistor 23 are connected in parallel to capacitor 21.

[0015] Also, resistor 23 generates a voltage Vis based on the current that shunts the resonance current Icr. Therefore, the voltage Vis is a voltage corresponding to the resonance current Icr. When the resonance current Icr flows in the direction of the arrow shown in FIG. 1, the resonance current Icr is referred to as a positive resonance current Icr, and the voltage Vis in this case is assumed to be a positive voltage. Also, when the resonance current Icr flows in the direction of the arrow, that is, when the resonance current Icr flows in the order of the primary coil L1, capacitor 22, and resistor 23, the direction of the resonance current Icr is positive. Also, when the resonance current Icr flows in the direction opposite to the direction of the arrow, that is, when the resonance current Icr flows in the order of resistor 23, capacitor 22, and primary coil L1, the direction of the resonance current Icr is negative.

[0016] The NMOS transistor 24 is a high-side power transistor, and the NMOS transistor 25 is a low-side power transistor. Specifically, the NMOS transistors 24 and 25 are connected in series between a node to which the input voltage Vin is applied and a node to which the ground voltage is applied. In this embodiment, the NMOS transistors 24 and 25 are used as switching elements, but for example, PMOS transistors or bipolar transistors may also be used. Also, the NMOS transistor 24 corresponds to the "first transistor", and the NMOS transistor 25 corresponds to the "second transistor".

[0017] The transformer 26 includes a primary coil L1, secondary coils L2 and L3, and an auxiliary coil La, and insulation is provided between the primary coil L1, the secondary coils L2 and L3, and the auxiliary coil La. In the transformer 26, voltages are generated in the secondary coils L2 and L3 and the auxiliary coil La in response to changes in the voltage across both ends of the primary coil L1 on the primary side.

[0018] Also, one end of the primary coil L1 is connected to the source of the NMOS transistor 24 and the drain of the NMOS transistor 25, and the other end is connected to the source of the NMOS transistor 25 via a capacitor 21.

[0019] Therefore, when the switching of the NMOS transistors 24 and 25 is started, the voltages of the secondary coils L2 and L3 and the auxiliary coil La will change. Note that the primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with opposite polarities, and the primary coil L1 and the auxiliary coil La are electromagnetically coupled with the same polarity.

[0020] The control block 27 is a circuit block for controlling the switching of the NMOS transistors 24 and 25, and details will be described later.

[0021] Diodes 30 and 31 rectify the voltages of the secondary coils L2 and L3, and capacitor 32 smoothes the rectified voltage. As a result, a smoothed output voltage Vout is generated across capacitor 32. Note that the output voltage Vout is a DC voltage at the target level.

[0022] The constant voltage circuit 33 is a circuit that generates a constant DC voltage and is configured using, for example, a shunt regulator.

[0023] The light-emitting diode 34 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 33, and together with the phototransistor 52 described later, forms a photocoupler. In this embodiment, as the level of the output voltage Vout increases, the intensity of the light from the light-emitting diode 34 increases.

[0024] Resistors 35 and 36 form a voltage-dividing circuit that divides the input voltage Vin, and a voltage Vbo is generated at the connection node of resistors 35 and 36.

[0025] <<<Control block 27>>> The control block 27 includes a control IC 40, a diode 50, capacitors 51, 53, and 54, a phototransistor 52, and resistors 55, 56, and 57. Note that the control IC 40 corresponds to a "switching control circuit".

[0026] The control IC 40 is an integrated circuit that controls the switching of NMOS transistors 24 and 25 and has terminals VCC, GND, FB, IS, CA, HO, LO, VS, BO, and VW.

[0027] Terminal VCC is a terminal to which a power supply voltage Vcc for operating the control IC40 is applied. The cathode of the diode 50 and the capacitor 51 with one end grounded are connected to the terminal VCC. Then, the capacitor 51 is charged by the voltage from the auxiliary coil La of the transformer 26 and becomes the voltage Vcc. Note that the control IC40 is activated by applying a divided voltage of the input voltage Vin obtained by rectifying the AC input through a terminal (not shown), and after being activated, it operates based on the power supply voltage Vcc.

[0028] Terminal GND is a terminal to which a ground voltage is applied, and is connected to, for example, the housing of a device in which the switching power supply circuit 10 is provided.

[0029] Terminal FB is a terminal at which a feedback voltage Vfb corresponding to the output voltage Vout is generated, and the phototransistor 52 and the capacitor 53 are connected. The phototransistor 52 allows a bias current I1 of a magnitude corresponding to the intensity of the light from the light-emitting diode 34 to flow from the terminal FB to the ground, and the capacitor 53 is provided to remove noise between the terminal FB and the ground. For this reason, the phototransistor 52 operates as a transistor that generates a sink current.

[0030] Terminal IS is a terminal for detecting the current value of the resonance current of the primary coil L1. Here, a voltage corresponding to the current value of the resonance current of the primary coil L1 is generated at the node to which the capacitor 22 and the resistor 23 are connected. For this reason, a voltage Vis corresponding to the current value of the resonance current of the primary coil L1 is applied to the terminal IS.

[0031] Terminal CA is a terminal to which a voltage Vca corresponding to the input power of the switching power supply circuit 10, which is generated based on the resonance current of the primary coil L1, is applied. Although details will be described later, the capacitor 54 and the resistor 55 are connected to the terminal CA.

[0032] Terminal HO is a terminal at which a drive voltage Vdr1 for driving the NMOS transistor 24 is output, and the gate of the NMOS transistor 24 is connected.

[0033] Terminal LO is a terminal from which a driving voltage Vdr2 for driving the NMOS transistor 25 is output, and the gate of the NMOS transistor 25 is connected thereto.

[0034] Terminal VS is a terminal to which the voltage of a connection node where the source terminal of the NMOS transistor 24 and the drain terminal of the NMOS transistor 25 are connected is applied. When the NMOS transistor 24 is turned on, the input voltage Vin is applied, and when the NMOS transistor 25 is turned on, the ground voltage is applied.

[0035] Also, the potential of the voltage Vs at terminal VS becomes the reference potential of the output voltage of a bootstrap circuit (not shown) for turning on the NMOS transistor 24 when the input voltage Vin is applied to terminal VS.

[0036] Terminal BO is a terminal to which a voltage Vbo generated by resistors 35 and 36 is applied.

[0037] Terminal VW is a terminal to which Vvw obtained by dividing the voltage of the auxiliary coil La by resistors 56 and 57 is applied.

[0038] <<<Details of control IC40>>> FIG. 2 is a diagram showing an example of the control IC40. The control IC40 is an integrated circuit that drives the NMOS transistors 24 and 25 based on states that transition according to the voltages applied to the respective terminals. The control IC40 includes a resistor 100, a hysteresis comparator 101, analog-to-digital conversion circuits (ADCs) 102, 103, 108, level shift circuits (LSs) 104, 106, a comparison circuit (CMP) 105, a comparator 107, a load detection circuit 109, a drive signal output circuit 110, and a drive circuit (DRV) 111. Here, the terminals VCC and GND are omitted for convenience.

[0039] The resistor 100 generates a feedback voltage Vfb based on the bias current I1 from the phototransistor 52. Note that a predetermined voltage Vdd is applied to one end of the resistor 100, and the other end is connected to the terminal FB. Therefore, if the resistance value of the resistor 100 is “R”, the feedback voltage Vfb generated at the terminal FB is represented by Equation (1).

[0040] Vfb = Vdd - R×I1 ···(1) As described above, in this embodiment, the current value of the bias current I1 increases in response to an increase in the output voltage Vout. Therefore, when the output voltage Vout increases, the feedback voltage Vfb will decrease.

[0041] The hysteresis comparator 101 is used when operating in an operation mode (i.e., “burst mode”) that intermittently drives the NMOS transistors 24, 25, and detects whether the feedback voltage Vfb is high. The hysteresis comparator 101 also compares the feedback voltage Vfb with a reference voltage Vref0_h generated from the reference voltage Vref0 and a reference voltage Vref_l lower than the reference voltage Vref0_h.

[0042] Specifically, when the output voltage Vout decreases and the feedback voltage Vfb exceeds the reference voltage Vref0_h, the hysteresis comparator 101 outputs a high-level (hereinafter referred to as “H” level) signal Sfb. On the other hand, when the output voltage Vout increases and the feedback voltage Vfb falls below the reference voltage Vref0_l, the hysteresis comparator 101 outputs a low-level (hereinafter referred to as “L” level) signal Sfb.

[0043] The analog-to-digital conversion circuit (ADC) 102 converts the feedback voltage Vfb at the terminal FB into a digital value and outputs it. The feedback voltage Vfb converted into a digital value is used by the drive signal output circuit 110 (described later) to output drive signals hо, lо (described later) in an operation mode (i.e., “normal mode”) that continuously drives at least the NMOS transistors 24, 25.

[0044] The analog-digital conversion circuit (ADC) 103 converts the voltage Vbo at the terminal BO into a digital value and outputs it. The voltage Vbo converted into a digital value is used by the drive signal output circuit 110 (described later) to output drive signals ho, lo (described later) at least in so-called soft start and soft end.

[0045] The level shift circuit (LS) 104 level-shifts the voltage Vvw.

[0046] The comparison circuit (CMP) 105 compares the level-shifted voltage Vvw with threshold values Thvw_h and Thvw_l corresponding to the voltage Vbo, and outputs pulse signals LOvwth and HOvwth. Specifically, when the level-shifted voltage Vvw becomes smaller than the threshold value Thvw_h, the comparison circuit 105 outputs a pulse signal HOvwth for turning off the NMOS transistor 24. On the other hand, when the level-shifted voltage Vvw becomes larger than the threshold value Thvw_l, the comparison circuit 105 outputs a pulse signal LOvwth for turning off the NMOS transistor 25. Note that the pulse signals HOvwth and LOvwth correspond to the "comparison result".

[0047] The level shift circuit (LS) 106 level-shifts the voltage Vis.

[0048] The comparator 107 detects the polarity of the resonance current Icr by comparing the level-shifted voltage Vis with the reference voltage Vref1, and outputs a signal Szero. Note that the reference voltage Vref1 is equal to the voltage obtained by level-shifting the voltage Vis when the resonance current Icr becomes zero. Also, the comparator 107 detects the timing when the resonance current Icr becomes zero, and the timing at which the logic level of the signal Szero changes is the timing when the resonance current Icr becomes zero. Note that the comparator 107 corresponds to the "detection circuit", and the signal Szero corresponds to the "detection result".

[0049] The analog-to-digital conversion circuit (ADC) 108 converts the voltage Vca at terminal CA into a digital value and outputs it. The voltage Vca converted into a digital value is used when the drive signal output circuit 110 (described later) switches between the "normal mode" and the "burst mode".

[0050] The load detection circuit 109 detects whether the state of the load 11 is a light load or a heavy load based on the voltage applied to terminal IS (in other words, the voltage Vis corresponding to the resonance current flowing through the resonance circuit) according to the power consumption of the load 11. Here, the power consumption of the load 11 is greater when the state of the load 11 is a heavy load than when it is a light load. Therefore, since the voltage Vis applied to terminal IS indicates a voltage corresponding to the power consumption of the load 11, when the voltage Vis is lower than a predetermined value, the load detection circuit 109 outputs a voltage Vca indicating that the state of the load 11 is a light load.

[0051] On the other hand, when the voltage Vis is higher than a predetermined value, the load detection circuit 109 outputs a voltage Vca indicating that the state of the load 11 is a heavy load. Note that the voltage Vca becomes higher as the state of the load 11 is a heavier load.

[0052] Note that "the state of the load 11 is a heavy load" refers to, for example, the case where the current value of the load current Iout flowing through the load 11 is equal to or greater than a predetermined value (for example, 1 A). Also, "the state of the load 11 is a light load" refers to, for example, the case where the current value of the load current Iout flowing through the load 11 is less than a predetermined value (for example, 1 A). Also, "the state of the load 11 is a no-load" refers to the case where the current value of the load current Iout flowing through the load 11 is extremely small or 0 (zero) A. Also, although the current value of the load current Iout for determining whether the state of the load 11 is a heavy load or a light load is described as 1 A, for example, this current value can be set variously.

[0053] The drive signal output circuit 110 outputs drive signals hо and lо based on a plurality of signals such as signal Sfb and digital values. Specifically, although details will be described later, the drive signal output circuit 110 outputs drive signals hо and lо that cause the switching power supply circuit 10 to operate in the "burst mode" when the load 11 is in a light load state. On the other hand, the drive signal output circuit 110 outputs drive signals hо and lо that cause the switching power supply circuit 10 to operate in the "normal mode" when the load 11 is in a heavy load state.

[0054] The drive circuit (DRV) 111 outputs drive voltages Vdr1 and Vdr2 for driving the NMOS transistors 24 and 25 in FIG. 1, respectively. Specifically, when the drive signal output circuit 110 outputs a drive signal hо at the "H" level, the drive circuit 111 outputs a drive voltage Vdr1 that turns on the NMOS transistor 24, and when the drive signal output circuit 110 outputs a drive signal hо at the "L" level, the drive circuit 111 outputs a drive voltage Vdr1 that turns off the NMOS transistor 24. Also, when the drive signal output circuit 110 outputs a drive signal lо at the "H" level, the drive circuit 111 outputs a drive voltage Vdr2 that turns on the NMOS transistor 25, and when the drive signal output circuit 110 outputs a drive signal lо at the "L" level, the drive circuit 111 outputs a drive voltage Vdr2 that turns off the NMOS transistor 25.

[0055] ===State Transition of Drive Signal Output Circuit 110=== FIG. 3 is a diagram showing the state transition of the drive signal output circuit 110. Note that since FIG. 3 shows how the state of the drive signal output circuit 110 transitions, how the drive signal output circuit 110 outputs the drive signals hо and lо in each state will be described later. Also, "State 1" to "State 4" indicate the respective states of the drive signal output circuit 110 when the switching power supply circuit 10 operates in the "burst mode". First, it is assumed that the control IC 40 is operating the switching power supply circuit 10 in the "normal mode".

[0056] In the "normal mode", when the state of the load 11 becomes a light load and the voltage Vca becomes lower than the threshold value Vca_l and a predetermined period Ta has elapsed, the state of the drive signal output circuit 110 becomes "state 1", which is a state during the transition from the "normal mode" to the "burst mode" (process S10).

[0057] Although details will be described later, "state 1" is a state in which the drive signal output circuit 110 outputs drive signals ho, lo based on the voltage Vvw (that is, peak power control is performed). Also, immediately after the operation of the switching power supply circuit 10 is shifted from the "normal mode" to the "burst mode", the state of the drive signal output circuit 110 becomes "state 3" without passing through "state 2" (described later) from "state 1".

[0058] On the other hand, when the switching power supply circuit 10 operates in the "burst mode" except immediately after the operation of the switching power supply circuit 10 starts in the "burst mode", the state of the drive signal output circuit 110 repeats the transition from "state 3" to "state 4" (described later), passing through "state 1" and then to "state 2".

[0059] In this way, by changing the state transition path from "state 1" to "state 4" immediately after the transition from the "normal mode" to "state 1" and in other cases, it is possible to suppress the output voltage Vout from becoming an overvoltage until the state of the drive signal output circuit 110 becomes "state 3".

[0060] Returning to FIG. 3, in "state 1", immediately after the transition from the "normal mode", when the state of the load 11 becomes a light load and the output voltage Vout rises and the feedback voltage Vfb becomes lower than the reference voltage Vref0_l, the state of the drive signal output circuit 110 becomes "state 3" without passing through "state 2" (described later) from "state 1" (process S20).

[0061] "State 3" is a state in which the driving of the NMOS transistors 24 and 25 in FIG. 1 is stopped. In "State 3", when the state of the load 11 becomes a heavy load and the output voltage Vout decreases and the feedback voltage Vfb becomes higher than the reference voltage Vref0_h which is higher than the reference voltage Vref0_l, the state of the drive signal output circuit 110 changes from "State 3" to "State 4" (process S21). Although details will be described later, in this embodiment, in order to suppress the increase in the output voltage Vout, immediately after shifting the operation of the switching power supply circuit 10 to the "burst mode", the state of the drive signal output circuit 110 changes from "State 1" to "State 3", and the soft end operation is not performed.

[0062] "State 4" is a state in which drive signals hо, lо that gradually increase the on-period of the NMOS transistors 24 and 25 are output (so-called soft start operation). When the soft start period is completed in "State 4", the state of the drive signal output circuit 110 changes from "State 4" to "State 1" (process S22).

[0063] So far, the operation immediately after the transition from the "normal mode" to the "burst mode" has been described. On the other hand, after the state of the drive signal output circuit 110 becomes "State 3" immediately after the switching power supply circuit 10 starts operating in the "burst mode", in order to drive the NMOS transistors 24 and 25 intermittently, the state of the drive signal output circuit 110 will repeat from "State 1" to "State 4".

[0064] Also, when the state of the drive signal output circuit 110 is in "State 1" other than immediately after the transition to the "burst mode", if the output voltage Vout increases and the feedback voltage Vfb becomes lower than the reference voltage Vref0_l, the state of the drive signal output circuit 110 changes from "State 1" to "State 2" (process S23).

[0065] "State 2" is a state in which drive signals ho, lo that gradually shorten the on-periods of NMOS transistors 24, 25 are output (so-called soft-end operation). Then, in "State 2", when the soft-end period is completed, the state of the drive signal output circuit 110 changes from "State 2" to "State 3" (process S24).

[0066] In this way, when the switching power supply circuit 10 continues to operate in "burst mode", the state of the drive signal output circuit 110 repeats changing from "State 3", through "State 4" and "State 1", to "State 2". Thereby, when driving the NMOS transistors 24, 25 in FIG. 1 in "burst mode", the buzzing sound in the transformer 26 in FIG. 1 can be suppressed.

[0067] Also, in "State 1", when the state of the load 11 becomes a heavy load and the voltage Vca becomes higher than the threshold value Vca_h, the state of the drive signal output circuit 110 changes from "State 1" during "burst mode" to "normal mode" so as to operate the switching power supply circuit 10 in "normal mode" (process S11). Note that "State 1" corresponds to "First State", "State 2" corresponds to "Second State", "State 3" corresponds to "Third State", and "State 4" corresponds to "Fourth State".

[0068] ===Output method of drive signals ho, lo in "normal mode"=== FIG. 4 is a diagram showing a drive pattern in "normal mode". When the switching power supply circuit 10 operates in "normal mode", as shown in FIG. 4, the drive signal output circuit 110 outputs drive signals ho, lo that continuously drive the NMOS transistors 24, 25 without intermittently stopping the switching operation.

[0069] ===Drive method in "normal mode"=== FIG. 5 is a diagram showing a driving method in the "normal mode". When the switching power supply circuit 10 operates in the "normal mode", the drive signal output circuit 110 outputs drive signals hо, lо in a driving method called phase ratio control. Note that "phase ratio control" is a driving method for controlling the switching of NMOS transistors 24 and 25 based on the direction (i.e., polarity) of the resonance current Icr and the feedback voltage Vfb.

[0070] Hereinafter, with reference to FIG. 5, a specific driving method of phase ratio control will be described. In FIG. 5, as shown in FIG. 6, the drive signal output circuit 110 outputs a drive signal lо of "L" level and then outputs a drive signal hо of "H" level after the dead time Td has elapsed. Similarly, as shown in FIG. 6, the drive signal output circuit 110 outputs a drive signal hо of "L" level and then outputs a drive signal lо of "H" level after the dead time Td has elapsed. Note that the "dead time" is the time when both NMOS transistors 24 and 25 are turned off so that no through current flows between the node to which the input voltage Vin is applied and the node to which the ground voltage is applied.

[0071] At time t0, the drive signal output circuit 110 outputs a drive signal lо of "L" level. Then, the drive signal output circuit 110 starts measuring the time Tbh from time t0. Also, the drive signal output circuit 110 acquires the feedback voltage Vfb at time t0. Note that time t0 indicates the start of a half cycle.

[0072] At time t1, the resonance current Icr becomes zero, and the comparator 107 in FIG. 2 outputs a signal Szero of "H" level. At this time, the drive signal output circuit 110 ends the measurement of the time Tbh and calculates the time Tah until the end of the half cycle based on the previously acquired feedback voltage Vfb and the time Tbh.

[0073] At time t2 when a time Tah has elapsed since time t1, as shown in FIG. 6, the drive signal output circuit 110 outputs a drive signal hо at the "L" level. Then, the drive signal output circuit 110 starts measuring a time Tbl from time t2, and the drive signal output circuit 110 acquires a feedback voltage Vfb at time t2. Note that time t2 indicates the start of a half cycle.

[0074] At time t3, the resonance current Icr becomes zero, and the comparator 107 outputs a signal Szero at the "L" level. At this time, the drive signal output circuit 110 ends the measurement of the time Tbl, and calculates a time Tal until the end of the half cycle based on the previously acquired feedback voltage Vfb and the time Tbl.

[0075] At time t4 when a time Tal has elapsed since time t3, as shown in FIG. 6, the drive signal output circuit 110 outputs a drive signal lо at the "L" level. Thereafter, the same operation is repeated.

[0076] As described above, the drive signal output circuit 110 calculates the end time of the half cycle based on, for example, a period Tbh measured from the time when the drive signal lо at the "L" level is output and the feedback voltage Vfb when the drive signal lо at the "L" level is output. That is, the drive signal output circuit 110 controls, for example, the ratio of the period Tbh to the period Tah (i.e., the phase ratio) with the feedback voltage Vfb. By performing such control using the period Tbh and the feedback voltage Vfb that change according to the state of the load 11, the drive signal output circuit 110 can maintain the output voltage Vout at the target level while following the change in the state of the load 11. Note that the drive signals hо and lо output by the drive signal output circuit 110 according to the phase ratio control correspond to the "first drive signal".

[0077] ===Output method of drive signals hо and lо in "burst mode"=== FIG. 7 is a diagram showing a driving pattern in the "burst mode". When the switching power supply circuit 10 operates in the "burst mode", the drive signal output circuit 110 outputs drive signals hо and lо that drive the NMOS transistors 24 and 25 intermittently (i.e., during the switching operation period) while providing a stop operation period, as shown in FIG. 7. Also, the state of the drive signal output circuit 110 transitions in the order of "state 4", "state 1", "state 2" during the switching operation period, and becomes "state 3" in which the driving of the NMOS transistors 24 and 25 is stopped during the stop operation period. Note that the drive signals hо and lо output by the drive signal output circuit 110 in "state 3" correspond to the "fourth drive signal".

[0078] === Driving Method in "State 4" during "Burst Mode" === FIG. 8 is a diagram showing the driving method in "state 4". When the switching power supply circuit 10 operates in the "burst mode" and the state of the drive signal output circuit 110 becomes "state 4", the drive signal output circuit 110 outputs the drive signals hо and lо in a driving method called so-called soft start. Note that "soft start" is an operation in which, as shown in the enlarged view in FIG. 8, the drive signals hо and lо are output with an on-period that gradually becomes longer according to the change amount ΔONW every predetermined number of times N (for example, N = 2). Hereinafter, the soft start operation will be described with reference to FIG. 8.

[0079] At time t10, the state of the drive signal output circuit 110 becomes "state 4". Then, the drive signal output circuit 110 outputs a drive signal lо of "H" level.

[0080] At time t11 when a predetermined on-period has elapsed from time t10, the drive signal output circuit 110 outputs a drive signal lо of "L" level. After time t11, the drive signal output circuit 110 outputs the drive signal lо with an on-period that gradually becomes longer according to the change amount ΔONW every predetermined number of times N. Also, the drive signal output circuit 110 outputs a drive signal hо with the same on-period as the drive signal lо alternately with the drive signal lо.

[0081] After the time t12 when the drive signal output circuit 110 outputs the drive signal lо a predetermined number of times N from the time t11, the drive signal output circuit 110 increases the ON period of the drive signal lо by an amount of change ΔONW every predetermined number of times N and outputs the drive signal lо.

[0082] The same operation is repeated after the time t12. As a result, in the soft start, the drive signal output circuit 110 outputs drive signals hо and lо whose ON periods gradually become longer. Also, the predetermined number of times N is set to increase as the voltage Vbo increases, as shown by the solid line in FIG. 9, and the amount of change ΔONW is set to decrease as the voltage Vbo increases, as shown by the broken line in FIG. 9. Thus, the drive signal output circuit 110 operates so as to gradually increase the ON periods of the drive signals hо and lо as the voltage Vbo indicating the input voltage Vin is higher, reducing the influence of the input voltage Vin on the output voltage Vout. Note that the drive signals hо and lо output by the drive signal output circuit 110 according to the soft start operation correspond to the "fifth drive signal".

[0083] ===Drive method in "state 1" during "burst mode"=== FIG. 10 is a diagram showing the drive method in the "state 1". When the switching power supply circuit 10 operates in the "burst mode", when the state of the drive signal output circuit 110 becomes the "state 1", the drive signal output circuit 110 outputs the drive signals hо and lо in a drive method called so-called peak power control. Note that "peak power control" is a drive method for controlling the switching of the NMOS transistors 24 and 25 based on the voltage Vvw, the comparison result of the high / low threshold values, and the dead time Td.

[0084] Hereinafter, with reference to FIG. 10, the specific drive method of the peak power control will be described. It is assumed that before the time t20, the drive signal output circuit 110 outputs a drive signal hо at the "L" level and a drive signal lо at the "H" level.

[0085] At time t20 when the voltage Vvw becomes greater than the threshold Thvw_l, the comparison circuit 105 outputs a pulse signal LOvwth. When the pulse signal LOvwth is input as shown in FIG. 11, the drive signal output circuit 110 outputs a drive signal lо at the "L" level.

[0086] At time t21 when the dead time Td has elapsed from time t20, the drive signal output circuit 110 outputs a drive signal hо at the "H" level as shown in FIG. 11.

[0087] At time t22 when the voltage Vvw becomes less than the threshold Thvw_h, the comparison circuit 105 outputs a pulse signal HOvwth. When the pulse signal HOvwth is input as shown in FIG. 11, the drive signal output circuit 110 outputs a drive signal hо at the "L" level.

[0088] At time t23 when the dead time Td has elapsed from time t22, the drive signal output circuit 110 outputs a drive signal lо at the "H" level as shown in FIG. 11.

[0089] At time t24 when the voltage Vvw becomes greater than the threshold Thvw_l, the comparison circuit 105 outputs a pulse signal LOvwth. When the pulse signal LOvwth is input as shown in FIG. 11, the drive signal output circuit 110 outputs a drive signal lо at the "L" level. Thereafter, the same operation is repeated.

[0090] Also, as shown by the solid line in FIG. 12, the threshold Thvw_h is set to increase as the voltage Vbo increases. On the other hand, as shown by the broken line in FIG. 12, the threshold Thvw_l is set to decrease as the voltage Vbo increases. Therefore, when the voltage Vbo increases, the drive signal output circuit 110 shortens the on-periods of the drive signals hо and lо, reducing the influence of the input voltage Vin on the output voltage Vout. Note that the pulse signals HOvwth and LOvwth correspond to the "predetermined conditions". Also, the drive signals hо and lо output by the drive signal output circuit 110 according to the peak power control correspond to the "second drive signals".

[0091] ===Drive method in "State 2" during "burst mode"=== FIG. 13 is a diagram showing the drive method in "State 2". When the switching power supply circuit 10 operates in "burst mode", when the state of the drive signal output circuit 110 becomes "State 2", the drive signal output circuit 110 outputs drive signals hо, lо in a drive method called a so-called soft end. Note that the "soft end" is an operation of outputting the drive signals hо, lо with an on-period that gradually becomes shorter according to the change amount ΔONW every predetermined number of times N (for example, N = 2), as shown in the enlarged view in FIG. 13. Hereinafter, the soft end operation will be described with reference to FIG. 11.

[0092] At time t30 when the drive signal output circuit 110 outputs a drive signal hо of "L" level, the state of the drive signal output circuit 110 becomes "State 2".

[0093] At time t31 when the dead time Td has elapsed from time t30, the drive signal output circuit 110 outputs a drive signal lо of "H" level. Thereafter, the drive signal output circuit 110 outputs the drive signal lо with an on-period that gradually becomes shorter according to the change amount ΔONW every predetermined number of times N (for example, 2 times). In addition, the drive signal output circuit 110 outputs a drive signal hо having the same on-period as the drive signal lо alternately with the drive signal lо.

[0094] As a result, at the soft end, the drive signal output circuit 110 outputs drive signals hо,lо with a gradually decreasing on-period. Also, similar to the case of soft start, the predetermined number N is set to increase as the voltage Vbo increases, as shown by the solid line in FIG. 9, and the change amount ΔONW is set to decrease as the voltage Vbo increases, as shown by the dashed line in FIG. 9. Thereby, the drive signal output circuit 110 operates to gradually shorten the on-period of the drive signals hо,lо as the voltage Vbo indicating the input voltage Vin is higher, reducing the influence of the input voltage Vin on the output voltage Vout. Note that the drive signals hо,lо output by the drive signal output circuit 110 according to the soft end operation correspond to the "third drive signal", and the state transition of the drive signal output circuit 110 in the "burst mode" corresponds to the "second pattern".

[0095] ===Operation immediately after transition from "normal mode" to "burst mode"=== FIG. 14 is a diagram showing the operation waveform immediately after transition from the "normal mode" to the "burst mode".

[0096] When the state of the load 11 becomes a light load and the voltage Vca becomes lower than the threshold value Vca_l, and at time t40 when a predetermined period Ta has elapsed, the state of the drive signal output circuit 110 becomes "state 1" during the "burst mode" from the "normal mode".

[0097] At time t41 when the output voltage Vout rises and the feedback voltage Vfb becomes lower than the reference voltage Vref0_l, the hysteresis comparator 101 outputs a signal Sfb of "L" level. The state of the drive signal output circuit 110 to which the signal Sfb of "L" level is input becomes "state 3". Therefore, as a final process, the drive signal output circuit 110 outputs drive signals hо,lо having a predetermined on-period and then stops driving the NMOS transistors 24, 25. Note that the drive signals hо,lо output during the final process correspond to the "sixth drive signal".

[0098] Therefore, after the output voltage Vout rises to a certain extent and the feedback voltage Vfb falls below the reference voltage Vref0_l, the drive signal output circuit 110 stops driving the NMOS transistors 24 and 25. As a result, since the drive signal output circuit 110 does not perform a soft end, it is possible to suppress the output voltage Vout from becoming an overvoltage. Note that the state transition of the drive signal output circuit 110 immediately after the transition from the "normal mode" to the "burst mode" corresponds to the "first pattern".

[0099] ===Drive Pattern during the Switching Operation Period in "Burst Mode"=== FIG. 15 is a diagram showing the drive pattern during the switching operation period in the "burst mode".

[0100] At time t50 when the output voltage Vout decreases and the feedback voltage Vfb exceeds the reference voltage Vref0_h, and the hysteresis comparator 101 outputs a signal Sfb at the "H" level, the state of the drive signal output circuit 110 becomes the "state 4". Therefore, the drive signal output circuit 110 starts soft start, outputs the drive signal lo, and then outputs the drive signal ho. Also, the drive signal output circuit 110 gradually lengthens the on-periods of the NMOS transistors 24 and 25. However, until time t51, it is an invalid switching period, and no output current Iout flows through the secondary side of the transformer 26.

[0101] At time t52 when the soft start is completed, the state of the drive signal output circuit 110 becomes the "state 1". Therefore, the drive signal output circuit 110 performs peak power control and outputs the drive signals ho and lo according to the timing determined by the voltage Vvw.

[0102] At time t53 when the output voltage Vout rises and the feedback voltage Vfb falls below the reference voltage Vref0_l, and the hysteresis comparator 101 outputs a signal Sfb at the "L" level, the state of the drive signal output circuit 110 becomes the "state 2". Therefore, the drive signal output circuit 110 starts a soft end and outputs the drive signals ho and lo that gradually become shorter.

[0103] Also, similar to the case of soft start, when the on-periods of the drive signals hо and lо become short, for example, after time t54, it becomes an invalid switching period, and no output current Iout flows through the secondary side of the transformer 26.

[0104] Then, when the soft end is completed, the state of the drive signal output circuit 110 becomes "state 3", and the drive signal output circuit 110 stops driving the NMOS transistors 24 and 25.

[0105] ===Comparative Example=== As described above, this embodiment has been explained. FIG. 16 is a diagram showing the operation waveform of a comparative example immediately after shifting from the "normal mode" to the "burst mode". In the comparative example, when the switching power supply circuit 10 is operated by switching from the "normal mode" to the "burst mode", the state of the drive signal output circuit 110 becomes the "state 3" in which the driving of the NMOS transistors 24 and 25 is stopped via the "state 1" and the "state 2". Since the times t60 and t61 in FIG. 17 are the same as the times t40 and t41 in FIG. 14, the description thereof is omitted.

[0106] From time t61 to the time t62 when the soft end ends, the drive signal output circuit 110 outputs drive signals hо and lо whose on-periods gradually become shorter. In this case, since the state of the load 11 is a light load, the switching power supply circuit 10 is operating in the "burst mode", but depending on the state of the load 11, the output voltage Vout may increase due to the soft end operation and become an overvoltage. After t62, the state of the drive signal output circuit 110 becomes "state 3", and since the drive signal output circuit 110 stops driving the NMOS transistors 24 and 25, the output voltage Vout gradually decreases and the feedback voltage Vfb gradually increases.

[0107] Thus, unlike the case of this embodiment, in the comparative example, before the state of the drive signal output circuit 110 becomes "state 3", it passes through the "state 2" in which the soft end is performed, so there is a possibility that the output voltage Vout becomes an overvoltage.

[0108] ===Summary=== As described above, the switching power supply circuit 10 of this embodiment has been explained. The control IC 40 includes a load detection circuit 109 and a drive signal output circuit 110. The drive signal output circuit 110 operates such that the state of the drive signal output circuit 110 becomes "state 3" directly from "state 1" without passing through "state 2" immediately after the operation mode transitions so that the switching power supply circuit 10 operates in the "burst mode" from the "normal mode". Thereby, a switching control circuit can be provided that can suppress the output voltage from becoming overvoltage when transitioning from the "normal mode" to the "burst mode".

[0109] Also, when the switching power supply circuit 10 operates in the "burst mode", the drive signal output circuit 110 repeatedly transitions the state of the drive signal output circuit 110 in the order of "state 3", "state 4", "state 1", "state 2", "state 3". Thereby, when intermittently driving the NMOS transistors 24, 25, the ringing of the transformer 26 can be prevented.

[0110] Also, the control IC 40 includes a comparator 107 and a comparison circuit 105. Thereby, when the switching power supply circuit 10 operates in the "normal mode", the control IC 40 can drive the NMOS transistors 24, 25 by performing phase ratio control. On the other hand, when the state of the drive signal output circuit 110 is "state 1", the control IC 40 can drive the NMOS transistors 24, 25 by performing peak power control.

[0111] Also, in the drive signal output circuit 110, when the input voltage Vin increases (i.e., the voltage Vbo increases) in "state 2", the change amount ΔONW of the on-period of the drive signals hо, lо is made smaller. Thereby, the influence of the input voltage Vin on the output voltage Vout can be reduced.

[0112] Also, when the input voltage Vin increases (i.e., the voltage Vbo increases) in the "State 4", the drive signal output circuit 110 reduces the change amount ΔONW of the on-period of the drive signals hо, lо. Thereby, the influence of the input voltage Vin on the output voltage Vout can be reduced.

[0113] Further, the control IC40 includes a load detection circuit 109 and a drive signal output circuit 110. When the switching power supply circuit 10 operates in the "burst mode", the drive signal output circuit 110 repeatedly transitions the state of the drive signal output circuit 110 in the order of "State 3", "State 4", "State 1", "State 2", "State 3". And when the input voltage Vin increases (i.e., the voltage Vbo increases) in each of the "State 2" and "State 4", the drive signal output circuit 110 reduces the change amount ΔONW of the on-period of the drive signals hо, lо. Thereby, the influence of the input voltage Vin on the output voltage Vout can be reduced.

[0114] Further, the control IC40 includes a drive signal output circuit 110. After the drive signal output circuit 110 outputs the drive signals hо, lо so as to operate in a pattern in which the state of the drive signal output circuit 110 transitions from "State 1" to "State 3" without passing through "State 2", it outputs the drive signals hо, lо so as to operate in a pattern in which the state of the drive signal output circuit 110 transitions from "State 1" to "State 3" via "State 2". Thereby, a switching control circuit can be provided that can suppress the output voltage from becoming an overvoltage when transitioning from the "normal mode" to the "burst mode".

[0115] Further, the control IC40 includes a load detection circuit 109. After the state of the load 11 changes from a heavy load to a light load, the drive signal output circuit 110 outputs the drive signals hо, lо as the state of the drive signal output circuit 110 transitions from "State 1" to "State 3" without passing through "State 2". Thereby, it is possible to suppress the output voltage from becoming an overvoltage according to the state of the load 11.

[0116] Further, when the state of the load 11 is a heavy load, the drive signal output circuit 110 drives the NMOS transistors 24 and 25 in the "normal mode". When the state of the load 11 is a light load, the state of the drive signal output circuit 110 repeatedly transitions in the order of "state 1", "state 2", "state 3", and "state 4", and outputs the drive signals ho and lo. Thereby, the control IC 40 can output appropriate drive signals ho and lo according to the state of the load 11.

[0117] Also, when transitioning from "state 1" to "state 3", the drive signal output circuit 110 outputs drive signals ho and lo having a predetermined on period and then outputs drive signals ho and lo that stop driving the NMOS transistors 24 and 25. Thereby, the influence on the output voltage Vout when outputting the drive signals ho and lo that stop driving the NMOS transistors 24 and 25 is reduced.

[0118] The above embodiments are for facilitating the understanding of the present invention and are not for limiting and interpreting the present invention. Further, the present invention can be changed and improved without departing from its gist, and it goes without saying that the present invention includes equivalents thereof.

Explanation of Reference Numerals

[0119] 10 Switching power supply circuit 11 Load 20, 21, 22, 32, 51, 53, 54 Capacitor 23, 35, 36, 55, 56, 57, 100 Resistor 24, 25 NMOS transistor 26 Transformer 27 Control block 30, 31, 50 Diode 33 Constant voltage circuit 34 Light-emitting diode 40 Control IC 52 Phototransistor 101 Hysteresis comparator 102, 103, 108 Analog-to-digital conversion circuit 104, 106 Level shift circuits 105 Comparison circuit 107 Comparator 109 Load detection circuit 110 Drive signal output circuit 111 Drive circuit

Claims

1. A power supply circuit including a transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors for controlling a current of the primary coil, and a resonance circuit including the primary coil and a first capacitor, and generating an output voltage of a target level from an input voltage on a secondary side, and a switching control circuit for controlling switching of the first and second transistors, a load detection circuit for detecting a state of a load of the power supply circuit based on a resonance current flowing through the resonance circuit, a drive signal output circuit for outputting a drive signal for operating the power supply circuit in a burst mode when the state of the load is a light load, and outputting the drive signal for operating the power supply circuit in a normal mode when the state of the load is a heavy load, comprising: the drive signal output circuit from a first state of outputting the drive signal based on a predetermined condition immediately after the power supply circuit starts operating in the burst mode, to a third state of stopping output of the drive signal without passing through a second state of outputting the drive signal for gradually shortening an on-period of the first and second transistors, a switching control circuit.

2. The switching control circuit according to claim 1, wherein the drive signal output circuit repeats an operation of transitioning to the third state through a fourth state of outputting the drive signal for gradually lengthening an on-period of the first and second transistors, the first state, and the second state, after transitioning to the third state immediately after the power supply circuit starts operating in the burst mode. a switching control circuit.

3. The switching control circuit according to claim 2, a detection circuit for detecting a polarity of the resonance current, a comparison circuit for comparing magnitudes of each of a plurality of thresholds determined based on the input voltage and a voltage corresponding to a voltage of the auxiliary coil, comprising: the drive signal output circuit outputs the drive signal based on a detection result of the detection circuit and a feedback voltage corresponding to the output voltage when the power supply circuit is operating in the normal mode, outputs the drive signal based on the predetermined condition determined based on a comparison result of the comparison circuit when the power supply circuit is operating in the first state in the burst mode. a switching control circuit.

4. The switching control circuit according to claim 3, wherein the drive signal output circuit In the second state, when the input voltage increases, the amount of change in the on-period of the drive signal is reduced. A switching control circuit.

5. The switching control circuit according to claim 4, wherein the drive signal output circuit In the fourth state, when the input voltage increases, the amount of change in the on-period of the drive signal is reduced. A switching control circuit.

6. A switching control circuit that includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors that control the current of the primary coil, and a resonance circuit that includes the primary coil and a first capacitor, and controls the switching of the first and second transistors of the power supply circuit that generates an output voltage of a target level on the secondary side from an input voltage, a load detection circuit that detects the state of the load of the power supply circuit based on the resonance current flowing through the resonance circuit; a drive signal output circuit that outputs a drive signal for operating the power supply circuit in a burst mode when the state of the load is a light load, and outputs the drive signal for operating the power supply circuit in a normal mode when the state of the load is a heavy load; and the drive signal output circuit repeats an operation that becomes a first state in which the drive signal is output based on a predetermined condition after the power supply circuit starts operating in the burst mode, a second state in which the drive signal for gradually shortening the on-periods of the first and second transistors is output, a third state in which the output of the drive signal is stopped, and a fourth state in which the drive signal for gradually lengthening the on-periods of the first and second transistors is output, in each of the second and fourth states, when the input voltage increases, the amount of change in the on-period of the drive signal is reduced. A switching control circuit.

7. A power supply circuit that generates an output voltage of a target level on the secondary side from an input voltage, including a transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors that control the current of the primary coil, a resonance circuit that includes the primary coil and a first capacitor, and a switching control circuit that controls the switching of the first and second transistors, and the switching control circuit includes a load detection circuit that detects the state of the load of the power supply circuit based on the resonance current flowing through the resonance circuit, When the load state is a light load, it outputs a drive signal for operating the power supply circuit in burst mode, and when the load state is a heavy load, it outputs the drive signal for operating the power supply circuit in normal mode. A drive signal output circuit, including The drive signal output circuit Immediately after the power supply circuit starts operating in burst mode, from a first state of outputting the drive signal based on a predetermined condition, without passing through a second state of outputting the drive signal that gradually shortens the on periods of the first and second transistors, it becomes a third state of stopping the output of the drive signal. Power supply circuit.

8. A transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors for controlling the current of the primary coil, and a resonance circuit including the primary coil and a first capacitor, and a switching control circuit for controlling the switching of the first and second transistors of the power supply circuit that generates an output voltage at a target level on the secondary side from an input voltage, A drive signal output circuit that outputs a plurality of types of drive signals for driving the first and second transistors, comprising The plurality of types of drive signals include a first drive signal output based on the polarity of the resonance current of the resonance circuit and a feedback voltage corresponding to the output voltage, a second drive signal output based on the timing when the voltage of the auxiliary coil reaches any of a plurality of predetermined levels and a dead time, a third drive signal output to gradually shorten the on periods of the first and second transistors, and a fourth drive signal output to stop driving the first and second transistors. The drive signal output circuit After outputting the first drive signal, after outputting the second drive signal, without outputting the third drive signal, after operating in a first pattern of outputting the fourth drive signal, It operates in a second pattern of outputting the second drive signal, the third drive signal, and the fourth drive signal in that order. Switching control circuit.

9. The switching control circuit according to claim 8, A load detection circuit for detecting the state of the load of the power supply circuit based on the resonance current flowing through the resonance circuit, comprising The drive signal output circuit After the load state changes from a heavy load to a light load, it operates in the first pattern. Switching control circuit.

10. The switching control circuit according to claim 9, The plurality of types of drive signals further including a fifth driving signal output to gradually increase the on-periods of the first and second transistors; the driving signal output circuit; when the load is in a heavy load state, outputting the first driving signal; when the load is in a light load state, as the second pattern, sequentially and repeatedly outputting the second driving signal, the third driving signal, the fourth driving signal, and the fifth driving signal; a switching control circuit.

11. The switching control circuit according to claim 10, wherein the plurality of types of driving signals include a sixth driving signal having a predetermined on-period, and the driving signal output circuit as the first pattern, after outputting the first driving signal, outputting the second driving signal, then without outputting the third driving signal, outputting the sixth driving signal, and then outputting the fourth driving signal; a switching control circuit.

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