Semiconductor device

Abstract

To improve performance of a semiconductor device.SOLUTION: A dummy field structure part 100 is included in a non-element formation region R2. The dummy field structure part 100 includes: a deep type well 110; an n-type well 120; a trench STI; a conductor layer 150; a first n-type semiconductor region 140; a second n-type semiconductor region 130A; and a second n-type semiconductor region 130B. A semiconductor device includes not only a parasitic bipolar transistor Tr1, but also a parasitic bipolar transistor Tr2.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having an element formation region and a non-element formation region.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2017-117882 (Patent Document 1) describes a technique related to a semiconductor device having an active barrier structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, in a semiconductor device connected to a circuit including an inductor, a parasitic bipolar transistor may operate due to noise based on a back electromotive force. In this case, the operation of the parasitic bipolar transistor modulates the potential of the circuit. As a result, malfunction of the circuit may occur. Therefore, in order to suppress malfunction of the circuit, a technique for suppressing the operation of the parasitic bipolar transistor is desired.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to an embodiment has a dummy field structure formed in a non-element formation region. This dummy field structure functions as a collector of a parasitic bipolar transistor. The dummy field structure is formed in the non-element formation region and includes a stacked structure of n-type semiconductor regions to which a fixed potential is supplied.

Advantages of the Invention

[0007] According to one embodiment, the performance of the semiconductor device can be improved.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 8

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Figure 10

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Figure 12

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Figure 16

Modes for Carrying Out the Invention

[0009] In addition, in all the drawings for explaining the embodiments, the same members are basically denoted by the same reference numerals, and repeated explanations thereof are omitted. Note that, for ease of understanding of the drawings, hatching may be added even to a plan view.

[0010] Elements such as transistors are formed in the "element formation region" as referred to in this specification. That is, elements constituting a circuit are formed in the "element formation region". In addition, no elements such as transistors are formed in the "non-element formation region" as referred to in this specification. That is, no elements constituting a circuit are formed in the "non-element formation region".

[0011] <Configuration Example of Transistor> Hereinafter, among a plurality of types of transistors, a p-type LDMOSFET (Lateral Defused Metal Oxide Semiconductor Field Effect Transistor), an npn-type bipolar transistor, and a lateral pnp-type bipolar transistor are exemplified.

[0012] <<Configuration of p-Type LDMOSFET>> In FIG. 1, the semiconductor device includes a p-type semiconductor substrate SUB, an n-type buried layer NBL, an n-type well NW1, an n-type well NW2, a p-type offset region OR, a p-type well PW, an n-type semiconductor region NR, a source region SR, a drain region DR, a gate insulating film GOX, and a gate electrode GE. The semiconductor device also includes a deep trench DTI, a trench STI1, a trench STI2, an interlayer insulating film IL, a plug PLG1, a plug PLG2, a source wiring WL1, and a drain wiring WL2.

[0013] For example, boron (B) as an acceptor is introduced into the p semiconductor substrate SUB. The concentration of boron is, for example, 0.3×10 16 (1 / cm 3 ) or more and 2.0×10 16 (1 / cm 3)The following is the case.

[0014] As shown in FIG. 1, an n-type buried layer NBL is formed in a p-type semiconductor substrate SUB. An n-type well NW1 is formed on the n-type buried layer NBL. Note that the n-type well NW1 is formed in a p-type epitaxial layer. The n-type buried layer NBL may be formed in the p-type epitaxial layer. A deep trench DTI penetrates through the n-type well NW1 and the n-type buried layer NBL. Then, the deep trench DTI has a bottom surface in the p-type semiconductor substrate SUB. An insulating material such as silicon oxide is embedded inside the deep trench DTI.

[0015] Although not shown in FIG. 1, the deep trench DTI is formed so as to surround the element formation region R1A in plan view. In other words, the element formation region R1A is surrounded by the deep trench DTI in plan view.

[0016] An n-type well NW2 and a p-type offset region OR are formed in the n-type well NW1. As shown in FIG. 1, the n-type well NW2 and the p-type offset region OR are separated from each other. The n-type well NW2 is in contact with the deep trench DTI and the trench STI1. An insulating material such as silicon oxide is embedded inside the trench STI1. The bottom surface of the trench STI1 is located in the n-type well NW2.

[0017] An n-type semiconductor region NR and a source region SR are formed in the n-type well NW2. The n-type semiconductor region NR is in contact with the trench STI1 and the source region SR. The impurity concentration of the n-type semiconductor region NR is higher than the impurity concentration of the n-type well NW2. The source region SR is composed of a p-type semiconductor region.

[0018] As shown in FIG. 1, the p-type offset region OR includes the trench STI2. Inside the trench STI2, an insulating material such as silicon oxide is embedded, for example. The bottom surface of the trench STI2 is located within the p-type offset region OR or within the p-type well PW. A p-type well PW is formed within the p-type offset region OR. The p-type well PW is in contact with the trench STI. The impurity concentration of the p-type well PW is higher than that of the p-type offset region OR. A drain region DR is formed within the p-type well PW. The drain region DR is in contact with the deep trench DTI and the trench STI2. The impurity concentration of the drain region DR is higher than that of the p-type well PW. The drain region DR is composed of a p-type semiconductor region.

[0019] The source region SR is formed at a position shallower than the bottom surface of the trench STI1. Also, the drain region DR is formed at a position shallower than the bottom surface of the trench STI2.

[0020] A gate electrode GE is formed via a gate insulating film GOX on a part of the source region SR, a part of the n-type well NW2, a part of the n-type well NW1, a part of the p-type offset region OR, and a part of the trench STI2.

[0021] An interlayer insulating film IL is formed to cover the gate electrode GE on the deep trench DTI, the trench STI1, the trench STI2, the source region SR, and the drain region DR. The interlayer insulating film IL is composed of, for example, a silicon oxide film. As shown in FIG. 1, plugs PLG1 and PLG2 are formed within the interlayer insulating film IL.

[0022] The plug PLG1 penetrates the interlayer insulating film IL and is in contact with the source region SR and the n-type semiconductor region NR. That is, the plug PLG1 is electrically connected to the source region SR and the n-type semiconductor region NR. Also, the plug PLG2 penetrates the interlayer insulating film IL and is in contact with the drain region DR. That is, the plug PLG2 is electrically connected to the drain region DR.

[0023] On the interlayer insulating film IL, a source wiring WL1 and a drain wiring WL2 are formed. The source wiring WL1 is connected to the plug PLG1. Therefore, the source wiring WL1 is electrically connected to the source region SR and the n-type semiconductor region NR via the plug PLG1. Also, the drain wiring WL2 is connected to the plug PLG2. Therefore, the drain wiring WL2 is electrically connected to the drain region DR via the plug PLG2.

[0024] In this way, a semiconductor device including a p-type LDMOSFET is formed.

[0025] Note that the semiconductor device has a stacked structure portion 1A. The stacked structure portion 1A is shown as the region surrounded by the thick line in FIG. 1. The n-type buried layer NBL, the n-type well NW1, the n-type well NW2, and the n-type semiconductor region NR (n-type body contact region) constitute the stacked structure portion 1A. As will be described later, the stacked structure portion 1A constitutes a parasitic bipolar transistor. In this specification, attention is paid to the parasitic bipolar transistor that causes malfunction of the circuit. For this reason, the stacked structure portion 1A included in the p-type LDMOSFET is clearly shown.

[0026] <<Configuration of npn bipolar transistor>> In FIG. 2, the semiconductor device has a p-type semiconductor substrate SUB, an n-type buried layer NBL, an n-type well NW3, an n-type well NW4, an n-type well NW5, a p-type well PW1, a collector region CR, an emitter region ER, and a base region BR. The semiconductor device also has a deep trench DTI, a trench STI, an interlayer insulating film IL, a plug PLG3, a plug PLG4, a plug PLG5, a plug PLG6, a collector wiring WL3, an emitter wiring WL4, and a base wiring WL5.

[0027] As shown in FIG. 2, an n-type buried layer NBL is formed in the p-type semiconductor substrate SUB. An n-type well NW3 is formed on the n-type buried layer NBL. Note that the n-type well NW3 is formed in a p-type epitaxial layer. The n-type buried layer NBL may be formed in the p-type epitaxial layer. The deep trench DTI penetrates the n-type well NW3 and the n-type buried layer NBL. Then, the deep trench DTI has a bottom surface in the p-type semiconductor substrate SUB. An insulating material such as silicon oxide is embedded inside the deep trench DTI.

[0028] Although not shown in FIG. 2, the deep trench DTI is formed so as to surround the element formation region R1B in plan view. In other words, the element formation region R1B is surrounded by the deep trench DTI in plan view.

[0029] An n-type well NW4, a p-type well PW1, and an n-type well NW5 are formed in the n-type well NW3. The n-type well NW4, the p-type well PW1, and the n-type well NW5 are separated from each other. Also, the trench STI is surrounded by the deep trench DTI. An insulating material such as silicon oxide is embedded inside the trench STI. The bottom surface of the trench STI is located in the n-type well NW3, the n-type well NW4, the p-type well PW1, or the n-type well NW5.

[0030] In the n-type well NW4, a collector region CR is formed. The collector region CR is in contact with the trench STI. And the collector region CR is formed at a position shallower than the bottom surface of the trench STI. The collector region CR is composed of an n-type semiconductor region. The impurity concentration of the collector region CR is higher than that of the n-type well NW4.

[0031] In the p-type well PW1, an emitter region ER and a base region BR are formed. Each of the emitter region ER and the base region BR is in contact with the trench STI. And each of the emitter region ER and the base region BR is formed at a position shallower than the bottom surface of the trench STI. The emitter region ER is composed of an n-type semiconductor region. Also, the base region BR is composed of a p-type semiconductor region. The impurity concentration of the base region BR is higher than that of the p-type well PW1.

[0032] On the deep trench DTI, the trench STI, the collector region CR, the emitter region ER, and the base region BR, an interlayer insulating film IL is formed.

[0033] The interlayer insulating film IL is composed of, for example, a silicon oxide film. As shown in FIG. 2, in the interlayer insulating film IL, a plug PLG3, a plug PLG4, a plug POLG5, and a plug PLG6 are formed. The plug PLG3 penetrates the interlayer insulating film IL and is in contact with the collector region CR. That is, the plug PLG3 is electrically connected to the collector region CR. Also, each of the plug PLG4 and the plug PLG5 penetrates the interlayer insulating film IL and is in contact with the emitter region ER. That is, each of the plug PLG4 and the plug PLG5 is electrically connected to the emitter region ER. Further, the plug PLG6 penetrates the interlayer insulating film IL and is in contact with the base region BR. That is, the plug PLG6 is electrically connected to the base region BR.

[0034] On the interlayer insulating film IL, a collector wiring WL3, an emitter wiring WL4, and a base wiring WL5 are formed. The collector wiring WL3 is connected to the plug PLG3. Therefore, the collector wiring WL3 is electrically connected to the collector region CR via the plug PLG3. Also, the emitter wiring WL4 is connected to the plugs PLG4 and PLG5. Therefore, the emitter wiring WL4 is electrically connected to the emitter region ER via the plugs PLG4 and PLG5. Further, the base wiring WL5 is connected to the plug PLG6. Therefore, the base wiring WL5 is electrically connected to the base region BR via the plug PLG6.

[0035] In this way, a semiconductor device including an npn bipolar transistor is formed.

[0036] Note that the semiconductor device has a stacked structure portion 1B. The stacked structure portion 1B is shown as the region surrounded by a thick line in FIG. 2. The n-type buried layer NBL, the n-type well NW3, the n-type well NW4, and the collector region CR constitute the stacked structure portion 1B. As will be described later, the stacked structure portion 1B constitutes a parasitic bipolar transistor. In this specification, attention is paid to the parasitic bipolar transistor that causes a malfunction in the circuit operation. For this reason, the stacked structure portion 1B included in the npn bipolar transistor is clearly shown.

[0037] <<Configuration of Lateral pnp Bipolar Transistor>> In FIG. 3, the semiconductor device has a p-type semiconductor substrate SUB, an n-type buried layer NBL, an n-type well NW6, a p-type well PW2, an n-type well NW7, a p-type well PW3, an n-type well NW8, a p-type well PW4, a collector region CR1, a base region BR1, an emitter region ER1, a base region BR2, and a collector region CR2. The semiconductor device also has a deep trench DTI, a trench STI, an interlayer insulating film IL, a plug PLG7, a plug PLG8, a plug PLG9, a plug PLG10, a plug PLG11, a plug PLG12, a collector wiring WL6, a base wiring WL7, an emitter wiring WL8, a base wiring WL9, and a collector wiring WL10.

[0038] As shown in FIG. 3, an n-type buried layer NBL is formed in the p-type semiconductor substrate SUB. An n-type well NW6 is formed on the n-type buried layer NBL. Note that the n-type well NW6 is formed in a p-type epitaxial layer. The n-type buried layer NBL may be formed in the p-type epitaxial layer. The deep trench DTI penetrates the n-type well NW6 and the n-type buried layer NBL. The deep trench DTI has a bottom surface in the p-type semiconductor substrate SUB. An insulating material such as silicon oxide is embedded inside the deep trench DTI.

[0039] Although not shown in FIG. 3, the deep trench DTI is formed so as to surround the element formation region R1C in plan view. In other words, the element formation region R1C is surrounded by the deep trench DTI in plan view.

[0040] Inside the n-type well NW6, a p-type well PW2, an n-type well NW7, a p-type well PW3, an n-type well NW8, and a p-type well PW4 are formed. The p-type well PW2, the n-type well NW7, the p-type well PW3, the n-type well NW8, and the p-type well PW4 are in contact with each other. Also, the trench STI is surrounded by the deep trench DTI. Inside the trench STI, an insulating material such as silicon oxide is embedded, for example. The bottom surface of the trench STI is located inside the p-type well PW2, inside the n-type well NW7, inside the p-type well PW3, inside the n-type well NW8, or inside the p-type well PW4.

[0041] Inside the p-type well PW2, a collector region CR1 is formed. The collector region CR1 is in contact with the trench STI. And the collector region CR1 is formed at a position shallower than the bottom surface of the trench STI. The collector region CR1 is composed of a p-type semiconductor region. The impurity concentration of the collector region CR1 is higher than the impurity concentration of the p-type well PW2.

[0042] Inside the n-type well NW7, a base region BR1 is formed. The base region BR1 is in contact with the trench STI. And the base region BR1 is formed at a position shallower than the bottom surface of the trench STI. The base region BR1 is composed of an n-type semiconductor region. The impurity concentration of the base region BR1 is higher than the impurity concentration of the n-type well NW7.

[0043] Inside the p-type well PW3, an emitter region ER1 is formed. The emitter region ER1 is in contact with the trench STI. And the emitter region ER1 is formed at a position shallower than the bottom surface of the trench STI. The emitter region ER1 is composed of a p-type semiconductor region. The impurity concentration of the emitter region ER1 is higher than the impurity concentration of the p-type well PW3.

[0044] Inside the n-type well NW8, a base region BR2 is formed. The base region BR2 is in contact with the trench STI. And the base region BR2 is formed at a position shallower than the bottom surface of the trench STI. The base region BR2 is composed of an n-type semiconductor region. The impurity concentration of the base region BR2 is higher than that of the n-type well NW8.

[0045] Inside the p-type well PW4, a collector region CR2 is formed. The collector region CR2 is in contact with the trench STI. And the collector region CR2 is formed at a position shallower than the bottom surface of the trench STI. The collector region CR2 is composed of a p-type semiconductor region. The impurity concentration of the collector region CR2 is higher than that of the p-type well PW4.

[0046] On the deep trench DTI, the trench STI, the collector region CR1, the base region BR1, the emitter region ER1, the base region BR2, and the collector region CR2, an interlayer insulating film IL is formed.

[0047] The interlayer insulating film IL is composed of, for example, a silicon oxide film. As shown in Figure 3, inside the interlayer insulating film IL, plugs PLG7, PLG8, plug POLG9, plug PLG10, plug PLG11, and plug PLG12 are formed.

[0048] The plug PLG7 penetrates the interlayer insulating film IL and is in contact with the collector region CR1. That is, the plug PLG7 is electrically connected to the collector region CR1. The plug PLG8 penetrates the interlayer insulating film IL and is in contact with the base region BR1. That is, the plug PLG8 is electrically connected to the base region BR1. Each of the plug PLG9 and the plug PLG10 penetrates the interlayer insulating film IL and is in contact with the emitter region ER1. That is, each of the plug PLG9 and the plug PLG10 is electrically connected to the emitter region ER1. The plug PLG11 penetrates the interlayer insulating film IL and is in contact with the base region BR2. That is, the plug PLG11 is electrically connected to the base region BR2. The plug PLG12 penetrates the interlayer insulating film IL and is in contact with the collector region CR2. That is, the plug PLG12 is electrically connected to the collector region CR2.

[0049] On the interlayer insulating film IL, a collector wiring WL6, a base wiring WL7, an emitter wiring WL8, a base wiring WL9, and a collector wiring WL10 are formed.

[0050] The collector wiring WL6 is connected to the plug PLG7. Therefore, the collector wiring WL6 is electrically connected to the collector region CR1 via the plug PLG7. The base wiring WL7 is connected to the plug PLG8. Therefore, the base wiring WL7 is electrically connected to the base region BR1 via the plug PLG8. The emitter wiring WL8 is connected to each of the plug PLG9 and the plug PLG10. Therefore, the emitter wiring WL8 is electrically connected to the emitter region ER1 via each of the plug PLG9 and the plug PLG10. The base wiring WL9 is connected to the plug PLG11. Therefore, the base wiring WL9 is electrically connected to the base region BR2 via the plug PLG11. The collector wiring WL10 is connected to the plug PLG12. Therefore, the collector wiring WL10 is electrically connected to the collector region CR2 via the plug PLG12.

[0051] In this way, a semiconductor device including a lateral pnp bipolar transistor is formed.

[0052] Note that the semiconductor device has a stacked structure portion 1C. The stacked structure portion 1C is shown as a region surrounded by a thick line in FIG. 3. The n-type buried layer NBL, the n-type well NW6, the n-type well NW7, and the base region BR1 constitute the stacked structure portion 1C. As will be described later, the stacked structure portion 1C constitutes a parasitic bipolar transistor. In this specification, attention is paid to the parasitic bipolar transistor that causes malfunction of the circuit. For this reason, the stacked structure portion 1C included in the lateral pnp bipolar transistor is clearly shown.

[0053] <Structure of the stacked structure portion> The stacked structure portion 1A shown in FIG. 1, the stacked structure portion 1B shown in FIG. 2, and the stacked structure portion 1C shown in FIG. 3 have a common structure. In this specification, the common structure among the stacked structure portion 1A, the stacked structure portion 1B, and the stacked structure portion 1C is represented by the stacked structure portion 10. That is, in the following description of the specification, the stacked structure portion 10 is used to describe the present embodiment.

[0054] FIG. 4 shows a p-type semiconductor substrate SUB, a deep trench DTI, and a stacked structure portion 10. As shown in FIG. 4, the stacked structure portion 10 is formed on the p-type semiconductor substrate SUB. This stacked structure portion 10 is surrounded by the deep trench DTI.

[0055] The stacked structure portion 10 has an n-type buried layer 20, a deep n-type well 40, an n-type well 50, and an n-type diffusion layer 60. The n-type buried layer 20 is formed in the p-type semiconductor substrate SUB. A p-type epitaxial layer 30 is formed on the n-type buried layer 20. The n-type buried layer NBL may be formed in the p-type epitaxial layer 30.

[0056] A deep n-well 40, an n-well 50, and an n-diffusion layer 60 are formed in the p-type epitaxial layer 30. The n-well 50 is formed on the deep n-well 40. The n-diffusion layer 60 is formed on the n-well 50.

[0057] Here, the region surrounded by the deep trench DTI is the device formation region DFR. Specifically, in FIG. 4, the stacked structure portion 10 is shown in the device formation region DFR surrounded by the deep trench DTI. For example, the n-diffusion layer 60 of the stacked structure portion 10 corresponds to the n-type semiconductor region NR (n-type body contact region) of the stacked structure portion 1A, the collector region CR of the stacked structure portion 1B, or the base region BR1 of the stacked structure portion 1C.

[0058] In this specification, in order to focus on the stacked structure portion of the transistor formed in the device formation region, for example, in FIG. 4, the stacked structure portion 10 is shown in the device formation region DFR surrounded by the deep trench DTI.

[0059] <Description of the First Related Technology> In this specification, the "first related technology" is a technology that is not a known technology but has the problems found by the inventor and is the technology that is the premise of the present disclosure.

[0060] In FIG. 5, the semiconductor device in the first related technology includes a p-type semiconductor substrate SUB1, a p-type epitaxial layer EPI1, an n-type buried layer 20, a p-type epitaxial layer EPI2, a p-type well 70, deep trenches DTI1, DTI2, DTI3, a stacked structure portion 10A, a stacked structure portion 10B, and a GND structure portion 80.

[0061] As shown in FIG. 5, the semiconductor device has an element formation region DFR1, an element formation region DFR2, and a non-element formation region R2. The element formation region DFR1 is surrounded by a deep trench DTI1. A stacked structure portion 10A is formed within this element formation region DFR1. Also, the element formation region DFR2 is surrounded by a deep trench DTI2. A stacked structure portion 10B is formed within this element formation region DFR2.

[0062] The stacked structure portion 10A has an n-type embedded layer 20, a deep n-type well 40A, an n-type well 50A, and an n-type diffusion layer 60A. Also, the stacked structure portion 10B has an n-type embedded layer 20, a deep n-type well 40B, an n-type well 50B, and an n-type diffusion layer 60B.

[0063] The GND structure portion 80 is formed so as to be surrounded by a deep trench DTI3. As shown in FIG. 5, the GND structure portion 80 has a groove reaching from the upper surface S1 of the p-type epitaxial layer EPI2 to the p-type epitaxial layer EPI1, and a conductive material (for example, polysilicon) embedded in the groove. Thereby, a GND potential (0 V) can be supplied to the p-type epitaxial layer EPI1 and the p-type semiconductor substrate SUB1. That is, the GND structure portion 80 has a function of supplying a GND potential to the p-type semiconductor substrate SUB1.

[0064] Note that a deep n-type well 40A, a deep n-type well 40B, an n-type well 50A, an n-type well 50B, an n-type diffusion layer 60A, an n-type diffusion layer 60B, a p-type well 70, a deep trench DTI1, a deep trench DTI2, and a deep trench DTI3 are formed in the p-type epitaxial layer EPI2.

[0065] A p-type impurity (acceptor) is introduced into the p-type semiconductor substrate SUB1. For example, boron (B) as an acceptor is introduced into the p-type semiconductor substrate SUB1. The concentration of boron is, for example, 0.5×10 19 (1 / cm 3 ) or more and 4.0×10 19 (1 / cm 3)The above is the case.

[0066] <<Parasitic Bipolar Transistor>> For example, the stacked structure portion 10A is a component of a transistor formed within the element formation region DFR1. Here, consider the case where the semiconductor device is connected to a circuit including an inductor. In particular, consider the case where negative potential noise caused by the back electromotive force generated in the inductor is transmitted to the stacked structure portion 10A of the transistor.

[0067] In this case, negative potential noise is input to the stacked structure portion 10A. Also, a GND potential is supplied from the GND structure portion 80 to the p-type semiconductor substrate SUB1 and the p-type epitaxial layer EPI1. Therefore, when negative potential noise is input to the stacked structure portion 10A, the pn junction formed by the stacked structure portion 10A and the p-type epitaxial layer EPI1 is forward-biased. As a result, current flows from the p-type semiconductor substrate SUB1 through the p-type epitaxial layer EPI1 to the stacked structure portion 10A. In other words, electrons flow from the stacked structure portion 10A through the p-type epitaxial layer EPI1 to the p-type semiconductor substrate SUB1.

[0068] And, as shown in FIG. 5, the stacked structure portion 10A, the p-type semiconductor substrate SUB1, and the stacked structure portion 10B constitute a parasitic bipolar transistor Tr1 (npn-type bipolar transistor). The stacked structure portion 10A constitutes the emitter, the p-type semiconductor substrate SUB1 constitutes the base, and the stacked structure portion 10B constitutes the collector. For this reason, the emitter current flows from the p-type semiconductor substrate SUB1 to the stacked structure portion 10A. When the base-emitter voltage generated by this emitter current flowing through the base resistance exceeds a predetermined voltage, collector current flows from the stacked structure portion 10B through the p-type semiconductor substrate SUB1 to the stacked structure portion 10A. In other words, electrons flow to the stacked structure portion 10B. As a result, the potential of the circuit including the stacked structure portion 10B is modulated. For this reason, in the semiconductor device in the first related art, there is a possibility of causing a malfunction of the circuit.

[0069] The phenomenon in which such parasitic bipolar transistor Tr1 operates is called "substrate injection". And the ratio of the collector current to the emitter current (collector current / emitter current) of the parasitic bipolar transistor Tr1 is called "α". The smaller "α" is, the higher the performance of the semiconductor device. For example, the larger the distance D shown in FIG. 5, the smaller "α" becomes. However, a larger distance D means that the size of the semiconductor device becomes larger. Therefore, it is desired to reduce "α" while reducing the size of the semiconductor device.

[0070] <<Advantages of p-type semiconductor substrate SUB1>> In the first related art, a p-type semiconductor substrate SUB1 is used. Thereby, the first related art can suppress the above-described "substrate injection". The p-type semiconductor substrate SUB1 has a relatively high boron concentration. This means that the resistance value of the p-type semiconductor substrate SUB1 is low. That is, in the first related art, the base resistance can be lowered. From this, the base-emitter voltage generated by the current flowing through the base resistance is unlikely to increase. This means that the base-emitter voltage is unlikely to exceed a predetermined voltage. That is, the parasitic bipolar transistor Tr1 is unlikely to turn on. Therefore, by using the p-type semiconductor substrate SUB1, "substrate injection" generated by the parasitic bipolar transistor Tr1 turning on can be suppressed.

[0071] In this way, by using the p-type semiconductor substrate SUB1, "substrate injection" can be suppressed. However, in the first related art using the p-type semiconductor substrate SUB1, there are also disadvantages.

[0072] <<Room for improvement in the first related art>> For example, as shown in FIG. 5, in the first related art, since a p-type semiconductor substrate SUB1 is used, a p-type epitaxial layer EPI1 and a p-type epitaxial layer EPI2 are required. This is because it is difficult to form an n-type embedded layer 20 in the p-type semiconductor substrate SUB1 by doping a donor (n-type impurity) into the p-type semiconductor substrate SUB1 having a high acceptor concentration. That is, it is easier to form a p-type epitaxial layer EPI1 having an acceptor concentration lower than that of the p-type semiconductor substrate SUB1 on the p-type semiconductor substrate SUB1, and to dope a donor (n-type impurity) into this p-type epitaxial layer EPI1 to form the n-type embedded layer 20.

[0073] Therefore, in the first related art using the p-type semiconductor substrate SUB1, two epitaxial growth steps are required. From this, in the first related art, it is necessary to perform the epitaxial growth step a plurality of times (twice). As a result, in the first related art, the manufacturing process becomes complicated and the manufacturing cost of the semiconductor device may increase.

[0074] Therefore, the second related art shown below is being considered.

[0075] <Explanation of the Second Related Art> In this specification, the "second related art" is a technology that is not a known technology but has the problems found by the inventor, and is a technology that is a premise of the present disclosure.

[0076] The configuration of the semiconductor device in the second related art shown in FIG. 6 is substantially the same as the configuration of the semiconductor device in the first related art shown in FIG. 5. On the other hand, in the first related art, the p-type semiconductor substrate SUB1 is used, while in the second related art, the p-type semiconductor substrate SUB is used. For example, boron (B) as an acceptor is introduced into the p-type semiconductor substrate SUB. The concentration of boron is, for example, 0.3×10 16 (1 / cm 3 ) or more and 1×10 16 (1 / cm 3 ) or less.

[0077] Accordingly, in the semiconductor device of the second related art, it is not necessary to form two p-type epitaxial layers EPI1 and EPI2 as in the first related art. That is, in the semiconductor device of the second related art, only one p-type epitaxial layer EPI is formed.

[0078] Therefore, in the second related art, the number of times of performing the epitaxial growth process can be reduced to one. From this, the second related art can simplify the manufacturing process of the semiconductor device compared to the first related art 1. Furthermore, according to the second related art, since the number of times of performing the epitaxial growth process can be reduced, the manufacturing cost of the semiconductor device can be reduced. Thus, the second related art can suppress an increase in the manufacturing cost in the first related art by using the p-type semiconductor substrate SUB.

[0079] <<Room for improvement existing in the second related art>> In the second related art, a p-type semiconductor substrate SUB is used. Compared with the first related art, since the p-type semiconductor substrate SUB has a low boron concentration, the resistance value of the p-type semiconductor substrate SUB is high. For example, the resistance value of the p-type semiconductor substrate SUB is 100 to 1000 times higher than the resistance value of the p-type semiconductor substrate SUB1.

[0080] Therefore, in the second related art, the base resistance of the parasitic bipolar transistor Tr1 becomes high. This means that even if the current flowing between the base and the emitter is small, the base-emitter voltage becomes high. That is, in the second related art, due to the high base resistance, the parasitic bipolar transistor Tr1 is likely to turn on. In other words, in the second related art, "substrate injection" is likely to occur.

[0081] Regarding this point, in order to suppress "substrate injection", it is conceivable to increase the distance D between the stacked structure portion 10A and the stacked structure portion 10B. Thereby, "α" can be made small. However, if the distance D is increased, the size of the semiconductor device becomes large. Therefore, it is desired to make "α" small without increasing the distance D.

[0082] From the above, it is difficult to satisfy both of the following requirements (1) and (2) in any of the above-described first related technology and second related technology.

[0083] Requirement (1) is to have one p-type epitaxial layer formed in the semiconductor device. If this requirement (1) is satisfied, the epitaxial growth process can be reduced, resulting in the simplification of the manufacturing process and the reduction of the manufacturing cost of the semiconductor device.

[0084] Requirement (2) is to reduce "α" without increasing the distance D. If this requirement (2) is satisfied, the malfunction of the circuit due to "substrate injection" can be suppressed without increasing the size of the semiconductor device.

[0085] Therefore, in the present embodiment, in order to satisfy both of the above-described requirements (1) and (2), a device is made in the configuration of the semiconductor device.

[0086] <Basic idea in the embodiment> In FIG. 7, the basic idea is to devise the configuration of the non-element formation region R2 so that not only the parasitic bipolar transistor Tr1 but also the parasitic bipolar transistor Tr2 is formed. That is, the basic idea is to devise the configuration of the semiconductor device so that the collector of the parasitic bipolar transistor Tr2 is formed in the non-element formation region R2. Thereby, according to the basic idea, "α" can be reduced. That is, according to the basic idea, the malfunction of the circuit due to "substrate injection" can be suppressed.

[0087] For example, in the first related art and the second related art, the parasitic bipolar transistor Tr2 does not exist. Therefore, when a negative potential noise is input from the outside into the element formation region DFR1, as shown in FIG. 7, when the parasitic bipolar transistor Tr1 is turned on, a plurality of electrons flow from the element formation region DFR1 (emitter E) toward the element formation region DFR2 (collector C). At this time, when the number of electrons flowing into the collector C increases, "α" increases. And when "α" increases, the circuit is likely to malfunction.

[0088] In contrast, in the basic idea, not only the parasitic bipolar transistor Tr1 but also the parasitic bipolar transistor Tr2 is formed. Therefore, when a negative potential noise is input from the outside into the element formation region DFR1, both the parasitic bipolar transistor Tr1 and the parasitic bipolar transistor Tr2 are turned on. As a result, a plurality of electrons flowing into the p - type semiconductor substrate (base B) from the element formation region DFR1 (emitter E) flow separately into the element formation region DFR2 (collector C) and the non-element formation region R2 (collector C1). Thereby, the number of electrons flowing into the element formation region DFR2 (collector C) decreases by the amount of electrons flowing into the non-element formation region R2 (collector C1). That is, "α" becomes smaller.

[0089] In this way, according to the basic idea, by devising the configuration of the non-element formation region R2 so that not only the parasitic bipolar transistor Tr1 but also the parasitic bipolar transistor Tr2 is formed, "α" can be made smaller. Therefore, according to the basic idea, the circuit malfunction caused by "substrate injection" can be suppressed.

[0090] <Embodiment> <<Configuration of Semiconductor Device>> As shown in FIG. 8, the semiconductor device includes a p-type semiconductor substrate SUB, an n-type embedded layer 20, a p-type epitaxial layer EPI, a p-type well 70, deep trenches DTI1, DTI2, DTI3, a trench STI, a stacked structure portion 10A, a stacked structure portion 10B, a dummy field structure portion 100, a GND structure portion 80, an interlayer insulating film IL, plugs PLGA, PLGB, PLGC, PLGD, and PLGE.

[0091] The semiconductor device has an element formation region DFR1, an element formation region DFR2, and a non-element formation region R2. Here, although not shown in FIG. 8, for example, in a plan view, the element formation region DFR1 is surrounded by the non-element formation region R2. Also, in a plan view, the element formation region DFR2 is surrounded by the non-element formation region R2.

[0092] Boron as an acceptor is introduced into the p-type semiconductor substrate SUB. The concentration of boron is 0.3×10 16 (1 / cm 3 ) or more and 2.0×10 16 (1 / cm 3 ) or less. That is, the concentration of boron introduced into the p-type semiconductor substrate SUB is lower than, for example, the concentration of boron introduced into the p-type semiconductor substrate SUB1 in the first related art. As a result, the resistance value of the p-type semiconductor substrate SUB is higher than the resistance value of the p-type semiconductor substrate SUB1. Specifically, the resistance value of the p-type semiconductor substrate SUB is about 100 to 1000 times higher than the resistance value of the p-type semiconductor substrate SUB1.

[0093] A p-type epitaxial layer EPI is formed on the p-type semiconductor substrate SUB. And an n-type embedded layer 20 is formed in the p-type semiconductor substrate SUB or in the p-type epitaxial layer EPI.

[0094] Although not specifically shown, the element formation region DFR1 is surrounded by the deep trench DTI1 in a plan view. In FIG. 8, a stacked structure portion 10A is formed in the element formation region DFR1. Although not specifically shown, the element formation region DFR2 is surrounded by the deep trench DTI2 in a plan view. A stacked structure portion 10B is formed in this element formation region DFR2. Further, the non-element formation region R2 is in contact with both the deep trench DTI1 and the deep trench DT12. A dummy field structure portion 100 is formed in this non-element formation region R2.

[0095] In the right region of the deep trench DTI2 shown in FIG. 8, a p-type well 70 is formed in the p-type epitaxial layer EPI. Also, in the left region of the deep trench DTI1 shown in FIG. 8, a p-type well 70 is formed in the p-type epitaxial layer EPI. A deep trench DTI3 is formed so as to be in contact with this p-type well 70. And a GND structure portion 80 is formed so as to be surrounded by the deep trench DTI3.

[0096] The GND structure portion 80 is surrounded by the deep trench DTI3 in a plan view. As shown in FIG. 8, the GND structure portion 80 has a groove reaching from the upper surface S1 of the p-type epitaxial layer EPI to the p-type epitaxial layer EPI1, and a conductive material (for example, polysilicon) embedded in the groove. Thereby, a GND potential (0V) can be supplied to the p-type semiconductor substrate SUB. That is, the GND structure portion 80 has a function of supplying a GND potential to the p-type semiconductor substrate SUB.

[0097] In the p-type epitaxial layer EPI, a deep n-type well 40A, a deep n-type well 40B, an n-type well 50A, an n-type well 50B, an n-type diffusion layer 60A, an n-type diffusion layer 60B, a p-type well 70, a deep n-type well 110, an n-type well 120, a first n-type semiconductor region 140, a second n-type semiconductor region 130A, a second n-type semiconductor region 130B, a deep trench DTI1, a deep trench DTI2, a deep trench DTI3, and a trench STI are formed.

[0098] Each of the deep trench DTI1, the deep trench DTI2, and the deep trench DTI3 penetrates the n-type buried layer 20. An insulating material such as silicon oxide is embedded in each of the deep trench DTI1, the deep trench DTI2, and the deep trench DTI3.

[0099] The stacked structure portion 10A has a deep n-type well 40A, an n-type well 50A, and an n-type diffusion layer 60A. Specifically, each of the deep n-type well 40A, the n-type well 50A, and the n-type diffusion layer 60A is formed in the p-type epitaxial layer EPI. The n-type well 50A is formed on the deep n-type well 40A. Further, the n-type diffusion layer 60A is formed on the n-type well 50A. Thus, the stacked structure portion 10A is composed of a stacked structure of n-type semiconductors.

[0100] Note that when the stacked structure portion 10A is represented by the structure shown in FIGS. 1 to 3, it is configured as follows. That is, the stacked structure portion 10A has a first n-type well (NW1, NW3, NW6), a second n-type well (NW2, NW4, NW7), and a first n-type diffusion layer (NR, CR, BR1). The first n-type well, the second n-type well, and the first n-type diffusion layer are formed in the element formation region DFR1. The first n-type well is formed on the n-type buried layer 20. And the second n-type well is included in the first n-type well. Further, the first n-type diffusion layer is included in the second n-type well.

[0101] The stacked structure portion 10B has a deep n-type well 40B, an n-type well 50B, and an n-type diffusion layer 60B. Specifically, each of the deep n-type well 40B, the n-type well 50B, and the n-type diffusion layer 60B is formed within a p-type epitaxial layer EPI. And the n-type well 50B is formed on the deep n-type well 40B. Further, the n-type diffusion layer 60B is formed on the n-type well 50B. Thus, the stacked structure portion 10B is composed of a stacked structure of n-type semiconductors.

[0102] Note that when the stacked structure portion 10B is represented by the structures shown in FIGS. 1 to 3, it is configured as follows. That is, the stacked structure portion 10B has a third n-type well (NW1, NW3, NW6), a fourth n-type well (NW2, NW4, NW7), and a second n-type diffusion layer (NR, CR, BR1). The third n-type well, the fourth n-type well, and the second n-type diffusion layer are formed within an element formation region DFR2. The third n-type well is formed on an n-type buried layer 20. And the fourth n-type well is included in the third n-type well. Further, the second n-type diffusion layer is included in the fourth n-type well.

[0103] The dummy field structure portion 100 has a deep n-type well 110, an n-type well 120, a trench STI, a conductor layer 150, a first n-type semiconductor region 140, a second n-type semiconductor region 130A, and a second n-type semiconductor region 130B. And the dummy field structure portion 100 is formed within a non-element formation region R2.

[0104] The n-type well 120 is formed within a p-type epitaxial layer EPI. Further, the n-type well 120 has a first region RA and a second region RB.

[0105] Here, the "first region RA" as referred to in this specification is shown in FIG. 11 as the region of the n-type well 120 where the conductor layer 150 is formed on the upper part of the n-type well 120. Also, the "second region RB" as referred to in this specification is shown in FIG. 12 as the region of the n-type well 120 where the second n-type semiconductor region 130A or the second n-type semiconductor region is formed inside the n-type well 120.

[0106] The deep n-type well 110 is disposed between the n-type buried layer 20 and the n-type well 120. And the deep n-type well 110 is connected to the n-type buried layer 20 and the n-type well 120.

[0107] The trench STI has a bottom surface within the n-type well 120. In contrast, each of the deep trenches DTI1 and DTI2 penetrates the n-type buried layer 20 formed below the n-type well 120. Therefore, the trench STI is shallower than each of the deep trenches DTI1 and DTI2.

[0108] The technical significance of forming the trench STI in the non-device formation region R2 is as follows. For example, a plurality of transistors are formed in the device formation region DFR1 and the device formation region DFR2. And in order to electrically isolate the plurality of transistors from each other, device isolation regions are formed in the device formation region DFR1 and the device formation region DFR2. The device isolation region is formed, for example, by embedding an insulating material in a trench. The process of forming this device isolation region includes a CMP (chemical mechanical polishing) process. In order to improve the flatness of the surface to be polished in the CMP process, it is desirable that the density of the trenches is uniform over the entire surface to be polished. This is because if the density of the trenches is non-uniform, "dishing" will occur where polishing is excessive in the region where the density of the trenches is low.

[0109] Therefore, in order to suppress "dishing" that occurs in the CMP process, trench STIs are also formed in the non-device formation region R2. That is, the technical significance of forming trench STIs in the non-device formation region R2 is to equalize the density of trench STIs across the entire surface to be polished. By forming trench STIs in the non-device formation region R2, "dishing" in the CMP process can be suppressed.

[0110] The conductor layer 150 is formed on the n-type well 120. The conductor layer 150 is formed of, for example, a polysilicon film.

[0111] For example, a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are formed in the device formation region DFR1 and the device formation region DFR2. Since each of the plurality of MOSFETs has a gate electrode, a plurality of gate electrodes are arranged in the device formation region DFR1 and the device formation region DFR2. In contrast, no MOSFET is formed in the non-device formation region R2. Therefore, no gate electrode is formed in the non-device formation region R2. Thus, the density of the gate electrodes is non-uniform.

[0112] Here, as shown in FIG. 8, an interlayer insulating film IL is formed so as to cover the gate electrode. Then, in order to planarize the upper surface of the interlayer insulating film IL, a CMP process is performed on the upper surface of the interlayer insulating film IL. Therefore, in order to improve the flatness of the upper surface of the interlayer insulating film IL, it is desirable to make the density of the gate electrodes uniform.

[0113] Therefore, the conductor layer 150 is formed in the non-device formation region R2. The conductor layer 150 functions as a dummy gate electrode. That is, the conductor layer 150 is formed in the non-device formation region R2 in order to suppress "dishing" of the interlayer insulating film IL.

[0114] For example, in order to apply a gate voltage to the gate electrode, the gate electrode is connected to a plug. In contrast, the conductor layer 150 is a dummy gate electrode that does not function as a gate electrode. Therefore, there is no need to apply a gate voltage to the conductor layer 150. Accordingly, the conductor layer 150 is arranged so as not to be connected to the plug.

[0115] The first n-type semiconductor region 140 is formed within the n-well 120. The first n-type semiconductor region 140 is formed at a position shallower than the bottom surface of the trench STI. The first n-type semiconductor region 140 is in contact with the trench STI. The impurity concentration of the first n-type semiconductor region 140 is higher than the impurity concentration (donor concentration) of the n-well 120.

[0116] The second n-type semiconductor region 130A is formed within the n-well 120. The second n-type semiconductor region 130A is formed at a position shallower than the bottom surface of the trench STI. The second n-type semiconductor region 130A is in contact with the trench STI. The impurity concentration of the second n-type semiconductor region 130A is higher than the impurity concentration (donor concentration) of the n-well 120.

[0117] The second n-type semiconductor region 130B is formed within the n-well 120. The second n-type semiconductor region 130B is formed at a position shallower than the bottom surface of the trench STI. The second n-type semiconductor region 130B is in contact with the trench STI. The impurity concentration of the second n-type semiconductor region 130B is higher than the impurity concentration (donor concentration) of the n-well 120.

[0118] Thus, the second n-type semiconductor region 130A and the second n-type semiconductor region 130B are formed within the non-element formation region R2. That is, a plurality of second n-type semiconductor regions (130A, 130B) are formed within the non-element formation region R2.

[0119] As shown in FIG. 8, plugs PLGA, PLGB, PLGC, PLGD, and PLGE are formed within the interlayer insulating film IL. The interlayer insulating film IL is formed of, for example, a silicon oxide film.

[0120] The plug PLGA penetrates through the interlayer insulating film IL. The plug PLGA is disposed on the n-type diffusion layer 60A. The plug PLGA is connected to the n-type diffusion layer 60A.

[0121] The plug PLGB penetrates through the interlayer insulating film IL. The plug PLGB is disposed on the n-type diffusion layer 60B. The plug PLGB is connected to the n-type diffusion layer 60B.

[0122] The plug PLGC penetrates through the interlayer insulating film IL. The plug PLGC is disposed on the second n-type semiconductor region 130A. The plug PLGC is connected to the second n-type semiconductor region 130A. Thereby, a fixed potential is supplied to the second n-type semiconductor region 130A via the plug PLGC. The fixed potential is, for example, a ground potential.

[0123] The plug PLGD penetrates through the interlayer insulating film IL. The plug PLGD is disposed on the second n-type semiconductor region 130B. The plug PLGD is connected to the second n-type semiconductor region 130B. Thereby, a fixed potential is supplied to the second n-type semiconductor region 130B via the plug PLGD. The fixed potential is, for example, a ground potential.

[0124] The plug PLGE penetrates through the interlayer insulating film IL. The plug PLGE is disposed on the GND structure portion 80. The plug PLGE is connected to the GND structure portion 80.

[0125] As shown by the thick solid line in FIG. 8, the stacked structure portion 10A, the p-type semiconductor substrate SUB, and the stacked structure portion 10B constitute a parasitic bipolar transistor Tr1.

[0126] Also, as shown by the thick dotted line in FIG. 8, the stacked structure portion 10A, the p-type semiconductor substrate SUB, and the dummy field structure portion 100 constitute a parasitic bipolar transistor Tr2.

[0127] Here, the stacked structure portion 10A functions as the emitter of the parasitic bipolar transistor Tr1 and the emitter of the parasitic bipolar transistor Tr2. p - The p-type semiconductor substrate SUB functions as the base of the parasitic bipolar transistor Tr1 and the base of the parasitic bipolar transistor Tr2. The stacked structure portion 10B functions as the collector of the parasitic bipolar transistor Tr1. The dummy field structure portion 100 functions as the collector of the parasitic bipolar transistor Tr2. Thus, the basic idea is embodied.

[0128] As shown in FIG. 9, in a plan view, each of the element formation regions DFR1 and DFR2 is surrounded by the non-element formation region R2. That is, in a plan view, each of the element formation regions DFR1 and DFR2 is included in the non-element formation region R2.

[0129] In FIG. 9, the element formation region DFR1 is surrounded by the deep trench DTI1 in a plan view. That is, the region surrounded by the deep trench DTI1 constitutes the element formation region DFR1. Also, the element formation region DFR2 is surrounded by the deep trench DTI2 in a plan view. That is, the region surrounded by the deep trench DTI2 constitutes the element formation region DFR2.

[0130] As shown in FIG. 10, the trench STI has a lattice-like planar shape. And in a plan view, the conductor layer 150 is included in the trench STI. That is, in a plan view, the conductor layer 150 is surrounded by the trench STI. Also, in a plan view, a first n-type semiconductor region 140 is formed between the trench STI and the conductor layer 150. The first n-type semiconductor region 140 is surrounded by the trench STI in a plan view. Also, the first n-type semiconductor region 140 surrounds the conductor layer 150 in a plan view.

[0131] Thus, the conductor layer 150 and the first n-type semiconductor region 140 are formed in some of the regions surrounded by the trench STI.

[0132] In FIG. 10, among the plurality of regions surrounded by the trench STI, there are regions where the conductor layer 150 is not formed. In this region, for example, the second n-type semiconductor region 130A or the second n-type semiconductor region 130B is formed. The second n-type semiconductor region 130A is surrounded by the trench STI in plan view. Similarly, the second n-type semiconductor region 130B is surrounded by the trench STI in plan view. A plug PLGC is disposed on the second n-type semiconductor region 130A. The second n-type semiconductor region 130A is connected to the plug PLGC. Similarly, a plug PLGD is disposed on the second n-type semiconductor region 130B. The second n-type semiconductor region 130B is connected to the plug PLGD.

[0133] Thus, in some other regions among the plurality of regions surrounded by the trench STI, the second n-type semiconductor region 130A or the second n-type semiconductor region 130B is formed.

[0134] As shown in FIG. 11, a conductor layer 150 is formed on the first region RA in the n-type well 120. And a first n-type semiconductor region 140 is formed in the n-type well 120 between the first region RA and the trench STI. The first n-type semiconductor region 140 surrounds the conductor layer 150 in plan view as understood from FIG. 10. In other words, the first n-type semiconductor region 140 surrounds the first region RA.

[0135] As shown in FIG. 12, a second n-type semiconductor region 130A is formed in the second region RB in the n-type well 120. The second n-type semiconductor region 130A is surrounded by the trench STI in plan view as understood from FIG. 10. And as shown in FIG. 12, a plug PLGC is disposed on the second n-type semiconductor region 130A. The second n-type semiconductor region 130A is connected to the plug PLGC. Thereby, a fixed potential can be supplied to the second n-type semiconductor region 130A via the plug PLGC.

[0136] As described above, the semiconductor device in the embodiment is configured.

[0137] <<Features in the Embodiment>> The first feature in the embodiment is that, for example, as shown in FIG. 8, a p-type semiconductor substrate SUB is used. Thereby, a single p-type epitaxial layer formed on the p-type semiconductor substrate SUB can be obtained. Therefore, according to the first feature in the embodiment, the epitaxial growth process can be reduced, and as a result, the manufacturing process can be simplified and the manufacturing cost of the semiconductor device can be reduced.

[0138] The second feature in the embodiment is that, for example, as shown in FIG. 8, a dummy field structure portion 100 is formed in the non-element formation region R2 so that not only the parasitic bipolar transistor Tr1 but also the parasitic bipolar transistor Tr2 is formed. The dummy field structure portion 100 has, as shown in FIG. 8, a deep n-type well 110, an n-type well 120, a trench STI, a conductor layer 150, a first n-type semiconductor region 140, a second n-type semiconductor region 130A, and a second n-type semiconductor region 130B.

[0139] Thereby, a collector of the parasitic bipolar transistor Tr2 can be formed in the non-element formation region R2. Therefore, in the embodiment, not only the parasitic bipolar transistor Tr1 but also the parasitic bipolar transistor Tr2 is formed in the semiconductor device.

[0140] From this, when a negative potential noise is input from the outside into the element formation region DFR1, both the parasitic bipolar transistor Tr1 and the parasitic bipolar transistor Tr2 are turned on. As a result, a plurality of electrons flowing from the element formation region DFR1 (emitter E) to the p-type semiconductor substrate (base B) are separated and flow into the element formation region DFR2 (collector C) and the non-element formation region R2 (collector C1). Thereby, the number of electrons flowing into the element formation region DFR2 (collector C) is reduced by the amount of electrons flowing into the non-element formation region R2 (collector C1). That is, "α" becomes smaller.

[0141] In this way, by forming a dummy field structure in the non-element formation region R2, "α" can be reduced. Therefore, according to the second feature, malfunction of the circuit due to "substrate injection" can be suppressed.

[0142] In particular, in the embodiment, a p-type well 70 is not formed in the non-element formation region R2. For this reason, the collector area of the parasitic bipolar transistor Tr2 can be increased. Also, in the embodiment, a plurality of second n-type semiconductor regions (130A, 130B) are formed. And a fixed potential is supplied to each of the plurality of second n-type semiconductor regions (130A, 130B) via plugs (PLGC, PLGD). From this, in the embodiment, there are a plurality of paths for extracting electrons from the parasitic bipolar transistor Tr2. As a result, the number of electrons flowing in the non-element formation region R2 (collector C1) can be increased. This means that the number of electrons flowing in the element formation region DFR2 (collector C) can be reduced. Thereby, according to the embodiment, "α" can be reduced.

[0143] As understood from FIG. 13, according to the embodiment, at a distance D ≧ 150 μm, α ≦ 10 -4 can be achieved. That is, when a first current flows through the emitter (E) and a second current flows through the collector (C) of the parasitic bipolar transistor Tr1, and the second current / first current = α, at a distance D ≧ 150 μm, α ≦ 10 -4 can be achieved. Therefore, according to the embodiment, "α" can be effectively reduced without making the distance D larger than 150 μm.

[0144] From the above, according to the semiconductor device in the embodiment, without increasing the size of the semiconductor device, simplification of the manufacturing process and reduction of the manufacturing cost of the semiconductor device can be achieved, and "substrate injection" can be suppressed.

[0145] <Modification Example> In the above-described embodiment, an example using a p-type semiconductor substrate SUB has been described. However, the technical idea in the present embodiment is not limited thereto, and can be applied to, for example, a semiconductor device using a p-type semiconductor substrate SUB1.

[0146] As also described in the first related art, in a semiconductor device using a p-type semiconductor substrate SUB1, the parasitic bipolar transistor Tr1 is difficult to turn on. Therefore, when the p-type semiconductor substrate SUB1 is used, "substrate injection" caused by the turning on of the parasitic bipolar transistor Tr1 is less likely to occur.

[0147] However, by applying the technical idea in the present embodiment to a semiconductor device using a p-type semiconductor substrate SUB1, "substrate injection" can be reduced even if the parasitic bipolar transistor Tr1 is turned on.

[0148] Therefore, from the viewpoint of improving the performance of the semiconductor device, it is useful to apply the technical idea in the present embodiment to a semiconductor device using a p-type semiconductor substrate SUB1.

[0149] <Application Example> In FIG. 14, the semiconductor device has an element formation region NR1, an element formation region NR2, an element formation region PR1, an element formation region PR2, and a non-element formation region NR3. And the semiconductor device has an n-type well 200, an n-type well 210, an n-type well 220, a p-type well 310, a p-type well 320, a p-type well 330, and a p-type well 340.

[0150] As shown in FIG. 14, an n-type well 210, an n-type well 220, a p-type well 310, and a p-type well 320 are formed in the central portion of the semiconductor device. On the other hand, an n-type well 200 is formed in the peripheral portion surrounding the central portion of the semiconductor device.

[0151] The n-type well 210 is formed within the element formation region NR1. The n-type well 210 is surrounded by a p-type well 330. The p-type well 330 is surrounded by an n-type well 200. For example, a p-type MOSFET is formed in the n-type well 210.

[0152] The n-type well 220 is formed within the element formation region NR2. The n-type well 220 is surrounded by a p-type well 340. The p-type well 340 is surrounded by an n-type well 200. For example, a p-type MOSFET is formed in the n-type well 220.

[0153] The p-type well 310 is formed within the element formation region PR1. The p-type well 310 is surrounded by an n-type well 200. For example, an n-type MOSFET is formed in the p-type well 310.

[0154] The p-type well 320 is formed within the element formation region PR2. The p-type well 310 is surrounded by an n-type well 200. For example, an n-type MOSFET is formed in the p-type well 320.

[0155] The n-type well 200 is formed within the non-element formation region NR3. The n-type well 200 surrounds the p-type well 330 that surrounds the n-type well 210. Similarly, the n-type well 200 surrounds the p-type well 340 that surrounds the n-type well 220. Also, the n-type well 200 surrounds the p-type well 310. Similarly, the n-type well 200 surrounds the p-type well 320. No element is formed in the n-type well 200.

[0156] In FIG. 15, the semiconductor device includes a p-type semiconductor substrate SUB, an n-type buried layer 20, a p-type epitaxial layer EPI, an n-type well 200, an n-type well 210, an n-type well 220, a p-type well 330, a p-type well 340, a deep n-type well 410, and a deep n-type well 420. Here, as shown in FIG. 15, a parasitic bipolar transistor Tr1 is formed between the element formation region NR1 and the element formation region NR2.

[0157] In FIG. 16, the semiconductor device includes a p-type semiconductor substrate SUB, an n-type buried layer 20, a p-type epitaxial layer EPI, an n-type well 200, an n-type well 210, a p-type well 310, a p-type well 330, a deep n-type well 400, and a deep n-type well 410.

[0158] Boron, which is an acceptor, is introduced into the p-type semiconductor substrate SUB. The concentration of boron is 0.3×10 16 (1 / cm 3 ) or more and 2.0×10 16 (1 / cm 3 ) or less.

[0159] A p-type epitaxial layer EPI is formed on the p-type semiconductor substrate SUB. And an n-type buried layer 20 is formed in the p-type semiconductor substrate SUB or in the p-type epitaxial layer EPI.

[0160] The n-type well 200 is formed in the non-element formation region NR3. The n-type well 200 is formed in the p-type epitaxial layer EPI.

[0161] The deep n-type well 400 is disposed between the n-type buried layer 20 and the n-type well 200. The deep n-type well 400 is connected to the n-type buried layer 20 and the n-type well 200.

[0162] The n-type well 210 is formed in the element formation region NR1. The n-type well 210 is formed in the p-type epitaxial layer EPI.

[0163] The deep n-type well 410 is disposed between the n-type buried layer 20 and the n-type well 210. The deep n-type well 410 is connected to the n-type buried layer 20 and the n-type well 210.

[0164] The n-type well 210 is surrounded by the p-type well 330. The p-type well 330 has a function of electrically separating the n-type well 200 and the n-type well 210.

[0165] The p-type well 310 is formed within the element formation region PR1. The p-type well 310 is formed within the p-type epitaxial layer EPI. The p-type well 310 is surrounded by the n-type well 200.

[0166] Here, as shown in FIG. 16, a parasitic bipolar transistor Tr2 is formed between the element formation region NR1 and the non-element formation region NR3.

[0167] In this way, also in the application example, the parasitic bipolar transistor Tr1 and the parasitic bipolar transistor Tr2 are formed. Therefore, the application example embodies the basic idea in this embodiment. From this, also in the application example, when a negative potential noise is input from the outside into the element formation region NR1, both the parasitic bipolar transistor Tr1 and the parasitic bipolar transistor Tr2 turn on. As a result, a plurality of electrons flowing from the element formation region NR1 (emitter E) to the p-type semiconductor substrate (base B) branch and flow into the element formation region NR2 (collector C) and the non-element formation region NR3 (collector C1). Thereby, the number of electrons flowing into the element formation region NR2 (collector C) decreases by the amount of electrons flowing into the non-element formation region NR3 (collector C1). That is, "α" becomes smaller.

[0168] In this way, according to the application example, by devising the configuration of the non-element formation region NR3, "α" can be made smaller. Therefore, also in the application example, the malfunction of the circuit due to "substrate injection" can be suppressed.

[0169] As described above, the invention made by the present inventor has been specifically described based on its embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0170] 1A Stacked structure portion 1B Stacked structure portion 1C Stacked structure portion 10 Stacked structure section 10A Stacked structure section 10B Stacked structure section 20 n-type buried layer 30 p-type epitaxial layer 40 Deep n-well 40A Deep n-well 40B Deep n-well 50 n-well 50A n-well 50B n-well 60 n-type diffusion layer 60A n-type diffusion layer 60B n-type diffusion layer 70 p-well 80 GND structure section 100Dummy field structure section 110 Deep n-well 120 n-well 130A Second n-type semiconductor region 130B Second n-type semiconductor region 140 First n-type semiconductor region 150 Conductor layer 200 n-well 210 n-well 220 n-well 310 p-well 320 p-well 330 p-well 340 p-well 400 Deep n-well 410 Deep n-well 420 Deep n-well B Base BR Base region BR1 Base region BR2 Base region C Collector C1 Collector CR Collector region CR1 Collector region CR2 Collector region DFR Element formation region DFR1 Element Formation Region DFR2 Element Formation Region DR Drain Region DTI Deep Trench DTI1 Deep Trench DTI2 Deep Trench DTI3 Deep Trench E Emitter EPI p-Type Epitaxial Layer EPI1 p-Type Epitaxial Layer EPI2 p-Type Epitaxial Layer ER Emitter Region ER1 Emitter Region GE Gate Electrode GOX Gate Insulating Film IL Interlayer Insulating Film NBL n-Type Implanted Layer NR n-Type Semiconductor Region NR1 Element Formation Region NR2 Element Formation Region NR3 Non-Element Formation Region NW1 n-Type Well NW2 n-Type Well NW3 n-Type Well NW4 n-Type Well NW5 n-Type Well NW6 n-Type Well NW7 n-Type Well NW8 n-Type Well OR p-Type Offset Region PLGA Plug PLGB Plug PLGC Plug PLGD Plug PLGE Plug PLG1 Plug PLG2 Plug PLG3 Plug PLG4 Plug PLG5 Plug PLG6 Plug PLG7 Plug PLG8 Plug PLG9 Plug PLG10 Plug PLG11 Plug PLG12 Plug PR1 Element Formation Region PR2 Element Formation Region PW p-Type Well PW1 p-Type Well PW2 p-Type Well PW3 p-Type Well PW4 p-Type Well R1A Element Formation Region R1B Element Formation Region R1C Element Formation Region R2 Non-Element Formation Region RA First Region RB Second Region SR Source Region STI Trench STI1 Trench STI2 Trench SUB p-Type Semiconductor Substrate SUB1 p-Type Semiconductor Substrate S1 Top Surface Tr1 Parasitic Bipolar Transistor Tr2 Parasitic Bipolar Transistor WL1 Source Wiring WL2 Drain Wiring WL3 Collector Wiring WL4 Emitter Wiring WL5 Base Wiring WL6 Collector Wiring WL7 Base Wiring WL8 Emitter Wiring WL9 Base Wiring WL10 Collector Wiring

Claims

1. A semiconductor device having an element formation region and a non-element formation region, a p-type semiconductor substrate, a p-type epitaxial layer formed on the p-type semiconductor substrate, an n-type buried layer formed in the p-type semiconductor substrate or in the p-type epitaxial layer, an n-type well formed in the non-element formation region, in the p-type epitaxial layer, and having a first region and a second region, a deep n-type well formed in the non-element formation region, disposed between the n-type buried layer and the n-type well, and connected to the n-type buried layer and the n-type well, a deep trench that surrounds the element formation region in plan view and penetrates the n-type buried layer, a trench formed in the non-element formation region and having a bottom surface in the n-type well, a conductor layer formed in the non-element formation region, surrounded by the trench in plan view, and formed on the first region, a first n-type semiconductor region formed in the non-element formation region, surrounded by the trench in plan view, formed in the n-type well, surrounding the first region in plan view, and formed at a position shallower than the bottom surface of the trench, a second n-type semiconductor region formed in the non-element formation region, surrounded by the trench in plan view, formed in the second region of the n-type well, and formed at a position shallower than the bottom surface of the trench, a plug disposed on the second n-type semiconductor region and connected to the second n-type semiconductor region, comprising, a first insulating material is embedded inside the deep trench, a second insulating material is embedded inside the trench, the impurity concentration of the first n-type semiconductor region is higher than the impurity concentration of the n-type well, the impurity concentration of the second n-type semiconductor region is higher than the impurity concentration of the n-type well, a semiconductor device in which a fixed potential is supplied to the second n-type semiconductor region via the plug.

2. The semiconductor device according to claim 1, wherein the first n-type semiconductor region surrounds the conductor layer in plan view.

3. The semiconductor device according to claim 1, wherein the fixed potential is a ground potential.

4. The semiconductor device according to claim 1, wherein the conductor layer is arranged so as not to be connected to the plug.

5. In the semiconductor device according to claim 1, the element formation region has a first element formation region and a second element formation region, the deep trench has a first deep trench and a second deep trench, the semiconductor device includes a first deep trench that surrounds the first element formation region in a plan view and penetrates the n-type embedded layer, a first n-type well formed in the first element formation region and on the n-type embedded layer, a second n-type well formed in the first element formation region and enclosed by the first n-type well, a first n-type diffusion layer formed in the first element formation region and enclosed by the second n-type well, a second deep trench that surrounds the second element formation region in a plan view and penetrates the n-type embedded layer, a third n-type well formed in the second element formation region and on the n-type embedded layer, a fourth n-type well formed in the second element formation region and enclosed by the third n-type well, a second n-type diffusion layer formed in the second element formation region and enclosed by the fourth n-type well, and the semiconductor device having the above.

6. In the semiconductor device according to claim 5, in a plan view, the first element formation region is surrounded by the non-element formation region, in a plan view, the second element formation region is surrounded by the non-element formation region, and the semiconductor device.

7. In the semiconductor device according to claim 5, each of the first n-type diffusion layer and the second n-type diffusion layer constitutes an n-type body contact region of a p-type LDMOSFET, a collector region of an npn-type bipolar transistor, or a base region of a lateral pnp-type bipolar transistor, and the semiconductor device.

8. In the semiconductor device according to claim 5, the n-type embedded layer, the deep n-type well, the n-type well, and the second n-type semiconductor region formed in the non-element formation region constitute a dummy field structure portion, the n-type embedded layer, the first n-type well, the second n-type well, and the first n-type diffusion layer formed in the first element formation region constitute a first stacked structure portion, the n-type embedded layer, the third n-type well, the fourth n-type well, and the second n-type diffusion layer formed in the second element formation region constitute a second stacked structure portion, The first stacked structure portion, the p-type semiconductor substrate, and the second stacked structure portion constitute a first parasitic bipolar transistor. The first stacked structure portion, the p-type semiconductor substrate, and the dummy field structure portion constitute a second parasitic bipolar transistor. The first stacked structure portion functions as an emitter of the first parasitic bipolar transistor and an emitter of the second parasitic bipolar transistor. The p-type semiconductor substrate functions as a base of the first parasitic bipolar transistor and a base of the second parasitic bipolar transistor. The second stacked structure portion functions as a collector of the first parasitic bipolar transistor. The dummy field structure portion functions as a collector of the second parasitic bipolar transistor, a semiconductor device.

9. In the semiconductor device according to claim 8, A first current flows through the emitter, A second current flows through the collector of the first parasitic bipolar transistor. When the ratio of the second current to the first current is α, α ≤ 10 －４ This is a semiconductor device.

10. In the semiconductor device according to claim 1, Boron is introduced into the p-type semiconductor substrate. The concentration of boron is 0.5×10 １９ ( / cm ３ ) or more and 4.0×10 １９ ( / cm ３ ), and the semiconductor device is as follows.

11. In the semiconductor device according to claim 1, Boron is introduced into the p-type semiconductor substrate. The concentration of boron is 0.3×10 １６ ( / cm ３ ) or more and 2.0×10 １６ ( / cm ３ ) or less, a semiconductor device.

12. A p-type semiconductor substrate, A p-type epitaxial layer formed on the p-type semiconductor substrate, An n-type buried layer formed in the p-type semiconductor substrate or the p-type epitaxial layer, An n-type well formed in the p-type epitaxial layer, A deep n-type well disposed between the n-type buried layer and the n-type well and connected to the n-type buried layer and the n-type well, A p-type well surrounded by the n-type well in a plan view, A semiconductor device comprising.

13. In the semiconductor device according to claim 12, The n-type well has a first n-type well and a second n-type well that are electrically separated, The deep n-type well is A first deep n-type well disposed between the first n-type well and the n-type buried layer and connected to the first n-type well and the n-type buried layer, A second deep n-type well disposed between the second n-type well and the n-type buried layer and connected to the second n-type well and the n-type buried layer, Having, The first n-type well is formed in a non-element formation region, The second n-type well is formed in an element formation region, a semiconductor device.

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