Circuit, light emitting device, and image forming apparatus

Abstract

To prevent a reduction in the accuracy of reproducing current.SOLUTION: A circuit comprises: a current source that is electrically connected to a first voltage node; a first MOS transistor of a first type; a second MOS transistor of a second type that is electrically connected to a second voltage node; a third MOS transistor of the first type; and first wiring connected to a gate of the first MOS transistor and a gate of the third MOS transistor. The current source, first MOS transistor, and second MOS transistor are arranged in order on an electrical path between the first voltage node and the second voltage node. A current corresponding to a current flowing in the electrical path flows in the third MOS transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit, a light-emitting device, and an image forming apparatus.

Background Art

[0002] Patent Document 1 discloses a current mirror circuit having a function of replicating a current flowing through one circuit to another circuit.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the current mirror circuit, the voltage may drop due to variations in the wiring resistance included in the current mirror circuit, and the accuracy of replicating the current may decrease.

[0005] An object of the present invention is to provide a circuit capable of suppressing a decrease in the accuracy of replicating a current.

Means for Solving the Problems

[0006] According to one disclosure of this specification, a circuit is provided that includes a current source electrically connected to a first voltage node, a first MOS transistor of a first type, a second MOS transistor of a second type electrically connected to a second voltage node, a third MOS transistor of the first type, and a first wiring connected to the gate of the first MOS transistor and the gate of the third MOS transistor. The current source, the first MOS transistor, and the second MOS transistor are arranged in sequence in an electrical path between the first voltage node and the second voltage node, and a current corresponding to the current flowing in the electrical path flows through the third MOS transistor.

Advantages of the Invention

[0007] An object of the present invention is to provide a circuit capable of suppressing a decrease in the accuracy of current replication.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0009] Hereinafter, each embodiment will be described with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] In this specification, terms indicating specific directions and positions (for example, "up", "down", "right", "left", and other terms including these terms) are used as necessary. The use of these terms is for facilitating the understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of these terms.

[0011] When it is described in this specification that "member A and member B are electrically connected", it is not limited to the case where member A and member B are directly connected. For example, even if another member C is connected between member A and member B, it is sufficient that they are electrically connected.

[0012] The relationship of "substantially equal" in this specification will be described. Although it is an equal relationship in design, a slight difference may occur due to manufacturing errors. This "substantially equal" includes the slight difference caused by this manufacturing error.

[0013] 〈First Embodiment〉 The circuit according to the first embodiment of the present invention will be described with reference to FIG. 1.

[0014] FIG. 1 is an example of a circuit diagram of a circuit according to the present embodiment.

[0015] As shown in FIG. 1, the circuit 1 includes a current mirror circuit 10, a load circuit 20, a power supply circuit 30, and a first voltage node 100. The first voltage node 100 can be, for example, a node that supplies a reference voltage.

[0016] The current mirror circuit 10 includes a current source 110, a first MOS transistor 120, a second MOS transistor 130, a plurality of third MOS transistors 140, and a plurality of fourth MOS transistors 150. Further, the current mirror circuit 10 includes a first wiring 160 and a second wiring 170. The first MOS transistor 120 and the plurality of third MOS transistors 140 have a configuration in which the ratio of the gate width to the gate length is substantially equal.

[0017] The first wiring 160 is electrically connected to the gate of the first MOS transistor 120 and supplies a control signal to the gate. Further, the first wiring 160 is electrically connected to each of the gates of the plurality of third MOS transistors 140 and supplies a control signal to each of the gates. That is, the gate of the first MOS transistor 120 and each of the gates of the plurality of third MOS transistors 140 are electrically connected via the first wiring 160.

[0018] The second wiring 170 is electrically connected to the gate of the second MOS transistor 130 and supplies a control signal to the gate. Further, the second wiring 170 is electrically connected to each of the gates of the plurality of fourth MOS transistors 150 and supplies a control signal to each of the gates. That is, the gate of the second MOS transistor 130 and each of the gates of the plurality of fourth MOS transistors 150 are electrically connected via the second wiring 170. The voltage value applied via the second wiring 170 is set to, for example, a voltage value at which the second MOS transistor 130 and the fourth MOS transistor 150 operate in the saturation region.

[0019] The current source 110, the first MOS transistor 120, and the plurality of third MOS transistors 140 function as a current mirror circuit. By supplying current from the current source 110 to the first MOS transistor 120, the gate voltage of the first MOS transistor 120 is determined. That gate voltage is applied to each gate of the plurality of third MOS transistors 140 arranged in the corresponding column as a control signal. As a result, a current corresponding to the current flowing through the first MOS transistor 120 is supplied to the load circuit 20 via the plurality of third MOS transistors 140 arranged in the corresponding column. That is, the current value of the current flowing through the electrical path between the first voltage node 100 and the second voltage node 300 described later is substantially equal to the current value of the current flowing through the third MOS transistor 140.

[0020] Incidentally, hereinafter, when it is necessary to distinguish the third MOS transistors 140 from each other, an identification number (1, 2,..., n) is added to the end of the reference numeral of the components of the third MOS transistor 140. However, when it is not necessary to distinguish the third MOS transistors 140 from each other, the identification number at the end of the reference numeral of the components of the third MOS transistor 140 is omitted. Incidentally, hereinafter, when it is necessary to distinguish the fourth MOS transistors 150 from each other, an identification number (1, 2,..., n) is added to the end of the reference numeral of the components of the fourth MOS transistor 150. However, when it is not necessary to distinguish the fourth MOS transistors 150 from each other, the identification number at the end of the reference numeral of the components of the fourth MOS transistor 150 is omitted.

[0021] The load circuit 20 has a plurality of load elements 200. Incidentally, hereinafter, when it is necessary to distinguish the load elements 200 from each other, an identification number (1, 2,..., n) is added to the end of the reference numeral of the components of the load element 200. However, when it is not necessary to distinguish the load elements 200 from each other, the identification number at the end of the reference numeral of the components of the load element 200 is omitted.

[0022] The power supply circuit 30 includes a second voltage node 300, a plurality of resistance elements 310, and a third wiring 320. The plurality of resistance elements 310 are arranged on the third wiring 320, and each of the plurality of resistance elements 310 is electrically connected. Note that the second voltage node 300 can be, for example, a node that supplies a power supply voltage. Hereinafter, when it is necessary to distinguish the resistance elements 310 from each other, an identification number (1, 2,..., n) is added to the end of the reference numeral of the component of the resistance element 310. However, when it is not necessary to distinguish the resistance elements 310 from each other, the identification number at the end of the reference numeral of the component of the load element 200 is omitted. Note that the resistance element 310 is formed of a MOS transistor provided as an element, a sheet resistance element, or the like. However, instead of providing the resistance element 310, the parasitic resistance included in the third wiring 320 may be used as the resistance element 310 of the present embodiment.

[0023] In FIG. 1, the first MOS transistor 120 is of P-type, the second MOS transistor 130 is of N-type, the third MOS transistor 140 is of P-type, and the fourth MOS transistor 150 is of N-type. However, the first MOS transistor 120 may be of N-type, the second MOS transistor 130 may be of P-type, the third MOS transistor 140 may be of N-type, and the fourth MOS transistor 150 may be of P-type. In that case, the first voltage node 100 can be, for example, a node that supplies a power supply voltage, and the second voltage node 300 can be, for example, a node that supplies a reference voltage. In the following description, the P-type may be referred to as the first type and the N-type may be referred to as the second type.

[0024] Hereinafter, on the premise that the first MOS transistor 120 and the third MOS transistor 140 are of P-type and the second MOS transistor 130 and the fourth MOS transistor 150 are of N-type, the source and the drain are defined. However, when the first MOS transistor 120 and the third MOS transistor 140 are of N-type and the second MOS transistor 130 and the fourth MOS transistor 150 are of P-type, the source in the following description indicates the drain, and the drain indicates the source.

[0025] The current source 110 is electrically connected to the first voltage node 100, and the first voltage node 100 supplies a reference voltage to the current source 110. The drain of the first MOS transistor 120 is electrically connected to the current source 110. The source of the second MOS transistor 130 is electrically connected to the source of the first MOS transistor 120. The second voltage node 300 is electrically connected to the drain of the second MOS transistor 130, and the second voltage node 300 supplies a power supply voltage to the second MOS transistor 130. That is, the first voltage node 100, the current source 110, the first MOS transistor 120, the second MOS transistor 130, and the second voltage node 300 are electrically connected in sequence. Also, a wiring is arranged to electrically connect the node between the current source 110 and the drain of the first MOS transistor 120 and the node between the gate of the first MOS transistor 120 and the gate of the third MOS transistor 130_1.

[0026] Each of the drains of the plurality of third MOS transistors 140 is electrically connected to each of the corresponding plurality of load elements 200. For example, the drain of the third MOS transistor 140_1 is electrically connected to the load element 200_1.

[0027] Each of the sources of the plurality of fourth MOS transistors 150 is electrically connected to each of the sources of the corresponding plurality of third MOS transistors 140. For example, the source of the fourth MOS transistor 150_1 is electrically connected to the source of the third MOS transistor 140_1.

[0028] The third wiring 320 is electrically connected to the drain of the second MOS transistor 130. Also, the third wiring 320 is electrically connected to each of the drains of the plurality of fourth MOS transistors 150. That is, the drain of the second MOS transistor 130 and each of the drains of the plurality of fourth MOS transistors 150 are electrically connected via the third wiring 320.

[0029] Each of the plurality of resistance elements 310 is arranged between a drain of the second MOS transistor 130 or a drain of the plurality of fourth MOS transistors 150 and a plurality of connection nodes where the third wiring 320 is connected. For example, the resistance element 310_1 is arranged between a connection node where the drain of the second MOS transistor 130 and the third wiring 320 are connected and a connection node where the drain of the fourth MOS transistor 150_1 and the third wiring 320 are connected. That is, the load element 200, the third MOS transistor 140, the fourth MOS transistor 150, the resistance element 310, and the second voltage node 300 are electrically connected in sequence.

[0030] Here, when the load circuit 20 is driven, let the current flowing through the first MOS transistor 120 be I 120 Then, under the saturation condition of the MOS transistor, the following formula (1) holds.

[0031]

Equation

[0032] Note that μ represents the electron mobility, C OX represents the gate oxide capacitance per unit area, W represents the gate width, and L represents the gate length. Also, V gs120 represents the gate-source voltage of the first MOS transistor 120, V th represents the threshold voltage, λ represents the channel length modulation effect coefficient, and V ds120 represents the drain-source voltage of the first MOS transistor 120.

[0033] Also, let the source voltage of the first MOS transistor 120 be V s120 , the gate voltage of the second MOS transistor 130 be V g130 , and the gate-source voltage of the second MOS transistor 130 be V gs130 . Focusing on the second MOS transistor 130, V s120 satisfies the following formula (2).

[0034] [Number]

[0035] Also, let the gate voltage of the first MOS transistor 120 be V g120 , and the voltage between the gate and source of the first MOS transistor 120 be V gs120 . Focusing on the first MOS transistor 120, using Equation (2), V g120 satisfies the following Equation (3).

[0036] [Number]

[0037] Also, when driving the load circuit 20, let the current flowing through the fourth MOS transistor 150 be I 150 , the voltage between the gate and source of the fourth MOS transistor 150 be V gs150 , and the voltage between the drain and source of the second MOS transistor 130 be V ds130 . Also, let the voltage drop in the power supply circuit 30 be ΔV, and the change in current caused by the voltage drop be ΔI d . Under the saturation condition of the MOS transistor, the following Equation (4) holds.

[0038] [Number]

[0039] When Equation (4) is transformed, V gs150 satisfies the following Equation (5).

[0040] [Number]

[0041] Also, when driving the load circuit 20, let the current flowing through the third MOS transistor 140 be I 140 , and the voltage between the gate and source of the third MOS transistor 140 be V gs140, let the drain-source voltage of the third MOS transistor 140 be V ds140 Under the saturation condition of the MOS transistor, the following equation (6) holds.

[0042]

Equation

[0043] Also, let the source voltage of the third MOS transistor 140 be V s140 , and the gate-source voltage of the fourth MOS transistor 150 be V gs150 . Focusing on the fourth MOS transistor 150, V s140 satisfies the following equation (7).

[0044]

Equation

[0045] Also, focusing on the third MOS transistor 140, V gs140 satisfies the following equation (8).

[0046]

Equation

[0047] Here, using Equation (3) and Equation (7) to transform Equation (8), the following Equation (9) holds.

[0048]

Equation

[0049] Here, using Equation (9) to transform Equation (6), the following Equation (10) holds.

[0050]

Equation

[0051] By substituting Equation (5) into Equation (10), I 140 is derived using ΔV. Note that the current fluctuation caused by ΔV affects as a change in the short-channel length effect of the fourth MOS transistor 150 generated by the change in ΔV. Therefore, λ(V ds -ΔV) including ΔV generally satisfies the relationship of "λ(V ds -ΔV)≪1". Thus, I 140 is not greatly affected by ΔV.

[0052] Here, in order to explain the effects of the first embodiment, a circuit according to a comparative reference example will be described. The circuit according to the reference example will be described with reference to FIG. 2.

[0053] FIG. 2 is an example of a circuit diagram of a circuit according to a reference example. Note that the same reference numerals are assigned to the same components as those in the first embodiment, and the description of these components may be omitted or simplified.

[0054] As shown in FIG. 2, the circuit 1 includes a current mirror circuit 10, a load circuit 20, a power supply circuit 30, and a first voltage node 100. Note that the first voltage node 100 may be a node that supplies a reference voltage, for example.

[0055] The current mirror circuit 10 includes a current source 110, a first MOS transistor 120, a fifth MOS transistor 180, a plurality of third MOS transistors 140, and a plurality of sixth MOS transistors 185. Further, the current mirror circuit 10 includes a first wiring 160 and a fourth wiring 190. Note that the first MOS transistor 120 and the plurality of third MOS transistors 140 have a configuration in which the ratio of the gate width to the gate length is substantially equal.

[0056] The first wiring 160 is electrically connected to the gate of the first MOS transistor 120 and supplies a control signal to the gate. Further, the first wiring 160 is electrically connected to each of the gates of the plurality of third MOS transistors 140 and supplies a control signal to each of the gates. That is, the gate of the first MOS transistor 120 and each of the gates of the plurality of third MOS transistors 140 are electrically connected via the first wiring 160.

[0057] The fourth wiring 190 is electrically connected to the gate of the fifth MOS transistor 180 and supplies a control signal to the gate. Further, the fourth wiring 190 is electrically connected to each of the gates of the plurality of sixth MOS transistors 185 and supplies a control signal to each of the gates. That is, the gate of the fifth MOS transistor 180 and each of the gates of the plurality of sixth MOS transistors 185 are electrically connected via the fourth wiring 190. The voltage value applied via the fourth wiring 190 is different from the voltage value applied via the second wiring 170.

[0058] The current source 110, the first MOS transistor 120, and the plurality of third MOS transistors 140 function as a current mirror circuit. By supplying a current from the current source 110 to the first MOS transistor 120, the gate voltage of the first MOS transistor 120 is determined. That gate voltage is applied to each gate of the plurality of third MOS transistors 140 arranged in the corresponding column as a control signal. As a result, a current corresponding to the current flowing through the first MOS transistor 120 is supplied to the load circuit 20 via the plurality of third MOS transistors 140 arranged in the corresponding column. That is, the current value of the current flowing through the electrical path between the first voltage node 100 and the second voltage node 300 described later is substantially equal to the current value of the current flowing through the third MOS transistor 140.

[0059] In the following, when it is necessary to distinguish the third MOS transistors 140 from each other, an identification number (1, 2, …, n) is added to the end of the reference numeral of the components of the third MOS transistor 140. However, when it is not necessary to distinguish the third MOS transistors 140 from each other, the identification number at the end of the reference numeral of the components of the third MOS transistor 140 is omitted. In the following, when it is necessary to distinguish the sixth MOS transistors 185 from each other, an identification number (1, 2, …, n) is added to the end of the reference numeral of the components of the sixth MOS transistor 185. However, when it is not necessary to distinguish the sixth MOS transistors 185 from each other, the identification number at the end of the reference numeral of the components of the sixth MOS transistor 185 is omitted.

[0060] The load circuit 20 has a plurality of load elements 200. In the following, when it is necessary to distinguish the load elements 200 from each other, an identification number (1, 2, …, n) is added to the end of the reference numeral of the components of the load element 200. However, when it is not necessary to distinguish the load elements 200 from each other, the identification number at the end of the reference numeral of the components of the load element 200 is omitted.

[0061] The power supply circuit 30 has a second voltage node 300, a plurality of resistor elements 310, and a third wiring 320. The plurality of resistor elements 310 are arranged on the third wiring 320, and each of the plurality of resistor elements 310 is electrically connected. Note that the second voltage node 300 can be, for example, a node that supplies a power supply voltage. In the following, when it is necessary to distinguish the resistor elements 310 from each other, an identification number (1, 2, …, n) is added to the end of the reference numeral of the components of the resistor element 310. However, when it is not necessary to distinguish the resistor elements 310 from each other, the identification number at the end of the reference numeral of the components of the load element 200 is omitted. Note that the resistor element 310 is formed of a MOS transistor provided as an element, a sheet resistance element, or the like. However, instead of providing the resistor element 310, the parasitic resistance included in the third wiring 320 may be used as the resistor element 310 of the present embodiment.

[0062] In FIG. 2, the first MOS transistor 120, the third MOS transistor 140, the fifth MOS transistor 180, and the sixth MOS transistor 185 are P-type. However, the first MOS transistor 120, the third MOS transistor 140, the fifth MOS transistor 180, and the sixth MOS transistor 185 may be N-type. Also, in that case, the first voltage node 100 may be a node that supplies, for example, a power supply voltage, and the second voltage node 300 may be a node that supplies, for example, a reference voltage.

[0063] Note that hereinafter, on the premise that the first MOS transistor 120, the third MOS transistor 140, the fifth MOS transistor 180, and the sixth MOS transistor 185 are P-type, the source and the drain are defined. However, when the first MOS transistor 120, the third MOS transistor 140, the fifth MOS transistor 180, and the sixth MOS transistor 185 are N-type, the source in the following description indicates the drain, and the drain indicates the source.

[0064] The current source 110 is electrically connected to the first voltage node 100. The drain of the fifth MOS transistor 180 is electrically connected to the current source 110. The drain of the first MOS transistor 120 is electrically connected to the source of the fifth MOS transistor 180. The second voltage node 300 is electrically connected to the source of the first MOS transistor 120. That is, the first voltage node 100, the current source 110, the fifth MOS transistor 180, the first MOS transistor 120, and the second voltage node 300 are electrically connected in sequence. Also, a wiring is arranged to electrically connect the node between the current source 110 and the drain of the fifth MOS transistor 180 and the node between the gate of the first MOS transistor 120 and the gate of the third MOS transistor 130_1.

[0065] Each of the drains of the plurality of sixth MOS transistors 185 is electrically connected to each of the corresponding plurality of load elements 200. For example, the drain of the sixth MOS transistor 185_1 is electrically connected to the load element 200_1.

[0066] Each of the drains of the plurality of third MOS transistors 140 is electrically connected to each of the sources of the corresponding plurality of sixth MOS transistors 185. For example, the drain of the third MOS transistor 140_1 is electrically connected to the source of the sixth MOS transistor 185_1.

[0067] The third wiring 320 is electrically connected to the source of the first MOS transistor 120. Also, the third wiring 320 is electrically connected to each of the sources of the plurality of third MOS transistors 140. That is, the source of the first MOS transistor 120 and each of the sources of the plurality of third MOS transistors 140 are electrically connected via the third wiring 320.

[0068] Each of the plurality of resistor elements 310 is arranged between the source of the first MOS transistor 120 or the sources of the plurality of third MOS transistors 140 and the plurality of connection nodes where the third wiring 320 is connected. For example, a resistor element 310_1 is arranged between the connection node where the source of the first MOS transistor 120 and the third wiring 320 are connected and the connection node where the source of the third MOS transistor 140_1 and the third wiring 320 are connected. That is, the load element 200, the sixth MOS transistor 185, the third MOS transistor 140, the resistor element 310, and the second voltage node 300 are electrically connected in sequence.

[0069] Note that the current mirror circuit 10 may not have the fifth MOS transistor 180, the plurality of sixth MOS transistors 185, and the fourth wiring 190. In that case, the drain of the first MOS transistor 120 is electrically connected to the current source 110. That is, the first voltage node 100, the current source 110, the first MOS transistor 120, and the second voltage node 300 are electrically connected in sequence. Also, each of the drains of the plurality of third MOS transistors 140 is electrically connected to each of the corresponding plurality of load elements 200. For example, the drain of the third MOS transistor 140_1 is electrically connected to the load element 200_1.

[0070] Here, when the load circuit 20 is driven, let the current flowing through the third MOS transistor 140 be I 140 and the gate-source voltage of the first MOS transistor 120 be V gs120 and the drain-source voltage of the third MOS transistor 140 be V ds140 . Also, let the voltage drop amount in the power supply circuit 30 be ΔV and the change amount of the current caused by the voltage drop be ΔI d . Under the saturation condition of the MOS transistor, the following equation (11) holds.

[0071]

Equation

[0072] In Equation (11), V gs120ΔV decreases. Here, an electrical path via a third wiring 320 between the source of the first MOS transistor 120 and the source of the third MOS transistor 140_1 is defined as a first electrical path. Also, an electrical path via a third wiring 320 between the source of the first MOS transistor 120 and the source of the third MOS transistor 140_n is defined as an nth electrical path. The length of the nth electrical path becomes longer as n increases. That is, the length of the third wiring 320 included in the nth electrical path is longer than the length of the third wiring 320 included in the first electrical path. Therefore, the number of resistance elements 310 included in the nth electrical path is larger than the number of resistance elements 310 included in the first electrical path. That is, ΔV in the third wiring 320 included in the nth electrical path is larger than ΔV in the third wiring 320 included in the first electrical path.

[0073] Therefore, since ΔV varies according to the electrical path, a difference occurs in the current flowing through each of the plurality of third MOS transistors 140, and the accuracy with which the current mirror circuit 10 replicates the current decreases. Note that ΔV may also vary depending on the distribution of the arrangement of the plurality of load elements 200 in the driving state, or the number of the plurality of load elements 200 in the driving state, or the current flowing through the first MOS transistor 120, and the accuracy of replicating the current may decrease.

[0074] The reference example is I 140 has a direct impact on ΔV. On the other hand, in the first embodiment, since ΔV indirectly affects I 140 via the fourth MOS transistor 150, I 140 is not greatly affected by ΔV. Therefore, a difference is less likely to occur in the current flowing through each of the plurality of third MOS transistors 140, and a decrease in the accuracy with which the current mirror circuit 10 replicates the current is suppressed.

[0075] Note that the MOS transistor described above may be a bipolar transistor. Instead of the P-type MOS transistor, a PNP bipolar transistor can be used, and instead of the N-type MOS transistor, an NPN bipolar transistor can be used. Each of the gate, source, and drain of the MOS transistor described in this embodiment can be the base, emitter, and collector, respectively.

[0076] The photoelectric conversion device according to the modified example of the first embodiment of the present invention will be described with reference to FIG. 3. Note that the same reference numerals are assigned to the same components as those in the first embodiment, and the description of these components may be omitted or simplified.

[0077] In the modified example of the first embodiment, the number of circuit blocks included in circuit 1 is different from that in the first embodiment. FIG. 3 is an example of a circuit diagram of the circuit according to this modified example.

[0078] As shown in FIG. 3, circuit 1 includes a current mirror circuit 10 divided into a plurality of blocks, a load circuit 20 divided into a plurality of blocks, and a power supply circuit 30 divided into a plurality of blocks. Here, as shown in FIG. 1, a configuration in which a plurality of third MOS transistors 140, a plurality of fourth MOS transistors 150, a plurality of load elements 200, and a plurality of resistance elements 310 are provided in n columns is regarded as one first circuit block. On the other hand, as shown in FIG. 3, a configuration in which a plurality of third MOS transistors 140, a plurality of fourth MOS transistors 150, a plurality of load elements 200, and a plurality of resistance elements 310 are provided in, for example, n / 4 columns is regarded as one second circuit block. The second circuit block includes a first voltage node 100, a current source 110, a first MOS transistor 120, a second MOS transistor 130, and a second voltage node 300. FIG. 3 has four independent second circuit blocks. Note that the number of columns included in one second circuit block is not limited to n / 4, and may be n / m (m is an arbitrary natural number). In that case, circuit 1 has m independent second circuit blocks.

[0079] Therefore, in this modified example, it is difficult for a difference to occur in the current flowing through each of the plurality of third MOS transistors 140, and it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current.

[0080] Furthermore, in this modified example, since the number of independent circuit blocks included in the circuit 1 increases, it is possible to reduce the influence of voltage drop in each circuit block, and it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current.

[0081] <Second Embodiment> A circuit according to a second embodiment of the present invention will be described with reference to FIG. 4. Note that the same reference numerals are assigned to the same components as those in the first embodiment, and the description of these components may be omitted or simplified.

[0082] The second embodiment is different from the first embodiment in the configuration of the current mirror circuit 10. FIG. 4 is an example of a circuit diagram of the circuit according to this embodiment.

[0083] As shown in FIG. 4, the circuit 1 includes a current mirror circuit 10, a load circuit 20, a power supply circuit 30, and a first voltage node 100. Note that the first voltage node 100 can be, for example, a node that supplies a reference voltage.

[0084] The current mirror circuit 10 includes a current source 110, a first MOS transistor 120, a second MOS transistor 130, and a fifth MOS transistor 180. Furthermore, the current mirror circuit 10 includes a plurality of third MOS transistors 140, a plurality of fourth MOS transistors 150, and a plurality of sixth MOS transistors 185. Furthermore, the current mirror circuit 10 includes a first wiring 160, a second wiring 170, and a fourth wiring 190. Note that the first MOS transistor 120 and the plurality of third MOS transistors 140 are configured such that the ratio of the gate width to the gate length is substantially equal.

[0085] The fourth wiring 190 is electrically connected to the gate of the fifth MOS transistor 180 and supplies a control signal to the gate. Further, the fourth wiring 190 is electrically connected to each of the gates of the plurality of sixth MOS transistors 185 and supplies a control signal to each of the gates. That is, the gate of the fifth MOS transistor 180 and each of the gates of the plurality of sixth MOS transistors 185 are electrically connected via the fourth wiring 190. The voltage value applied via the fourth wiring 190 is different from the voltage value applied via the second wiring 170.

[0086] The load circuit 20 has a plurality of load elements 200.

[0087] The power supply circuit 30 has a second voltage node 300, a plurality of resistor elements 310, and a third wiring 320. The plurality of resistor elements 310 are arranged on the third wiring 320, and each of the plurality of resistor elements 310 is electrically connected. Note that the second voltage node 300 can be, for example, a node that supplies a power supply voltage.

[0088] In FIG. 4, the first MOS transistor 120, the third MOS transistor 140, the fifth MOS transistor 180, and the sixth MOS transistor 185 are P-type. Also, the second MOS transistor 130 and the fourth MOS transistor 150 are N-type. However, the first MOS transistor 120, the third MOS transistor 140, the fifth MOS transistor 180, and the sixth MOS transistor 185 may be N-type. Also, in that case, the second MOS transistor 130 and the fourth MOS transistor 150 may be P-type. Further, in that case, the first voltage node 100 can be, for example, a node that supplies a power supply voltage, and the second voltage node 300 can be, for example, a node that supplies a reference voltage.

[0089] The current source 110 is electrically connected to the first voltage node 100, and the first voltage node 100 supplies a reference voltage to the current source 110. The drain of the fifth MOS transistor 180 is electrically connected to the current source 110. The drain of the first MOS transistor 120 is electrically connected to the source of the fifth MOS transistor 180. The source of the second MOS transistor 130 is electrically connected to the source of the first MOS transistor 120. The second voltage node 300 is electrically connected to the drain of the second MOS transistor 130, and the second voltage node 300 supplies a power supply voltage to the second MOS transistor 130. That is, the first voltage node 100, the current source 110, the fifth MOS transistor 180, the first MOS transistor 120, the second MOS transistor 130, and the second voltage node 300 are electrically connected in sequence. Also, a wiring is arranged to electrically connect the node between the current source 110 and the drain of the fifth MOS transistor 180 and the node between the gate of the first MOS transistor 120 and the gate of the third MOS transistor 130_1.

[0090] Each of the drains of the plurality of sixth MOS transistors 185 is electrically connected to each of the corresponding plurality of load elements 200. For example, the drain of the sixth MOS transistor 185_1 is electrically connected to the load element 200_1.

[0091] Each of the drains of the plurality of third MOS transistors 140 is electrically connected to each of the sources of the corresponding plurality of sixth MOS transistors 185. For example, the drain of the third MOS transistor 140_1 is electrically connected to the source of the sixth MOS transistor 185_1.

[0092] Each of the sources of the plurality of fourth MOS transistors 150 is electrically connected to each of the sources of the corresponding plurality of third MOS transistors 140. For example, the source of the fourth MOS transistor 150_1 is electrically connected to the source of the third MOS transistor 140_1.

[0093] The third wiring 320 is electrically connected to the drain of the second MOS transistor 130. Also, the third wiring 320 is electrically connected to each of the drains of the plurality of fourth MOS transistors 150. That is, the drain of the second MOS transistor 130 and each of the drains of the plurality of fourth MOS transistors 150 are electrically connected via the third wiring 320.

[0094] Each of the plurality of resistance elements 310 is disposed between a plurality of connection nodes where the drain of the second MOS transistor 130 or the drains of the plurality of fourth MOS transistors 150 and the third wiring 320 are connected. For example, a resistance element 310_1 is disposed between a connection node where the drain of the second MOS transistor 130 and the third wiring 320 are connected and a connection node where the drain of the fourth MOS transistor 150_1 and the third wiring 320 are connected. That is, the load element 200, the sixth MOS transistor 185, the third MOS transistor 140, the fourth MOS transistor 150, the resistance element 310, and the second voltage node 300 are electrically connected in sequence.

[0095] Therefore, in this embodiment, it is difficult for a difference to occur in the current flowing through each of the plurality of third MOS transistors 140, and it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current.

[0096] Furthermore, in this embodiment, since circuit elements having a similar configuration are electrically connected to the drain of the first MOS transistor 120 and the drain of the third MOS transistor 140, it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current. This is because the fifth MOS transistor 180 is electrically connected to the drain of the first MOS transistor 120 and the sixth MOS transistor 185 is electrically connected to the drain of the third MOS transistor 140. That is, since the difference between the drain-source voltage of the first MOS transistor 120 and the drain-source voltage of the third MOS transistor 140 becomes small, it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current.

[0097] Note that the MOS transistor described above may be a bipolar transistor. Instead of the P-type MOS transistor, a PNP bipolar transistor can be used, and instead of the N-type MOS transistor, an NPN bipolar transistor can be used. Each of the gate, source, and drain of the MOS transistor described in this embodiment can be the base, emitter, and collector, respectively.

[0098] The photoelectric conversion device according to a modification of the second embodiment of the present invention will be described with reference to FIG. 5. Note that the same reference numerals are given to the same components as those in the second embodiment, and the description of these components may be omitted or simplified.

[0099] In the modification of the second embodiment, the number of circuit blocks included in circuit 1 is different from that in the second embodiment. FIG. 5 is an example of a circuit diagram of the circuit according to this modification.

[0100] As shown in FIG. 5, circuit 1 includes a current mirror circuit 10 divided into a plurality of blocks, a load circuit 20 divided into a plurality of blocks, and a power supply circuit 30 divided into a plurality of blocks. Here, as shown in FIG. 4, a configuration in which a plurality of third MOS transistors 140, a plurality of fourth MOS transistors 150, a plurality of sixth MOS transistors 185, a plurality of load elements 200, and a plurality of resistor elements 310 are provided in n columns is regarded as one first circuit block. On the other hand, as shown in FIG. 5, a configuration in which a plurality of third MOS transistors 140, a plurality of fourth MOS transistors 150, a plurality of sixth MOS transistors 185, a plurality of load elements 200, and a plurality of resistor elements 310 are provided in n / 4 columns is regarded as one second circuit block. Further, the second circuit block includes a first voltage node 100, a current source 110, a first MOS transistor 120, a second MOS transistor 130, a fifth MOS transistor 180, and a second voltage node 300. FIG. 5 has four independent second circuit blocks. Note that the number of columns included in one second circuit block is not limited to n / 4 and may be n / m (m is an arbitrary natural number). In that case, circuit 1 has m independent second circuit blocks.

[0101] Therefore, in this modified example, it is difficult for a difference to occur in the current flowing through each of the plurality of third MOS transistors 140, and it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current.

[0102] Furthermore, in this modified example, as the number of independent circuit blocks included in circuit 1 increases, it is possible to reduce the influence of voltage drop in each circuit block, and it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current.

[0103] <Third Embodiment> A driver IC according to the third embodiment of the present invention will be described with reference to FIG. 6. Note that the same reference numerals are given to the same components as those in the first and second embodiments, and the description of these components may be omitted or simplified.

[0104] The third embodiment is applicable to both the first embodiment and the second embodiment. FIG. 6 is an example of a schematic diagram for explaining a driver IC including the circuits of the above-described embodiments.

[0105] As shown in FIG. 6, the driver IC 40 includes a current source array 50, a load element array 60, a first voltage wiring 70, a second voltage wiring 80, a first voltage pad 90, and a second voltage pad 95. The current source array 50 has a plurality of current mirror circuits 10 arranged in parallel in the horizontal direction. The load element array 60 has a plurality of load circuits 20 arranged in parallel in the horizontal direction. The first voltage wiring 70 has a plurality of first voltage nodes 100 arranged in parallel in the horizontal direction. The second voltage wiring 80 has a plurality of power supply circuits 30 arranged in parallel in the horizontal direction. Circuit 1 has a part of each of the current source array 50, the load element array 60, the first voltage wiring 70, and the second voltage wiring 80.

[0106] The first voltage supplied to the first voltage pad 90 is supplied to Circuit 1 via the first voltage node 100. Also, the second voltage supplied to the second voltage pad 95 is supplied to Circuit 1 via the second voltage node 300. Note that the first voltage node 100 may be a node that supplies, for example, a reference voltage, and the second voltage node 300 may be a node that supplies, for example, a power supply voltage.

[0107] This embodiment is provided on a semiconductor chip, but in order to reduce the cost of the semiconductor chip, it is desirable to reduce the distance in the vertical direction. On the other hand, since a plurality of rows of Circuit 1 are provided in the horizontal direction, the distance in the horizontal direction may be longer than the distance in the vertical direction. In such a configuration, the first voltage wiring 70 and the second voltage wiring 80 may have high resistance, and the accuracy with which the current mirror circuit 10 replicates current may decrease.

[0108] However, since the driver IC 40 includes Circuit 1 of the above-described embodiment, a decrease in the accuracy with which the current mirror circuit 10 replicates current is suppressed.

[0109] Note that the load element array 60 may not be included in the driver IC 40. For example, the load element array 60 may be provided outside the semiconductor chip on which the driver IC 40 is provided.

[0110] <Fourth Embodiment> The light-emitting device according to the fourth embodiment of the present invention will be described with reference to FIG. 7. Note that the same reference numerals are given to the same components as those in the first, second, and third embodiments, and the description of these components may be omitted or simplified.

[0111] FIG. 7 is an example of a schematic diagram for explaining a light-emitting device including the driver IC of the third embodiment. The light-emitting device of this embodiment can be used, for example, as an exposure light source of an image forming apparatus. The light-emitting device of this embodiment has a rectangular shape having a long side parallel to the first direction and a short side parallel to the direction intersecting the first direction. For example, the first direction may be a direction along the rotation axis direction of the photoreceptor of the image forming apparatus.

[0112] As shown in FIG. 7, the substrate 701 has a polygonal shape, and here, an example of a rectangular substrate 701 will be described. In this specification, the long side direction of the rectangular substrate 701 is referred to as the first direction, and the short side direction orthogonal to the long side direction is referred to as the second direction. In addition, the polygon in this specification includes a shape with rounded corners. A moisture-resistant ring 700 that serves to suppress and prevent the intrusion of moisture into the light-emitting device is disposed on the rectangular substrate 701. The moisture-resistant ring 700 can be, for example, a guard ring formed of a wiring layer.

[0113] Inside the moisture-resistant ring 700, a light-emitting region 702, a contact region 703, and a circuit region 704 are arranged. In this embodiment, the contact region 703 has a first contact region 703_1, a second contact region 703_2, and a third contact region 703_3.

[0114] The circuit region 704 is a part of the circuit for driving each light-emitting device. Specific examples include, but are not limited to, an input protection circuit, an input circuit to which data for each drive is input, a logic circuit for processing data, etc. Further, the circuit region 704 includes the driver IC 40.

[0115] In the light-emitting region 702, light-emitting elements EL are arranged side by side in a matrix direction. The contact region 703 is a region where wirings for electrically connecting to the common electrode of the light-emitting element EL are arranged.

[0116] The outer peripheral shape of the moisture-resistant ring 700 may include a plurality of recessed portions. This portion can be used, for example, as a contact region for abutting a rib which is a part of a mask for vapor deposition in a film-forming process.

[0117] Each of the plurality of light-emitting elements EL arranged side by side in a matrix in the light-emitting region 702 is composed of a light-emitting layer, a first electrode and a second electrode sandwiching the light-emitting layer. In the present embodiment, an example is shown in which the first electrode is an independent electrode provided for each light-emitting element EL, and the second electrode is a common electrode provided in common for each light-emitting element EL.

[0118] For example, in the light-emitting region 702, when the light-emitting elements EL are arranged in 4 rows, as illustrated in FIG. 7, the first position of the light-emitting elements EL in the first row and the first position of the light-emitting elements EL in the second row may be shifted in the X direction by 1 / 4 of the X-direction dimension of the light-emitting element EL. When there are N rows where N is an integer of 2 or more, the first position of the light-emitting elements EL in the first row and the first position of the light-emitting elements EL in the second row may be shifted in the X direction by 1 / N of the X-direction dimension of the light-emitting element EL. Such a configuration is advantageous for improving the resolution.

[0119] The contact region 703 is an adjacent region of the light-emitting region 702 of the substrate 701 and is arranged inside the moisture-resistant ring 700. Further, at least one of the contact region 703 and the circuit region 704 may be arranged between the light-emitting region 702 and one long-side end of the substrate 701 together with the recess of the moisture-resistant ring 700 and arranged in series in the long-side direction.

[0120] In this way, by providing the contact region 703, the circuit region 704, etc. at the same position in the short side direction, the length of the light-emitting device in the short side direction can be reduced, and the light-emitting device can be miniaturized.

[0121] The light-emitting device of this embodiment has a plurality of contact regions 703 between the common electrode of the light-emitting element EL and the power supply wiring along the long side end of the light-emitting device. When the common electrode is made of, for example, a transparent electrode material with a relatively high electrical resistance, the voltage drop amount may be large in the major axis direction. Therefore, depending on the distance from the contact region where the potential is supplied, there is a difference in the voltage applied to each OLED. As a result, among the OLEDs to which the same voltage for emitting the same luminance is applied, the actual emission luminance is different, and shading or the like may occur. By having a plurality of contact regions 703 in the major axis direction as in this embodiment, the voltage drop of the common electrode in the long side direction can be suppressed, and the occurrence of shading or the like can be suppressed.

[0122] By the light-emitting device including the driver IC 40 of the above embodiment, it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates the current.

[0123] <Fifth Embodiment> An image forming apparatus according to a fifth embodiment of the present invention will be described with reference to FIG. 8. Note that the same reference numerals are assigned to the same components as those in the first, second, third, and fourth embodiments, and the description of these components may be omitted or simplified.

[0124] FIG. 8 is an example of a schematic diagram for explaining an image forming apparatus including the light-emitting device of the fourth embodiment. An example in which the light-emitting device is used as an exposure light source of the image forming apparatus will be described with reference to FIG. 8.

[0125] FIG. 8(a) is a schematic diagram of an image forming apparatus 800 according to an embodiment of the present invention. The image forming apparatus includes a photoreceptor, an exposure light source, a developing unit, a charging unit, a transferrer, a conveyance roller, and a fixing unit.

[0126] Light 815 is irradiated from an exposure light source 810 provided opposite to the photoreceptor 805, and an electrostatic latent image is formed on the surface of the photoreceptor 805. This exposure light source has an organic light emitting element according to the present invention. The developing unit 825 has toner or the like. The charging unit 820 charges the photoreceptor. The transferrer 830 transfers the developed image onto a recording medium 840. The conveyance unit 835 conveys the recording medium 840. The recording medium 840 is, for example, paper. The fixing unit 845 fixes the image formed on the recording medium 840.

[0127] FIGS. 8(b) and 8(c) are schematic diagrams showing a state in which a plurality of light emitting portions 850 are arranged on a long substrate in the exposure light source 810. 855 is a direction parallel to the axis of the photoreceptor and represents the column direction in which the organic light emitting elements are arranged. This column direction is the same as the direction of the axis around which the photoreceptor 805 rotates. This direction can also be called the major axis direction of the photoreceptor.

[0128] FIG. 8(b) shows a form in which the light emitting portions are arranged along the major axis direction of the photoreceptor. FIG. 8(c) shows a form different from (b), in which the light emitting portions are alternately arranged in the column direction in each of the first column and the second column. The first column and the second column are arranged at different positions in the row direction.

[0129] In the first column, a plurality of light emitting portions are arranged at intervals. The second column has light emitting portions at positions corresponding to the intervals between the light emitting portions in the first column. That is, also in the row direction, a plurality of light emitting portions are arranged at intervals.

[0130] The arrangement in FIG. 8(c) can also be described as, for example, a state of being arranged in a grid pattern, a state of being arranged in a staggered grid, or a checkerboard pattern.

[0131] By the image forming apparatus including the light emitting device of the above-described embodiment, it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 duplicates a current.

[0132] <Sixth Embodiment> A display device according to a sixth embodiment of the present invention will be described with reference to FIG. 9. Note that the same reference numerals are given to the same components as those in the first to fifth embodiments, and descriptions of these components may be omitted or simplified.

[0133] FIG. 9 is an example of a schematic diagram for explaining an image forming apparatus including the light emitting device of the fourth embodiment. An example in which the light emitting device is used for a head substrate 900 of an exposure head of an image forming apparatus will be described with reference to FIG. 9.

[0134] FIG. 9(a) is a schematic perspective view of the head substrate 900. FIG. 9(b) shows an arrangement of a plurality of light emitting elements EL provided on the head substrate 900, and FIG. 9(c) shows an enlarged view of a part of FIG. 9(b).

[0135] An LED chip 903 is mounted on the head substrate 900. As the LED chip 903, for example, the light emitting device described in the fourth embodiment can be used.

[0136] As shown in FIG. 9(a), the LED chip 903 is provided on one surface of the head substrate 900, and a long flexible flat cable (FFC) connector 907 is provided on the other surface. One surface of the head substrate 900 referred to here is the surface (upper surface, front surface) on which the LED chip 903 is provided. The other surface of the substrate is the surface (lower surface, back surface) opposite to the side on which the LED chip 903 is provided.

[0137] The FFC connector 907 is attached to the other surface (lower surface, back surface) of the head substrate 900 such that its longitudinal direction is along the longitudinal direction of the head substrate 900. The long FFC connector 907 is provided for inputting a control signal (drive signal) from the control circuit section of the apparatus main body of the image forming apparatus, and the control signal is transferred to each LED chip 903. The LED chip 903 is driven (light emission, lighting and extinguishing operation) by the control signal input to the head substrate 900.

[0138] The LED chip 903 mounted on the head substrate 900 will be described. As shown in FIGS. 9(b) and 9(c), a plurality of light emitting elements EL are arranged on one surface of the head substrate 900. For example, LED chips 903-1 to 903-29 (29 pieces) are arranged. In FIG. 9(b), LED chips 903_1, 903_13, 903_14, 903_15, 903_16, and 903_29 are illustrated. Each of the LED chips 903-1 to 903-29 has a plurality of light emitting elements EL arranged in its longitudinal direction, and for example, 516 light emitting elements EL are arranged.

[0139] In the longitudinal direction of the LED chip 903, the center-to-center distance k2 between adjacent light emitting elements EL corresponds to the resolution of the image forming apparatus. For example, when the resolution of the image forming apparatus of this embodiment is 1200 dpi, in the longitudinal direction of the LED chips 903-1 to 903-29, the light emitting elements EL are arranged such that the center-to-center distance k2 between adjacent light emitting elements EL is 21.16 μm. Therefore, the exposure range of the exposure head of this embodiment is about 314 mm.

[0140] The photosensitive layer of the photosensitive drum is formed with a width of 314 mm or more. Since the length of the long side of the A4 size recording paper and the length of the short side of the A3 size recording paper are 297 mm, the exposure head of this embodiment has an exposure range capable of forming an image on the A4 size recording paper and the A3 size recording paper. In FIG. 9, an example in which a plurality of light emitting elements EL are arranged in the longitudinal direction is shown, but the light emitting elements EL may be arranged in the short side direction in addition to the longitudinal direction.

[0141] LED chips 903-1 to 903-29 are arranged in a plurality along the axial direction of the photosensitive drum. Specifically, LED chips 903-1 to 903-29 are alternately arranged in two rows along the axial direction of the photosensitive drum. That is, as shown in Fig. 9(b), starting from the left, the odd-numbered LED chips 903-1, 903-3, ··· 903-29 are mounted in a row in the longitudinal direction of the substrate 900. Also, starting from the left, the even-numbered LED chips 903-2, 903-4, ··· 903-28 are mounted in a row in the longitudinal direction of the substrate 900. The LED chips 903 are arranged in this way.

[0142] Thereby, as shown in Fig. 9(c), in the longitudinal direction of the LED chip 903, the center-to-center distance k1 of the light-emitting elements EL can be made equal to the center-to-center distance k2 of the light-emitting elements EL. Here, the center-to-center distance k1 of the light-emitting elements EL indicates the center-to-center distance of the light-emitting elements EL arranged at one end of the LED chip 903_13 and the other end of the LED chip 903_14. Also, the center-to-center distance k2 of the light-emitting elements EL indicates the center-to-center distance k2 of the adjacent light-emitting elements EL in the LED chip 903_14.

[0143] That is, the center-to-center distance k1 of the adjacent light-emitting elements EL arranged at one end of the LED chip 903 and the other end of the other LED chip 903 can be made equal to the center-to-center distance k2 of the adjacent light-emitting elements EL on one LED chip 903.

[0144] Note that in this embodiment, the light-emitting element EL is an organic light-emitting element and is a current-driven light-emitting element. The organic light-emitting elements are arranged, for example, in a line on a TFT (Thin Film Transister) substrate along the main scanning direction (axial direction of the photosensitive drum 2), and are electrically connected in parallel by a power supply wiring provided along the same main scanning direction.

[0145] When the light-emitting device is used in the exposure head, since exposure is performed linearly, the ratio of the longitudinal direction (first direction X) to the short transverse direction (second direction Y) of the light-emitting region 702 is larger than when the light-emitting device is used in a display device or the like. Also, the ratio of the longitudinal direction (first direction X) to the short transverse direction (third direction Y) of the shape of the substrate of the LED chip becomes larger.

[0146] Specifically, for example, the length of the long side of the LED chip is 5 times or more the length of the short side of the LED chip, and may be 10 times or more. For example, the length of the long side of the LED chip can be 20 times or more the length of the short side of the LED chip.

[0147] The LED chip 903 may have a color filter. By having a color filter, it is possible to absorb stray light from an unintended direction without reducing the normal amount of light incident on the photosensitive drum, thereby improving the printing quality.

[0148] By the image forming apparatus including the light-emitting device of the above embodiment, it is possible to suppress a decrease in the accuracy with which the current mirror circuit 10 replicates a current.

[0149] <Seventh Embodiment> The display device according to the seventh embodiment of the present invention will be described with reference to FIG. 10. Note that the same reference numerals are given to the same components as those in the first to sixth embodiments, and the description of these components may be omitted or simplified. The display device according to the present embodiment includes the driver IC of the third embodiment.

[0150] FIG. 10 is a schematic diagram showing an example of a display device according to the present embodiment. The display device 1000 may include a touch panel 1003, a display panel 1005, a frame 1006, a circuit board 1007, and a battery 1008 between an upper cover 1001 and a lower cover 1009. The touch panel 1003 and the display panel 1005 are connected to flexible printed circuits FPC 1002 and 1004. A transistor is printed on the circuit board 1007. The battery 1008 may not be provided if the display device is not a portable device, or may be provided at another position even if it is a portable device.

[0151] The display device according to the present embodiment may include a color filter having red, green, and blue. The red, green, and blue of the color filter may be arranged in a delta array.

[0152] The display device according to the present embodiment may be used for a display unit of a portable terminal. In that case, it may have both a display function and an operation function. Examples of the portable terminal include mobile phones such as smartphones, tablets, and head-mounted displays.

[0153] The display device according to the present embodiment may be used for a display unit of an imaging device having an optical unit having a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may have a display unit that displays information acquired by the imaging element. Further, the display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed in the viewfinder. The imaging device may be a digital camera or a digital video camera.

[0154] <Eighth Embodiment> An imaging device according to the eighth embodiment of the present invention will be described with reference to FIG. 11. Note that the same reference numerals are assigned to the same components as those in the first to seventh embodiments, and the description of these components may be omitted or simplified. The imaging device according to the present embodiment includes the driver IC of the third embodiment.

[0155] FIG. 11(a) is a schematic diagram showing an example of an imaging device according to the present embodiment. The imaging device 1100 may include a viewfinder 1101, a rear display 1102, an operation unit 1103, and a housing 1104. The viewfinder 1101 may include a display device according to the present embodiment. In that case, the display device may display not only the image to be captured but also environmental information, imaging instructions, and the like. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject moves, the possibility that the subject is blocked by an obstacle, and the like.

[0156] Since the timing suitable for imaging is a very short time, it is better to display information as soon as possible. Therefore, it is preferable to use the display device using the organic light emitting element of the present invention. This is because the organic light emitting element has a high response speed. The display device using the organic light emitting element can be more preferably used than these devices, such as a liquid crystal display device, which require a high display speed.

[0157] The imaging device 1100 has an optical unit (not shown). The optical unit has a plurality of lenses and forms an image on an image sensor housed in the housing 1104. The plurality of lenses can adjust the focus by adjusting their relative positions. This operation can also be performed automatically. The imaging device may be called a photoelectric conversion device. The photoelectric conversion device may include, as an imaging method, a method of detecting the difference from the previous image instead of sequentially imaging, a method of cutting out from the image always recorded, and the like.

[0158] Figure 11(b) is a schematic diagram showing an example of an electronic device according to the present embodiment. The electronic device 1200 includes a display unit 1201, an operation unit 1202, and a housing 1203. The housing 1203 may include a circuit, a printed circuit board having the circuit, a battery, and a communication unit. The operation unit 1202 may be a button or a reaction unit of a touch panel method. The operation unit may be a biometric recognition unit that recognizes a fingerprint and performs unlocking or the like. An electronic device having a communication unit can also be called a communication device. The electronic device may further have a camera function by including a lens and an imaging device. An image captured by the camera function is displayed on the display unit. Examples of the electronic device include a smartphone and a notebook personal computer.

[0159] <9th Embodiment> The display device according to the 9th embodiment of the present invention will be described with reference to FIG. 12. Note that the same reference numerals are given to the same components as those in the 1st to 8th embodiments, and the description of these components may be omitted or simplified. The display device according to the present embodiment includes the driver IC of the 3rd embodiment.

[0160] FIG. 12 is a schematic diagram showing an example of the display device according to the present embodiment. FIG. 12(a) shows a display device such as a TV monitor or a PC monitor. The display device 1300 has a frame 1301 and a display unit 1302. The light-emitting device according to the present embodiment may be used for the display unit 1302.

[0161] It has a frame 1301 and a base 1303 that supports the display unit 1302. The base 1303 is not limited to the form of FIG. 12(a). The lower side of the frame 1301 may also serve as the base.

[0162] In addition, the frame 1301 and the display unit 1302 may be bent. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0163] FIG. 12(b) is a schematic diagram showing another example of the display device according to the present embodiment. The display device 1310 in FIG. 12(b) is configured to be foldable and is a so-called foldable display device. The display device 1310 includes a first display unit 1311, a second display unit 1312, a housing 1313, and a bending point 1314. The first display unit 1311 and the second display unit 1312 may include a light-emitting device according to the present embodiment. The first display unit 1311 and the second display unit 1312 may be a single seamless display device. The first display unit 1311 and the second display unit 1312 can be separated at the bending point. The first display unit 1311 and the second display unit 1312 may display different images, or may display a single image together with the first and second display units.

[0164] <10th Embodiment> The lighting device according to the 10th embodiment of the present invention will be described with reference to FIG. 13. Note that the same reference numerals are assigned to the same components as those in the 1st to 9th embodiments, and the description of these components may be omitted or simplified. The lighting device according to the present embodiment includes the driver IC of the 3rd embodiment.

[0165] FIG. 13(a) is a schematic diagram showing an example of the lighting device according to the present embodiment. The lighting device 1400 may include a housing 1401, a light source 1402, a circuit board 1403, an optical film 1404, and a light diffusion unit 1405. The light source may include an organic light-emitting element according to the present embodiment. The optical filter may be a filter that improves the color rendering property of the light source. The light diffusion unit can effectively diffuse the light of the light source, such as lighting up, and deliver the light to a wide range. The optical filter and the light diffusion unit may be provided on the light-emitting side of the lighting. If necessary, a cover may be provided on the outermost side.

[0166] The lighting device is, for example, a device for illuminating a room. The lighting device may emit light of any color from white, warm white, to other colors from blue to red. It may have a dimming circuit for dimming them. The lighting device may have the organic light-emitting element of the present invention and a power supply circuit connected thereto. The power supply circuit is a circuit that converts an AC voltage into a DC voltage. Also, white means a color temperature of 4200 K and warm white means a color temperature of 5000 K. The lighting device may have a color filter.

[0167] Further, the lighting device according to the present embodiment may have a heat radiating part. The heat radiating part releases the heat inside the device to the outside of the device, and examples thereof include metals with high specific heat and liquid silicon.

[0168] FIG. 13(b) is a schematic diagram of an automobile which is an example of a moving body according to the present embodiment. The automobile has a tail lamp which is an example of a lighting device. The automobile 1500 may have a tail lamp 1501 and may be configured to turn on the tail lamp when a braking operation or the like is performed.

[0169] The tail lamp 1501 may have the organic light-emitting element according to the present embodiment. The tail lamp may have a protective member for protecting the organic EL element. The protective member has a certain degree of strength and may be made of any material as long as it is transparent, but is preferably made of polycarbonate or the like. A phthalic acid derivative, an acrylonitrile derivative, or the like may be mixed into the polycarbonate.

[0170] The automobile 1500 may have a vehicle body 1503 and a window 1502 attached thereto. The window may be a transparent display as long as it is not a window for checking the front and rear of the automobile. The transparent display may have the organic light-emitting element according to the present embodiment. In this case, the constituent materials such as the electrodes of the organic light-emitting element are made of transparent members.

[0171] The moving body according to the present embodiment may be a ship, an aircraft, a drone, or the like. The moving body may have a fuselage and lighting devices provided on the fuselage. The lighting devices may emit light for indicating the position of the fuselage. The lighting devices have the organic light-emitting element according to the present embodiment.

[0172] <11th Embodiment> A wearable device according to the 11th embodiment of the present invention will be described with reference to FIG. 14. Note that the same reference numerals are assigned to the same components as those in the first to tenth embodiments, and the descriptions of these components may be omitted or simplified. The wearable device according to the present embodiment includes the driver IC of the third embodiment.

[0173] With reference to FIG. 14, application examples of the display devices of the above-described embodiments will be described. The display device can be applied to a system that can be worn as a wearable device such as, for example, smart glasses, an HMD, or smart contacts. The imaging display device used in such an application example includes an imaging device capable of photoelectrically converting visible light and a display device capable of emitting visible light.

[0174] FIG. 14(a) illustrates glasses 1600 (smart glasses) according to one application example. An imaging device 1602 such as a CMOS sensor or a SPAD is provided on the front surface side of the lens 1601 of the glasses 1600. Further, the display device of each of the above-described embodiments is provided on the back surface side of the lens 1601.

[0175] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the imaging device 1602 and the display device according to each embodiment. Further, the control device 1603 controls the operations of the imaging device 1602 and the display device. An optical system for condensing light onto the imaging device 1602 is formed in the lens 1601.

[0176] FIG. 14(b) illustrates glasses 1610 (smart glasses) according to one application example. The glasses 1610 have a control device 1612. An imaging device corresponding to the imaging device 1602 and a display device are mounted on the control device 1612. An optical system for projecting light emitted by the display device in the control device 1612 is formed on the lens 1611, and an image is projected on the lens 1611. The control device 1612 functions as a power source for supplying power to the imaging device and the display device, and controls the operations of the imaging device and the display device. The control device may have a gaze detection unit for detecting the wearer's gaze. Infrared rays may be used for gaze detection. The infrared light emitting unit emits infrared light to the eyeball of the user who is gazing at the display image. The imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an imaging image of the eyeball. By having a reducing means for reducing the light from the infrared light emitting unit to the display unit in a plan view, a decrease in image quality is reduced.

[0177] The user's gaze with respect to the display image is detected from the imaging image of the eyeball obtained by imaging infrared light. Any known method can be applied to gaze detection using the imaging image of the eyeball. As an example, a gaze detection method based on the Purkinje image by reflection of irradiation light on the cornea can be used.

[0178] More specifically, gaze detection processing based on the pupillary corneal reflex method is performed. Using the pupillary corneal reflex method, a gaze vector representing the orientation (rotation angle) of the eyeball is calculated based on the image of the pupil and the Purkinje image included in the imaging image of the eyeball, thereby detecting the user's gaze.

[0179] The display device according to an embodiment of the present invention may have an imaging device having a light receiving element, and control the display image of the display device based on the user's gaze information from the imaging device.

[0180] Specifically, the display device determines, based on the line-of-sight information, a first display area that the user is gazing at and a second display area other than the first display area. The first display area and the second display area may be determined by the control device of the display device, or the display device may receive those determined by an external control device. In the display area of the display device, the display resolution of the first display area may be controlled to be higher than that of the second display area. That is, the resolution of the second display area may be made lower than that of the first viewing area.

[0181] Also, the display area has a first display area and a second display area different from the first display area, and based on the line-of-sight information, an area with a higher priority is determined from the first display area and the second display area. The first viewing area and the second viewing area may be determined by the control device of the display device, or the display device may receive those determined by an external control device. The resolution of the area with a higher priority may be controlled to be higher than that of the area other than the area with a higher priority. That is, the resolution of the area with a relatively lower priority may be made lower.

[0182] Note that AI may be used to determine the first display area or the area with a higher priority. AI may be a model configured to estimate the angle of the line of sight and the distance to the object at the tip of the line of sight from the eye image, using the eye image and the direction in which the eye of the image is actually looking as teacher data. The AI program may be possessed by the display device, the imaging device, or an external device. When it is possessed by an external device, it is transmitted to the display device via communication.

[0183] When performing display control based on visual recognition detection, it is preferably applicable to smart glasses further having an imaging device for imaging the outside. The smart glasses can display the captured external information in real time.

[0184] In this specification, expressions such as "A or B", "at least one of A and B", "at least one of A or / and B", "one or more of A or / and B", etc., include all possible combinations of the listed items unless otherwise explicitly defined. That is, the above expressions are understood to disclose all cases including at least one A, including at least one B, and including both at least one A and at least one B. This also applies equally to combinations of three or more elements.

[0185] As described above, the embodiments can be appropriately modified without departing from the technical idea. Note that the disclosure of this specification includes not only what is described in this specification but also all matters that can be grasped from this specification and the drawings attached hereto. Also, the disclosure of this specification includes the complementary set of the concepts described in this specification. That is, for example, if this specification describes that "A is larger than B", even if the description that "A is not larger than B" is omitted, it can be said that this specification discloses the meaning that "A is not larger than B". Because when the description that "A is larger than B" is made, it is premised that the case where "A is not larger than B" is considered.

[0186] Note that the disclosure of this embodiment includes the following configurations.

[0187] (Configuration 1) A current source electrically connected to a first voltage node, a first MOS transistor of a first type, a second MOS transistor of a second type electrically connected to a second voltage node, a third MOS transistor of the first type, and a first wiring connected to the gates of the first MOS transistor and the third MOS transistor, wherein the current source, the first MOS transistor, and the second MOS transistor are arranged in sequence in an electrical path between the first voltage node and the second voltage node, and a current corresponding to the current flowing in the electrical path flows through the third MOS transistor. A circuit characterized by this.

[0188] (Configuration 2) The circuit according to Configuration 1, wherein a current value of a current flowing through the electrical path is substantially equal to a current value of a current flowing through the third MOS transistor.

[0189] (Configuration 3) The circuit according to Configuration 1 or 2, wherein the first type is a P-type, the second type is an N-type, the second MOS transistor is electrically connected to a source side of the first MOS transistor, and the current source is electrically connected to a drain side of the first MOS transistor.

[0190] (Configuration 4) The circuit according to any one of Configurations 1 to 3, wherein the first voltage node supplies a reference voltage to the current source, and the second voltage node supplies a power supply voltage to the second MOS transistor.

[0191] (Configuration 5) The circuit according to any one of Configurations 1 to 4, wherein the first type is an N-type, the second type is a P-type, the second MOS transistor is electrically connected to a drain side of the first MOS transistor, and the current source is electrically connected to a source side of the first MOS transistor.

[0192] (Configuration 6) The circuit according to any one of Configurations 1 to 5, wherein the first voltage node supplies a power supply voltage to the current source, and the second voltage node supplies a reference voltage to the second MOS transistor.

[0193] (Configuration 7) The circuit according to any one of Configurations 1 to 6, further comprising a wiring connected to a node between a gate of the first MOS transistor and a gate of the third MOS transistor and a node between the first MOS transistor and the current source.

[0194] (Configuration 8) The fourth MOS transistor of the second type electrically connected to the second voltage node, a second wiring connected to the gate of the second MOS transistor and the gate of the fourth MOS transistor, and a load element electrically connected to the third MOS transistor, and the third MOS transistor and the fourth MOS transistor are arranged in this order in an electrical path between the load element and the second voltage node. The circuit according to any one of Configurations 1 to 7.

[0195] (Configuration 9) The voltage value applied to the second MOS transistor and the fourth MOS transistor via the second wiring is set to a voltage value at which the second MOS transistor and the fourth MOS transistor operate in the saturation region. The circuit according to any one of Configurations 1 to 8.

[0196] (Configuration 10) The circuit further includes a resistance element electrically connected to the fourth MOS transistor, and the third MOS transistor, the fourth MOS transistor, and the resistance element are arranged in this order in an electrical path between the load element and the second voltage node. The circuit according to any one of Configurations 1 to 9.

[0197] (Configuration 11) The circuit having a plurality of circuit blocks including the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor. The circuit according to any one of Configurations 1 to 10.

[0198] (Configuration 12) The fifth MOS transistor of the first type electrically connected to the first MOS transistor, the sixth MOS transistor of the first type electrically connected to the third MOS transistor, and a fourth wiring connected to the gates of the fifth MOS transistor and the sixth MOS transistor, further comprising, in an electrical path between the first voltage node and the second voltage node, the current source, the fifth MOS transistor, the first MOS transistor, and the second MOS transistor arranged in this order, and in an electrical path between the load element and the second voltage node, the sixth MOS transistor, the third MOS transistor, and the fourth MOS transistor arranged in this order, the circuit according to any one of Configurations 1 to 11.

[0199] (Configuration 13) The circuit according to any one of Configurations 1 to 12, further comprising a wiring connected to a node between the gates of the first MOS transistor and the third MOS transistor and a node between the fifth MOS transistor and the current source.

[0200] (Configuration 14) The circuit according to any one of Configurations 1 to 13, wherein a voltage value applied to the second MOS transistor and the fourth MOS transistor via the second wiring is different from a voltage value applied to the fifth MOS transistor and the sixth MOS transistor via the fourth wiring.

[0201] (Configuration 15) The circuit according to any one of Configurations 1 to 14, comprising a plurality of circuit blocks including the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor.

[0202] (Configuration 16) The circuit according to any one of Configurations 1 to 15, characterized in that the current source, the first MOS transistor, and the third MOS transistor function as a current mirror circuit.

[0203] (Configuration 17) A light-emitting device having a light-emitting region and a circuit region for driving the light-emitting region, wherein the circuit region includes the circuit according to any one of Configurations 1 to 16.

[0204] (Configuration 18) An image forming apparatus having a photoreceptor, a light-emitting device disposed opposite to the photoreceptor for exposing the photoreceptor to form a latent image on the photoreceptor, and developing means for developing the latent image formed on the photoreceptor with toner, wherein the light-emitting device is the light-emitting device according to Configuration 17.

Explanation of Reference Numerals

[0205] 100 First voltage node 110 Current source 120 First MOS transistor 130 Second MOS transistor 140 Third MOS transistor 160 First wiring 300 Second voltage node

Claims

1. A current source electrically connected to a first voltage node, a first MOS transistor of a first type, a second MOS transistor of a second type electrically connected to a second voltage node, a third MOS transistor of the first type, a first wiring connected to the gate of the first MOS transistor and the gate of the third MOS transistor, comprising: in an electrical path between the first voltage node and the second voltage node, the current source, the first MOS transistor, and the second MOS transistor are arranged in sequence, a current corresponding to the current flowing in the electrical path flows through the third MOS transistor A circuit characterized by this.

2. The circuit according to claim 1, characterized in that the current value of the current flowing in the electrical path and the current value of the current flowing through the third MOS transistor are substantially equal.

3. The first type is P-type, the second type is N-type, the second MOS transistor is electrically connected to the source side of the first MOS transistor, and the current source is electrically connected to the drain side of the first MOS transistor. The circuit according to claim 1, characterized by this.

4. The circuit according to claim 3, characterized in that the first voltage node supplies a reference voltage to the current source, and the second voltage node supplies a power supply voltage to the second MOS transistor.

5. The first type is N-type, the second type is P-type, the second MOS transistor is electrically connected to the drain side of the first MOS transistor, and the current source is electrically connected to the source side of the first MOS transistor. The circuit according to claim 1, characterized by this.

6. The circuit according to claim 5, characterized in that the first voltage node supplies a power supply voltage to the current source, and the second voltage node supplies a reference voltage to the second MOS transistor.

7. The circuit according to claim 1, further comprising a wiring connected to a node between the gate of the first MOS transistor and the gate of the third MOS transistor and a node between the first MOS transistor and the current source.

8. The fourth MOS transistor of the second type electrically connected to the second voltage node, a second wiring connected to the gate of the second MOS transistor and the gate of the fourth MOS transistor, and a load element electrically connected to the third MOS transistor are further provided, and the third MOS transistor and the fourth MOS transistor are arranged in order in an electrical path between the load element and the second voltage node. The circuit according to claim 1, characterized in that.

9. The voltage value applied to the second MOS transistor and the fourth MOS transistor via the second wiring is set to a voltage value at which the second MOS transistor and the fourth MOS transistor operate in the saturation region. The circuit according to claim 8, characterized in that.

10. The circuit according to claim 8, further comprising a resistance element electrically connected to the fourth MOS transistor, wherein the third MOS transistor, the fourth MOS transistor, and the resistance element are arranged in order in an electrical path between the load element and the second voltage node.

11. The circuit according to claim 8, characterized by having a plurality of circuit blocks including the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor.

12. The fifth MOS transistor of the first type electrically connected to the first MOS transistor, the sixth MOS transistor of the first type electrically connected to the third MOS transistor, and a fourth wiring connected to the gate of the fifth MOS transistor and the gate of the sixth MOS transistor are further provided, and the current source, the fifth MOS transistor, the first MOS transistor, and the second MOS transistor are arranged in order in an electrical path between the first voltage node and the second voltage node, and the sixth MOS transistor, the third MOS transistor, and the fourth MOS transistor are arranged in order in an electrical path between the load element and the second voltage node. The circuit according to claim 8, characterized in that.

13. A circuit according to claim 12, further comprising a wiring connected to a node between the gate of the first MOS transistor and the gate of the third MOS transistor and a node between the fifth MOS transistor and the current source.

14. A circuit according to claim 12, wherein a voltage value applied to the second MOS transistor and the fourth MOS transistor via the second wiring is different from a voltage value applied to the fifth MOS transistor and the sixth MOS transistor via the fourth wiring.

15. A circuit according to claim 12, comprising a plurality of circuit blocks each including the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor.

16. A circuit according to claim 1, wherein the current source, the first MOS transistor, and the third MOS transistor function as a current mirror circuit.

17. A light-emitting region, a circuit region for driving the light-emitting region, and having a light-emitting device, wherein the circuit region includes the circuit according to any one of claims 1 to 16.

18. A photoreceptor, a light-emitting device disposed opposite to the photoreceptor for exposing the photoreceptor to form a latent image on the photoreceptor, a developing means for developing the latent image formed on the photoreceptor with toner, and having an image forming apparatus, wherein the light-emitting device is the light-emitting device according to claim 17.

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