Semiconductor device

Abstract

To reduce the chip size of a semiconductor device.SOLUTION: A semiconductor device includes a plurality of fuse circuits FC. Each of the fuse circuits FC includes a fuse element FS and a disconnection transistor CT. The fuse elements FS and the disconnection transistors CT are arranged in a first direction on a first main surface of a semiconductor substrate. In a plan view, each of the fuse elements FS is surrounded by each of a plurality of deep groove separation parts DTI. In a plan view, each of the disconnection transistors CT is surrounded by each of a plurality of power supply units PTAP. The power supply units PTAP are integrally surrounded by the deep groove separation parts DTI. The disconnection transistors CT are formed in a well region PW. Each of the power supply units PTAP has the same conductivity type as the well region PW and is formed in the well region PW.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including, for example, a MISFET and a fuse element.

Background Art

[0002] A semiconductor device incorporates various semiconductor elements such as a metal insulator semiconductor field effect transistor (MISFET). In some cases, a semiconductor device may also incorporate a fuse element. For example, a fuse element can be provided in advance in a semiconductor device, and the fuse element can be cut as needed to adjust circuit characteristics or eliminate a defective circuit. The fuse element can be cut by irradiating it with a laser beam or melted by Joule heat by passing an electric current through it.

[0003] Japanese Patent Application Laid-Open No. 2020-27852 (Patent Document 1) describes a technique for melting a fuse element by passing an electric current through a fuse element having a stacked structure including a silicon pattern and a metal silicide layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The inventors of the present application have identified the following problems in a semiconductor device having a plurality of fuse circuits each including a fuse element and a cut-off transistor for passing an electric current through the fuse element.

[0006] In the fuse circuit region of a semiconductor device, a plurality of fuse circuits are arranged. Each of the fuse circuits handles 1-bit data. With the increasing functionality of semiconductor devices, the number of data bits (in other words, the number of bits) handled by a plurality of fuse circuits has increased from several tens of bits to several hundreds of bits in the conventional case, and thus the occupied area of the fuse circuit region has increased. Therefore, reduction of the occupied area of the fuse circuit region, that is, miniaturization of the semiconductor device is required.

[0007] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0008] A semiconductor device according to an embodiment includes a plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse element and a cut-off transistor. The plurality of fuse elements and the plurality of cut-off transistors are each arranged in a first direction on a first main surface of a semiconductor substrate. In a plan view, each of the plurality of fuse elements is surrounded by each of a plurality of first deep trench isolation portions. In a plan view, each of the plurality of cut-off transistors is surrounded by each of a plurality of power supply portions, and the plurality of power supply portions are integrally surrounded by a second deep trench isolation portion. The plurality of cut-off transistors are formed in a well region, and each of the plurality of power supply portions has the same conductivity type as the well region and is formed in the well region.

Effects of the Invention

[0009] According to one embodiment, the semiconductor device can be miniaturized.

Brief Description of the Drawings

[0010]

Figure 1

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Figure 17

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Figure 19

Embodiments for Carrying Out the Invention

[0011] In all the drawings for explaining the embodiments, the same members are generally denoted by the same reference numerals, and the repeated description thereof is omitted.

[0012] In the following embodiments, N-type means an N-type conductivity type, and P-type means a P-type conductivity type. Further, the P-type semiconductor region can be read as a P-type impurity region, and the N-type semiconductor region can be read as an N-type impurity region.

[0013] The X direction and the Y direction are along the first main surface of the semiconductor substrate and are perpendicular to each other.

[0014] (Embodiment) The semiconductor device in the present embodiment has a fuse circuit, and the fuse circuit includes a fuse element and a cut-off transistor that passes current through the fuse element. The fuse element is blown by Joule heat generated by the current flowing through the fuse element.

[0015] (Technical problems of related art) (Related art 1) As shown in FIG. 16, the semiconductor device in related art 1 includes a plurality of fuse circuits FC that handle n-bit data. The fuse circuit FC that handles 1-bit data includes a fuse element FS and a cut-off transistor CT, and the plurality of fuse circuits FC that handle n-bit data are arranged, for example, in the X direction. The n fuse elements FS and the n cut-off transistors CT are each arranged in the X direction, and one of the plurality of fuse elements FS and one of the plurality of cut-off transistors CT are arranged in the Y direction.

[0016] In a plan view, each of the n fuse elements FS is surrounded by a deep trench isolation portion DTI. Each of the n cut-off transistors CT is formed inside each of the n P-type well regions PW, and in a plan view, each of the n cut-off transistors CT is surrounded by each of the n power supply portions PTAP. Further, in a plan view, each of the n power supply portions PTAP is surrounded by each of the n deep trench isolation portions DTI.

[0017] As the number of bits of data handled by the fuse circuit FC increases, the occupied area of the fuse circuit region expands, so a reduction in the occupied area is required.

[0018] <Related Art 2> Related Art 2 is a structure for reducing the occupied area of the fuse circuit region in Related Art 1. As shown in FIG. 17, the semiconductor device in Related Art 2 includes a plurality of fuse circuits FC that handle n-bit data, similar to Related Art 1. In a plan view, n fuse elements FS are integrally surrounded by a deep trench isolation portion DTI. The n cutting transistors CT are formed in one P-type well region PW. And in a plan view, the n cutting transistors CT are integrally surrounded by one power supply portion PTAP, and the periphery of the power supply portion PTAP is surrounded by one deep trench isolation portion DTI. Compared with Related Art 1, Related Art 2 can omit the deep trench isolation portion DTI between two adjacent fuse elements FS, and further can omit the power supply portion PTAP and the deep trench isolation portion DTI between two adjacent cutting transistors CT. Therefore, in the X direction, the occupied area of the fuse circuit region can be reduced.

[0019] As a result of the study by the inventor of the present application, the following problems have been found in Related Art 2. First, in a plan view, n fuse elements FS are integrally surrounded by a deep trench isolation portion DTI, and there is no deep trench isolation portion DTI between two adjacent fuse elements FS. The fuse element FS is formed on a shallow trench isolation portion STI described later. The fuse element FS is blown by Joule heat generated by the current flowing through the fuse element FS. And at the time of blowing, it was confirmed that cracks occurred in the shallow trench isolation portion STI under the fuse element FS and reached the adjacent fuse element FS. As will be described later, the fuse element FS has a laminated structure including a polycrystalline silicon layer and a silicide layer. And when the silicide layer of the blown fuse element FS extends in the crack and reaches the adjacent fuse element FS, the two adjacent fuse elements FS are short-circuited. When the two adjacent fuse elements FS are short-circuited, although one of the fuse elements FS is cut, it is erroneously determined that the fuse element FS has not been cut, and a malfunction of the fuse circuit FC occurs.

[0020] Also, as shown in FIG. 17, n cutting transistors CT are formed in the P-type well region PW and are integrally surrounded by the power supply portion PTAP in a plan view. Compared with the cutting transistor CT that handles the data of the first bit or the cutting transistor CT that handles the data of the nth bit, the cutting transistor CT that handles the data of the n / 2th bit is arranged away from the power supply portion PTAP in the X direction. Therefore, the parasitic resistance R of the P-type well region PW PW is large. As shown in FIG. 18, in the cutting transistor CT, there is a possibility that a parasitic NPN transistor including a drain that acts as a collector, a source that acts as an emitter, and a P-type well region PW that acts as a base is turned on. Then, as shown in FIG. 19, the larger the parasitic resistance R of the P-type well region PW PW is, the lower the on-voltage of the parasitic NPN transistor, and the parasitic NPN transistor is turned on at a low drain voltage. Then, a large current flows between the drain and the source of the cutting transistor CT, and the cutting transistor CT is destroyed. As a result, a malfunction of the fuse circuit FC occurs.

[0021] From the above, the technical problems derived from Related Art 1 and Related Art 2 are to reduce the occupied area of the fuse circuit region. And further, it is to prevent the malfunction of the fuse circuit FC caused by the defects of the fuse element FS and the cutting transistor CT.

[0022] <Structure of semiconductor device> As shown in FIG. 1, a fuse circuit FC that handles 1-bit data has a fuse element FS, a cut-off transistor CT, a control circuit CC, and a determination circuit DC. The fuse element FS and the cut-off transistor CT are connected in series between a power supply potential VDD and a reference potential GND. One end of the fuse element FS is connected to a terminal P1, and the terminal P1 is connected to the power supply potential VDD. The other end of the fuse element FS is connected to the drain D of the cut-off transistor CT. The source of the cut-off transistor CT is connected to a terminal P3, and the terminal P3 is connected to the reference potential GND. The gate G of the cut-off transistor CT is connected to a terminal P2, and the control circuit CC is connected to the terminal P2. The other end of the fuse element FS and the drain D of the cut-off transistor CT are connected to a terminal P4, and a determination circuit DC is connected between the terminal P4 and the terminal P1.

[0023] As shown in FIG. 2, a plurality of fuse circuits FC that handle n-bit data are arranged in the X direction. In a fuse element region FSR, n fuse elements FS are arranged in a row in the X direction. In the Y direction, in a cut-off transistor region CTR adjacent to the fuse element region FSR, n cut-off transistors CT are arranged in a row in the X direction. Each of the cut-off transistors CT is composed of a plurality of MISFETs connected in parallel. And each of the cut-off transistors CT includes a plurality of gates G extending in the Y direction, and the plurality of gates G are connected in parallel to each other.

[0024] In a plan view, each of the n fuse elements FS is surrounded by a deep trench isolation portion DTI. The n cut-off transistors CT are integrally formed in a P-type well region. And in a plan view, each of the n cut-off transistors CT is surrounded by a power supply portion PTAP. Further, in a plan view, the n cut-off transistors CT and the n power supply portions PTAP are integrally surrounded by a deep trench isolation portion DTI. The deep trench isolation portion DTI includes two X portions extending in the X direction and two Y portions extending in the Y direction, and the two X portions and the two Y portions form a rectangular frame.

[0025] FIG. 3 is a plan view of a fuse element FS and a cut-off transistor CT that constitute a fuse circuit FC. FIG. 3 shows, as an example, one fuse circuit FC, and each of the plurality of fuse circuits FC has a similar structure. However, in a plan view, a portion of the deep trench isolation DTI that extends in the Y direction does not exist between two adjacent cut-off transistors CT. The connection between the fuse element FS and the cut-off transistor CT is as described with reference to FIG. 1.

[0026] As shown in FIG. 4, the fuse element FS has a stacked structure including a polycrystalline silicon layer PS and a silicide layer SIL disposed on the polycrystalline silicon layer PS. The fuse element FS is formed on a shallow trench isolation STI formed on a first main surface SBa of a semiconductor substrate SB. In a direction perpendicular to the first main surface SBa of the semiconductor substrate SB, a P-type well region PW and an N-type buried semiconductor layer NBL are sequentially formed under the shallow trench isolation STI. Note that a second main surface SBb of the semiconductor substrate SB is located on the opposite side of the first main surface SBa of the semiconductor substrate SB. As can be seen from FIGS. 3 and 4, in a plan view, the shallow trench isolation STI, the P-type well region PW, and the N-type buried semiconductor layer NBL in the formation region of the fuse element FS are surrounded by the deep trench isolation DTI. The depth of the deep trench isolation DTI from the first main surface SBa is greater than the depth of the shallow trench isolation STI from the first main surface SBa. Therefore, the shallow trench isolation STI in the region where the fuse element FS for handling the n-th bit data is formed and the shallow trench isolation STI in the region where the fuse element FS for handling the (n - 1)-th bit data is formed are separated by the deep trench isolation DTI. That is, two adjacent shallow trench isolations STI are separated by the deep trench isolation DTI. Also, two adjacent P-type well regions PW and two adjacent N-type buried semiconductor layers NBL are separated by the deep trench isolation DTI. Note that both the shallow trench isolation STI and the deep trench isolation DTI are insulating films and include a silicon oxide film, a silicon nitride film, or the like. Further, an N-type well region NW may be used instead of the P-type well region PW. And when the N-type well region NW is used, it is not necessary to form the N-type buried semiconductor layer NBL.

[0027] As shown in FIG. 3, the cutting transistor CT includes a plurality of gates G, and the plurality of gates G are connected to each other. Each of the plurality of gates G has a predetermined width in the X direction and extends in the Y direction. The cutting transistor CT has a source S and a drain D, and in a plan view, a gate G is disposed between the source S and the drain D. That is, the cutting transistor CT is composed of a plurality of N-type MISFETs (NM) connected in parallel to each other. That is, the mutual conductance of the cutting transistor CT can be improved, and a large current can flow through the fuse element FS. FIG. 3 shows an example in which the cutting transistor CT is composed of two N-type MISFETs (NM).

[0028] Also, in a plan view, the cutting transistor CT that constitutes the fuse circuit FC for handling 1-bit data is surrounded by the power supply portion PTAP. On the power supply portion PTAP, a plurality of connection portions CP are arranged in the X direction and the Y direction, and through each of the plurality of connection portions CP, the power supply portion PTAP is electrically connected to the reference potential GND.

[0029] As shown in FIG. 5, the cutting transistor CT is formed in the P-type well region PW. And the n cutting transistors CT included in the plurality of fuse circuits FC for handling n-bit data are formed in one P-type well region PW in a plan view (see FIG. 2). In the depth direction of the semiconductor substrate SB, an N-type buried semiconductor layer NBL is formed under the P-type well region PW. As shown in FIG. 2, in a plan view, the P-type well region PW is surrounded by the deep trench isolation portion DTI. As can be seen from FIGS. 2 and 5, in a plan view, the N-type buried semiconductor layer NBL is also surrounded by the deep trench isolation portion DTI. That is, in a plan view, the P-type well region PW in which the n cutting transistors CT are formed is electrically separated from the P-type well regions PW arranged around the aforementioned P-type well region PW.

[0030] The cut-off transistor CT has a gate insulating film GI formed on the first main surface SBa, a gate G formed on the gate insulating film GI, and a source S and a drain D formed in a P-type well region PW. The gate G has a laminated structure including a polycrystalline silicon layer PS and a silicide layer SIL formed on the polycrystalline silicon layer PS. The source S and the drain D are each an N-type semiconductor region NR.

[0031] The power supply part PTAP is composed of a P-type semiconductor region PR, and the P-type semiconductor region PR is formed in the P-type well region PW. That is, the power supply part PTAP has a P-type conductivity type and is formed in the P-type well region PW. As shown in FIG. 3, the power supply part PTAP includes two X parts extending in the X direction and two Y parts extending in the Y direction, and the two X parts and the two Y parts constitute a rectangular frame. In a plan view, the cut-off transistor CT is surrounded by a rectangular frame. Also, in a plan view, in the two frames surrounding each of the two adjacent cut-off transistors CT, the two Y parts located between the two adjacent cut-off transistors CT are integrated. That is, one Y part is arranged between the two adjacent cut-off transistors CT. Then, the reference potential GND is supplied to the P-type well region PW through the P-type semiconductor region PR which is the power supply part PTAP.

[0032] As shown in FIG. 7, in the Y direction, a fuse element region FSR, a cut-off transistor region CTR, and a control circuit region CCR are arranged in this order. In the Y direction, the cut-off transistor region CTR is arranged between the fuse element region FSR and the control circuit region CCR. The control circuit region CCR includes a PMIS region PMR and an NMIS region NMR. In order to configure a fuse circuit FC that handles 1-bit data, a plurality of P-type MISFETs (PM) are arranged in the PMIS region PMR, and a plurality of N-type MISFETs (NM) are arranged in the NMIS region NMR. In plan view, a plurality of P-type MISFETs (PM) surrounded by one power supply portion NTAP constitute one block, and a plurality of N-type MISFETs (NM) surrounded by one power supply portion PTAP constitute one block. In the PMIS region PMR, the plurality of P-type MISFETs (PM) included in each block are integrally surrounded by the power supply portion NTAP. Similarly, in the NMIS region NMR, in plan view, the plurality of N-type MISFETs (NM) included in each block are integrally surrounded by the power supply portion PTAP. The power supply portion NTAP includes two X portions extending in the X direction and two Y portions extending in the Y direction, and the two X portions and the two Y portions constitute a rectangular frame.

[0033] The plurality of P-type MISFETs (PM) included in n blocks are formed within one N-type well region NW. Similarly, the plurality of N-type MISFETs (NM) included in n blocks are formed within one P-type well region PW. Then, as shown in FIG. 8, the power supply section PTAP is composed of a P-type semiconductor region PR, and the P-type semiconductor region PR is formed within the P-type well region PW. As shown in FIG. 7, in a plan view, the plurality of N-type MISFETs (NM) included in each block are integrally surrounded by a P-type semiconductor region PR. Also, the power supply section NTAP is composed of an N-type semiconductor region NR, and the N-type semiconductor region NR is formed within the N-type well region NW. As shown in FIG. 7, in a plan view, the plurality of P-type MISFETs (PM) included in each block are integrally surrounded by an N-type semiconductor region NR. Then, the P-type well region PW is connected to the reference potential GND via the P-type semiconductor region PR which is the power supply section PTAP, and the N-type well region NW is connected to the power supply potential VDD via the N-type semiconductor region NR which is the power supply section NTAP.

[0034] Furthermore, the plurality of P-type MISFETs (PM) included in n blocks, the n power supply sections NTAP, the plurality of N-type MISFETs (NM) included in n blocks, and the n power supply sections PTAP are integrally surrounded by a deep trench isolation section DTI in a plan view.

[0035] Note that in FIG. 7, although n power supply sections NTAP are arranged in the NMIS region NMR, as a modification of FIG. 7, in a plan view, all the N-type MISFETs (NM) arranged in the NMIS region NMR may be surrounded by one power supply section PTAP. Furthermore, in a plan view, all the P-type MISFETs (PM) arranged in the PMIS region PMR may be surrounded by one power supply section NTAP.

[0036] <Features of the semiconductor device> As shown in FIG. 2, in a plan view, each of the n fuse elements FS is surrounded by a deep trench isolation (DTI) section, thereby preventing malfunction of the fuse circuit FC described above. That is, it is possible to prevent malfunction of the fuse circuit FC caused by a short circuit between two adjacent fuse elements FS. And even in a structure in which each fuse element FS is surrounded by a deep trench isolation section DTI in a plan view, the formation region of the fuse circuit FC that handles 1-bit data in the X direction does not expand. This is because, as shown in FIG. 6, in the X direction, the outer dimension b of the power supply section PTAP surrounding the cut-off transistor CT in a plan view is larger than the outer dimension a of the deep trench isolation section DTI surrounding the fuse element FS.

[0037] As described with reference to FIGS. 2, 3, and 5, n cut-off transistors CT are formed in one P-type well region PW, and in a plan view, each cut-off transistor CT is surrounded by a power supply section PTAP. As a result, the parasitic resistance R of the P-type well region PW in the region where each cut-off transistor CT is formed PW can be reduced as compared with Related Art 2, and destruction of the cut-off transistor CT caused by turning on of the parasitic NPN transistor can be prevented. Also, since the parasitic resistance R of the P-type well region PW in the region where each cut-off transistor CT is formed PW can be made uniform, the breakdown voltage of the n cut-off transistors CT can be made constant without being affected by the arrangement position of the cut-off transistors CT. Therefore, in the n cut-off transistors CT, destruction caused by turning on of the parasitic NPN transistor can be prevented. That is, malfunction of the fuse circuit FC can be prevented.

[0038] Also, in a plan view, an N-type buried semiconductor layer NBL is provided under the P-type well region PW in which the n cut-off transistors CT are formed, and in a plan view, the P-type well region PW and the buried semiconductor layer NBL are surrounded by a deep trench isolation section DTI. Thereby, it is possible to prevent electrical interference between the P-type well region PW in which the n cut-off transistors CT are formed in a plan view and the P-type well regions PW arranged around the P-type well region PW described above.

[0039] Also, in a plan view, by surrounding n cutting transistors CT and n power supply parts PTAT integrally with a deep trench isolation part DTI, the formation region of a plurality of fuse circuits FC that handle n-bit data in the X direction can be reduced compared to Related Art 1.

[0040] Also, in a control circuit region CCR, in a plan view, by surrounding a plurality of N-type MISFETs (NM) and n power supply parts PTAP included in n blocks integrally with a deep trench isolation part DTI, the control circuit region CCR of a plurality of fuse circuits FC that handle n-bit data in the X direction can be reduced.

[0041] Similarly, in a plan view, by surrounding a plurality of P-type MISFETs (PM) and n power supply parts NTAP included in n blocks integrally with a deep trench isolation part DTI, the control circuit region CCR of a plurality of fuse circuits FC that handle n-bit data in the X direction can be reduced.

[0042] As shown in FIG. 7, a plurality of N-type MISFETs (NM) included in n blocks are formed in one P-type well region PW, and in a plan view, the plurality of N-type MISFETs (NM) included in each block are surrounded by a power supply part PTAP. As a result, in each block, the parasitic resistance R PW of the P-type well region PW can be reduced, and the breakdown of the N-type MISFET (NM) caused by the parasitic NPN transistor being turned on can be prevented. Also, in each block, the parasitic resistance R PW of the P-type well region PW can be made uniform, so that the breakdown of the N-type MISFET (NM) caused by the parasitic NPN transistor being turned on can be prevented without being affected by the arrangement position of the blocks. That is, malfunction of the control circuit included in the fuse circuit FC can be prevented.

[0043] Also, in the n blocks, an N-type buried semiconductor layer NBL is provided under the P-type well region PW, and in a plan view, the P-type well region PW and the buried semiconductor layer NBL are surrounded by a deep trench isolation part DTI. Thereby, electrical interference between the P-type well region PW included in the control circuit region CCR and the P-type well regions PW in other regions can be prevented.

[0044] Also, in a plan view, by surrounding the PMIS region PMR and the NMIS region NMR included in the control circuit region CCR integrally with the deep trench isolation part DTI, the control circuit region CCR can be reduced.

[0045] <Modification Example 1> Modification Example 1 relates to the control circuit region CCR of the above-described embodiment.

[0046] As shown in FIG. 9, the control circuit region CCR includes a PMIS region PMR1 and a PMIS region PMR2, and an NMIS region NMR1 and an NMIS region NMR2. The PMIS region PMR1 and the PMIS region PMR2 have the same structure as each other, and the NMIS region NMR1 and the NMIS region NMR2 have the same structure as each other.

[0047] The NMIS region NMR1 includes one P-type well region PW and n power supply parts PTAP. In a plan view, a plurality of N-type MISFETs (NM) are formed in the region surrounded by the power supply part PTAP. And in a plan view, the plurality of N-type MISFETs (NM) surrounded by the power supply part PTAP constitute a block. The NMIS region NMR1 includes n blocks. The plurality of N-type MISFETs (NM) included in the n blocks are formed in one P-type well region PW.

[0048] The PMR1 in the PMIS region includes one N-type well region NW and n power supply parts NTAP. In a plan view, a plurality of P-type MISFETs (PM) are formed in the region surrounded by the power supply parts NTAP. And, in a plan view, the plurality of P-type MISFETs (PM) surrounded by the power supply parts NTAP constitute a block. The PMIS region PMR1 includes n blocks. The plurality of P-type MISFETs (PM) included in the n blocks are formed in one N-type well region NW.

[0049] The control circuit region CCR in the above embodiment is formed by one PMIS region PMR and one NMIS region NMR, while in Modification 1, the control circuit region CCR is formed by two PMIS regions PMR1 and PMR2, and two NMIS regions NMR1 and NMR2. Modification 1 can reduce the area of the P-type well region PW in each block in the control circuit region CCR compared to the above embodiment. That is, in the control circuit region CCR, the parasitic resistance R PW of the P-type well region PW in each block can be reduced. Therefore, in each block, the on-breakdown voltage of the N-type MISFET (NM) can be improved, and the breakdown of the N-type MISFET (NM) caused by the on of the parasitic NPN transistor can be prevented.

[0050] <Modification 2> Modification 2 is an example in which a determination circuit region DCR is added to Modification 1.

[0051] As shown in FIG. 10, in the Y direction, the fuse element region FSR is arranged between the determination circuit region DCR and the cut-off transistor region CTR. The determination circuit region DCR includes a PMIS region PMR and an NMIS region NMR. Note that in the control circuit region CCR, only the PMIS region PMR1 and the NMIS region NMR1 are shown, and the PMIS region PMR2 and the NMIS region NMR2 are omitted.

[0052] The NMIS region NMR includes one P-type well region PW and n power supply parts PTAP. In a plan view, a plurality of N-type MISFETs (NM) are formed in the region surrounded by the power supply parts PTAP. And, in a plan view, the plurality of N-type MISFETs (NM) surrounded by the power supply parts PTAP constitute a block. The NMIS region NMR includes n blocks. The plurality of N-type MISFETs (NM) included in the n blocks are formed in one P-type well region PW.

[0053] The PMIS region PMR includes one N-type well region NW and n power supply parts NTAP. In a plan view, a plurality of P-type MISFETs (PM) are formed in the region surrounded by the power supply parts NTAP. And, in a plan view, the plurality of P-type MISFETs (PM) surrounded by the power supply parts NTAP constitute a block. The PMIS region PMR includes n blocks.

[0054] In Modification 2, in the determination circuit region DCR, in a plan view, each of the n blocks is surrounded by the power supply part PTAP. Therefore, the parasitic resistance R PW of the P-type well region PW in each block can be reduced. Accordingly, in each block, the on-state breakdown voltage of the N-type MISFET (NM) can be improved, and the destruction of the N-type MISFET (NM) caused by the on of the parasitic NPN transistor can be prevented.

[0055] Also, by arranging the determination circuit region DCR adjacent to the fuse element region FSR, the arrangement of the wiring connecting the determination circuit DC and the fuse element FS becomes easy. Also, the length of the wiring connecting the determination circuit DC and the fuse element FS can be reduced.

[0056] <Modification 3> Modification 3 is a modification regarding the control circuit region CCR of the above Modification 2.

[0057] As shown in FIGS. 11 and 12, the control circuit region CCR includes a PMIS region PMR and an NMIS region NMR. In the X direction, the PMIS region PMR and the NMIS region NMR are alternately arranged.

[0058] The PMIS region PMR includes one N-type well region NW and one power supply part NTAP. In a plan view, a plurality of P-type MISFETs (PM) are formed in a region surrounded by the power supply part NTAP. The control circuit CC of the fuse circuit FC that handles 2-bit data is configured using the plurality of P-type MISFETs (PM) described above.

[0059] The NMIS region NMR includes one P-type well region PW and one power supply part PTAP. In a plan view, a plurality of N-type MISFETs (NM) are formed in a region surrounded by the power supply part PTAP. The control circuit CC of the fuse circuit FC that handles 2-bit data is configured using the plurality of N-type MISFETs (NM) described above.

[0060] As shown in FIGS. 11 and 12, the control circuit CC of the fuse circuit FC that handles the data of the m-th bit is configured using a plurality of P-type MISFETs (PM) that are a part included in the PMIS region PMR. Further, the control circuit CC of the fuse circuit FC that handles the data of the m-th bit is configured using a plurality of N-type MISFETs (NM) that are a part included in the NMIS region NMR adjacent to the right side of the PMIS region PMR described above.

[0061] The control circuit CC of the fuse circuit FC that handles the data of the (m - 1)-th bit is configured using a plurality of P-type MISFETs (PMs), which are other parts included in the aforementioned PMIS region PMR. Further, the control circuit CC of the fuse circuit FC that handles the data of the (m - 1)-th bit is configured using a plurality of N-type MISFETs (NMs), which are a part included in the NMIS region NMR adjacent to the left side of the aforementioned PMIS region PMR. However, in the PMIS region PMR or the NMIS region NMR, at the end in the X direction, there may be a case where only P-type MISFETs (PMs) or N-type MISFETs (NMs) for configuring the control circuit CC of the fuse circuit FC that handles 1-bit data are provided, so 2 ≤ m ≤ (n - 1). m is a natural number.

[0062] As shown in FIGS. 11 and 12, a plurality of control circuits CC include the (m - 1)-th control circuit CC and the m-th control circuit CC that are adjacent to each other in the X direction. The (m - 1)-th control circuit CC handles the data of the (m - 1)-th bit, and the m-th control circuit CC handles the data of the m-th bit. Then, in the adjacent PMIS region PMR and NMIS region NMR, a part of the plurality of P-type MISFETs (PMs) is connected to the m-th control circuit CC, and the other part of the plurality of P-type MISFETs (PMs) is connected to the (m - 1)-th control circuit CC. Further, a part of the plurality of N-type MISFETs (NMs) is connected to the m-th control circuit CC. And a part of the plurality of P-type MISFETs (PMs) connected to the m-th control circuit CC and the other part of the plurality of P-type MISFETs (PMs) connected to the (m - 1)-th control circuit CC are surrounded by a common power supply body NTAP in a plan view.

[0063] In this way, in the X direction, a part of the plurality of P-type MISFETs (PMs) and the other part of the plurality of P-type MISFETs (PMs) connected to two adjacent control circuits CC are arranged within one PMIS region PMR. Then, by arranging a part of the plurality of P-type MISFETs (PMs) and the other part of the plurality of P-type MISFETs (PMs) commonly within one N-type well region NW and surrounding them with one power supply part NTAP, the occupied area of the control circuit region CCR can be reduced in the X direction.

[0064] As shown in FIGS. 14 and 15, similarly in the control circuit region CCR of the comparative example, in the X direction, the PMIS region PMR and the NMIS region NMR are alternately arranged. A plurality of control circuits CC include, in the X direction, the (m-1)-th control circuit CC and the m-th control circuit CC adjacent to each other. To configure the (m-1)-th control circuit CC, a PMIS region PMR and an NMIS region NMR are arranged in the control circuit region CCR. Further, to configure the m-th control circuit CC, a PMIS region PMR and an NMIS region NMR are arranged in the control circuit region CCR. That is, in the X direction, the PMIS region PMR, the NMIS region NMR, the PMIS region PMR, and the NMIS region NMR are arranged in order. And a plurality of P-type MISFETs (PM) included in the PMIS region PMR are formed in the N-type well region NW in a plan view and are surrounded by the power supply portion NTAP. Similarly, a plurality of N-type MISFETs (NM) included in the NMIS region NMR are formed in the P-type well region PW in a plan view and are surrounded by the power supply portion PTAP.

[0065] Thus, in the X direction, a plurality of P-type MISFETs (PM) connected to two adjacent control circuits CC are independently arranged in two N-type well regions NW and are surrounded by two power supply portions NTAP. Therefore, the semiconductor device of the comparative example has an increased occupied area of the control circuit region CCR in the X direction compared to the semiconductor device of Modification 3.

[0066] As described above, the invention made by the present inventor has been specifically described based on its embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Description of Reference Numerals

[0067] CC Control circuit CCR Control circuit region CP Connection portion CT Cut-off transistor CTR Cut-off Transistor Region D Drain (Drain Region) DC Judgment Circuit DCR Judgment Circuit Region DTI Deep Trench Isolation (Deep Trench Isolation Film) FC Fuse Circuit FS Fuse Element FSR Fuse Element Region G Gate (Gate Electrode) GI Gate Insulating Film GND Reference Potential NBL Buried Semiconductor Layer NM N-type MISFET NMR, NMR1, NMR2 NMIS Region NR N-type Semiconductor Region NTAP Power Supply Section (N-type Power Supply Section) NW N-type Well Region P1, P2, P3, P4 Terminals PM P-type MISFET PMR, PMR1, PMR2 PMIS Region PR Semiconductor Region (P-type Semiconductor Region) PTAP Power Supply Section (P-type Power Supply Section) PS Polycrystalline Silicon Layer PW P-type Well Region S Source (Source Region) SIL Silicide Layer (Metal Silicide Layer) STI Shallow Trench Isolation (Shallow Trench Isolation Film) SB Semiconductor Substrate SBa First Main Surface SBb Second Main Surface VDD Power Supply Potential

Claims

1. A semiconductor substrate having a first main surface and a second main surface located on the opposite side of the first main surface; A plurality of fuse elements formed on the first main surface of the semiconductor substrate and arranged side by side in a first direction; A plurality of cut-off transistors formed on the first main surface of the semiconductor substrate, adjacent to the plurality of fuse elements in a second direction perpendicular to the first direction, and arranged side by side in the first direction; A plurality of fuse circuits; A plurality of first deep trench isolation parts formed in the semiconductor substrate; A plurality of first power supply parts formed in the semiconductor substrate; A second deep trench isolation part formed in the semiconductor substrate and integrally surrounding the plurality of first power supply parts in a plan view; A first well region of a first conductivity type extending from the first main surface to the second main surface of the semiconductor substrate; And having; In a plan view, each of the plurality of first deep trench isolation parts surrounds each of the plurality of fuse elements; In a plan view, each of the plurality of first power supply parts surrounds each of the plurality of cut-off transistors; Each of the plurality of fuse circuits includes each of the plurality of cut-off transistors and each of the plurality of fuse elements; Each of the plurality of cut-off transistors; A gate formed on the semiconductor substrate; A source of a second conductivity type, which is different from the first conductivity type, formed in the semiconductor substrate; A drain of the second conductivity type formed in the semiconductor substrate; And comprising; In a plan view, the plurality of cut-off transistors are formed in the first well region; Each of the plurality of first power supply parts has the first conductivity type and is formed in the first well region, a semiconductor device.

2. In the semiconductor device according to Claim 1, In the first direction, the second deep trench isolation part is arranged so as not to be formed between two adjacent ones of the plurality of cut-off transistors, a semiconductor device.

3. In the semiconductor device according to Claim 1, In the first direction, the outer dimension of each of the plurality of first power supply parts is smaller than the outer dimension of each of the plurality of first deep trench isolation parts, a semiconductor device.

4. In the semiconductor device according to Claim 3, In a plan view, the gate includes a plurality of first polycrystalline silicon layers arranged in the first direction; Each of the plurality of first polycrystalline silicon layers extends in the second direction; On each of the plurality of first polycrystalline silicon layers, a first silicide layer is formed. The plurality of first polycrystalline silicon layers are electrically connected in parallel, a semiconductor device.

5. In the semiconductor device according to claim 1, The semiconductor substrate has the first conductivity type. Between the first well region and the second main surface, an embedded semiconductor layer of the second conductivity type is formed. The second deep trench isolation part extends in a direction from the first main surface toward the second main surface and penetrates the embedded semiconductor layer, a semiconductor device.

6. In the semiconductor device according to claim 1, Each of the plurality of fuse elements is formed on a shallow trench isolation part formed in the semiconductor substrate on the first main surface. The depth of the shallow trench isolation part from the first main surface is smaller than the depth of each of the plurality of first deep trench isolation parts from the first main surface, a semiconductor device.

7. In the semiconductor device according to claim 6, Each of the plurality of fuse elements includes a second polycrystalline silicon layer and a second silicide layer formed on the second polycrystalline silicon layer, a semiconductor device.

8. In the semiconductor device according to claim 1, Each of the plurality of fuse elements and the path from the drain to the source of each of the plurality of cut-off transistors are connected in series between a power supply potential and a ground potential. The first well region is connected to the ground potential via the plurality of first power supply parts, a semiconductor device.

9. In the semiconductor device according to claim 1, The plurality of fuse circuits include a plurality of control circuits. Each of the plurality of control circuits is connected to the gate of each of the plurality of cut-off transistors. The plurality of control circuits include a plurality of first blocks including a plurality of first MISFETs of the second conductivity type, a plurality of second power supply parts, a plurality of second blocks including a plurality of second MISFETs of the first conductivity type, a plurality of third power supply parts, and include In a plan view, each of the plurality of second power supply parts integrally surrounds the plurality of first MISFETs included in each of the plurality of first blocks. In a plan view, each of the plurality of third power supply parts integrally surrounds the plurality of second MISFETs included in each of the plurality of second blocks, a semiconductor device.

10. In the semiconductor device according to claim 9, In a plan view, the plurality of first MISFETs included in the plurality of first blocks are formed in a second well region of the first conductivity type. In a plan view, the plurality of second MISFETs included in the plurality of second blocks are formed in a third well region of the second conductivity type. Each of the plurality of second power supply parts has the first conductivity type and is formed in the second well region. Each of the plurality of third power supply parts has the second conductivity type and is formed in the third well region. A semiconductor device.

11. In the semiconductor device according to claim 10, In a plan view, the plurality of second power supply parts are arranged in the first direction. In a plan view, the plurality of third power supply parts are arranged in the first direction. In the second direction, the plurality of third power supply parts are adjacent to the plurality of second power supply parts. In a plan view, the plurality of second power supply parts and the plurality of third power supply parts are integrally surrounded by a third deep trench isolation part. A semiconductor device.

12. In the semiconductor device according to claim 11, The plurality of control circuits Further, A plurality of third blocks including a plurality of third MISFETs of the second conductivity type; In a plan view, a plurality of fourth power supply parts integrally surrounding the plurality of third MISFETs; A plurality of fourth blocks including a plurality of fourth MISFETs of the first conductivity type; In a plan view, a plurality of fifth power supply parts integrally surrounding the plurality of fourth MISFETs; Have In a plan view, the plurality of third MISFETs included in the plurality of third blocks are formed in a fourth well region of the first conductivity type. In a plan view, the plurality of fourth MISFETs included in the plurality of fourth blocks are formed in a fifth well region of the second conductivity type. Each of the plurality of fourth power supply parts has the first conductivity type and is formed in the fourth well region. Each of the plurality of fifth power supply parts has the second conductivity type and is formed in the fifth well region. A semiconductor device.

13. In the semiconductor device according to claim 12, In a plan view, the plurality of fourth power supply parts are arranged in the first direction. In a plan view, the plurality of fifth power supply parts are arranged in the first direction. In a plan view, the plurality of second power supply parts, the plurality of third power supply parts, the plurality of fourth power supply parts and the plurality of fifth power supply parts are integrally surrounded by the third deep trench isolation part. A semiconductor device.

14. In the semiconductor device according to claim 13, In the second direction, the second deep trench isolation part is arranged between the plurality of first deep trench isolation parts and the third deep trench isolation part, a semiconductor device.

15. In the semiconductor device according to claim 9, The plurality of fuse circuits include a plurality of determination circuits, Each of the plurality of determination circuits is connected in parallel with each of the plurality of fuse elements, The plurality of determination circuits, A plurality of fifth blocks including the plurality of fifth MISFETs of the second conductivity type, A plurality of sixth power supply parts, Including, In a plan view, the plurality of fifth MISFETs included in the plurality of fifth blocks are formed in the sixth well region of the first conductivity type, In a plan view, each of the plurality of sixth power supply parts surrounds the plurality of fifth MISFETs included in each of the plurality of fifth blocks, Each of the plurality of sixth power supply parts has the first conductivity type and is formed in the sixth well region, a semiconductor device.

16. In the semiconductor device according to claim 15, In a plan view, the plurality of sixth power supply parts are arranged in the first direction, In a plan view, the plurality of sixth power supply parts are integrally surrounded by a fourth deep trench isolation part, a semiconductor device.

17. In the semiconductor device according to claim 16, In the second direction, the plurality of first deep trench isolation parts are arranged between the second deep trench isolation part and the fourth deep trench isolation part, a semiconductor device.

18. In the semiconductor device according to claim 9, The plurality of control circuits include an (m - 1)th control circuit and an mth control circuit adjacent to each other in the first direction, In the first direction, each of the plurality of first blocks and each of the plurality of second blocks are alternately arranged, Among the plurality of first blocks and the plurality of second blocks, in the first direction, between one of the plurality of first blocks adjacent to each other and one of the plurality of second blocks adjacent to each other, A part of the plurality of second MISFETs is connected to the mth control circuit, Another part of the plurality of second MISFETs is connected to the (m - 1)th control circuit, A part of the plurality of first MISFETs is connected to the (m - 1)th control circuit, a semiconductor device.

19. In the semiconductor device according to claim 18, In a plan view, the plurality of first MISFETs included in each of the plurality of first blocks are formed in a seventh well region of the first conductivity type. In a plan view, the plurality of second MISFETs included in each of the plurality of second blocks are formed in an eighth well region of the second conductivity type. Each of the plurality of second power supply parts has the first conductivity type and is formed in the seventh well region. A semiconductor device in which each of the plurality of third power supply parts has the second conductivity type and is formed in the eighth well region.

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