Manufacturing method of semiconductor device and semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device capable of performing transfer and processing using the same device as a wafer before processing by suppressing reduction of a wafer diameter, and a semiconductor device.SOLUTION: A manufacturing method of a semiconductor includes the steps of: forming a semiconductor element structure on a second principal surface of a wafer comprising a first principal surface and the second principal surface which are opposed to each other; grinding an outer peripheral part of the second principal surface of the wafer, on which the semiconductor element structure is formed, to the middle in a thickness direction from the second principal surface toward the first principal surface; dividing the waver in a direction vertical to the thickness direction at a position shallower from the second principal surface than a depth in which the outer peripheral part of the wafer is ground, and dividing a first divided wafer, which does not include the semiconductor element structure, from the wafer; grinding an outer peripheral part of a divided surface of the first divided wafer; and forming a semiconductor element structure on the divided surface of the first divided wafer in which the outer peripheral part of the divided surface is ground.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a technique for reducing the substrate cost by using a thinly sliced wafer as a base for epitaxial growth.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above method, it is necessary to bevel the wafer before slicing. Since this beveling reduces the wafer diameter, there is a problem that it is impossible to use the same apparatus for conveyance and processing as the wafer before processing, or it is necessary to adjust the apparatus so as to cope with the change in the wafer diameter.

[0005] In order to solve the above problems, an object of the present disclosure is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of performing conveyance and processing using the same apparatus as the wafer before processing by suppressing reduction of the wafer diameter.

Means for Solving the Problems

[0006] A first aspect of the present disclosure includes a step of forming a semiconductor element structure on a second main surface of a wafer having a first main surface and a second main surface facing each other; a step of grinding an outer peripheral portion of the second main surface of the wafer on which the semiconductor element structure is formed to a middle position in the thickness direction from the second main surface toward the first main surface; a step of dividing the wafer in a direction perpendicular to the thickness direction at a position shallower than the depth at which the outer peripheral portion of the wafer is ground, to divide the wafer into a first divided wafer not including the semiconductor element structure; a step of grinding an outer peripheral portion of a dividing surface of the first divided wafer; and a step of forming a semiconductor element structure on the dividing surface of the first divided wafer whose outer peripheral portion of the dividing surface has been ground. It is preferably a method for manufacturing a semiconductor device including these steps.

[0007] A second aspect of the present disclosure includes a first divided wafer having a first main surface and a second main surface facing each other and having a semiconductor element structure on the second main surface, and a second divided wafer joined to the first main surface of the first divided wafer. It is preferably a semiconductor device in which an unjoined region is formed in an outer peripheral portion of a joining interface between the first divided wafer and the second divided wafer.

[0008] A third aspect of the present disclosure includes a first divided wafer having a first main surface and a second main surface facing each other, an epitaxial film formed on the second main surface of the first divided wafer, and a semiconductor element structure formed on the epitaxial film. It is preferably a semiconductor device in which a cross section of the first divided wafer has a convex structure.

[0009] A fourth aspect of the present disclosure includes a first divided wafer having a first main surface and a second main surface facing each other and having a semiconductor element structure on the second main surface. It is preferably a semiconductor device in which a cross section of the first divided wafer has a convex structure.

Advantages of the Invention

[0010] According to the first to fourth aspects of the present disclosure, by suppressing the reduction of the wafer diameter, conveyance and processing can be performed using the same apparatus as the wafer before processing.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0012] Embodiment 1 [Method for Processing a Semiconductor Device According to Embodiment 1 of the Present Disclosure] A method for processing a semiconductor device according to Embodiment 1 of the present disclosure will be described. FIG. 1 is a diagram showing a semiconductor device according to Embodiment 1 of the present disclosure. The semiconductor device 100 includes a wafer 12. The wafer 12 is, for example, a single-crystalline SiC wafer having a second main surface facing the first main surface. Note that the first main surface is the back surface of the wafer, and the second main surface is the front surface of the wafer.

[0013] The wafer 12 may be formed of Si, or may be formed of a wide-bandgap semiconductor having a larger bandgap than Si. The wide-bandgap semiconductor is, for example, SiC, a GaN-based material, a gallium oxide-based material, or diamond. By forming a switching element or a diode element using a wide-bandgap semiconductor, the breakdown voltage and the allowable current density can be increased, so that miniaturization becomes possible.

[0014] Aspects of the present disclosure are particularly effective in semiconductor devices that use wafers with high cost performance and are difficult to obtain. A particularly effective example is the case where the wafer 12 is formed of SiC. SiC wafers are difficult to increase in diameter compared to Si wafers, are costly, and have a poor yield due to crystal defects. That is, SiC wafers have the problem of poor cost performance.

[0015] In addition, single crystals of SiC are generally produced by the sublimation method. In this sublimation method, as the diameter of the wafer increases, the temperature difference within the crystal becomes larger, and crystal defects increase. That is, SiC wafers have the problem that it becomes difficult to obtain a substrate with few crystal defects as the diameter of the wafer increases.

[0016] The problems of the above-described SiC wafers can be solved simultaneously by regenerating and using SiC wafers with few crystal defects.

[0017] An epitaxial film is formed on the second main surface of the wafer 12. A semiconductor element structure 14 is formed on the epitaxial film. The semiconductor element structure 14 is a power device structure such as a MOSFET, diode, IGBT, etc. The formation of the semiconductor element structure 14 includes ion implantation and the formation of a surface electrode. Note that the semiconductor element structure 14 is formed inside the outermost peripheral portion of the wafer 12 having a tapered shape.

[0018] When the wafer 12 is made of GaN, the semiconductor element structure 14 is, for example, a GaN high-frequency device structure. Alternatively, a GaN high-frequency device structure may be formed on the wafer 12 made of SiC.

[0019] FIG. 2 is a diagram showing a grinding process according to Embodiment 1 of the present disclosure. In the grinding process of the present embodiment, by grinding the outer peripheral portion of the second main surface of the wafer 12 to the middle in the thickness direction from the second main surface toward the first main surface, a wafer 16 having a convex cross-section is formed. As a result, a semiconductor device 102 in which the semiconductor element structure 14 protrudes more than the outer peripheral portion is formed.

[0020] This grinding process can be carried out, for example, using a device in which a grinding wheel is attached to a rotary edge processing machine. The grinding wheel is adjusted so that the wafer can be formed into an arbitrary shape by grinding the outer periphery of the wafer. Also, this grinding process may be formed by half-cutting the outer periphery with a dicing device.

[0021] FIG. 23 is a view showing a grinding process performed by an apparatus in which a grinding wheel is attached to a rotary edge processing machine. The left view of FIG. 23 shows a wafer after grinding when using a newly replaced grinding wheel. The right view of FIG. 23 shows a wafer after grinding when using a worn grinding wheel. When processing a plurality of wafers using the same grinding wheel, the grinding wheel wears out and it becomes impossible to perform grinding as expected, so the shape of the wafer after processing becomes as shown in the right view of FIG. 23. In this case, due to the grinding process, corners 50 and 51 on the wafer become rounded corners 50a and 51a, respectively. This

[0022] If corner 50a has a radius R of 500 μm or less, dust generation and chipping caused by the knife edge described later can be reduced. If it is even smaller, with R = 300 μm or less, dust generation or chipping can be further reduced. If R = 100 μm or less, dust generation or chipping due to the edge shape can be almost suppressed.

[0023] FIG. 24 is a view showing the kerf loss associated with the grinding process of FIG. 23. The left view of FIG. 24 shows the wafer before splitting, and the right view of FIG. 24 shows the wafer after splitting. FIG. 24 shows the kerf loss that occurs when each 51 in the left view of FIG. 23 becomes a corner 51b with a large R due to the grinding process.

[0024] Note that the kerf loss is so-called material loss and indicates the portion removed as chips along with the cutting of the wafer. Specifically, in the right view of FIG. 24, the portion corresponding to the boundary of the wafer after splitting is the kerf loss.

[0025] When the radius R of corner 51b is large as in the left view of FIG. 24, the end shape becomes sharp as in the right view of FIG. 24. This shape is hereinafter referred to as a knife edge. Due to this knife edge, chipping and dust generation occur.

[0026] Chipping and dust generation by the knife edge are suppressed more as the kerf loss during dicing is larger. That is, even when the R of the corner 51b is large, the concerns about chipping and dust generation are reduced. For example, when the kerf loss during dicing is larger than 100 μm, R = 200 μm or less is acceptable. Also, when the kerf loss is even smaller, from 100 μm to 80 μm, R = 150 μm or less is acceptable. In addition, when the kerf loss is even smaller, 60 μm or less, R = 100 μm or less is acceptable. However, when one of the diced wafers is processed and reused to form a device again, it is preferable that the kerf loss and the R of the corner 51b are smaller.

[0027] Furthermore, if the angle of the terrace is from 45 degrees to 135 degrees, dust generation or chipping by the knife edge can be reduced. If it is from 60 degrees to less than 120 degrees, dust generation or chipping can be further reduced. If it is from 75 degrees to less than 105 degrees, dust generation or chipping due to the edge shape can be almost suppressed.

[0028] Note that in this grinding process, it is preferable that the width to be processed is smaller. When the grinding width is large, in the outer peripheral portion of the wafer 16, the region where the substrate thickness is thin becomes large, so chipping and cracks are likely to occur. It has been found that this chipping and cracking occur frequently when the grinding width is 10 mm or more. Therefore, the grinding width is preferably less than 10 mm, and even smaller, for example, less than 5 mm, less than 3 mm, or less than 1 mm is more preferable.

[0029] Also, this grinding process is preferably performed to a depth that leaves a substrate thickness of 100 μm or more. Thereby, it is possible to suppress cracks and chips generated at the ends of the wafers reused after the dicing process described later.

[0030] Furthermore, this grinding process may be performed before or after the formation of the epitaxial film that is performed before forming the semiconductor element structure 14. Also, this grinding process is performed outside the semiconductor element structure 14 so as not to damage the semiconductor element structure 14.

[0031] FIG. 3 is a diagram showing the splitting process according to Embodiment 1 of the present disclosure. In the splitting process of the present embodiment, the wafer 16 is split in a direction perpendicular to the thickness direction at a position shallower than the depth at which the outer peripheral portion of the wafer 12 is ground from the second main surface. As a result, the semiconductor device 102 is split into a split wafer 18 including the semiconductor element structure 14 and a split wafer 20 not including the semiconductor element structure 14. That is, the split wafer 20 not including the semiconductor element structure 14 is split from the wafer 16.

[0032] At this time, the outer peripheral portion of the split wafer 18 does not become a knife edge. This is because the outermost peripheral portion that could become a knife edge has been excluded in advance by performing the grinding process shown in FIG. 2. As a result, the split wafer 18 can proceed with the manufacturing process of the semiconductor device without generating dust or chipping.

[0033] Furthermore, the wafer diameter of the split wafer 20 is the same as the wafer diameter of the original wafer 12. This is because the grinding process of the present embodiment does not exclude the outermost peripheral portion, unlike the beveling process described later with reference to FIG. 10. That is, by suppressing the reduction of the wafer diameter, conveyance and processing can be performed using the same apparatus as the wafer before processing.

[0034] Note that the splitting method may be a method involving contact by a dicing saw or the like, or a method not involving contact by a laser or the like. For example, a laser slicing technique may be used in which a modified layer is provided by a laser and then split in a direction perpendicular to the direction from the first main surface toward the second main surface.

[0035] Also, the substrate thickness of the split wafer 20 is preferably 100 μm or more. This is because if the substrate thickness of the split wafer 20 is thin, problems such as cracking or warping may occur during the subsequent processes of FIGS. 4 to 7, making conveyance and processing difficult.

[0036] FIG. 4 is a diagram showing the bonding process according to Embodiment 1 of the present disclosure. In the bonding process of the present embodiment, another divided wafer 20 is bonded to the first main surface of the divided wafer 20. As a result, a bonded wafer 21 having the same wafer diameter as the original wafer 12 is formed. In this way, by bonding a plurality of divided wafers 20 to increase the substrate thickness, the wafer warpage can be suppressed more effectively than when using a single divided wafer 20.

[0037] FIG. 5 is an enlarged view showing the bonding process according to Embodiment 1 of the present disclosure. The bonding process of the present embodiment may be carried out using a technique such as room temperature bonding. At this time, an amorphous layer 24 is formed at the bonding interface of the bonded wafer 21.

[0038] Room temperature bonding is a bonding method that does not include a metal layer or the like at the bonding interface, so a clean interface can be obtained. In addition, by performing a flattening process of polishing at least one of the bonding interfaces before the bonding process to make it flat, the adhesive force during bonding can be improved. Note that the flattening may be performed by CMP or the like instead of polishing.

[0039] FIG. 6 is a diagram showing the beveling process according to Embodiment 1 of the present disclosure. In the beveling process of the present embodiment, the outer peripheral portion on the second main surface side of the bonded wafer 21 is ground into a tapered shape. That is, the outer peripheral portion of the dividing surface of the divided wafer 20 on the second main surface side is ground into a tapered shape. As a result, a divided wafer 30 having a tapered outer peripheral portion on the second main surface side and a bonded wafer 23 in which the unprocessed divided wafer 20 is bonded are formed. By this process, the shape of the bonded wafer 21 can be made closer to the shape of the original wafer 12, so that fine adjustment for wafer alignment becomes unnecessary.

[0040] The fine adjustment of wafer alignment will be described in detail. In wafer alignment, when a laser beam is scanned over the wafer, the location where the light transmission amount becomes equal to or less than the threshold value is recognized as the wafer edge. When the edge of the wafer is processed into a tapered shape, it becomes difficult for light to pass through due to surface roughness of the tapered portion, so the wafer edge is more easily recognized.

[0041] On the other hand, for example, when the cross-section of the wafer is ground so as to have a convex structure, the wafer edge becomes thinner compared to the central part of the wafer. In this case, the light transmission amount at the wafer edge may not fall below the threshold value, and the wafer edge may not be recognized.

[0042] Therefore, when processing this wafer and a normal wafer using the same apparatus, it is necessary to adjust the light transmission threshold value each time, or to set a new threshold value that can recognize the edges of both wafers. That is, in either case, fine adjustment for wafer alignment is required. In the bevel processing step of the present embodiment, since the outer peripheral portion on the second main surface side of the bonded wafer 21 is ground into a tapered shape, there is an advantage that this fine adjustment becomes unnecessary.

[0043] Also, the bonded wafer 23 may be processed so that the whole has a desired substrate thickness, for example, by grinding, polishing, CMP, or the like. The desired substrate thickness may be, for example, the same substrate thickness as the wafer 12. Thereby, when reusing the bonded wafer 23 as a wafer, it is possible to perform conveyance and processing using the same apparatus as the wafer before processing without performing adjustment due to the difference in substrate thickness.

[0044] FIG. 7 is a diagram showing an element formation step according to Embodiment 1 of the present disclosure. In the element formation step of the present embodiment, an epitaxial film is formed on the second main surface side of the bonded wafer 23, and a semiconductor element structure 14 is formed on the epitaxial film. That is, a semiconductor element structure 14 is formed on the dividing surface of the divided wafer 30. Note that the semiconductor element structure 14 is formed inside the outermost peripheral portion of the divided wafer 30 having a tapered shape.

[0045] The semiconductor device 108 thus obtained has the same functions as the semiconductor device 100. Therefore, the semiconductor device 108 can also sequentially perform the steps shown in FIGS. 2 to 7 in the same manner as the semiconductor device 100.

[0046] As described above, by suppressing the reduction of the wafer diameter of the semiconductor device through the steps shown in FIGS. 2 to 7, it is possible to perform conveyance and processing using the same apparatus as the wafer before processing. [Processing Method of Semiconductor Device According to Comparative Example] To explain the effects of the semiconductor device according to the present disclosure, a processing method of a semiconductor device according to a comparative example will be described. FIG. 8 is a diagram showing a semiconductor device according to a first comparative example. The semiconductor device 500 includes a wafer 502 and a semiconductor element structure 504, and has the same configuration as the semiconductor device 100.

[0047] FIG. 9 is a diagram showing a dicing process according to the first comparative example. In the dicing process according to the first comparative example, the wafer 502 is diced in a direction perpendicular to the thickness direction. As a result, the semiconductor device 500 is divided into a diced wafer 506 including the semiconductor element structure 504 and a diced wafer 508 not including the semiconductor element structure 504.

[0048] At this time, the outer peripheral portion of the diced wafer 506 becomes a thin and sharp knife edge. When the manufacturing process of the semiconductor device is advanced using a wafer with a knife edge at the outer peripheral portion, problems such as dust generation by scraping the carrier for storing the wafer and chipping occur. Therefore, when performing the wafer dicing process, processing is required so that the outer peripheral portion does not become a knife edge.

[0049] FIG. 10 is a diagram showing a bevel processing step according to a second comparative example. In the second comparative example, a bevel processing step is performed on the semiconductor device 500 having the same configuration as the first comparative example before the dicing step.

[0050] In the bevel processing step according to the second comparative example, the outer peripheral portion of the wafer 502 is ground so as to penetrate in the thickness direction. That is, the outermost peripheral portion of the wafer 502 is excluded. As a result, a diced wafer 510 including the semiconductor element structure 504 and a wafer outer peripheral portion 512 not including the semiconductor element structure 504 are generated.

[0051] FIG. 11 is a diagram showing a dicing process according to the second comparative example. In the dicing process according to the second comparative example, the diced wafer 510 is diced in a direction perpendicular to the thickness direction. As a result, the diced wafer 510 is divided into a diced wafer 514 including the semiconductor element structure 504 and a diced wafer 516 not including the semiconductor element structure 504.

[0052] At this time, the outer peripheral portion of the divided wafer 514 does not become a knife edge. This is because the outermost peripheral portion that could become a knife edge has been excluded in advance by performing the beveling process shown in FIG. 10. As a result, the divided wafer 514 can proceed with the manufacturing process of the semiconductor device without generating dust or chipping.

[0053] On the other hand, the wafer diameter of the divided wafer 516 becomes smaller compared to the wafer diameter of the original wafer 502. This is because the outermost peripheral portion has been excluded by performing the beveling process shown in FIG. 10. As a result, when reusing the divided wafer 516, there arises a problem that it is not possible to use the same apparatus for conveyance and processes as the wafer before processing, or it is necessary to adjust the apparatus so as to be able to cope with the change in the wafer diameter. The present disclosure can solve this problem.

[0054] [Method for processing a semiconductor device according to a modification of Embodiment 1 of the present disclosure] Hereinafter, a processing method according to a modification of the present embodiment will be described. FIG. 12 is a diagram showing a modification of the grinding process according to Embodiment 1 of the present disclosure. The grinding process of the modification is different from the grinding process of FIG. 6 in that it further includes a process of grinding the entire outer peripheral portion of the wafer.

[0055] The upper diagram in FIG. 12 is a diagram showing the semiconductor device 100 before the grinding process. The lower diagram in FIG. 12 is a diagram showing the semiconductor device 102a after the grinding process. The grinding process of the modification includes, in addition to the grinding process of Embodiment 1, a process of grinding the entire outermost peripheral portion of the wafer. Therefore, the wafer diameter of the wafer 16a after the grinding process is smaller than the wafer diameter of the wafer 12.

[0056] Since the end portion on the back side of the wafer 16 has a tapered shape, the substrate thickness becomes thinner as it is closer to the end portion. As a result, there is a possibility that cracks and chips may occur at the end portion on the back side of the wafer 16. The grinding process of the modification has an effect of suppressing cracks and chips at this end portion by also grinding the outer peripheral portion on the back side of the wafer 16a.

[0057] In addition, in the grinding process of the modification example, it is preferable that the width of grinding the entire outermost peripheral portion of the wafer, that is, the reduction in the wafer diameter is small. This is because when the width to be processed is large, the wafer diameter of the wafer to be reused in the future becomes small, causing a problem that conveyance and processing during the formation of the device structure become impossible.

[0058] If the reduction in the wafer diameter is less than 1 mm, it can be dealt with by adjusting the device or changing the jig. Also, if the reduction in the wafer diameter is less than 0.8 mm, the number of devices that can be dealt with without adjusting the device or changing the jig increases. Further, if the reduction in the wafer diameter is less than 0.5 mm, the number of devices that can be dealt with without adjusting the device or changing the jig further increases. From the above, the width of grinding the entire outer peripheral portion of the wafer is preferably less than 1 mm, more preferably less than 0.8 mm, and even more preferably less than 0.5 mm.

[0059] Also, the width of grinding the entire outermost peripheral portion of the wafer in the grinding process of the modification example is much smaller than the width of processing the outer peripheral portion in the bevel processing step according to the second comparative example. This is because the purpose of the bevel processing step according to the second comparative example can be achieved by forming a convex structure in the grinding process of the modification example. Therefore, the grinding process of the modification example has the effect of suppressing the reduction in the wafer diameter as compared with the comparative example.

[0060] FIG. 13 is a diagram showing a first modification example of the bonding step according to Embodiment 1 of the present disclosure. In the bonding step of the first modification example, a divided wafer 20 and a divided wafer 22 having a smaller wafer diameter than the divided wafer 20 are bonded. As a result, a bonded wafer 21a having a convex cross-sectional structure is formed. By forming the bonded wafer having such a convex structure, in addition to suppressing the warpage of the wafer, the bevel processing step that has been continuously performed can be omitted.

[0061] FIG. 14 is a diagram showing a second modification of the bonding process according to Embodiment 1 of the present disclosure. The bonding process of the second modification is different from that of Embodiment 1 in the planarization process performed before bonding. Specifically, more polishing is performed on the outer peripheral portion of the bonding interface than on the central portion of the bonding interface. As a result, the outer peripheral portion of the wafer becomes thinner than the central portion, and an unbonded region 26 is formed in the outer peripheral portion of the bonding interface of the bonded wafer 21b.

[0062] By measuring this unbonded region 26 with, for example, an optical interference type wafer thickness measuring instrument, the substrate thickness of each divided wafer that is bonded can be measured. That is, the depth of the bonding interface of the bonded wafer 21b can be detected in advance.

[0063] For example, when using a wafer in which the dicing process and the bonding process are repeated multiple times, a bonding interface may exist in the vicinity of the semiconductor element structure 14 of the completed semiconductor device. In this case, problems such as characteristic defects and reliability degradation of the completed semiconductor device occur. Here, this modification can detect in advance the bonding interface existing in the vicinity of the semiconductor element structure 14. Therefore, by grinding and removing the corresponding bonding interface, the above problems can be avoided.

[0064] Note that moisture penetrates into this unbonded region in the subsequent wet etching process. This moisture cannot be removed by spin drying performed as a post-treatment of the wet etching process, and may cause problems in subsequent manufacturing processes. On the other hand, if the unbonded region is 1 mm or less from the outer periphery, the amount of moisture that penetrates can be ignored. Therefore, the unbonded region is preferably 1 mm or less from the outer periphery of the bonded wafer 21b.

[0065] FIG. 15 is a diagram showing a modified example of the bevel processing step according to Embodiment 1 of the present disclosure. In the bevel processing step of the modified example, the outer peripheral portion on the second main surface side of the bonding wafer 21 is processed so that the cross section has a convex structure. As a result, a bonded wafer 23a is formed by bonding a divided wafer 30a whose inner diameter has become smaller due to the outer peripheral portion being uniformly ground, and a divided wafer 20a whose cross section has a convex structure due to the outer peripheral portion being uniformly ground to a certain depth. That is, the inner diameter of the upper surface of the divided wafer 20a becomes the same as the inner diameter of the divided wafer 30a.

[0066] The bevel processing step of this modified example may be performed, for example, on the bonding wafer 21b according to the second modified example of the bonding step. In this case, the unbonded region 26 can be removed by the bevel processing step.

[0067] Embodiment 2 [Processing Method of Semiconductor Device According to Embodiment 2 of the Present Disclosure] FIG. 16 is a diagram showing a thickening step according to Embodiment 2 of the present disclosure. In Embodiment 1, in order to suppress the warping of the divided wafers 20, a bonding step of bonding a plurality of divided wafers 20 was performed. On the other hand, in the thickening step of this embodiment, an epitaxial film 32 is formed on the divided wafer 20. As a result, a thick film wafer 41 having the same wafer diameter as the original wafer 12 is formed. By increasing the substrate thickness in this way, the warping of the wafer can be suppressed more than when the divided wafer 20 is used alone. Note that the epitaxial film may be formed on either the first main surface or the second main surface.

[0068] Here, it is preferable that the difference in specific resistance between the epitaxial film 32 and the divided wafer 20 is small. When the difference in specific resistance between the epitaxial film 32 and the divided wafer 20 becomes large, the electrical characteristics change. As a result, there is a problem that the electrical characteristics of the entire semiconductor device fluctuate when the semiconductor element structure 14 is formed in the subsequent step.

[0069] If the difference in specific resistance described above is within 30 mΩ·m, the variation in the electrical characteristics of the entire semiconductor device will be within the range where it can be used equivalently to the original semiconductor device. Also, if the difference in specific resistance described above is within 15 mΩ·m, the variation in the electrical characteristics of the entire semiconductor device will be within the error range. Furthermore, if the difference in specific resistance described above is within 6 mΩ·m, the variation in the electrical characteristics of the entire semiconductor device will be almost zero.

[0070] From the above, the difference in specific resistance between the epitaxial film 32 and the divided wafer 20 is preferably within 30 mΩ·m, more preferably within 15 mΩ·m, and even more preferably within 6 mΩ·m.

[0071] Also, it is preferable that the epitaxial film 32 is thicker. This is because when the epitaxial film 32 is thin, there will be a problem that the effect of suppressing the warp of the divided wafer 20 cannot be sufficiently obtained.

[0072] If the thickness of the epitaxial film 32 is 50 μm or more, the warp can be sufficiently suppressed, but there may be an error in conveyance or adsorption in the manufacturing apparatus used. Also, if the thickness of the epitaxial film 32 is 100 μm or more, the warp can be sufficiently suppressed, and at the same time, an error in conveyance or adsorption in the manufacturing apparatus used hardly occurs. Furthermore, if the thickness of the epitaxial film 32 is 150 μm, the semiconductor device 114 will have the same thickness as the wafer before division, so an error in conveyance or adsorption in the manufacturing apparatus used does not occur.

[0073] From the above, the thickness of the epitaxial film 32 is preferably 50 μm or more, more preferably 100 μm or more, and even more preferably 150 μm.

[0074] FIG. 17 is a diagram showing the bevel processing step according to Embodiment 2 of the present disclosure. In the bevel processing step of the present embodiment, the outer peripheral portion on the second main surface side of the thick film wafer is processed into a tapered shape. As a result, a thick film wafer 43 is obtained in which an epitaxial film 34 having the outer peripheral portion on the second main surface side processed into a tapered shape is formed on the unprocessed divided wafer 20.

[0075] Also, the thick film wafer 43 may be processed to have a desired substrate thickness, for example, by grinding, polishing, CMP, or the like. The desired substrate thickness may be, for example, the same substrate thickness as the wafer 12. Thereby, when the thick film wafer 43 is reused as a wafer, conveyance and processing can be performed using the same apparatus as the wafer before processing without performing adjustment due to the difference in substrate thickness.

[0076] FIG. 18 is a diagram showing an element formation process according to Embodiment 2 of the present disclosure. In the element formation process of the present embodiment, an epitaxial film is formed on the second main surface side of the thick film wafer 43, and a semiconductor element structure 14 is formed on the epitaxial film. Note that the semiconductor element structure 14 is formed inside the outermost peripheral portion of the epitaxial film 34 having a tapered shape.

[0077] The semiconductor device 118 obtained thereby has the same functions as the semiconductor device 100. Therefore, the semiconductor device 118 can also sequentially perform the processes shown in FIGS. 2 to 7, or FIGS. 2 to 3 and FIGS. 16 to 18, similarly to the semiconductor device 100.

[0078] As described above, by suppressing the reduction in the wafer diameter of the semiconductor device through the processes shown in FIGS. 16 to 18, conveyance and processing can be performed using the same apparatus as the wafer before processing.

[0079] [Processing method of semiconductor device according to a modification of Embodiment 2 of the present disclosure] FIG. 19 is a diagram showing a modification of the bevel processing step according to Embodiment 2 of the present disclosure. In the bevel processing step of the modification, the outer peripheral portion on the second main surface side of the thick film wafer 41 is processed so that the cross section has a convex structure. As a result, a thick film wafer 43a is obtained in which an epitaxial film 34a having a uniformly ground outer peripheral portion is formed on a divided wafer 20b whose outer peripheral portion is uniformly ground to a certain depth.

[0080] For example, the bevel processing step of this modification may be performed on a semiconductor device having an unbonded region 26, such as the semiconductor device 104b. In this case, the unbonded region 26 can be removed by the bevel processing step.

[0081] Embodiment 3 FIG. 20 is a diagram showing a bevel processing step according to Embodiment 3 of the present disclosure. In Embodiments 1 and 2, in order to suppress the warpage of the wafer 16, the bevel processing step was performed after thickening the entire wafer. On the other hand, the substrate thickness of the divided wafer according to the present embodiment is such that its warpage is within a range that does not cause problems in the manufacturing process. Therefore, it is reused without thickening the divided wafer. As a result, the man-hours required for wafer reuse can be reduced.

[0082] In the bevel processing step of the present embodiment, the outer peripheral portion on the second main surface side of the divided wafer is processed into a tapered shape. As a result, a divided wafer 30b having the outer peripheral portion on the second main surface side processed into a tapered shape is obtained.

[0083] FIG. 21 is a diagram showing an element formation step according to Embodiment 3 of the present disclosure. In the element formation step of the present embodiment, an epitaxial film is formed on the second main surface side of the divided wafer 30b, and a semiconductor element structure 14 is formed on the epitaxial film. Note that the semiconductor element structure 14 is formed inside the outermost peripheral portion of the divided wafer 30b having a tapered shape.

[0084] The semiconductor device 128 obtained thereby has the same functions as the semiconductor device 100. Therefore, the semiconductor device 128 can also sequentially perform the steps shown in FIGS. 2 to 7 in the same manner as the semiconductor device 100.

[0085] As described above, by suppressing the reduction of the wafer diameter of the semiconductor device through the steps shown in FIGS. 20 to 21, it is possible to perform conveyance and processing using the same device as the wafer before processing.

[0086] FIG. 22 is a diagram showing a modification of the bevel processing step according to Embodiment 3 of the present disclosure. In the bevel processing step of the modification, the outer peripheral portion on the second main surface side of the divided wafer may be processed so that the cross section has a convex structure. As a result, a divided wafer 30c having the outer peripheral portion uniformly ground is obtained.

[0087] In the present disclosure, a mode of bonding two divided wafers has been described, but any mode of bonding a plurality of divided wafers may be used. That is, the content of the present disclosure may be applied to a mode of bonding three or more divided wafers.

[0088] Hereinafter, the aspects of the present disclosure will be summarized as appendices.

[0089] (Appendix 1) A step of forming a semiconductor element structure on the second main surface of a wafer having a first main surface and a second main surface facing each other; A step of grinding an outer peripheral portion of the second main surface of the wafer on which the semiconductor element structure is formed to a position midway in the thickness direction from the second main surface toward the first main surface; A step of dividing the wafer in a direction perpendicular to the thickness direction at a position shallower than the depth of grinding of the outer peripheral portion of the wafer, and dividing the wafer into a first divided wafer that does not include the semiconductor element structure; A step of grinding an outer peripheral portion of a dividing surface of the first divided wafer; A step of forming a semiconductor element structure on the dividing surface of the first divided wafer whose outer peripheral portion of the dividing surface has been ground; A method for manufacturing a semiconductor device including: (Appendix 2) The method for manufacturing a semiconductor device according to Appendix 1, further including a step of bonding a second divided wafer to the first main surface of the first divided wafer. (Appendix 3) The method for manufacturing a semiconductor device according to Appendix 2, wherein an amorphous layer is formed at a bonding interface between the first divided wafer and the second divided wafer. (Appendix 4) The method further includes a step of polishing and planarizing a bonding interface of the first divided wafer or the second divided wafer before bonding, The method for manufacturing a semiconductor device according to Appendix 2 or 3, wherein polishing at an outer peripheral portion of the bonding interface is performed more than polishing at a central portion of the bonding interface. (Appendix 5) A cross section of the wafer after grinding the outer peripheral portion of the second main surface and before dividing is a convex structure. A method for manufacturing a semiconductor device according to any one of claims 1 to 4. (Appendix 6) The method for manufacturing a semiconductor device according to claim 5, further comprising a step of grinding the entire outermost peripheral portion of the wafer before dividing the wafer. (Appendix 7) The outer peripheral portion of the dividing surface of the first divided wafer is ground in a tapered shape. A method for manufacturing a semiconductor device according to any one of claims 1 to 6. (Appendix 8) After grinding the outer peripheral portion of the dividing surface of the first divided wafer and before forming the semiconductor element structure on the dividing surface, the cross section of the wafer is a convex structure. A method for manufacturing a semiconductor device according to any one of claims 1 to 6. (Appendix 9) The method further comprises a step of forming an epitaxial film on the first divided wafer. A method for manufacturing a semiconductor device according to claim 1. (Appendix 10) The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the wafer is formed of a wide bandgap semiconductor. (Appendix 11) A first divided wafer having a first main surface and a second main surface facing each other, and having a semiconductor element structure on the second main surface, and A second divided wafer bonded to the first main surface of the first divided wafer comprising: An unbonded region is formed at the outer peripheral portion of the bonding interface between the first divided wafer and the second divided wafer. A semiconductor device. (Appendix 12) An amorphous layer is formed on the bonding interface. A semiconductor device according to claim 11. (Appendix 13) The outer peripheral portion of the first divided wafer is processed in a tapered shape. A semiconductor device according to claim 11 or 12. (Appendix 14) The wafer diameter of the first divided wafer is smaller than the wafer diameter of the second divided wafer. The semiconductor device according to any one of claims 11 to 13. (Appendix 15) The cross section of the second divided wafer has a convex structure, The inner diameter of the upper surface of the second divided wafer is the same as the inner diameter of the first divided wafer. The semiconductor device according to any one of claims 11 to 14. (Appendix 16) A first divided wafer having a first main surface and a second main surface facing each other, An epitaxial film formed on the second main surface of the first divided wafer, A semiconductor element structure formed on the epitaxial film and comprising A semiconductor device in which the cross section of the first divided wafer has a convex structure. (Appendix 17) The epitaxial film is 50 μm or more. The semiconductor device according to claim 16. (Appendix 18) Comprising a first divided wafer having a first main surface and a second main surface facing each other and having a semiconductor element structure on the second main surface, The cross section of the first divided wafer has a convex structure Semiconductor device.

Explanation of Signs

[0090] 12 Wafer 14 Semiconductor element structure 16 Wafer 16a Wafer 18 Divided wafer 20 Divided wafer 20a Divided wafer 20b Divided wafer 22 Divided wafer 24 Amorphous layer 26 Unbonded region 30 Divided wafer 30a Divided wafer 30b Divided wafer 30c Split Wafer 32 Epitaxial Film 34 Epitaxial Film 34a Epitaxial Film 100 Semiconductor Device 102 Semiconductor Device 102a Semiconductor Device 104b Semiconductor Device 108 Semiconductor Device 114 Semiconductor Device 118 Semiconductor Device 128 Semiconductor Device 500 Semiconductor Device 502 Wafer 504 Semiconductor Element Structure 506 Split Wafer 508 Split Wafer 510 Split Wafer 514 Split Wafer 516 Split Wafer

Claims

1. Forming a semiconductor element structure on the second main surface of a wafer having first and second main surfaces facing each other; Grinding the outer peripheral portion of the second main surface of the wafer on which the semiconductor element structure has been formed to a position midway in the thickness direction from the second main surface toward the first main surface; Dividing the wafer in a direction perpendicular to the thickness direction at a position shallower than the depth to which the outer peripheral portion of the wafer has been ground, and dividing a first divided wafer that does not include the semiconductor element structure from the wafer; Grinding the outer peripheral portion of the dividing surface of the first divided wafer; Forming a semiconductor element structure on the dividing surface of the first divided wafer whose outer peripheral portion of the dividing surface has been ground A method for manufacturing a semiconductor device comprising the steps of.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of bonding a second divided wafer to the first main surface of the first divided wafer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein an amorphous layer is formed at the bonding interface between the first divided wafer and the second divided wafer.

4. Further comprising a step of polishing and planarizing the bonding interface of the first divided wafer or the second divided wafer before bonding, The method for manufacturing a semiconductor device according to claim 2, wherein polishing at the outer peripheral portion of the bonding interface is performed more than polishing at the central portion of the bonding interface.

5. The cross-section of the wafer after grinding the outer peripheral portion of the second main surface and before dividing is a convex structure The method for manufacturing a semiconductor device according to claim 1.

6. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of grinding the entire outermost peripheral portion of the wafer before dividing the wafer.

7. The outer peripheral portion of the dividing surface of the first divided wafer is ground in a tapered shape The method for manufacturing a semiconductor device according to claim 1.

8. The cross-section of the wafer after grinding the outer peripheral portion of the dividing surface of the first divided wafer and before forming the semiconductor element structure on the dividing surface is a convex structure The method for manufacturing a semiconductor device according to claim 1.

9. Further comprising a step of forming an epitaxial film on the first divided wafer The method for manufacturing a semiconductor device according to claim 1.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the wafer is formed of a wide bandgap semiconductor.

11. A first divided wafer having first and second main surfaces facing each other and having a semiconductor element structure on the second main surface, and A second divided wafer bonded to the first main surface of the first divided wafer and a semiconductor device in which an unbonded region is formed at an outer peripheral portion of a bonding interface between the first divided wafer and the second divided wafer .

12. The semiconductor device according to claim 11, wherein an amorphous layer is formed on the bonding interface .

13. The semiconductor device according to claim 11, wherein an outer peripheral portion of the first divided wafer is processed into a tapered shape .

14. The semiconductor device according to claim 11, wherein a wafer diameter of the first divided wafer is smaller than a wafer diameter of the second divided wafer .

15. The semiconductor device according to claim 11, wherein a cross section of the second divided wafer has a convex structure, and an inner diameter of an upper surface of the second divided wafer is the same as an inner diameter of the first divided wafer .

16. A first divided wafer having a first main surface and a second main surface facing each other, an epitaxial film formed on the second main surface of the first divided wafer, and a semiconductor element structure formed on the epitaxial film and a semiconductor device in which a cross section of the first divided wafer has a convex structure .

17. The semiconductor device according to claim 16, wherein the epitaxial film is 50 μm or more .

18. A semiconductor device including a first divided wafer having a first main surface and a second main surface facing each other, and having a semiconductor element structure on the second main surface, wherein a cross section of the first divided wafer has a convex structure

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