Printed wiring board and power conversion device

Abstract

To provide a printed circuit board and a power conversion device that implement reduction in electric field strength and prevention of dielectric breakdown.SOLUTION: A printed wiring board 100 includes an insulating substrate 1, an inner layer conductor pattern 2, an interlayer insulating layer 3 formed so as to cover the inner layer conductor pattern, and an outer layer conductor pattern 4 that is formed on a surface opposite to a surface on the insulating substrate side and facing the inner layer conductor pattern in a plate thickness direction. The inner layer conductor pattern has a surface region 7 which is a surface on the outer layer conductor pattern side, and the outer layer conductor pattern has an inner layer surface 4b which is a surface on the interlayer insulating layer side and a side edge portion 4a which is a side surface on which an edge is formed. An end portion of the inner layer surface of the outer layer conductor pattern is formed at a position where it does not overlap with the surface region of the inner layer conductor pattern in a planar direction. The distance X in the planar direction between the end portion of the inner layer surface of the outer layer conductor pattern and the end portion of the surface region of the inner layer conductor pattern is longer than half the distance Z in the plate thickness direction between the outer layer conductor pattern and the inner layer conductor pattern.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a printed wiring board and a power conversion device.

Background Art

[0002] In order to effectively utilize resources, promote energy conservation, and suppress the emission of global warming gases, power conversion devices using power semiconductor devices are widely used in various fields such as consumer, automotive, railway, industrial, and infrastructure applications. For example, automotive power conversion devices include electric vehicles (EVs) driven by motors and hybrid cars (HEVs) that combine motor drive and engine drive. In particular, in EVs, since they run only on the driving force of the motor, which is electric power, a power conversion device capable of handling high voltages is required. Also, in the case of EVs, due to the relationship of the cruising range, the size of the battery increases and the weight increases, so miniaturization, light weight, and high capacity of the battery are required, and at the same time, miniaturization and light weight of the power conversion device are also required.

[0003] For example, in Patent Document 1 below, a first heat sink, a second heat sink facing the first heat sink, a printed circuit board having a first circuit pattern formed on the surface and the back surface facing the first heat sink, a first insulating member provided between the first heat sink and the printed circuit board, an electrode portion composed of a metal plate whose back surface is electrically joined to the first circuit pattern via a first joining member, a semiconductor chip electrically joined to the electrode portion, a resin portion for sealing a part of the surface side of the electrode portion and the semiconductor chip, a switching element having the above, a first fixing member whose back surface is joined to the exposed surface on the surface side of the electrode portion, a heat radiating member provided between one end joined to the surface of the electrode portion via the first fixing member and the other end facing the surface of the resin portion of the switching element and the second heat sink, a second insulating member sandwiched between the second heat sink and the heat radiating member, and a mounting portion for fixing the first heat sink and the second heat sink by connecting one end to the first heat sink and the other end to the second heat sink respectively, and a configuration for mounting a power semiconductor device on a printed circuit board for miniaturization and weight reduction is disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the configuration described in Patent Document 1, due to the handling of high voltage and large current, the wiring of the printed wiring board uses a conductor foil or conductor plate with a thickness of 100 μm or more. Therefore, the lower end of the circuit conductor pattern formed by etching needs to be sharpened as the conductor foil becomes thicker. At the tip of the sharp-angled lower end formed in this way, the electric field is concentrated and the electric field strength becomes high, making it easy for partial discharge to occur and for insulation degradation due to migration to progress. Therefore, in the printed wiring board, there is a possibility of dielectric breakdown between conductor patterns overlapping in the board thickness direction.

Means for Solving the Problems

[0006] The printed wiring board and the power conversion device include an insulating substrate, an inner layer conductor pattern formed on the insulating substrate, an interlayer insulating layer formed on the insulating substrate to cover the inner layer conductor pattern, and an outer layer conductor pattern formed on a surface of the interlayer insulating layer opposite to the surface on the insulating substrate side and provided to face the inner layer conductor pattern in the plate thickness direction. The inner layer conductor pattern has a surface region that is a surface on the outer layer conductor pattern side. The outer layer conductor pattern has an inner layer surface that is a surface on the interlayer insulating layer side and a side edge portion that is a side surface where an edge is formed. An end portion of the inner layer surface of the outer layer conductor pattern is formed at a position that does not overlap with the surface region of the inner layer conductor pattern in the planar direction. A first distance in the planar direction between the end portion of the inner layer surface of the outer layer conductor pattern and the end portion of the surface region of the inner layer conductor pattern is longer than half of a second distance in the plate thickness direction between the outer layer conductor pattern and the inner layer conductor pattern. Different voltages with different potentials are applied to the outer layer conductor pattern and the inner layer conductor pattern.

Advantages of the Invention

[0007] It is possible to provide a printed wiring board and a power conversion device that realize reduction of electric field strength and prevention of dielectric breakdown.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Modes for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and for the sake of clarity of explanation, omissions and simplifications are made as appropriate. The present invention can also be implemented in various other forms. Unless otherwise specified, each component may be in a single or plural number.

[0010] In the drawings, the positions, sizes, shapes, ranges, etc. of the respective components shown may not represent the actual positions, sizes, shapes, ranges, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

[0011] (One Embodiment and Overall Configuration) (FIG. 1) The printed wiring board 100 included in the power conversion device has an insulating substrate 1, an inner layer conductor pattern 2, an interlayer insulating layer 3, an outer layer conductor pattern 4, and a solder resist 5. Although not shown, the power conversion device is composed of a power module including power semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor) and SiC, a printed wiring board 100, a bus bar, a capacitor, and the like.

[0012] The insulating substrate 1 is a substrate with a thickness of 250 μm, and inner layer conductor patterns 2, which are copper foils with a thickness of 210 μm, are formed on both sides thereof. As the material of the insulating substrate 1, glass epoxy in which glass cloth is impregnated with epoxy resin is used, but any organic insulating material, inorganic insulating material, or organic-inorganic composite insulating material may be used. For example, glass phenol in which glass cloth is impregnated with phenol resin, inorganic-organic composite materials such as glass fiber-reinforced polyamide impregnated with polyamide resin, organic materials such as polyimide resin, and insulating substrates made of inorganic materials such as ceramics such as aluminum oxide and silicon nitride may be used.

[0013] The inner layer conductor pattern 2 has a two-stage structure. On the side surfaces of each stage, a first side edge portion 2a and a second side edge portion 2b having edges formed by etching are provided.

[0014] A method for forming the inner layer conductor pattern 2 will be described. First, a copper foil is formed on the surface of the insulating substrate 1, a dry film (not shown) is attached to the formed copper foil, a mask on which the inner layer conductor pattern 2 is formed is superposed, and exposure and development are performed. Then, unnecessary copper foil portions other than the circuit of the inner layer conductor pattern 2 are removed by chemical etching, and the dry film is further removed. Thereby, the inner layer conductor pattern 2 having the first side edge portion 2a is first formed.

[0015] Subsequently, a dry film is formed again on the surface of the inner layer conductor pattern 2, a mask patterned so as to perform half etching from the surface region 7 which is the surface on the outer layer conductor pattern 4 side in the inner layer conductor pattern 2 is superposed, and exposure and development are performed. Then, the inner layer conductor pattern 2 is half-etched so that the remaining copper foil thickness after the half-etching of the inner layer conductor pattern 2 becomes 100 μm which is about half of the copper foil thickness 210 μm of the inner layer conductor pattern 2. Thereby, the second side edge portion 2b is formed on the upper part of the first side edge portion 2a, and the recess 6 described later is also formed. In this way, the inner layer conductor pattern 2 has a stepped structure in which the step on the insulating substrate 1 side is the first step and the step on the outer layer conductor pattern 4 side which is the outer side is the second step.

[0016] The inner layer conductor pattern 2 has a surface region 7 which is the surface facing the surface on the insulating substrate 1 side. The inner layer conductor pattern 2 has a convex-shaped portion 7a which is a convex-shaped conductor portion in the second stage of the inner layer conductor pattern 2. The convex-shaped portion 7a protrudes in the plate thickness direction toward the outer layer conductor pattern 4 and has a protruding shape with the surface region 7 as the top surface. Further, the inner layer conductor pattern 2 has a recess 6 formed around the convex-shaped portion 7a in the planar direction. In the inner layer conductor pattern 2, the thickness between the surface on the insulating substrate 1 side and the recess 6 in the plate thickness direction is smaller than the thickness between the surface on the insulating substrate 1 side and the surface region 7 in the plate thickness direction.

[0017] Interlayer insulating layers 3 are formed on both sides of the insulating substrate 1. A method for forming the interlayer insulating layers 3 will be described. Four glass epoxy prepregs each having a thickness of 60 μm are sequentially stacked on the surface of the inner layer conductor pattern 2 which is a copper foil with a thickness of 210 μm, and then heated and pressed by a lamination press machine. As shown in the figure, the inner layer conductor pattern 2 is covered on the insulating substrate 1, and the interlayer insulating layers 3 are formed on both sides of the insulating substrate 1. Note that the interlayer insulating layer 3 may be made of an organic insulating material or an organic-inorganic composite insulating material.

[0018] On the side of the interlayer insulating layer 3 opposite to the surface on the insulating substrate 1 side, an outer layer conductor pattern 4 is formed on the outer side provided to face the inner layer conductor pattern 2 in the plate thickness direction. A method for forming the outer layer conductor pattern 4 will be described. Copper foils of four-layer laminate are formed on the surface of the interlayer insulating layer 3. The thickness of the formed copper foil is 210 μm. A dry film is attached to the surface of the formed copper foil, and a mask on which the outer layer conductor pattern 4 is formed is overlaid, followed by exposure and development. Then, unnecessary copper foils other than the copper foils required for the circuit of the outer layer conductor pattern 4 are removed by chemical etching, and further the dry film is removed, thereby forming the outer layer conductor pattern 4 shown in the figure.

[0019] The outer layer conductor pattern 4 has an inner layer which is the surface on the interlayer insulating layer 3 side and a side edge portion 4a which is the side surface where the edge is formed. The wiring substrate 100 has a solder resist 5 so as to cover the outer layer conductor pattern 4 on the interlayer insulating layer 3. The method for forming the solder resist 5 is to drill a portion to be a through hole (not shown) with a drilling machine, remove the smear on the hole wall, form a through hole by copper plating, and connect the patterns between the layers. Then, it is formed on the surface so as to cover the outer layer conductor pattern 4. By completing the above steps, a four-layer multilayer printed wiring board 100 can be formed. Note that different voltages with different potentials are applied to the outer layer conductor pattern 4 and the inner layer conductor pattern 2.

[0020] In the outer layer conductor pattern 4, the distance in the planar direction between the end portion 4b of the inner layer surface on the interlayer insulation layer 3 side and the end portion 2c of the surface region 7 of the inner layer conductor pattern 2 is defined as distance X (the first distance). Also, in the plate thickness direction, the distance between the outer layer conductor pattern 4 and the inner layer conductor pattern 2 is defined as distance Z (the second distance). The end portion 4b of the inner layer surface of the outer layer conductor pattern 4 is formed at a position that does not overlap with the surface region 7 of the inner layer conductor pattern 2 in the planar direction, and the distance X is formed to be longer than half of the distance Z. The illustrated distance X is 200 μm and the distance Z is 200 μm.

[0021] (First Modified Example) (Fig. 2) The inner layer conductor pattern 2 may be formed to be wide in cross-section on the insulating substrate 1 in order to facilitate the flow of a large current. Note that the outer layer conductor pattern 4 is the same as in the above-described embodiment. At a position between the two outer layer conductor patterns 4 in the planar direction, recesses 6 are respectively formed at the central portions of the inner layer conductor pattern 2 at positions that overlap with the end portions 4b of the respective outer layer conductor patterns 4 in the planar direction.

[0022] Each recess 6 provided at the central portion of the inner layer conductor pattern 2 is formed such that the copper foil thickness after half etching is 100 μm, which is approximately half of the copper foil thickness 210 μm of the inner layer conductor pattern 2. In this modified example, the distance X is 150 μm and the distance Z is 200 μm.

[0023] (Second Modified Example) (Fig. 3) The width of the surface on the interlayer insulation layer 3 side of the outer layer conductor pattern 4 may be formed wider than the width of the surface region 7 of the inner layer conductor pattern 2. In this modified example, the distance X is 250 μm and the distance Z is 200 μm.

[0024] (Electric field analysis of the conductor pattern comparing the embodiment of the present invention with Comparative Examples 1 and 2) (Figs. 4 to 6) To verify the effects of the present invention, an analysis of the electric field strength ratio was performed using the embodiments of the present invention, Comparative Example 1, and Comparative Example 2. Note that Comparative Example 1 has the configuration shown in FIG. 4, and Comparative Example 2 has the configuration shown in FIG. 5. The manufacturing methods of the respective multilayer printed wiring boards are the same as those of the embodiments of the present invention.

[0025] As shown in FIG. 4, in the printed wiring board 100 of Comparative Example 1, the end portion 4b of the inner layer surface of the outer layer conductor pattern and the end portion 2c of the surface region 7 of the inner layer conductor pattern 2 are formed at substantially the same position in the planar direction. In Comparative Example 1, the distance X was 0 μm and the distance Z was 200 μm. Also, in the printed wiring board 100 of Comparative Example 2 in FIG. 5, the inner layer conductor pattern 2 is formed wide in the same manner as in the embodiment shown in FIG. 2, but the end portion 4b of the inner layer surface of the outer layer conductor pattern and the end portion 2c of the surface region 7 of the inner layer conductor pattern 2 are formed at substantially the same position in the planar direction. In Comparative Example 2, the distance X was 0 μm and the distance Z was 200 μm.

[0026] The graph in FIG. 6 is a graph showing the results of an analysis of the electric field strength ratio using the embodiment of the present invention, Comparative Example 1, and Comparative Example 2. The horizontal axis of this graph takes the calculated value of the calculation formula X - Z / 2 established by the value of the distance X and the value of the distance Z. Also, the vertical axis of this graph takes the maximum electric field strength of each of the end portion 4b of the inner layer surface of the outer layer conductor pattern 4 and the end portion 2c of the surface region 7 of the inner layer conductor pattern 2, and calculates the electric field strength ratio. Note that the vertical axis represents the maximum electric field strength ratio of the end portion 4b of the inner layer surface of the outer layer conductor pattern 4 when X - Z / 2 = 0 as 100%, and represents each electric field strength relative thereto as the electric field strength ratio.

[0027] In the graph of FIG. 6, the configuration of the embodiment of the present invention is represented as (1), the configuration of the first modified example as (2), the configuration of the second modified example as (3), the configuration of Comparative Example 1 as (4), and the configuration of Comparative Example 2 as (5), and the maximum electric field strength ratios of the end portion 4b of the inner layer surface of the outer layer conductor pattern 4 and the end portion 2c of the surface region 7 of the inner layer conductor pattern 2 in each case are plotted.

[0028] According to the graph of Fig. 6, the electric field strength at the end 2c of the surface area 7 of the inner layer conductor pattern 2 was 70.0% for (4) and 38.0% for (5). On the other hand, for the end 4b of the outer layer conductor pattern 4, the electric field was 122.5% for (4) and 145.0% for (5). Thus, it can be seen that in Comparative Example 1 and Comparative Example 2, high electric field strength is generated, which causes partial discharge and migration degradation.

[0029] In the embodiments (1) to (3) of the present invention, the electric field strength at the end 4b of the outer layer conductor pattern 4 was 78.3% for (1), 88.7% for (2), and 68.5% for (3), respectively. Furthermore, the electric field at the end 4b of the surface area 7 of the inner layer conductor pattern 2 increases but is smaller than the electric field strength ratio of 100%. Thus, in the configurations of the embodiments of the present invention compared to Comparative Example 1 and Comparative Example 2, the electric field strength is a small value in all cases. Therefore, with the configuration of the present invention, the electric field strength can be reduced, and the occurrence of partial discharge and insulation degradation due to migration can be prevented.

[0030] (High temperature and high humidity bias test) (Fig. 7) Subsequently, using the embodiments of the present invention and Comparative Example 1 and Comparative Example 2 used in the analysis of Fig. 6, a high temperature and high humidity bias test of the wiring board 100 was performed. The wiring boards 100 having the configurations (1) to (5) representing each of the embodiments of the present invention and Comparative Example 1 and Comparative Example 2 were placed in a high temperature and high humidity chamber at 85°C / 85% RH, and a voltage of DC500V or 1000V was applied between the outer layer conductor pattern 4 and the inner layer conductor pattern 2 of the wiring board 100, and the change in the insulation resistance between the outer layer conductor pattern 4 and the inner layer conductor pattern 2 was continuously measured.

[0031] This test was conducted up to 2000 hours. As the test determination, those in which the insulation resistance continued to be maintained at 1 MΩ or more until 2000 hours of the test completion were judged as pass (〇), and those in which the insulation resistance dropped below 1 MΩ earlier than 2000 hours were judged as fail (×). In the case of a fail determination, the time from the start of the test to the insulation drop was described in the table of Fig. 7 as the life of the printed wiring board 100.

[0032] According to the test results in Fig. 7, when a test voltage of 500 V was applied, the wiring boards (1) to (5) maintained an insulation resistance of 1 MΩ or more continuously for 2000 hours, and all configurations passed the judgment. On the other hand, when a test voltage of 1000 V was applied, in cases (1) to (3), the insulation resistance continued to be maintained at 1 MΩ or more even after 2000 hours of continuous testing and passed the judgment. However, in case (4), the insulation resistance dropped below 1 MΩ after 897.6 hours from the start of the test, and in case (5), it dropped below 1 MΩ after 761.1 hours, respectively reaching their lifetimes. Therefore, at a test voltage of 1000 V, Comparative Example 1 and Comparative Example 2 failed the test. Through the above verification, it became clear that the configuration of the present invention can maintain the insulation resistance even at high voltages, and it was found that the high voltage of the power conversion device can be realized while maintaining the reliability of preventing dielectric breakdown.

[0033] According to the embodiments of the present invention described above, the following operational effects are achieved.

[0034] (1) The printed wiring board 100 includes an insulating substrate 1, an inner layer conductor pattern 2 formed on the insulating substrate 1, an interlayer insulating layer 3 formed on the insulating substrate 1 to cover the inner layer conductor pattern 2, and an outer layer conductor pattern 4 formed on the surface of the interlayer insulating layer 3 opposite to the surface on the insulating substrate 1 side and provided to face the inner layer conductor pattern 2 in the plate thickness direction. The inner layer conductor pattern 2 has a surface region 7 which is the surface on the outer layer conductor pattern 4 side. The outer layer conductor pattern 4 has an inner layer surface which is the surface on the interlayer insulating layer 3 side and a side edge portion 4a which is the side surface where the edge is formed. The end portion 4b of the inner layer surface of the outer layer conductor pattern 4 is formed at a position that does not overlap with the surface region 7 of the inner layer conductor pattern 2 in the planar direction. The first distance X in the planar direction between the end portion 4b of the inner layer surface of the outer layer conductor pattern 4 and the end portion 2c of the surface region 7 of the inner layer conductor pattern 2 is longer than half of the second distance Z in the plate thickness direction between the outer layer conductor pattern 4 and the inner layer conductor pattern 2. Different voltages with different potentials are applied to the outer layer conductor pattern 4 and the inner layer conductor pattern 2. By doing so, reduction of the electric field strength and prevention of dielectric breakdown can be realized.

[0035] (2) The inner layer conductor pattern 2 has a recess 6 between the end of the surface on the insulating substrate 1 side and the end of the surface region 7. In the inner layer conductor pattern 2, the thickness between the surface on the insulating substrate 1 side and the recess 6 is smaller than the thickness between the surface on the insulating substrate 1 side and the surface region 7. By doing so, a distance X is generated, which contributes to the reduction of the electric field strength.

[0036] (3) The thicknesses of the inner layer conductor pattern 2 and the outer layer conductor pattern 4 are each 100 μm or more. By doing so, a power conversion device that handles a large current can be realized.

[0037] (4) The interlayer insulating layer 3 is made of an organic insulating material or an organic-inorganic composite insulating material. By doing so, the functions and effects of the present invention can be realized.

[0038] (5) The insulating substrate 1 is made of an organic insulating material, an inorganic insulating material, or an organic-inorganic composite insulating material. By doing so, the functions and effects of the present invention can be realized.

[0039] (6) A power conversion device including the printed wiring board 100 having the above configuration is adopted. By doing so, reduction of the electric field strength and prevention of dielectric breakdown can be realized, and a power conversion device can be provided.

[0040] Note that the present invention is not limited to the above-described embodiments, and various modifications and combinations with other configurations can be made without departing from the gist thereof. Also, the present invention is not limited to those having all the configurations described in the above embodiments, and those in which a part of the configuration is deleted are also included.

Description of Reference Numerals

[0041] 1 Insulating substrate 2 Inner layer conductor pattern 2a First side edge portion of the inner layer conductor pattern 2b Second side edge portion of the inner layer conductor pattern 2c End portion of the surface region of the inner layer conductor pattern 3 Interlayer insulating layer 4 Outer layer conductor pattern Side edge portion of the outer layer conductor pattern 4a End portion of the inner layer surface of the outer layer conductor pattern 4b 5 Solder resist 6 Recessed portion Surface region of the inner layer conductor pattern 7 7a Convex-shaped portion 100 Printed wiring board

Claims

1. An insulating substrate, An inner layer conductor pattern formed on the insulating substrate, An interlayer insulating layer formed on the insulating substrate to cover the inner layer conductor pattern, In the interlayer insulating layer, an outer layer conductor pattern formed on a surface opposite to the surface on the insulating substrate side and provided to face the inner layer conductor pattern in the plate thickness direction, and The inner layer conductor pattern has a surface region that is a surface on the outer layer conductor pattern side, The outer layer conductor pattern has an inner layer surface that is a surface on the interlayer insulating layer side and a side edge portion that is a side surface where an edge is formed, An end portion of the inner layer surface of the outer layer conductor pattern is formed at a position that does not overlap with the surface region of the inner layer conductor pattern in the planar direction, A first distance in the planar direction between an end portion of the inner layer surface of the outer layer conductor pattern and an end portion of the surface region of the inner layer conductor pattern is longer than half of a second distance in the plate thickness direction between the outer layer conductor pattern and the inner layer conductor pattern, Voltages having different potentials are applied to the outer layer conductor pattern and the inner layer conductor pattern, respectively. A printed wiring board.

2. The inner layer conductor pattern has a convex portion that protrudes in the plate thickness direction toward the outer layer conductor pattern and has the surface region as a top surface, and a concave portion formed around the convex portion in the planar direction, In the inner layer conductor pattern, a thickness between a surface on the insulating substrate side in the plate thickness direction and the concave portion is smaller than a thickness between a surface on the insulating substrate side in the plate thickness direction and the surface region. The printed wiring board according to claim 1.

3. The thicknesses of the inner layer conductor pattern and the outer layer conductor pattern are each 100 μm or more. The printed wiring board according to claim 1.

4. The material of the interlayer insulating layer is an organic insulating material or an organic-inorganic composite insulating material. The printed wiring board according to claim 1.

5. The material of the insulating substrate is an organic insulating material, an inorganic insulating material, or an organic-inorganic composite insulating material. The printed wiring board according to claim 1.

6. A power conversion device comprising the printed wiring board according to any one of claims 1 to 5. A power conversion device.

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