Power semiconductor element and electric power conversion equipment including the same
The power semiconductor device addresses electric field concentration and reliability issues in SiC MOSFETs by employing a specific doping region and well structure, improving high-speed switching performance and simplifying manufacturing.
Patent Information
- Application Number
- JP2024219694
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-07-03
- Filing Date
- 2024-12-16
- Publication Date
- 2025-07-01
AI Technical Summary
Conventional SiC MOSFETs with a trench structure face issues of electric field concentration in the lower edge region of the trench gate, leading to device reliability concerns and difficulty in precisely controlling the channel region, especially during high-speed switching.
The power semiconductor device incorporates a substrate with a first conductivity type epi-layer and second conductivity type wells, a gate between the wells, a gate insulating layer, and a first conductivity type doping region with varying doping concentrations and arrangements to prevent electric field concentration and improve reliability.
The solution effectively prevents electric field concentration at the trench gate edge, enhances device reliability during high-speed switching, and simplifies the manufacturing process by eliminating the need for a separate P-shield process.
Smart Images
Figure 2025097945000001_ABST
Abstract
Description
Technical Field
[0001] The embodiments relate to a power semiconductor device and a power conversion device including the same.
Background Art
[0002] Power Semiconductor is one of the core elements that determine the efficiency, speed, durability, and reliability of power electronic systems.
[0003] Recently, with the development of the power electronics industry, the silicon (Si) power semiconductors previously used have reached their physical limits, and active research has been conducted on wide bandgap (WBG) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace them.
[0004] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, thereby having characteristics such as a low intrinsic carrier concentration, a high breakdown electric field (about 4 - 20 times), a high thermal conductivity (about 3 - 13 times), and a high electron saturation velocity (about 2 - 2.5 times).
[0005] Due to such characteristics, they can operate in high-temperature and high-voltage environments and have a high switching speed and low switching loss. Among them, GaN (Gallium Nitride) power semiconductor devices can be used in low-voltage systems, and SiC (Silicon Carbide) power semiconductor devices are suitable for high-voltage systems.
[0006] Conventional SiC MOSFETs can be classified according to their structures into MOSFETs with a trench structure, MOSFETs with a vertical doubly implanted structure (DIMOSFETs), MOSFETs with a lateral diffused structure, etc. DIMOSFETs are sometimes called Planar MOSFETs or VDMOSFETs.
[0007] On the other hand, MOSFETs with a trench structure have a problem that the electric field concentrates in the edge region due to the shape of the trench gate. Even if a P-shield process or the like is performed to solve this problem, there are problems such as the addition of a mask layer, an increase in the process difficulty, and an increase in the cell pitch, and a new solution is required.
[0008] Also, conventionally, MOSFETs with a trench structure have a problem that the reliability of the device decreases because it is difficult to precisely control the channel region and the short circuit characteristics.
Summary of the Invention
Problems to be Solved by the Invention
[0009] One of the technical problems of the embodiment is to prevent the electric field concentration in the lower edge region of the trench gate.
[0010] Also, one of the technical problems of the embodiment is to improve the reliability of the device during high-speed switching.
[0011] The technical problems of the embodiment are not limited to those described in this item, and include those that can be grasped from the description of the invention.
Means for Solving the Problems
[0012] The power semiconductor device according to the embodiment and the power conversion device including the same include a substrate 110, a first conductivity type epi-layer 117 disposed on the substrate 110, a plurality of second conductivity type wells 130 disposed separately from each other on the first conductivity type epi-layer 117, a gate 160 disposed between the plurality of second conductivity type wells 130, and a gate insulating layer 155 disposed to cover at least a part of the gate 160. The power semiconductor device includes a first conductivity type doping region disposed on a side portion of the gate insulating layer 155. The first conductivity type doping region includes a first conductivity type first doping region 140a and a first conductivity type second doping region 140b disposed under the first conductivity type first doping region 140a. The doping concentration of the first conductivity type second doping region 140b may be lower than the doping concentration of the first conductivity type first doping region 140a.
[0013] Also, in the embodiment, the lower surface of the first conductivity type second doping region 140b may be located higher than the lower surface of the gate 160.
[0014] Also, in the embodiment, the lower end edge region of the gate insulating layer 155 may be in contact with the second conductivity type well 130.
[0015] Also, in the embodiment, the bottom surface of the second conductivity type well 130 may be located lower than the bottom surface of the gate insulating layer 155.
[0016] Also, in the embodiment, the first conductivity type doping region 140 and the first conductivity type epi-layer 117 do not contact each other, and a second conductivity type well 130 may be located between the first conductivity type doping region 140 and the first conductivity type epi-layer 117.
[0017] Also, in the embodiment, the first conductivity type first doping region 140a and the first conductivity type second doping region 140b may be in contact with one side surface of the gate insulating layer 155.
[0018] In the embodiment, the length direction of the first-conductivity-type first doping region 140a may be the horizontal direction, and the length direction of the first-conductivity-type second doping region 140b may be the vertical direction.
[0019] In the embodiment, the horizontal width of the first-conductivity-type second doping region 140b may be smaller than the horizontal width of the first-conductivity-type first doping region 140a.
[0020] In the embodiment, the depth of the first-conductivity-type doping region 140 may be smaller than the depth of the gate 160.
[0021] In the embodiment, the first-conductivity-type second doping region 140b may not overlap perpendicularly with the source contact layer 145.
[0022] In the embodiment, it further includes a JFET region 150 disposed on the lower surface of the gate insulating layer 155, and the JFET region 150 can be in contact with a plurality of second-conductivity-type wells 130.
[0023] The horizontal width of the JFET region may be larger than the horizontal width of the gate.
[0024] The first length L1 of the first-conductivity-type second doping region 140b in contact with the gate insulating layer 155 may be longer than the second length L2 of the second-conductivity-type well 130 in contact with the gate insulating layer 155.
[0025] The region of the second-conductivity-type well 130 in contact with the gate insulating layer is disposed under the first-conductivity-type second doping region 140b.
[0026] In addition, the power semiconductor device according to the embodiment may include a substrate, a first conductivity type epi-layer 117 disposed on the substrate, a plurality of second conductivity type wells 130 disposed separately from each other on the first conductivity type epi-layer 117, a gate disposed between the plurality of second conductivity type wells 130, and a gate insulating layer 155 disposed so as to cover at least a part of the gate.
[0027] In addition, the embodiment includes a first conductivity type doping region 140 disposed on a side portion of the gate insulating layer 155, and the first conductivity type doping region 140 may include a first conductivity type first doping region 140a and a first conductivity type second doping region 140b disposed under the first conductivity type first doping region 140a.
[0028] The doping concentration of the first conductivity type second doping region 140b may be lower than the doping concentration of the first conductivity type first doping region 140a.
[0029] The upper surface of the second doping region may be in contact with the bottom surface of the first doping region.
[0030] The inner surface of the second doping region is vertically aligned with the inner surface of the first doping region.
[0031] The thickness of the second doping region in the vertical direction may be greater than 1 / 2 of the thickness of the gate in the vertical direction.
[0032] In addition, the power semiconductor device according to the embodiment may include a substrate, a first conductivity type epi-layer disposed on the substrate, a plurality of wells disposed separately from each other on the epi-layer, a gate disposed in the plurality of wells, and a gate insulating layer disposed so as to cover at least a part of the gate.
[0033] It includes a doping region of a first conductivity type disposed on a side portion of the gate insulating layer, and the doping region can include a first doping region and a second doping region disposed under the first doping region.
[0034] The horizontal width of the second doping region may be smaller than the horizontal width of the first doping region.
[0035] The doping concentration of the second doping region may be lower than the doping concentration of the first doping region.
[0036] The lower surface of the second doping region is located higher than the lower surface of the gate, and the lower edge region of the gate insulating layer can be in contact with the well.
[0037] The bottom surface of the well is located lower than the bottom surface of the gate insulating layer, the doping region and the epitaxial layer are separated from each other, and the well can be located between the doping region and the epitaxial layer.
[0038] The inner surface of the second doping region is aligned vertically with the inner surface of the first doping region, and the vertical thickness of the second doping region may be greater than 1 / 2 of the vertical thickness of the gate.
Advantages of the Invention
[0039] The power semiconductor device according to the embodiment has a technical effect of preventing electric field concentration in the lower edge region of the trench gate.
[0040] For example, in the embodiment, by arranging the second conductivity type well to cover the lower edge region of the trench gate, electric field concentration is prevented in the lower edge region of the trench gate.
[0041] In addition, the embodiment can prevent the electric field concentration in the lower edge region of the trench gate without a separate P-shield process, and since a large-energy ion implantation process is unnecessary, it has the technical effect of preventing element damage and simplifying the process.
[0042] In addition, the embodiment has the technical effect of improving the reliability of the element during high-speed switching.
[0043] For example, in the embodiment, by forming the doping concentration of the first conductivity type second doping region disposed on the side of the trench gate to be lower than the doping concentration of the first conductivity type first doping region, the saturation current decreases, the SCWT (Short Circuit Withstand Time) increases, and the reliability of the element during high-speed switching is improved.
[0044] The technical effects of the embodiment are not limited to those described in this item, and include those that can be grasped from the description of the invention.
Brief Description of the Drawings
[0045]
Figure 1
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Figure 4b
Figure 4c
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Figure 4e
Figure 4f
DETAILED DESCRIPTION OF THE INVENTION
[0046] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings. The suffixes “module” and “section” for the components used in the following description are given or mixed for the purpose of facilitating the preparation of the specification, and do not have meanings or roles that are distinct from each other by themselves. Also, the accompanying drawings are for the purpose of facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawings. Also, when an element such as a layer, region, or substrate is referred to as being “on” another component, this includes the case where it is directly on another element or there may be another intermediate element therebetween.
[0047] The meaning of “Configuration A includes at least one of a, b, and / or c” in the specification or claims is as follows: (1) when Configuration A includes a, (2) when Configuration A includes b, (3) when Configuration A includes c, (4) when Configuration A includes a and b, (5) when Configuration A includes b and c, (6) when Configuration A includes a and c, and (7) when Configuration A includes all of a, b, and c.
[0048] Singular expressions include not only singular but also plural expressions unless the context clearly indicates otherwise. For example, the meaning of “Configuration A includes one structure” can include the meaning of “Configuration A includes one or more structures”.
[0049] FIG. 1 is an exemplary configuration diagram of the power conversion device 1000 according to the embodiment.
[0050] The power conversion device 1000 according to the embodiment can receive a DC power supply from a battery or a fuel cell and convert it into an AC power supply, and can supply the AC power supply to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive a DC power supply from a battery, convert it into a three-phase AC power supply, and supply it to the motor M. The motor M can provide power for an electric vehicle, a fuel cell vehicle, etc.
[0051] The power conversion device 1000 according to the embodiment can include a power semiconductor device 100. The power semiconductor device 100 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).
[0052] For example, the power conversion device 1000 can include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, 100f, and can include a plurality of diodes (not shown). Each of the plurality of diodes may be inherent in each of the power semiconductor devices 100a, 100b, 100c, 100d, 100e, 100f in the form of an internal diode, but is not limited thereto, and may be separately arranged.
[0053] The embodiment can convert a DC power supply into an AC power supply by on / off control of a plurality of power semiconductor devices 100a to 100f. For example, the power conversion device 1000 according to the embodiment can turn on the first power semiconductor device 100a and turn off the second power semiconductor device 100b in the first time period of one cycle to supply a positive-polarity power supply to the motor M, and turn off the first power semiconductor device 100a and turn on the second power semiconductor device 100b in the second time period of one cycle to supply a negative-polarity power supply to the motor M.
[0054] In an embodiment, a group of power semiconductor devices arranged in series between a high-voltage line and a low-voltage line on the input side can be referred to as an "arm". For example, the first power semiconductor device 100a and the second power semiconductor device 100b constitute the first arm, the third power semiconductor device 100c and the fourth power semiconductor device 100d constitute the second arm, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f can constitute the third arm.
[0055] The upper and lower power semiconductor devices in the arm are controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b do not turn on simultaneously but turn on and off alternately.
[0056] A high power supply is applied to each of the power semiconductor devices 100a to 100f in the off state. For example, when the first power semiconductor device 100a is on and the second power semiconductor device 100b is off, the input voltage is applied to the second power semiconductor device 100b as it is. The voltage input to the second power semiconductor device 100b is a relatively high voltage, and the breakdown voltage of each of the power semiconductor devices 100a to 100f can be designed to a high level so as to withstand such a high voltage.
[0057] Each of the power semiconductor devices 100a to 100f can conduct a high current in the on state. The motor M is driven by a relatively high current, and such a high current is supplied to the motor M through the power semiconductor that is on.
[0058] The high voltage applied to each of the power semiconductor devices 100a to 100f can induce a high switching loss. The high current flowing through the power semiconductor devices 100a to 100f can induce a high conduction loss. In order to dissipate the heat generated by such losses, the power semiconductor devices 100a to 100f can be packaged in a power semiconductor module including a heat dissipation means.
[0059] The power semiconductor device 100 of the embodiment may be a SiC (Silicon Carbide) power semiconductor device, which can operate in a high-temperature and high-voltage environment and can have a high switching speed and low switching loss.
[0060] On the other hand, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.
[0061] For example, a plurality of power semiconductor devices 100a to 100f illustrated in FIG. 1 are packaged in one power semiconductor module, or the power semiconductor devices constituting each arm are packaged in one power semiconductor module.
[0062] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f illustrated in FIG. 1 are packaged in one power semiconductor module.
[0063] In addition, additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a to 100f may be further included to increase the current capacity. In such a case, the number of power semiconductor devices included in the power semiconductor module is more than six.
[0064] The power conversion device 1000 according to the embodiment may also include power semiconductor devices in the form of diodes in addition to the power semiconductor devices 100a to 100f in the form of transistors. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor device 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor device 100b. And such diodes may also be packaged together in one power semiconductor module. Further, the diodes may be arranged in the form of internal diodes in each power semiconductor device.
[0065] Next, the power semiconductor devices constituting each arm are packaged in one power semiconductor module.
[0066] For example, the first power semiconductor device 100a and the second power semiconductor device 100b constituting the first arm are packaged in the first power semiconductor module, the third power semiconductor device 100c and the fourth power semiconductor device 100d constituting the second arm are packaged in the second power semiconductor module, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f constituting the third arm are packaged in the third power semiconductor module.
[0067] In addition, additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a to 100f can be further included to increase the current capacity. In this case, the number of power semiconductor devices included in each power semiconductor module is more than two. And each arm includes, in addition to the power semiconductor devices 100a to 100f in transistor form, power semiconductor devices in diode form (not shown), and such diodes may also be packaged together in one power semiconductor module. Also, the diode may be arranged in the form of an internal diode in each power semiconductor device.
[0068] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor devices 100 according to the embodiment.
[0069] The power semiconductor device 100 according to the embodiment can include a source electrode 190 disposed above a predetermined semiconductor epitaxial layer 120, a gate electrode 175, and a drain electrode 105 disposed below the semiconductor epitaxial layer 120.
[0070] In the form of a MOSFET, the source electrode 190 or the gate electrode 175 can include an Al-based metal, and the drain electrode 105 can include a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.
[0071] Next, FIG. 3 is a cross-sectional view of a power semiconductor device according to an embodiment. Referring to FIG. 3, the power semiconductor device according to the embodiment may include at least one of a substrate 110, a drain electrode 115, a first conductivity type epi layer 117, a second conductivity type well 130, a first conductivity type doping region 140, a source contact layer 145, a gate 160, and a gate insulating layer 155. The “first conductivity type epi layer” may be referred to as an “epi layer”, and the “second conductivity type well” may be referred to as a “well”. Also, in other configurations, the expressions of “first conductivity type” or “second conductivity type” may be omitted and referred to.
[0072] Specifically, in the embodiment, the drain electrode 115 is disposed under the substrate 110. Also, the first conductivity type epi layer 117 is disposed on the substrate 110. The first conductivity type epi layer 117 may be an N-type drift region, but is not limited thereto.
[0073] Also, the second conductivity type well 130 is disposed on the first conductivity type epi layer 117. The second conductivity type well 130 may include a plurality of wells that are spaced apart from each other. A gate 160 and a gate insulating layer 155 are disposed between the plurality of second conductivity type wells 130. The gate insulating layer 155 is disposed so as to cover the side surface and the lower surface of the gate 160. The gate 160 may be located inside the gate insulating layer 155. Also, a JFET region 150 may be disposed under the gate 160 and the gate insulating layer 155 to protect the gate insulating layer 155, but is not limited thereto.
[0074] On the other hand, in the case of a trench MOSFET studied internally, a problem has been studied in which an electric field is concentrated in the lower edge region of the trench gate and the gate insulating layer is damaged. Accordingly, a separate ion implantation region such as a P-shield process is formed to prevent electric field concentration, but there are difficulties in the separate ion implantation region formation process.
[0075] In addition, in the case of a trench-structured MOSFET, it is difficult to precisely control the channel region and the short circuit characteristics, resulting in a problem of reduced device reliability.
[0076] To solve the above problems, in an embodiment, the second conductivity type well 130 is formed deeper than the gate 160 and the gate insulating layer 155. Specifically, the lower surface of the second conductivity type well 130 can be positioned lower than the lower surfaces of the gate 160 and the gate insulating layer 155. Also, the second conductivity type well 130 can be in contact with the gate insulating layer 155. Thus, the embodiment has a technical effect of being able to prevent electric field concentration by arranging the second conductivity type well 130 to cover the lower edge region of the trench gate.
[0077] In addition, in the embodiment, a first conductivity type doping region 140, a second conductivity type ion implantation region 135, and a source contact layer 145 are arranged on the second conductivity type well 130. The first conductivity type doping region 140 is arranged on the side surface of the gate insulating layer 155. The first conductivity type doping region 140 is arranged to extend along the gate insulating layer 155 to the source contact layer 145. The source contact layer 145 is electrically connected to a source electrode (not shown).
[0078] On the other hand, the first conductivity type doping region 140 can include a first conductivity type first doping region 140a and a first conductivity type second doping region 140b arranged under the first conductivity type first doping region 140a. The first conductivity type first doping region 140a can be in contact with the source contact layer 145. Also, the first conductivity type first doping region 140a can be in contact with the second conductivity type ion implantation region 135.
[0079] In addition, the first conductivity type first doping region 140a can be in contact with the gate insulating layer 155. The height of the upper surface of the first conductivity type first doping region 140a can correspond to the height of the upper surface of the gate 160. The length direction of the first conductivity type first doping region 140a may be a horizontal direction. Also, the length direction of the first conductivity type second doping region 140b may be a vertical direction.
[0080] In addition, the first conductivity type second doping region 140b can be in contact with the side surface of the gate insulating layer 155. The first conductivity type second doping region 140b is disposed to extend vertically at the lower surface of the first conductivity type first doping region 140a. Also, the lower surface of the first conductivity type second doping region 140b can be located higher than the lower surface of the gate 160. Also, the horizontal width of the first conductivity type second doping region 140b may be smaller than the horizontal width of the first conductivity type second doping region 140b. Also, one side surface of the first conductivity type second doping region 140b can have a width corresponding to one side surface of the insulating layer 165 covering the gate 160.
[0081] On the other hand, the doping concentration of the first conductivity type second doping region 140b may be lower than the doping concentration of the first conductivity type first doping region 140a. The first conductivity type doping region 140 in contact with the side surface of the gate insulating layer 155 has a doping concentration that changes in the vertical direction.
[0082] On the other hand, in the embodiment, current can flow through the drain electrode 115, the substrate 110, the first conductivity type epitaxial layer 117, the second conductivity type well 130, the first conductivity type second doping region 140b, the first conductivity type first doping region 140a, and a source electrode (not shown). Also, a channel is formed between the lower surface of the first conductivity type second doping region 140b and the lower surface of the second conductivity type well 130.
[0083] Therefore, in the embodiment, the current passes through the first conductivity type doping region 140 where the doping concentration changes in the vertical direction from the side surface of the trench gate, so that the saturation current decreases. Specifically, by controlling the sheet resistance in the first conductivity type second doping region 140b doped lower than the first conductivity type first doping region 140a to relatively increase, the on-resistance (Ron) in the first conductivity type second doping region 140b is controlled to relatively increase, and the saturation current decreases. Therefore, the embodiment has a technical effect of improving the reliability during high-speed switching by increasing the SCWT (Short Circuit Withstand Time) due to the decrease in the saturation current.
[0084] Hereinafter, with reference to FIGS. 4a to 4f, the manufacturing process of the power semiconductor device according to the embodiment will be described, and the technical features of the embodiment will be described in detail.
[0085] Referring to FIG. 4a, a first conductivity type epi-layer 117 can be formed on the substrate 110.
[0086] The substrate 110 and the first conductivity type epi-layer 117 can include, but are not limited to, SiC (Silicon Carbide).
[0087] For example, the substrate 110 and the first conductivity type epi-layer 117 can include, but are not limited to, a 4H-SiC material. For example, the substrate 110 and the first conductivity type epi-layer 117 can include 3C-SiC or 6H-SiC.
[0088] In addition, the first conductivity type epi-layer 117 can include a plurality of layers having different concentrations and can have the function of a current spreading layer (CSL).
[0089] For example, the first conductivity type epi-layer 117 may include a first conductivity type buffer layer (not shown) and a first conductivity type drift layer (not shown).
[0090] Also, the first conductivity type may be N-type, and the second conductivity type may be P-type, but it is not limited thereto.
[0091] Also, a first conductivity type first doping region 140a and a second conductivity type ion implantation region 135 are formed on the first conductivity type epi-layer 117 by an implant process. The first conductivity type first doping region 140a can be located between the second conductivity type ion implantation regions 135. The length direction of the first conductivity type first doping region 140a may be the horizontal direction.
[0092] For example, the first conductivity type first doping region 140a can function as a source region of the first conductivity type, and an N-type dopant such as nitrogen or phosphorus is about 1×10 19 cm -3 ~ about 3×10 20 cm -3 It can be formed by ion implantation at a concentration of.
[0093] Also, the second conductivity type ion implantation region 135 can contact the source electrode hereafter. Also, the second conductivity type ion implantation region 135 can function to maintain the potential of the second conductivity type well 130 and can function as a body diode.
[0094] Next, referring to FIG. 4b, after arranging a first mask 180a on the first conductivity type first doping region 140a, a second conductivity type well 130 can be formed by an implant process. The second conductivity type well 130 has a P-type dopant of about 1×10 16 cm -3 ~ about 2×10 19 cm -3It may be ion-implanted at the concentration of. For example, aluminum, boron, etc. may be implanted, but it is not limited thereto. The second conductivity type well 130 may include a plurality of regions that are separated by placing the first conductivity type epitaxial layer 117 therebetween by the first mask 180a.
[0095] Next, referring to FIG. 4c, after placing the second mask 180b on a part of the first conductivity type first doping region 140a, the first conductivity type second doping region 140b can be formed under the first conductivity type first doping region 140a by an implant process. The horizontal width of the first conductivity type second doping region 140b may be formed smaller than the horizontal width of the first conductivity type first doping region 140a. Also, the depth of the first conductivity type second doping region 140b may be shallower than the depth of the second conductivity type well 130.
[0096] For example, the depth of the first conductivity type second doping region 140b can have 50% - 80% of the depth of the second conductivity type well 130, but it is not limited thereto.
[0097] The region of the second conductivity type well 130 exposed in the subsequent trench etching process may be the channel region.
[0098] Also, the doping concentration of the first conductivity type second doping region 140b may be lower than the doping concentration of the first conductivity type first doping region 140a.
[0099] For example, the first conductivity type second doping region 140b may be ion-implanted with an N-type dopant such as nitrogen or phosphorus at a concentration of about 1×10 17 cm -3 ~ about 3×10 19 cm -3 to form, but it is not limited thereto.
[0100] According to the embodiment, the doping concentration of the first-conductivity-type second doping region 140b is controlled to be lower than the doping concentration of the first-conductivity-type first doping region 140a. As a result, the on-resistance (Ron) in the first-conductivity-type second doping region 140b relatively increases and the saturation current decreases, so that the SCWT (Short Circuit Withstand Time) increases, and there is a technical effect that the reliability is improved during high-speed switching.
[0101] Next, referring to FIG. 4d, a spacer 185 formed of an insulating layer or the like can be disposed on the side surface of the second mask 180b. The spacer 185 is disposed such that the side surface of the spacer 185 corresponds to one side surface of the second-conductivity-type well 130. For example, the spacer 185 can have an inverted form of the first mask 180a used above.
[0102] Thereafter, a part of the first-conductivity-type first doping region 140a, the first-conductivity-type second doping region 140b, and the first-conductivity-type epitaxial layer 117 can be etched to form a trench 170. The bottom surface of the trench 170 can be located higher than the lower surface of the second-conductivity-type well 130, but is not limited thereto.
[0103] In the embodiment, the first length L1 of the first-conductivity-type second doping region 140b exposed by the trench 170 may be longer than the second length L2 of the second-conductivity-type well 130 exposed by the trench 170. For example, the second length L2 of the second-conductivity-type well 130 exposed by the trench 170 can have about 40% to 70% of the overall depth of the trench 170, but is not limited thereto.
[0104] The second length L2 region of the second-conductivity-type well 130 exposed by the trench 170 can function as a channel region.
[0105] According to the embodiment, a channel region is formed, and the second conductivity type well 130 is disposed to cover the lower edge region of the trench gate, so that there is a technical effect of preventing electric field concentration in the lower edge region of the trench gate.
[0106] Thus, in the embodiment, the second conductivity type well 130 can be formed to cover the lower edge region of the trench gate without a separate P-Shield process. Since this eliminates the need for a high-energy ion implantation process, there is a technical effect of preventing element damage and improving element reliability.
[0107] Next, referring to FIG. 4e, a JFET region 150 can be formed by an implantation process below the trench 170, but is not limited thereto. The JFET region 150 can be located between a plurality of second conductivity type wells 130. Also, the lower surface of the JFET region 150 can be located lower than the lower surface of the second conductivity type well 130.
[0108] Next, referring to FIG. 4f, a gate insulating layer 155 is formed on the trench. The gate insulating layer 155 may be a thermal oxide film or a deposited oxide film, but is not limited thereto. Also, a gate 160 is formed inside the gate insulating layer 155. The height of the upper surface of the gate 160 is formed to correspond to the upper surface of the first conductivity type first doping region 140a. Also, the lower surface of the gate 160 can be located lower than the lower surface of the first conductivity type second doping region 140b. Also, the edge region at the lower end of the gate insulating layer 155 can be in contact with the second conductivity type well 130. Thus, the embodiment has a technical effect of preventing electric field concentration in the lower edge region of the trench gate by forming the second conductivity type well 130 in contact with the lower edge region of the trench gate.
[0109] Also, a source contact layer 145 is formed on the second conductivity type ion implantation region 135, and a source electrode (not shown) is formed on the source contact layer 145 in a later process.
[0110] Next, an insulating layer 165 is formed over the gate 160 and the gate insulating layer 155. The insulating layer 165 can be made of, but is not limited to, an oxide film, a nitride film, or the like.
[0111] Also, a source electrode (not shown) can be formed over the source contact layer 145. The source electrode is formed to cover the insulating layer 165. The source electrode can be made of, but is not limited to, Al or the like. Further, the source electrode can further include a barrier metal layer.
[0112] Also, a drain electrode 115 is formed on the lower side of the substrate 110. The drain electrode 115 can include, but is not limited to, a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, NiV / Ag, V (vanadium) / Ni / Ag, or the like.
[0113] The power semiconductor device according to the embodiment has a technical effect of preventing electric field concentration in the lower edge region of the trench gate.
[0114] For example, in the embodiment, by arranging the second conductivity type well in contact with the lower edge region of the trench gate, electric field concentration is prevented in the lower edge region of the trench gate.
[0115] Also, the embodiment can prevent electric field concentration in the lower edge region of the trench gate without a P-Shield formation process, and since a large energy ion implantation process is unnecessary, it has a technical effect of preventing damage to the device and simplifying the process.
[0116] Also, the embodiment has a technical effect of improving the reliability of the device during high-speed switching.
[0117] For example, in the embodiment, by forming the doping concentration of the first conductivity type second doping region disposed on the side of the trench gate to be lower than the doping concentration of the first conductivity type first doping region, the saturation current is decreased, the SCWT (Short Circuit Withstand Time) is increased, and the reliability of the element during high-speed switching is improved.
[0118] Although the embodiments of the present invention have been described above with reference to the embodiments, those having ordinary knowledge in the relevant technical field should easily understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the following claims.
Explanation of Reference Numerals
[0119] 110: Substrate 115: Drain electrode 117: First conductivity type epitaxial layer 130: Second conductivity type well 135: Second conductivity type ion implantation region 140: First conductivity type doping region 140a: First conductivity type first doping region 140b: First conductivity type second doping region 145: Source contact layer 150: JFET region 155: Gate insulating layer 160: Gate 165: Insulating layer 170: Trench 180a: First mask 185: Spacer
Claims
1. A substrate; a first conductivity type epitaxial layer disposed on the substrate; a plurality of second conductivity type wells spaced apart from one another on the first conductivity type epitaxial layer; a gate disposed between the plurality of second conductivity type wells and a gate insulating layer disposed to cover at least a portion of the gate; a first conductive type doped region disposed on a side of the gate insulating layer; the first conductive type doped region includes a first conductive type first doped region and a first conductive type second doped region disposed under the first conductive type first doped region, A doping concentration of the first conductive type second doped region is lower than a doping concentration of the first conductive type first doped region.
2. The power semiconductor device according to claim 1 , wherein a bottom surface of the first conductive type second doping region is located higher than a bottom surface of the gate.
3. The power semiconductor device according to claim 1 , wherein a lower edge region of the gate insulating layer contacts the second conductive well.
4. The power semiconductor device according to claim 1 , wherein a bottom surface of the second conductive type well is located lower than a bottom surface of the gate insulating layer.
5. the first conductive type doping region and the first conductive type epitaxial layer are spaced apart from each other; The power semiconductor device according to claim 1 , wherein the second conductive type well is located between the first conductive type doping region and the first conductive type epitaxial layer.
6. The power semiconductor device of claim 1 , wherein the first doped region of the first conductivity type and the second doped region of the first conductivity type contact one side of the gate insulating layer.
7. The power semiconductor device of claim 1 , wherein a thickness of the first conductive type first doped region in a depth direction is smaller than a thickness of the first conductive type second doped region in a depth direction.
8. The power semiconductor device of claim 1 , wherein a horizontal width of the first conductive type second doped region is smaller than a horizontal width of the first conductive type first doped region.
9. The gate insulating layer further includes a JFET region disposed on a lower surface of the gate insulating layer, The power semiconductor device according to claim 1 , wherein the JFET region contacts the plurality of second conductivity type wells.
10. A power conversion device comprising the power semiconductor device according to claim 1 .