Catalyst enhanced pattern transfer technology

Abstract

To provide a silicon etching apparatus using catalyst enhanced chemical etching technology that can be employed in the manufacture of semiconductor elements, with applications to three-dimensional memory architecture and transistors.SOLUTION: A catalyst enhanced chemical etching (CICE) is a catalyst-based etching method that can be used for semiconductor and multilayer semiconductor, and the catalyst is used to etch a semiconductor substrate and produce (shape) features with high aspect ratios.SELECTED DRAWING: Figure 8C

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to U.S. Provisional Patent Application No. 62 / 591,326, filed on November 28, 2017, entitled "Formation of 3D Memory Architectures Using Catalyst Mesh Patterns", U.S. Provisional Patent Application No. 62 / 665,084, filed on May 1, 2018, entitled "Multilayer Electrochemical Etching Processes for Semiconductor Device Fabrication (Processing)", U.S. Provisional Patent Application No. 62 / 701,049, filed on June 20, 2018, entitled "Catalyst - Based Electrochemical Etching Processes for Semiconductor Device Fabrication (Processing)", and U.S. Provisional Patent Application No. 62 / 729,361, filed on September 10, 2018, entitled "Catalyst - Assisted Chemical Etching Technology: Applications in Semiconductor Devices", all of which are hereby incorporated by reference in their entirety for all purposes.

[0002] (Statement Regarding Federally Sponsored Research) This invention was made with government support under Grant No. EEC1160494 awarded by the National Science Foundation and Grant No. FA8650 - 15 - C - 7542 awarded by the Air Force Research Laboratory. The United States government has certain rights in this invention.

[0003] (Technical Field) Various embodiments of the present technology generally relate to semiconductor device architectures and manufacturing techniques. More specifically, some embodiments of the present technology relate to silicon etching using catalyst - enhanced chemical etching techniques, with applications to 3D memory architectures and transistors.

Background Art

[0004] The semiconductor manufacturing of various transistors, memories, integrated circuits, photonic devices, and other semiconductor devices has led to the spread of modern computing devices and other electronic systems. For example, computers, mobile phones, automobiles, household appliances, etc. are all direct products of the progress in semiconductor manufacturing. An essential part of the manufacturing (processing) of these devices is pattern transfer. The dry plasma etching process used in the semiconductor industry to anisotropically etch highly controlled nanopatterns requires expensive vacuum equipment and cannot easily maintain the cross-sectional shape when patterning high aspect ratios. These are troubled by etching problems such as aspect ratio-dependent etching (ARDE) and etching tapers.

Summary of the Invention

[0005] Various embodiments of the present technology generally relate to memory architectures and manufacturing technologies. More specifically, some embodiments of the present technology relate to silicon etching using catalytic chemical etching technology, involving applications to three-dimensional memory architectures and transistors.

[0006] In one embodiment of the present technology, a method for preventing substantial collapse of a plurality of high aspect ratio semiconductor structures by catalytic chemical etching includes patterning a catalyst layer on the surface of a semiconductor material, where the catalyst layer includes an intended design and a plurality of lithography links. Further, the plurality of lithography links substantially connect one or more isolated features of the catalyst layer and / or the semiconductor material. This method further includes exposing the patterned catalyst layer on the surface of the semiconductor material to an etchant, where the patterned catalyst layer causes etching of the semiconductor material to form a plurality of internally connected high aspect ratio structures.

[0007] In other embodiments of the present technology, a method for preventing substantial collapse of a plurality of high aspect ratio semiconductor structures includes creating a structure with a capping material deposited either on a patterned catalyst layer or on top of a low-height structure. This method further includes exposing the structure to an etchant. This method further includes forming a plurality of high aspect ratio semiconductor structures by using catalytic chemical etching on the structure with the capping material to prevent substantial collapse of the plurality of high aspect ratio semiconductor structures.

[0008] In a further embodiment of the present technology, an apparatus for catalytic chemical etching includes a plurality of sensors configured to detect the etching state of a semiconductor material.

[0009] In other embodiments of the present technology, a method for creating a plurality of nanostructures with substantially uncollapsed alternating multilayers includes creating a material stack comprising two or more layers of alternating semiconductor films, where each of the two or more layers of alternating semiconductor films differs from the others in at least one of material, doping concentration, and dopant material. This method further includes etching the material stack by catalytic chemical etching such that the plurality of layers with different characteristics produce a plurality of etched nanostructures that differ from each other in at least one of morphology, porosity, etching rate, and heat treatment rate.

[0010] In a further embodiment of the present technology, a method for creating a plurality of features with substantially uncollapsed alternating multilayers includes creating a material stack comprising two or more layers of alternating semiconductor films, where each of the two or more layers of alternating semiconductor films differs from the others in at least one of material, doping concentration, and dopant material. This method further includes etching the material stack by crystal orientation-dependent etching to form a taper along a crystal plane. This method further includes etching a taper along a crystal plane to expose one of the two or more layers of alternating semiconductor films during the etching of a portion of another layer to create a stepped structure.

[0011] Embodiments of the present technology also include a computer-readable storage medium including a set of instructions for causing one or more processors to execute the methods, method variations, and other operations described herein.

[0012] While multiple embodiments are disclosed, further and other embodiments of the present technology will become apparent to those skilled in the art from the following detailed description that illustrates and describes exemplary embodiments of the technology. As will be understood later, the present technology is capable of being modified in various aspects without departing from the scope of the present technology. Accordingly, the drawings and detailed description are to be regarded essentially as illustrative and not restrictive.

[0013] Embodiments of the present technology are described and illustrated with reference to the accompanying drawings.

Brief Description of the Drawings

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[0015] These drawings are not necessarily drawn to scale. Similarly, for the purpose of explaining some embodiments of the present technology, some components and / or operations may be separated into different blocks or combined into a single block. Furthermore, the present technology can undergo various changes and alternative forms, but specific embodiments are illustrated as examples and will be described in detail below. However, the intention is not to limit the present technology to the specific embodiments described. On the contrary, the present technology is intended to cover all modifications, equivalents, and alternatives within the scope of the technology defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Various embodiments of the present technology describe a novel anisotropic etching process. Manufacturing (processing) tools therefor are also disclosed. This enables the present technology to be adopted in the fabrication of semiconductor devices. Some embodiments use catalytic chemical etching (CICE) for the fabrication of transistors and various memory architectures. Furthermore, various embodiments of the CICE process exhibit very high aspect ratios without losing the feature size.

[0017] The various embodiments of the present technology also provide various control schemes in catalyst-based chemical etching. A wafer-scale multi-scale precision catalyst-influenced chemical etching (MSP-CICE) manufacturing (processing) tool for that purpose is also disclosed. Some embodiments use various control schemes and tool designs to extend the performance of CICE from small areas (sub-150 mm substrates) without etching depth control in modern literature to large areas with local and global control and measurement (e.g., 300 mm Si wafers). This makes it possible to adopt the present technology in the fabrication of semiconductor devices such as 3D NAND flash, DRAM, FinFET, and nanosheet transistors.

[0018] The various embodiments of the present technology generally relate to memory architectures and manufacturing technologies. More specifically, some embodiments of the present technology relate to silicon etching using a catalyst-assisted chemical etching technique, which involves applications to three-dimensional memory architectures and transistors. The scalability of advanced memory architectures by current pattern transfer techniques is limited by the degradation of the etching mask by high aspect ratio plasma etching, sidewall damage, and non-zero tapers. In non-volatile semiconductor memories such as three-dimensional (3D) NAND flash, very high aspect ratio etching of alternating materials with more than 64 layers is required to increase the storage capacity of flash drives. With the increase in the number of layers, not only the staircase etching for defining the contacts to each layer, but also the cost and reliability of anisotropic and high aspect ratio channel and trench etching become the main limiting factors for scaling. A non-zero plasma etching taper angle limits the maximum number of layer stacks that can be reliably achieved.

[0019] The dry plasma etching process used in the semiconductor industry to anisotropically etch a height-controlled nanoscale pattern requires an expensive vacuum apparatus and cannot easily maintain the cross-sectional shape when patterning a high aspect ratio. In addition, it is troubled by etching problems such as aspect ratio dependent etching (ARDE) and etching taper. In the design of 3D NAND flash, the simultaneous etching of circular channels and rectangular slits cannot be reliably achieved by plasma etching that precisely controls the sidewalls. Similarly, in the case of features with connection links, sub-10nm links between pillars cannot be maintained at a high aspect ratio.

[0020] Furthermore, DRAM scaling is limited by the area occupied by the capacitor and the cell size factor. Therefore, the current technology in the scaling of memory architectures is limited because of the many steps of lithography and high aspect ratio etching. Various embodiments provide improved techniques for DRAM manufacturing.

[0021] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that embodiments of the present technology may be practiced without some of these specific details.

[0022] The technology introduced here can be embodied as dedicated hardware (e.g., circuitry), as a programmable circuit appropriately programmed with software or firmware, or as a combination of dedicated circuitry and programmable circuitry. Thus, embodiments may include a machine-readable medium storing instructions used to program a computer (or other electronic device) to perform processing. The machine-readable medium may include, but is not limited to, optical disks, compact disk read-only memory (CD-ROM), magneto-optical disks, ROM, random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or other types of media / machine-readable media suitable for storing electronic instructions.

[0023] Phrases such as "in some embodiments", "in accordance with some embodiments", "in the embodiments shown", "in other embodiments", etc. generally may mean that the particular feature, structure, or characteristic following that phrase is included in at least one implementation of the technology, and may be included in more than one implementation. Additionally, such phrases do not necessarily refer to the same or different embodiments.

[0024] Various embodiments of the technology use catalytic chemical etching (CICE) for the manufacture of transistors and various memory architectures. CICE is applicable to Si, Ge, Si x Ge 1-xIt is a catalyst-based etching method that can be used for semiconductors such as GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, and multilayer semiconductors. CICE uses a catalyst to etch a semiconductor substrate and is used to fabricate (process) high aspect ratio features using patterning techniques such as photolithography, electron beam lithography, nanosphere lithography, block copolymer, laser interference lithography, colloidal lithography, double patterning, quad patterning, nanoimprint lithography, and anodic aluminum oxide (AAO) templates for patterning the catalyst. The catalyst can be used together with etching retardant materials such as polymers and Cr.

[0025] In some embodiments, this setup can be immersed in a solution containing an etchant (e.g., fluoride species HF, NH4F, buffered HF, H2SO4, H2O) and an oxidizer (H202, V205, KMnO4, dissolved oxygen, etc.). Other chemicals such as alcohols (ethanol, isopropyl alcohol, ethylene glycol), materials for adjusting the etching uniformity (surfactants, soluble polymers, dimethyl sulfoxide - DMSO), solvents (ion-exchanged water, DMSO, etc.), and buffers can also be included in the etching composition. The chemicals used may depend on the semiconductor substrate being etched. Non-aqueous etchants can also be used if necessary. The etchant can be in the liquid or gas phase. Embodiments of such etchants for silicon substrates include ion-exchanged water, H2O, H2O2, ethanol, and HF.

[0026] Materials such as metals (e.g., Ag, Au, Pd, Pt, Cu, W, Ru, Ir), compounds such as TiN, TaN, RuO2, IrO2, and other conductive metal oxides and nitrides, graphene, carbon, etc. can function as catalysts for CICE. The mechanism of the CICE process for etching Si involves the reduction of the oxidizer by the catalyst, thereby generating positively charged holes h +Create them. Next, these holes are implanted into the metal-semiconductor interface through the metal, thereby oxidizing the semiconductor under the metal. The oxidized silicon is dissolved by the fluoride component of the etchant that diffuses from the side of the catalyst or through the catalyst, and the soluble product diffuses away. In the case of CICE of silicon using HF and H202, this redox reaction also produces hydrogen gas. The variables n = 2 to 4 are determined by the ratio of the oxidant to HF, which determines the etching regime (region) that occurs.

[0027] [Chemical formula]

[0028] The etching rate and the resulting morphology of this process depend on the dopant type, concentration, catalyst film thickness, and the concentration of the etchant. Using both electric and magnetic fields, higher uniformity / control of porosity has been achieved by hole diffusion during the etching process. The substrate with the obtained catalyst mesh is placed in the etchant solution and precisely etched to a certain depth that is actively controlled by an optical imaging system, temperature gradient, and electric field capable of determining the etching depth in situ. After CICE, the catalyst can be removed using chemical etching or plasma etching such as aqua regia, chlorine-based plasma, etc.

[0029] Diamond-shaped cross-section silicon nanowires made using jet and flash imprint lithography (J-FIL) and CICE with a gold catalyst have been demonstrated (see, for example, Figure 1). Capacitors made of diamond-shaped silicon nanowires exhibit a specific capacitance 90% higher than that of NWs with a circular cross-section of the same pitch and show the highest specific capacitance per area of NWs in the literature. J-FIL and CICE may be able to fabricate (process) Si nanostructures at a manufacturing (processing) cost of less than $1 per wafer based on a standard cost model.

[0030] FIG. 1A shows a J-FIL compatible catalyst-enhanced chemical etching (CICE) process 100 for making nanowires according to one or more embodiments of the present technology. As shown from FIG. 1A to FIG. 1B, in process step 110, a nanofeature 111 (e.g., a resist material) can be imprinted on a silicon substrate 112. The material (e.g., the resist) may remain in the trench 113 after the imprint process. In process step 120, "descum" etching can be performed to remove the thickness of the resist residual layer (RLT) and the resist in the trench 113. An example of descum etching is to etch the resist material using oxygen and argon plasma. In process step 130, gold (Au) 131 can be deposited in the trench 113 and on the nanofeature 111 using a directed deposition process such as electron beam evaporation. An adhesion layer such as Ti may be deposited before the deposition of gold. In process step 140, a trench 141 can be formed using CICE, and the gold 131 is disposed at the bottom of the trench 141 and on the top of the nanofeature 111. In process step 150, the gold (Au) 131 and the resist 111 can be removed, and the structure can be cleaned using plasma etching or a chemical etching agent such as aqua regia, potassium iodide, and liquid or vapor phase piranha. FIG. 1B shows a cross-sectional view of the case of manufacturing (processing) nanowires using the steps described in FIG. 1A according to one or more embodiments of the technology.

[0031] CICE is a superset of processes referred to as metal-assisted chemical etching (MACE). Apart from metals, there are certain non-metal catalysts such as graphene or TiN, TaN, RuO2, IrO2 that can potentially be used as catalysts. Further, the catalyst usually locally assists chemical etching by digging into the substrate in the presence of an etchant and an oxidant, but can also locally inhibit etching, as in the case of InP. To encompass all such processes, various embodiments refer to the process of catalyst-enhanced chemical etching (CICE).

[0032] However, the CICE anisotropic wet etching method used in high aspect ratio etching steps currently does not have precise etching depth control and wafer scale manufacturing (processing). Discontinuous catalyst features tend to fluctuate during CICE and tend to cause defects. The catalysts used are not easily etched by plasma or wet etching without redeposition or undercut. The lift-off process currently used to pattern noble metal catalysts has high defectivity. Various embodiments of the present technology enable the etching of any nanopattern with feature sizes in the range of mm to nm by precisely controlling various sensors and actuators such as the chemical properties of the etchant solution, electric fields, and optical / spectroscopic properties of nanostructures.

[0033] According to various embodiments, CICE can be used to create nanostructures of bulk materials or alternating layers of materials such as superlattices. CICE of bulk materials can be used in devices such as finFETs and nanowire sensors. Superlattice nanostructures have applications such as 3D NAND flash memory devices and nanosheet transistors. Superlattices can be created by performing CICE on a bulk semiconductor substrate with a time-varying electric field or on a substrate comprising alternating layers of semiconductor materials with different doping concentrations, materials, dopant types, etc. In embodiments using silicon as at least one of the materials of the substrate, the CICE process for creating superlattices is described as silicon superlattice etching (SiSE) as described below.

[0034] (Silicon Superlattice Etching (SiSE)) SiSE can be used on bulk silicon wafers and alternating layers of silicon with different doping concentrations. Etching agents (such as hydrofluoric acid HF), oxidizing agents (such as hydrogen peroxide H2O2), and optionally low surface tension liquids (such as ethanol) and deionized water can preferentially etch the semiconductor substrate at the positions of catalysts (Ag, Au, Pd, Pt, Cu, W, Ru, TiN, RuO2, IrO2, graphene, etc.). If necessary, non-aqueous etching agents can also be used. Lithography techniques (such as photolithography, electron beam lithography, double patterning, quad patterning, nanoimprint lithography, etc.) can be used to define the catalyst features. The obtained substrate with the catalyst mesh is placed in the MSP-CICE tool and precisely etched to a certain depth that is actively controlled by an optical imaging system, a thermal actuator, and an electric field based on the electrical and optical properties during etching.

[0035] Heterojunction materials, alloys, other semiconductors such as III-V, II-VI, and IV groups that can be etched by superlattice etching are Ge, Si x Ge 1-x , GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, etc. Although they can be included in the material design space, for various reasons such as high material and deposition costs and the lack of commercially available deposition and characterization methods, they will not be further described here. Reliable large-area wafer-scale etching using SiSE processes that can utilize various embodiments of SiSE processes containing silicon does not currently exist in the prior art. Various embodiments are assumed to incorporate various techniques to enable this.

[0036] Silicon superlattice etching (SiSE) creates a superlattice with alternating layers where at least one layer is porous while etching a semiconductor substrate using a catalyst. The alternating layers are formed by electric field parameter modulation and / or etching through layers with alternating doping characteristics. Figure 2 shows SiSE process control 200 according to one or more embodiments of the present technology. As shown in Figure 2, the patterning operation 210 can generate a patterned catalyst on the silicon substrate. According to various embodiments, a bulk substrate (as shown at 212) or a substrate with alternating doping layers (as shown at 214) may be used. Either the bulk substrate or the substrate with alternating doping layers may be loaded into the silicon superlattice etching tool in the loading operation 230. The SiSE process 240 can be precisely controlled to generate high aspect ratio nanostructures 250. According to various embodiments, the high aspect ratio nanostructures 250 may have a height to critical dimension (e.g., the average of the bottom and top diameters of the nanowire) ratio of 4:1, 5:1, or more.

[0037] Various feedback parameters 260 can be directly measured or estimated from direct measurements. These parameters include, but are not limited to, performance parameters of the etchant (e.g., concentration, volume, flow rate, Reynolds number, refractive index, etc.), electric field parameters (current, voltage, resistance, capacitance, etc.), optical variations across the wafer (e.g., reflectivity, intensity, etc.), ambient environment parameters (e.g., temperature, pressure, flow rate of inert gas, vapor pressure, etc.), and / or other parameters. Using these, a feedback signal can be generated for use with an input etching control signal to control various system parameters (e.g., flow rate, turbulent flow of the etchant, temperature, pressure, concentration, illumination, and electric field parameters such as current, voltage, resistance, capacitance, frequency, duty cycle, amplitude, waveform type, distance between electrodes, etc.).

[0038] In the case of bulk silicon etched by a catalyst patterned with a modulated electric field (as shown in 212), the alternating layers have different porosities. By modulating parameters such as current density and illumination density over time, a porous semiconductor multi-layer can be created. The current density, as shown in Figure 2, can be modulated in a p-type silicon substrate such that when the catalyst sinks into the silicon, a positive current density creates porosity, and a zero or negative current density creates a crystalline layer with only catalyst etching. This is unique compared to a process where only a modulated electric field is used without the presence of a catalyst. Because in such a case, an alternating layer with very low porosity in one of the alternating layers cannot be generated. Some embodiments of such a multi-layer stack can include one set of alternating layers with a porosity of less than 20% and another set of layers with a porosity of more than 30%.

[0039] When epitaxial layers with alternating high and low doping concentrations are deposited at a thickness of sub-microns per layer (for example, as shown in 214), due to limitations in the deposition process at high deposition rates and the diffusion of dopants across the interface, the concentration gradient across the interface of the two layers becomes shallow. As a result, the doping across the entire thickness of the stack does not change abruptly, such as the gradient across the entire interface being shallow. In SiSE, the etching is adjusted so that the morphology reliably changes from porous to non-porous at a specific doping concentration, thereby changing the shallow doping concentration gradient to a sharp step function at the porous / non-porous interface.

[0040] As SiSE progresses, the catalyst mesh etches the semiconductor material stack to expose high aspect ratio features with holes and slits for 3D NAND channel and word line isolation, and fins and trenches for nanosheet FETs. SiSE can be stopped using an etch stop layer and / or timed etching. Hole generation during the etchant composition and processing results in alternating films with different morphologies based on their materials and doping concentrations. Also, the exact time at which the morphology changes can be detected by measuring electrical parameters such as resistance, voltage, current, capacitance, etc. of the entire epitaxial layer. This information can then be used to precisely modulate the current throughout the stack.

[0041] Figures 3A through 3B show a sharp gradient interface between a porous layer and a non-porous layer after SiSE on a substrate comprising alternating layers of epitaxial silicon with different doping concentrations, according to one or more embodiments of the present technology. In Figure 3A, an interface 310 between layer A of porous film 320 and layer B of non-porous film 330 is shown. In Figure 3B, several collapsing walls 340 having porous and non-porous sections are shown.

[0042] (CMOS Compatibility of CICE Catalyst Materials) Various embodiments of CICE processing can use a patterned catalyst that sinks into the substrate as etching progresses, leaving unpatterned areas as high aspect ratio nanostructures. In semiconductor applications such as transistors and memory devices, the catalyst material should be CMOS-compatible to enable adoption in the industry and prevent deep level defects in silicon. Materials such as Au, Ag, Pt, Cu, Pd, W, Ni, Ru, graphene, TiN, RuO2, etc. can be used as SiSE catalysts. Processing metals such as Au and Cu at high temperatures results in deep level defects. Since SiSE is a process from room temperature to low temperature, the effects of such defects can potentially be minimized. Additionally, CMOS-compatible catalysts such as Pt, Pd, Ru, TiN, etc. can be used.

[0043] Figure 4 shows a SEM cross-section of silicon nanowires fabricated with a gold and platinum catalyst, and is an enlarged view of an image of the catalyst mesh at the bottom of the nanostructure, according to one or more embodiments of the present technology. In the case of a CMOS-compatible catalyst such as platinum (Figure 4), deposition and patterning are bound to have a high yield. Platinum can be etched using plasma etching with Cl2 to form PtCl2. At temperatures above 210 °C, PtCl2 is volatile and can thus be used as an executable method for etching the metal after deposition and lithography. A similar etching method can be used for palladium. Other deposition methods are via electrodeposition after lithography, where the metal is deposited only in the areas of the substrate that are not covered by the resist. Alternatively, the metal is deposited on the lithographed areas and the substrate, such as by electron beam deposition, but only the areas in contact with the substrate are etched by MACE without the need for lift-off.

[0044] To prevent the catalyst mesh from wobbling and for reliable transport of the etchant solution, continuous patterns and / or ceilings with connection links can be used in various embodiments with an electric field. The resulting high aspect ratio features can be prevented from collapsing by relaxation techniques such as using a low surface tension gradient, supercritical drying, and connected features. Wobbling and collapse can also be prevented by using patterning techniques that consist of connecting the desired links between features in both the catalyst and the substrate, or by converting the high aspect ratio linked features to the desired device structure using controlled deposition or etching after SiSE treatment.

[0045] The problem that occurs during high aspect ratio etching of severed features is the problem of collapse. This is very harmful to the device yield. Various embodiments solve this problem by creating an interconnect nanostructure with sub-10nm support features that prevent collapse and provide stability to the structure during and after etching. For example, in FIGS. 5A through 5B, a design of a catalyst for 3D NAND flash is shown. After SiSE, the resulting structure may be higher than 20 microns in height and have a feature size of less than 40 nm.

[0046] FIG. 5A shows a method of simultaneously connecting various isolated catalysts 520 and high aspect ratio (HAR) nanostructures 540 using a catalyst material and connection links 510 within a semiconductor structure, according to one or more embodiments of the present technology. FIG. 5B is a top view showing a connection region 540 that defines a high aspect ratio structure remaining after SiSE and a non-connection region representing the geometry of catalyst features 530. According to various embodiments, the isolated catalyst portions are connected using patterns that can be generated from an algorithm used to connect isolated features using links so that the HAR nanostructures can reliably stand, and also assist in preventing fluctuations in the catalyst mesh to ensure a uniform and controlled etching rate, creating diffusion paths for reactants and products of the etchant (FIG. 5A). Although fluctuations may occur because the catalyst features are severed, they may be prevented in some embodiments that use an electric field. The self-standing features are connected to prevent collapse by strengthening the high aspect ratio lines (FIG. 5B).

[0047] According to various embodiments, the generation of connected links can be performed by defining catalytic material or semiconductor nodes that can be isolated in an ideal intended design. Next, the links can be generated such that the structures etched with CICE are mechanically stable for sure. The links can also be optimized so that the catalyst does not wobble in CICE. The optimization of such processing excursions in catalyst design can be performed using standard algorithms such as graph theory-based methods and recursive partitioning methods.

[0048] The catalyst can include one or more of: a) lithography links that prevent wobbling - these features create gaps in the etched structure, which can be filled with material using various deposition processes such as atomic layer deposition, chemical vapor deposition, electroplating, etc., and / or b) lithography gaps for preventing the collapse of the etched structure - these features result in stabilizing the links within the etched structure. Based on design requirements, these links may be removed using lithography and etching, selective oxidation, selective oxidation and etching, etc. This can be done after depositing stabilizing material in other regions as needed.

[0049] When the catalyst mesh includes both lithography links and gaps, a linked structure is formed. It is very difficult to fabricate (process) sub-30nm features with smaller link connections. Patterning methods such as electron beam lithography can write sub-10nm features but are troubled by large overlays. On the other hand, photolithography has excellent overlays but low resolution. Photolithography and imprint lithography (whose template is made by electron beam lithography) can be used to obtain a linked final structure that will later become a nanoimprint template. An example of such a pattern is described in the section of 3D NAND and transistor devices.

[0050] In addition to using isolated or linked structures as catalysts, another way to extend the maximum aspect ratio used in various embodiments is by using a ceiling. Collapse prevention using a ceiling can be achieved by etching the feature to a short and stable height using plasma etching or SiSE, depositing the ceiling, and continuing the SiSE process. The "ceiling" can also be at a height along the length of a short pillar such as L / 2, where L is the height of the short and stable pillar. This provides additional support as the feature is further etched, and the maximum aspect ratio becomes larger than the aspect ratio of the ceiling at the top of the short pillar. This imparts structural stability to the high aspect ratio pillar and prevents collapse.

[0051] The ceiling can be deposited by methods such as inclined deposition, filling with a polymer, etch-back and ceiling deposition, or spin coating. Materials that can be used for the ceiling include polymers, sputter / deposited semiconductors, metals and oxides that do not react with the CICE etchant. For the Si CICE etchant, materials such as Cr, Cr2O3, carbon, silicon, Al2O3, polymers, etc. can be used. In some embodiments, the ceiling can also be made porous by a further low-resolution lithography step or by a reaction that induces porosity in the ceiling material. Once the substrate is etched and the catalyst is removed using liquid or vapor phase chemical etching, a memory film or dielectric filler can be deposited by methods such as atomic layer deposition before removing the porous ceiling. The ceiling material can also be adjusted to be non-selective with respect to atomic layer deposition (ALD) to prevent multiple holes from closing off the deposition path. After filling the feature, the ceiling is etched or polished. ALD can also be used to close the high aspect ratio shape after etching to create deep holes without using isolated catalysts.

[0052] (Etching tool) Various embodiments of the present technology enable high-aspect-ratio nano-structure wafer-scale etching in semiconductor materials with features such as a system (multi-scale precision CICE or MSP-CICE) that enables multi-scale precise control of CICE processing, including 1) high-speed (real-time), high-spatial-resolution functional or geometric metrology as etching progresses for precise process monitoring and control, and / or 2) based on real-time measurement and an array of independently addressable actuators that enable locally controlled etching processes to enable controlled manufacturing (processing) of devices with various arrays.

[0053] Figures 6A through 6E are diagrams showing CICE process chamber configurations according to one or more embodiments of the present technology. Figure 6A shows a system including an inkjet 605, an etchant circulation system 610, a front electrode 615, an electric field supply unit 620, a polymer wall 625, and a back electrode contact and thermal actuator 630. In the embodiment shown in Figure 6A, a silicon wafer 635 can be disposed between the front electrode 615 and the back electrode 630 to enable electric field control. Figure 6B shows some embodiments of the electric field configuration of CICE using a wafer chuck 640. Figure 6C shows a setup for bulk delivery of an etchant with a micromirror array for additional thermal control and back contacts for local electrical and thermal actuators used in some embodiments of the present technology. Figure 6D shows a setup for bulk delivery of an etchant with a micromirror array for additional thermal control, back contacts for local electrical and thermal actuators, and a front-side electrode pin 645 used in some embodiments of the present technology. Figure 6E shows a setup with a thermal chuck and embedded electrodes and thermal actuator 650 behind the substrate.

[0054] The embodiments shown in FIGS. 6A and 6B provide local control of etchant concentration and electric field using an inkjet 605 connected to a local top electrode 615 and a back electrode contact 630. Different regions for etching can be isolated from each other at the top of the wafer using polymer walls 625 that are tapered using low-resolution lithography. In one embodiment, these walls can be made of different etchant-resistant materials such as silicon nitride, aluminum oxide, amorphous carbon, silicon, or chromium. In FIG. 6A, the back electrode 630 includes both an electrical actuator and a thermal actuator, and the electrical contact is made using a conductive material such as a metal, silicon, silicon carbide, etc., which may or may not be doped to improve conductivity. In FIG. 6B, the back electrical contact 630 is made using an electrolyte locally included between the wafer 635 and the chuck 640. The electrolyte may be the same as the etchant or a different conductive liquid such as a CMOS-compatible dilute acid, base, or salts. In FIGS. 6A and 6B, the back electrode 630 can also include temperature control integrated within the electrode itself (FIG. 6A) or within the chuck (FIG. 6B).

[0055] In the embodiment shown in FIG. 6C, the back electrode contact 630 and the chuck 640 are the same as the configuration in FIG. 6B. On the other hand, the etchant may be distributed globally on the wafer using an inlet and circulated using an outlet for flow control. Any diffuser (not shown) may be used to ensure uniform dispersion of the etchant across the entire wafer. Different components of the etchant may be mixed in a separate mixing chamber or dynamically mixed by passing through the inlet and the diffuser. The electrode 615 can be made of a metal mesh, a doped silicon wafer, ITO (indium tin oxide), or other such materials and can be coated with an etchant-resistant material such as a polymer, PTFE, aluminum oxide, etc. The coated material can be doped to improve conductivity. Local heating can be implemented on either side of the wafer by a micro-mirror array on the upper side of the wafer or by an embedded thermal actuator in the chuck 640.

[0056] In the embodiment shown in FIG. 6D, the wafer 635 can face either the top or the bottom of the setup. The chuck 640 can be used to create an electric field using electrodes and an electrolyte. The electrolyte can be a very thin film, thereby enabling local temperature control via the embedded actuators of the chuck 640. Alternatively, a micromirror can be used. Any diffuser (not shown in FIG. 6D) can be used for both the uniform distribution of the etchant and optical measurements using an embedded optical fiber. Local electric field control can be created via sharp electrode tips 645 or by the embedded electrodes of the chuck 640.

[0057] FIG. 6E shows an embodiment in which the wafer 635 faces the base of the setup. The base contains electrodes and an etchant at a low temperature. The wafer can be held upside down using a head chuck with electrical and thermal actuators. A thin film of electrolyte may be present in the head chuck to improve electrical contact. The wafer can be rotated using the head chuck, and an overflow chamber can be used to transport excess etchant while rotating the wafer. Any diffuser (not shown) can be used in the base to enable the uniform dispersion of the etchant. The diffuser can also include a measurement optical cable.

[0058] CICE can be implemented in different applications, such as electrochemical etching, electroless chemical etching, catalytic vapor etching, catalytic plasma etching, electrochemical / electroless chemical etching of "digital" layers (e.g., alternating pulsing of H2O2 vapor and HF vapor, alternating pulsing of H2O2 liquid and HF liquid, alternating pulsing of H2O2 vapor and HF liquid, alternating pulsing of H2O2 vapor and HF liquid, alternating flows / pressures of H2O2, plasma, and fluoride ions to alternate porosity, using a strong oxidizing agent for the porous layer and a weak oxidizing agent for the non-porous layer, etc.), magneto-electrochemical / electroless chemical etching, gel-based etching (e.g., adding a thick polymer material and making local contact at the top / bottom of the wafer for local thermal and electric field control, or changing the gel concentration (gel consistency) along with the temperature), etc., using various etching agent delivery methods together with catalysts, electrical, magnetic, temperature actuators, etc.

[0059] In some embodiments, prior to the CICE process, the wetting characteristics of the chemical substances of the etching agent on the catalyst patterning substrate can be changed to be more hydrophobic or hydrophilic. This helps improve the uniformity of the etching process by ensuring that the start of etching begins simultaneously everywhere on the substrate. Exposing the substrate to vapor HF, piranha (sulfuric acid and hydrogen peroxide in different ratios), buffered oxide etching, hydrofluoric acid, etc., and rinsing with deionized water, isopropyl alcohol, acetone, etc., and drying to prevent water stains can improve the wetting of the etching agent on the substrate.

[0060] After the CICE process is completed, the substrate can be rinsed with deionized water, isopropyl alcohol, acetone, etc. so that the etchant can be completely removed from the substrate, thereby avoiding local excessive etching. The rinse station can be the same as the processing chamber where the wafer is rinsed with deionized water after the removal of the etchant. It can also be equipped with a spinning system for drying the wafer after rinsing. Alternatively, the wafer can be moved to other rinse and dry stations after the CICE process using automated handling.

[0061] FIG. 7A shows a cross-sectional view of an embodiment of an MSP-CICE processing chamber 700 with automated handling using a Z-motion actuator 710. The Z-motion actuator may include a voice coil within the head assembly, a bearing 715 within the base assembly, and compliance within the actuator system to ensure a good seal for leak prevention using a leak-check sensor 720. This Z-motion actuator is used to lower the head assembly 725 towards the base assembly 730. The Z-motion actuator may be controlled using a motion sensor, a force sensor, or a combination thereof so that the head assembly, wafer, and base assembly can be assembled to ensure the formation of an appropriate seal required for the electrolyte within the head assembly and the etchant within the base assembly. In this embodiment, the Si wafer substrate 735 faces the base.

[0062] The base includes a base electrode 740, a power supply 745 to the base electrode, and a sealing ring 750 which is a rectangular cross-section ring or an O-ring (circular cross-section polymer ring) made of an etching-resistant material such as a fluoropolymer, Al2O3, SiC, Teflon (registered trademark) coating material, etc. used to block the etching agent from the electrode and the Si wafer. The base also includes an inlet 755 and an outlet 760 for the flow and circulation of the etching agent, and a diffuser 765 which may include an optical fiber for optically sensing the etching process in situ. The base may also include an overflow chamber (not shown) to ensure that the etching agent fills (fills up to the edge) before mounting the Si wafer. The head assembly includes a pinch chuck zone 770, an electrolyte zone 785, and a power supply 795. The pinch chuck zone is connected to one or more vacuum ports 775.

[0063] The thermal actuator 780 can be embedded behind the pinch chuck zone. Embodiments using a thermal actuator with a proportional-integral controlled thermoelectric heating / cooling element such as a thermistor and a heat sink are incorporated herein by reference (Ajay, P. et al., 2016. Multi-field sub-5nm overlay in imprint lithography. Journal of vacuum science and technology. B, Nanotechnology & microelectronics: materials, processing, measurement, & phenomerna: JVST B, 34(6), p061605). The electrolyte ports 790 at both the inlet and the outlet are used to feed the electrolyte into one or more electrolyte zones and block it during etching. This enables a configuration where the head assembly can rotate with the Si wafer while the base remains stationary. The electrolyte may be different from the etching agent and may be, for example, a dilute acid, base, salts, etc. with sufficient conductivity to create an electric field across the entire Si wafer using the base electrode. A typical electrolyte includes dilute sulfuric acid.

[0064] Figure 7B shows a cross-sectional view and a top view of an embodiment of the head chuck. The pinch chuck zone 770 is used to hold the Si wafer 735, and the electrolyte zone 785 is used to create a contact between the Si wafer and the electrolyte. In this embodiment, a liquid electrolyte is used to create a reliable ohmic contact with the Si wafer. In other embodiments, a metal or SiC pad may be used instead of the liquid electrolyte within the "electrolyte zone". The pinch chuck and the electrolyte zone are separated from each other using a seal element 771 machined into the chuck. The local electric field boundary at the end of the electrolyte zone is discrete behind the Si wafer. However, due to the thickness and electronic properties of the Si wafer, the electric field lines between different electrolyte zones may converge in front of the Si wafer.

[0065] Electromagnetic simulations can be performed to determine the optimal placement of the electrolyte zone and the pinch chuck zone for effective local and global electric field control and end uniformity. In one embodiment, the seal element is 1 mm wide, the pinch chuck and the electrolyte zone are concentric and each 9 mm wide, and end at a central circular region as shown in Figure 7B. The vacuum port 775 may use a pneumatic element to ensure that the pinch chuck zone is under vacuum and the wafer is held against the pins 772. The electrolyte flow port 790 is used to flow the electrolyte after the Si wafer is held by the chuck. The discrete heat actuator 780 can be integrated behind the pinch chuck region of the Si wafer to facilitate local temperature control. In one embodiment, the head assembly comprises a pinch chuck element made of an aluminum oxide material.

[0066] In FIG. 7, automatic handling can be achieved by starting from the separation between the head and the base. The base is stationary and filled (buried) up to the edge with the etchant. This can be ensured using an overflow chamber and an etchant level monitor. The etchant of the base can be recycled using an inlet valve and an outlet valve. The robot arm is used to mount the Si wafer on the head chuck with the surface to be etched facing the base. In one embodiment, the robot arm contacts the front surface of the Si wafer only at the end (the exclusion zone, which is a zone of about 1 to 2 mm at the end of the wafer where no functional device is manufactured (processed)), and aligns the back surface of the wafer with the seal ring outside the head chuck. This then holds the Si wafer using vacuum in the pinch chuck zone. In an alternative embodiment, the head chuck may include "fingers" around the end of the wafer that project to grasp the end of the wafer after the robot arm holding the wafer facing the base has brought the wafer under the head chuck. The fingers grasp the end of the wafer and then pull the wafer towards the pins of the head chuck. Next, the vacuum zone grasps the wafer. This can be detected using the vacuum sensor of the chuck vacuum line. Next, the fingers retract into the head away from the end of the wafer.

[0067] Once the seal is created, the electrolyte is pumped into one or more electrolyte zones. This part may be thin to ensure the need to pump in a small amount of electrolyte. Next, the head assembly, together with the Si wafer, is lowered towards the base using a Z-motion actuator. To ensure smooth contact with the etchant in the base and minimize the formation of bubbles at the etchant-wafer interface, the head assembly is tilted slightly as it is lowered using an element of the Z-motion actuator such as a voice coil. When one end contacts the etchant, the head assembly tilts and returns to a horizontal configuration. This can prevent bubbles from accumulating at the wafer-base interface. Next, any bearings in the base clamp the assembly and use a force sensor to check whether an appropriate seal has been created between the base and the Si wafer.

[0068] Alternatively, excess etchant may flow into an overflow chamber near the edge of the wafer. Next, a leak test sensor checks that the wafer is ready to be processed. CICE may be performed by initiating an electric field across the wafer. In processes that require an oxidizing agent such as H2O2, the oxidizing agent may be pumped into the base etchant after the wafer is clamped so that etching is not prematurely initiated by any initial contact. In an alternative embodiment, the volume of the etchant in the base is slightly less than the amount required to contact the front surface of the Si wafer. Once the head assembly has completed its z-motion towards the base, a small amount of etchant is added to the base chamber to bring the etchant into contact with the Si wafer. To prevent bubbles from adversely affecting the etching, the head may be tilted slightly to allow the bubbles to escape and then returned to the horizontal position, thereby creating a uniform etchant-wafer interface for CICE.

[0069] The removal of the wafer after CICE processing in FIG. 7 may also be automatically handled. Once the CICE processing is completed, the head assembly including the wafer is separated from the base. Next, the etched side of the wafer is rinsed to remove the etching agent on the surface. This can be accomplished by rotating the head and spraying deionized water. Here, the rinsing system is moved to an area under the head and above the base. The rinsing system includes a drain, a spray for deionized water, and a source of heated air or nitrogen gas for drying the etched surface. Once the front surface of the Si wafer is clean, the electrolyte in the head is drained, and the wafer is placed face down on the end contacts of the rinsing station. Next, the back surface of the wafer is rinsed and dried in a similar manner. Next, the robot arm removes the Si wafer, and the rinsing system is moved away from the center of the base and the head. In an alternative embodiment, the head may move laterally and place the Si wafer in another rinsing station.

[0070] In wafer-scale etching of semiconductor bulk or superlattice nanostructures using CICE, various parameters such as etching depth variation, porosity of alternating layers, stability of high aspect ratio nanostructures, etching anisotropy, wafer edge effect, electric field uniformity, illumination uniformity, etc. can be monitored and controlled. Thereby, the etching parameters can be monitored layer by layer during SiSE. This can use local control of pattern geometry and measurement of current and voltage across the stack to determine, with a high level of accuracy across the wafer, parameters such as the number of etched layers.

[0071] Furthermore, the areas of the wafer used for peripheral circuits and non-3D NAND array circuits must be protected from SiSE processing. This can be accomplished by masking the non-array regions. The etching variations near the ends of these features can be adjusted using actuators.

[0072] When etching to a depth exceeding 10 microns (A.R > 250), the flow of the etchant through sub-40 nm holes is enabled by an electric field and the creation of alternating porous layers. The porous layers enhance the lateral flow of the etchant and regulate the etching uniformity. Another way to increase the flow of the etchant according to various embodiments is by connecting a plurality of holes using a connected link pattern.

[0073] As the etching progresses with an increase in the aspect ratio, the diffusion of the etchant may slow down, resulting in a decrease in the etching rate. Since each etched layer of the superlattice can bring about a step change in electrical properties such as the current or voltage across the entire electrode or the resistance of the stack, such changes can be detected through the change in the electrical properties of the entire stack. To prevent this reduction in diffusion, some embodiments utilize alternating porous layers to ensure that there are multiple paths for the etchant to reach the etch front, i.e., the catalytic site. In some embodiments, the rotation of the substrate during CICE can be performed at an optimized speed to improve the uniformity of the etchant concentration from the center to the edge of the wafer.

[0074] The main cause of catalyst fluctuations is the imbalance in the density of the holes under the catalyst. To prevent catalyst fluctuations and ensure the vertical anisotropy of etching, an electric field can be applied to direct the diffusion of the holes towards the bottom of the wafer. As SiSE progresses, the required electric field changes due to the change in resistivity between the electrodes associated with the change in the number of alternating doped layers being etched. By using a current control power supply circuit, the change in voltage can be compensated for.

[0075] Various embodiments of the SiSE tool system enable multi-scale precise control of SiSE processing based on real-time measurement and an array of independently addressable actuators that locally control the etching process to enable controlled manufacturing (processing) of devices with various shapes and multi-layers. Parameters such as the resistivity and doping of the substrate material, the required geometry and aspect ratio, the etchant ratio, the electric field, the temperature, the illumination of the processing chamber, etc. can be changed to control the etching. Once the SiSE process is completed by in-line measurement, the solution in the machine must be flushed and replaced with a wet etchant for the catalyst. Next, as the device dries, the capillary force can cause the collapse of high aspect ratio nanostructures, so an efficient and highly controlled fluid exchange combining advanced drying techniques and a novel mesh architecture and / or ceiling is used to prevent the collapse of the taper pattern.

[0076] In-line electrical measurement and electrochemical etching stop may be used in various embodiments. For example, the electrical bias when applied to a semiconductor substrate can control the etching profile in real time. Excessive etching due to the movement of excess holes generated under the catalyst can be controlled by an external electric field. A negative bias on the back side of the wafer attracts excess holes and prevents unnecessary holes in the Si. By setting a wide range of currents, biases, and polarities, including high-speed pulses and periodic reverse waveforms, the electric field across the wafer can be controlled in real time. Electric field parameters such as current, voltage, resistance, capacitance, waveform frequency, duty cycle, amplitude, distance between electrodes, etc. are used not only to control the porosity of the alternating layers while preventing catalyst fluctuations, but also to detect changes in the etching state.

[0077] Measurement of the current and voltage across the substrate as the etching progresses can be used to determine the number of alternating layers etched in 3D NAND flash processing. Also, the exact time when the morphology changes can be detected by measuring electrical parameters such as the resistance, voltage, current, capacitance, etc. of the entire epitaxial layer. This information can then be used to precisely modulate the current across the stack.

[0078] The electric field can be used for various functions during CICE processing. For example, the fabrication of alternating porous / non-porous layers, preventing catalyst fluctuations during etching, maintaining wafer-wide uniformity, detecting variations in etching depth within a die, die-to-die variations, and center-to-edge variations. To apply the electric field locally and globally across the substrate, tools and process designs are required to ensure compatibility with front and back contacts, edge-width contacts, electrical back-contact materials, etc., and different CMOS processing equipment. Some embodiments of this design are shown in FIGS. 6A through 6E.

[0079] Multiple electric fields can be applied across the wafer to perform multiple functions. For example, 1) a DC voltage across the wafer to prevent catalyst fluctuations, 2) an alternating electric field with a certain waveform, frequency, wavelength, duty cycle to create alternating porous / non-porous layers, 3) detecting local variations in etching from the center to the edge via a pulsed electric field at a frequency and voltage that do not affect the porosity of the substrate being etched. And / or 4) monitoring the etching depth by measuring the current, voltage, resistance, capacitance, etc. of each local electrode.

[0080] Apart from the electric field, temperature can also affect the etching rate of CICE. For example, the etching rate of CICE depends on the temperature of the etchant, and it has been shown in the literature that it decreases exponentially near 0°C. (Reference: Backers, A. et al., 2016. Temperature-Dependent Pore Formation in Metal-Assisted Chemical Etching of Silicon. ECS JOURNAL of Solid State Science and Technology, 5(12), pp. 653-656, which is hereby incorporated by reference in its entirety for all purposes). Various embodiments utilize this property by locally controlling the etching temperature by maintaining the local etchant temperature near zero degrees using coolants such as liquid nitrogen and dry ice, and locally changing the temperature of the substrate. This can be done using a thermal chuck, micromirror, or electrode near the wafer that can locally heat the solution. Alternatively, the temperature of the etchant can be locally controlled by using individual wells for each die. The individual wells are filled (or buried) with a finite volume of temperature-controlled etchant and are pumped out or circulated. In some embodiments, the temperature can be precisely mapped across the wafer using a thermal camera, thermocouple, etc.

[0081] An optical imaging system is used to measure the reflectivity of a large sample area in real time. The sample is irradiated with light of known spectral components. The light can be white light, colored light, a single wavelength, a narrow or broad spectral band, etc. Next, a camera can image the sample that reflects this light. The camera can be monochrome, color (RGB), multispectral, hyperspectral, etc. Due to the multi-megapixel resolution found in modern cameras, millions of locations on the sample can be observed simultaneously. The video frame rate enables in-situ real-time measurement. Each image can be divided by a reference image to calculate the reflectivity image of the sample or used as it is. Image processing algorithms determine the completion of the processing and collect data regarding the uniformity of MSP-CICE within and between samples. In an embodiment of creating Si nanowires (NWs) using CICE, the optical properties of the variable-shaped Si NWs result in a wide-spectrum coloration under white light illumination. In preliminary experiments using CICE, the sample shows a large change in hue during CICE etching. Since the pitch and diameter of the nanowires remain relatively fixed, observing the change in hue of the sample is a useful indicator of the height of the nanowires and thus the depth of etching. The change in hue can be characterized by measuring the reflectivity of the sample as a function of the spectral components of the light present.

[0082] The spectral characteristics of the alternating layers can also be used to enable the detection of the number and porosity of the layers during the etching process. Infrared (IR) spectroscopy can be used to determine the etching layer in-situ. This uses the same measurements as those used in the literature to characterize Bragg reflectors and rugate filters. In one embodiment, an optical cable within a diffuser plate in the etching chamber can be used to incorporate such measurement elements.

[0083] Visible light wavelengths from the backside of the wafer cannot detect the etching depth within the CICE. Instead, infrared (IR) spectroscopy can be used because it is a rapid and non-destructive in-situ method for detecting the etching state. Silicon is transparent at IR wavelengths, but catalysts such as Pt and Pd are not. This distinction can be used to determine both the etching rate and the etching depth in specific CICE processes.

[0084] The concentration of the etchant can be measured using various techniques. For example, in some embodiments, since HF has a linear dependence between concentration and conductivity, conductivity measurement can be used. In some embodiments, refractive index measurement can be used. For example, an optical measurement system can be used to measure the refractive index (RI) via a reflection type geometry that avoids turbidity, diffraction, and absorption using an optical window in contact with the solution.

[0085] To ensure the uniformity of the etchant concentration across the wafer, the wafer can be rotated using a wafer chuck. Here, a local electric field can be provided by connecting a spinning array of local electrodes on the chuck to a patterned fixed conductor disk. The local electrodes can be connected to the tapered fixed conductor disk using slip rings. The affinity with the chemical substance of the etchant can be ensured by using a Teflon coating.

[0086] In some embodiments, "pilot" wafers can be used to optimize etching, and the pilot wafers can be inspected using various in-situ (online) and ex-situ (offline) methods. Offline measurements consist of various destructive and non-destructive inspection methods such as scatterometry, ellipsometry, optical property size measurement, laser scanning, scanning electron microscope (SEM), atomic force microscope (AFM), transmission electron microscope (TEM), X-ray diffraction (XRD), etc. The collected data is analyzed using image processing algorithms to identify the causes of defects and process excursions.

[0087] Magnetic fields, pressure fluctuations, electromagnetic fields, solvents for improving the uniformity and preventing bubble adhesion, wafer rotation, edge effects, spraying of the etchant, and atomization of the etchant can also be included in some embodiments of the CICE tool as needed.

[0088] (Overall tool design and control scheme) Some embodiments provide a wafer-scale system for high aspect ratio etching of semiconductor substrates. The multi-scale precision (MSP) CICE system used in some embodiments can have a modular architecture that allows for the placement of sensors and actuators such as large-scale array electrodes and real-time optical imaging systems. FIGS. 8A through 8C show an example of an MSP_CICE tool set-up, an example of a detailed process chamber layout, and an example of a process flow used in one or more embodiments. In some embodiments, a non-linear optimal process control scheme can be used to achieve controlled wafer-scale nanofabrication based on a large-scale array of independently controlled electrodes.

[0089] FIG. 8A shows a cross-sectional view of a complete etching tool with an automated substrate, electrode, and etching cell mounting. FIG. 8B shows a detailed cross-sectional view of some embodiments of the processing chamber 815. As shown in FIG. 8B, the etching tool can include a loading dock 805, a robot arm 810, a processing chamber 815, an upper electrode 820, a tunable light source 825, a wafer chuck 830, a wafer chuck holder 835, a stirrer 840, a power supply 845, a plurality of sensors 850, a drain pipe 855, an optical measurement system 860, a high-resolution camera 865, a lower electrode 870, a circulation setup 880, an exhaust section 885, and an inlet flow 890. In the illustrated embodiment, the processing chamber 815 can include a robot arm 810 that places the wafer on the wafer chuck 830. The wafer chuck 830 can be positioned on the wafer chuck holder 835. The wafer chuck holder and the wafer chuck assembly separate the electrolyte that is in contact with the lower electrode 870 and the upper electrode 820. Thereby, an electric field is surely applied to the entire wafer. The processing chamber 815 can also include an in-line optical measurement system 860 that can include a high-resolution camera 865 and a tunable light source 825. The processing chamber 815 according to various embodiments can also include an etching flow system with an inlet flow 890 for the lower electrolyte and the upper electrolyte / etching agent, a drain pipe 855, and a circulation setup 880. The etching flow system can also include a stirrer 840 (e.g., a magnetic stirrer). An electric field can be applied to the entire wafer using a first electrode 820 and a second electrode 870 with a power supply 845. In-line measurement can be performed using a plurality of embedded sensors 850 (e.g., temperature, electric field characteristics, fluid concentration characteristics, etc.). The exhaust section 885 can be used for discharging the fumes. The processor 890 can control the processing using one or more algorithms.

[0090] In the embodiment shown in FIGS. 8A to 8B, a wafer having a patterned catalyst is loaded onto a loading dock 805. The wafer can be transferred to a processing chamber 815 using a robotic arm 810. Next, a transparent top electrode 820 can be placed on a rail above the wafer holder. When the processing is complete, the top electrode array 820 can be removed and the wafer is removed and returned to the loading dock 805. An important issue in constructing this tool is that all elements of the system are affinity with HF (hydrofluoric acid). Various embodiments propose to do this by coating all equipment in contact with HF with polymers such as Teflon PTFE, epoxy, TPX (or PMP), polypropylene (PP), and PVDF, which are also affinity with H2O2. TPX and epoxy are transparent and easy to process.

[0091] Depending on the requirements of the application, the wafer chuck may be a Bernoulli chuck without backside contact with the wafer, or may have an O-ring for introducing a wet etching agent onto the front surface of the wafer. Flow valves and actuators can be used to control the relative ratios of the etching agent components (HF, H2O2, ethanol, isopropyl alcohol, deionized water, etc.) within the chamber. The etching agent can be distributed locally by inkjet or over the entire wafer by a flow valve. After etching and removal of the catalyst mesh, the etching agent may be flushed with deionized water and replaced with a low surface tension liquid. The drain valve safely disposes of the fluid or stores it for use in subsequent etching.

[0092] FIG. 8C shows an example of the various processes that a wafer undergoes in an etching tool. The wafer can be loaded into the tool using a loading dock 812, which may include a FOUP (Front Opening Universal Pod) of the wafer. A robotic arm (or other transport mechanism) can transport the wafer from the loading dock 805 to the processing chamber 815. The processing chamber 815 may include one or more chambers for pre-treatment 816, etching 818, post-treatment 828, and rinse step 830.

[0093] The pretreatment step 816 may be a lift-off process or a surface modification step such as the dispensing of piranha (sulfuric acid and hydrogen peroxide), vapor HF, diluted HF, buffered oxide etch, ethanol, acetone, isopropyl alcohol, ion-exchanged water, etc. The pretreatment step may also be through plasma activation using oxidation plasmas such as oxygen, carbon dioxide plasma, or hydrogenation plasmas such as hydrogen, ammonia plasma. Helium or argon plasma can also be used.

[0094] Next, the etching process 818 can be performed on the wafer using sensors and actuators for in-situ monitoring and control. For example, as follows. ● Flow control 824 can include etching agent concentration measurement. According to various embodiments, the concentration of the etching agent is measured using two techniques. That is, a) Conductivity measurement - HF has a linear dependence between concentration and conductivity, and b) Refractive index measurement - an optical measurement system measures the refractive index (RI) through a reflection type geometry that avoids turbidity, diffraction, and absorption using an optical window in contact with the solution. ● Local temperature control 822: The etching rate depends on the local temperature and the mesh profile. Using a temperature actuator wafer chuck, various embodiments can control local temperature variations for process control. ● Environment control of the processing chamber (not shown in FIG. 8C): The tool is surrounded and there is a flow of inert gas. The pressure and overall temperature are monitored and controlled. A computer interface is used to promote operator safety, monitor etching using image processing, and control temperature and electric field. ● Electric field 826: When an electrical bias is applied to the semiconductor substrate, the etching profile can be controlled in real time. Excessive etching due to the movement of surplus holes generated under the catalyst can be controlled by an external electric field. A negative bias on the back side of the wafer attracts surplus holes and prevents unnecessary holes in the Si. Although the etching rate decreases with an increase in the electrical bias, a higher temperature can be used to keep the etching rate high enough for high throughput. Since MSP-CICE is used for various pattern densities and shapes in different regions of the wafer, an electrode array is used to locally control and attenuate the electric field on different patterns to ensure etching uniformity. The electric field across the entire wafer is controlled in real time by setting a wide range of currents, biases, and polarities, including high-speed pulses and periodic reverse waveforms. Optical measurements can be performed using a transparent top electrode such as an ITO film on a glass or sapphire wafer, a doped Si wafer (transparent to IR), a platinum mesh, or an optical fiber, above or below the wafer. The bottom electrode can be an array for local control, and a modular design is selected to enable easy installation and investigation of various bottom electrode arrays. The top electrode, bottom electrode, and electrolyte are isolated from each other using a wafer chuck and a wafer chuck holder assembly. Crosstalk is minimized using simulations. Measurement of the current and voltage across the entire substrate as the etching progresses can be used to determine the number of alternating layers etched in 3D NAND flash processing or, for example, as an etching stop indicator for nanostructure etching when there is a buried epi-layer in the substrate. ● In-line optical measurement 820: Using an optical imaging system including an RGB camera, an optical fiber, and a spectral imaging setup, the reflectivity of a wide sample area is measured in real time. Image processing algorithms determine the completion of the process and collect data regarding the uniformity of MSP-CICE within and between samples.

[0095] Post-treatment 828 may include etching of the catalytic metal and rinsing and drying of the substrate. To prevent collapse of the high aspect ratio etched nanostructures, fluid transfer is used to enable preparation of the wafer for surface tension gradient (Marangoni effect), low surface tension fluid transfer, or transfer to a critical point drying tool.

[0096] In one embodiment, the etching ratio can be adjusted based on the resistivity and doping of the silicon, and the required geometry and aspect ratio, to obtain the desired results. Factors such as the electric field, temperature, and illuminance of the processing chamber can also be changed to control the etching. Once the CICE process detected by in-line measurement is complete, the machine's solution must be flushed and replaced with a wet etching agent for the catalyst. Next, at the time of drying the device, the capillary force may cause the collapse of the high aspect ratio nanowires, so an efficient and highly controlled fluid exchange combining advanced drying techniques with a novel mesh architecture and / or ceiling is used to prevent the collapse of the tapered pattern.

[0097] Once the design and fabrication (processing) of the MSP-CICE system (including the optical imaging system and electrical parameter measurement) is complete, it is necessary to develop optimal control techniques for operating the MSP-CICE system to fabricate (process) device-specific VA-NS at the wafer scale. As described above, it is important to have the ability to monitor the progress of etching in multiple different layers in the shaped nanowires for DRAM or 3D NAND flash stacks. This requires local control of the pattern geometry and measurement of the current and voltage across the entire stack to determine, for example, the number of layers etched with a high level of accuracy across the entire wafer.

[0098] A key challenge is that a forward model of the entire system providing the relationship between the sensing output and the controlled variables across the wafer is expected to be highly nonlinear, making experimentally verified comprehensive models difficult to obtain due to the complexity of the MSP-CICE system. However, certain aspects of the process can be modeled through established physical models. For example, in various embodiments, the controlled variables can include temperature, chemical composition, and electric field, and the variation of the chemical composition can be analytically modeled with the help of equations governing transport. The control of the electric field and temperature can be distributed across a large array of actuators consisting of hundreds to thousands of actuators, providing localized control of the etch process. Their distribution can also be modeled using physical models. It can be modeled through a physical model.

[0099] However, models to establish the effect on the etching process are less clear. 2 It is expected to provide spectral information with high spatial resolution of 1 nm or better and high wavelength resolution of 1 nm or better. The optical, thermal, and electrical outputs of the system provide a large amount of sensory information that can be used to automatically control the process of the system using the aforementioned control variables. The automatic process control of the MSP-CICE system can be classified into two different categories: (i) offline optimization and adjustment of process parameters to obtain a target output, and (ii) real-time adjustment of process parameters to minimize defects and maximize yield. The latter relies on processes that are well established and provide large amount of data. The former relies on optimization of process parameters in the absence of large amount of data. In the following paragraphs, a scheme is described that can optimize process parameters to establish a baseline process for a given pattern geometry with the help of in-situ and offline measurements.

[0100] FIG. 9 shows a learning algorithm-based controller 900 that can be used to execute the first category of automatic processing control when there is no large-capacity data. That is, it is to determine the optimal processing parameters of the target output with the help of learning algorithms including evolutionary algorithms such as genetic algorithms and neural networks. This scheme depends on both in-situ electrical and optical feedback, as well as offline measurements such as ellipsometry and CD-SEM on the pilot wafer. Due to the existence of this offline component, the cycle time of each experiment using the pilot wafer may be too high, so rather than individual experiments, it is necessary to reduce the number of experiments or each pilot wafer representing a combination set. This embodiment will be further described in the context of genetic algorithms. The first step 910 of this scheme is to define the target output and the corresponding objective function for optimization. Next, an initial "population" 920 is generated. The genetic algorithm depends on the interaction between individuals within the population. Here, each individual is a set of control variables or model parameters 925. In one embodiment, each population may be an experimental plan and may be limited to a single wafer.

[0101] For example, if each wafer is composed of 10×10 square mm zones that can provide electrical and optical feedback, there may be O(700) such zones on each wafer, so a maximum population size of 700 can be provided for each experiment. In other embodiments, the population size may be maintained at a lower number such as 20, and each individual experiment has 35 copies across the wafer. Next, this population is used to execute the CICE process 930. Next, as shown in step 940, sensors are used to extract information about the substrate before, during, and after CICE. The information sensed in this scheme can include the outputs of both in-line measurement sensors such as imaging systems and offline measurements (CD-SEM, optical, electrical, etc.) on the wafer (945). Thereafter, the sensed information is adapted to the desired output or objective function (950).

[0102] Desired output parameters include the spectral signature of the etched structure, electrical parameters such as the resistance and capacitance of the entire wafer during etching, optical images of one or more portions of the wafer, and CD-SEM, etc. Based on the objective function calculated using the sensed information, a new batch of control variables is generated using the population interaction parameters (965). Next, CICE is executed using the new batch, and the results are evaluated using sensors. If the sensed information is within the range of the desired results, the adjustment of the control variables is completed. Otherwise, the control variable optimization process is repeated until the final number of wafers is reached (960). In one embodiment, the genetic algorithm controller is intentionally designed to approach the desired optimal processing parameters for actual process execution, and achieving the desired processing performance is then taken over by the real-time in-situ processing control scheme 935 described next.

[0103] The second category of automated process control relies on data analysis for real-time adjustment of process parameters to achieve desired process performance. Current advanced manufacturing factories, such as semiconductor manufacturing, rely heavily on these concepts to maximize manufacturing yield with a high level of automation. There are several concepts within this category of automated process control, ranging from in-execution control to predictive maintenance. An important concept that underpins this scheme is the use of large volumes of sensory information, such as in-situ optical output, to perform real-time analysis based on heuristics (e.g., neural networks that determine mappings between control and sensed variables), statistics (e.g., statistical process control), and physical or heuristic models to reach optimal process parameters. An example of a situation where benefits can be gained from such models is the ability to accurately predict the time delay from a change in a control variable to the corresponding change in the sensed output. Furthermore, using such techniques, a continuously adapting simulation of a virtual MSP-CICE tool, i.e., an actual tool that is a proxy for the physical forward model and can be used for off-line process adjustment by the first category, can also be constructed. Such virtual tool models are tool-specific and specific to the lithography pattern being etched. Also, since manufacturing tolerances in tools such as electrical and thermal controllers can cause different processing signatures, even with the same design, they can vary from tool to tool.

[0104] Various embodiments of the CICE system are Si, Ge, Si x Ge 1-xIt may support various substrates and semiconductor multilayers such as, but not limited to, GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, etc. Further, various catalysts such as, but not limited to, Ag, Au, Pd, Pt, Cu, Ni, Ti, Al, W, TiN, TaN, RuO2, IrO2, graphene, etc. may be used. Some embodiments of the MSP-CICE system may use various patterning techniques such as, but not limited to, plasma etching, chemical vapor etching, electrodeposition (selective), etc. Removal techniques that may be used in some embodiments include, but are not limited to, chemical vapor etching, electrolytic etching, and / or wet chemical etching. Some embodiments may use various etchants (e.g., HF, H2SO4, HCl, H2O, etc.), oxidants (e.g., H202, V205, KMnO4, O2, HNO3, electric field, etc.), solvents, additives (e.g., H2O, ethanol, IPA, DMSO, polymers (PVA, PLA, etc.), H2SO4, etc.), the state of the etchant (e.g., liquid, vapor, solid gel, plasma), and / or catalyst-assisted etching processes (e.g., electrochemical etching, electroless chemical etching, vapor-phase etching, plasma etching, electrochemical / electroless chemical etching of "digital" layers, magnetic field electrochemical / electroless chemical etching, gel-based etching), but are not limited to these. Further, various local and global etching monitoring techniques may be used. By way of example, it includes, but is not limited to, electric fields (e.g., current, voltage, capacitance, inductance, impedance, conductance, etc.), optical measurements (e.g., using a camera, spectrophotometer, image processing, etc.), concentration measurements (e.g., refractive index, conductance of the solution), pressure (e.g., vapor pressure), temperature (e.g., using a thermocouple, IR camera, etc.). Some embodiments may use local and global etching control based on electric fields (e.g., current, voltage, waveform, wavelength, frequency, duty cycle, pulsed electric field, etc.), optical measurements (e.g., illumination), concentration (e.g., etchant concentration, mixing and diffusion), and / or temperature (e.g., using a thermal chuck, micromirror, etc.). Various embodiments of the setup can etch industry-standard wafers or wafers that have undergone standard CMOS processing.Some such embodiments may be affinity with the etchant. Some embodiments may provide for the automated handling of all substrates and etching components and chemicals.

[0105] In one embodiment, the etchant can be in vapor form. The apparatus for vapor-based CICE comprises local temperature control using a thermal chuck, monitoring of the vapor pressure of each component, and / or applying an electric field in plasma form. Using the vapor, the electrochemical / electroless chemical etching of the "digital" layer can be facilitated in the following ways: 1) Alternating pulsing of H2O2 vapor and HF vapor, 2) Alternating pulsing of H2O2 liquid and HF liquid, 3) Alternating pulsing of H2O2 vapor and HF liquid, 4) Alternating pulsing of H2O2 vapor and HF liquid, 5) Alternating flows / pressures of H2O2, plasma, and fluoride ions staggered to alternate porosity, 6) Using a strong oxidant for the porous layer and a weak oxidant for the non-porous layer.

[0106] (3D NAND Flash) The scalability of advanced memory architectures made by current pattern transfer technologies is limited by the degradation of the etching mask due to high aspect ratio plasma etching, sidewall damage, and non-zero taper. In non-volatile memory architectures such as 3D NAND flash, in order to increase the storage capacity per unit area, very high aspect ratio etching of more than 64 layers of alternating materials is required. With the increase in the number of layers, the cost and reliability of (1) multi-layer deposition, (2) anisotropic and high aspect ratio channel and trench etching, and (3) staircase etching for defining the contacts to each layer become the main limiting factors for scaling. Various embodiments provide vertical 3D memory architectures and semiconductor process integration using anisotropic and highly selective etching techniques.

[0107] Various embodiments of the present technology define novel lithography patterns, material stacks, and processing flows that incorporate various interdisciplinary technologies to obtain improvements in memory performance and scalability. The 3D NAND flash processing flow incorporates a semiconductor material stack that enables metal or crystalline silicon gates, angled staircase etching, crystalline silicon channels, and low-k porous dielectrics while reducing the number of lithography and high aspect ratio etching steps. In some embodiments, a wafer-scale multi-scale precision silicon superlattice etching (MSP-SiSE) manufacturing (processing) tool for this purpose is also disclosed. The high selectivity and anisotropy of this etching technology enable a large number of 3D NAND flash layers.

[0108] In the ITRS roadmap for 3D NAND flash, the number of memory layers is steadily increasing from 48 layers in 2016 to 512 in 2030, and is predicted to reach an 80 nm half pitch. This requires significant development of highly anisotropic (-90°) high aspect ratio etching in alternating material layers. Current plasma etching methods involve expensive and time-consuming alternating deposition and etching steps to ensure the maintenance of this anisotropy and selectivity. Non-zero plasma etching taper angles limit the maximum number of layer stacks that can be reliably achieved. Also, non-zero tapers limit the number of layers that can be reliably scaled because the channels etched by plasma etching have a critical dimension that is much smaller than the top layer defined by lithography for the bottom layer. A workaround to overcome this limitation by stacking multiple wafers each with 64 memory layers is inefficient, expensive, and increases the volume of the device. Since plasma etching cannot simultaneously and reliably etch different shapes with aspect ratio dependent etching (ARDE), circular channels and rectangular slits require separate lithography and etching steps. The fabrication (processing) of "stairs" for contacts to individual layers requires multiple lithography and etching steps while attempting to preserve the etching mask. Various embodiments of the present technology aim to solve this by enabling inexpensive high aspect ratio etching with high selectivity and anisotropy that can scale to future requirements for 3D NAND flash.

[0109] Two of the most popular architectures in the industry are BiCS and TCAT. Both architectures use the basic concepts of stack (multi - layer of plates and dielectrics), punch (etching holes through the entire multi - layer stack), and plug (depositing a memory film and a pillar electrode into the etched hole). Next, staircase etching is performed to create contacts to each plate. BiCS uses a silicon oxide / poly - Si stack, while TCAT uses a silicon oxide / silicon nitride stack. In this case, the silicon nitride is later replaced with a material having a low resistivity for conducting wires, such as tungsten. P - BiCS is a variation of BiCS and has better source - gate performance and is lower.

[0110] For both vertical channel and vertical gate architectures, a new material stack and processing flow that can be etched using SiSE have been proposed. The catalyst pattern is defined by lithography so that both circular channels and rectangular slits can be etched simultaneously with high - aspect - ratio anisotropic etching. The material stack is made of alternating layers of bulk Si, or semiconductor materials such as Si and Ge with different dopant types and / or doping concentrations. CICE etching results in layers with different etching rates and oxidation rates for layer - selective processing. This enables an increase in the number of layers and a decrease in the half - pitch, and as a result, the memory capacity per die increases by several times. Also, by combining the lithography step for both channels and slits with the high - aspect - ratio etching step, the cost per wafer is significantly increased. Arbitrary alkali - crystal - face - dependent etching can also be performed on the taper that can be converted into a staircase by plasma etching.

[0111] One embodiment can be used for both charge trap (CT) and floating gate (FG) NAND flash memories. The lower select gate (LSG) can be fabricated (processed) either before or after the deposition of the alternating material stack. The memory material can be either CT or FG. Recesses can be created in the oxide porous layer of 3D FG NAND using timed etching. The deposition of polysilicon and core filler in the channel can be performed either before (last process of the channel) or after (last process of the dielectric) CICE etching. In one embodiment of the gate-last approach, Si and Ge layers can be etched and Ge can be removed before filling with a low-k dielectric. Thus, the final device is a 3D NAND flash memory array with more than 20 alternating layers of conductive (or doped semiconductor) and insulating materials. Here, the vertical gates or vertical channels are very vertical, with an angle exceeding 89.5°. This angle is measured by acquiring a cross-sectional image using a scanning electron microscope (SEM) and then using image analysis software such as ImageJ. The average taper angle is measured using a nearly isometric (conformal) straight line using a linear fitting algorithm between the differences in the feature sizes at the top and bottom of the critical feature. The critical dimension of the vertical gate architecture can be the width of the channel or the width of the trench between channels. In the case of the vertical channel embodiment, the critical dimension is the diameter of the channel or the width of the trench between memory blocks. Since the CICE process has a vertical sidewall angle greater than 89.5°, the center-to-center distance between important features such as circular channels and rectangular slits can be sub-20 nm. The dimensions of important features can be measured using metrology techniques such as SEM, CD-SEM, transmission electron microscope (TEM), atomic force microscope (AFM), etc. The circular channels can be arranged in a hexagonal pattern to create smaller 3D NAND cells.

[0112] Figure 13 shows all the manufacturing (processing) steps for creating a 3D NAND array for vertical channels and vertical gate architectures using SiSE. Since 3D NAND devices require alternating layers of conductive and insulating lines, the SiSE process is designed to obtain alternating layers of materials with different processing parameters such as oxidation rate and etching rate, enabling further processing through layer material replacement or modification. As shown in Table 1, various routes can be taken to obtain alternating layers of conductive and insulating structures. Routes I and II describe the initial substrates required to obtain superlattices. Route I uses a bulk silicon wafer without multilayer deposition, while Route II uses a stack of silicon layers with alternating doping concentrations. Routes A through G can be used in combination with both Routes I and II, i.e., bulk silicon or alternating layers of Si with different doping concentrations. Route A provides options including staircase etching by creating a taper using crystallographic etching or inclined etching. The dashed lines represent some of the options available for this step in the process flow. Routes B through G describe some of the ways to modify or replace the superlattices generated by the SiSE process to obtain the final 3D NAND array. Table 1: Routes I and II for 3D NAND array manufacturing (processing) using SiSE based on Figure 13

[0113]

Table 1

[0114] The main purpose of this alternating stack etching is to create a large difference in etching rate or heat treatment (such as oxidation or nitridation) rate between different layers (layer A and layer B in a two-layer stack), and this difference is used to modify the stack and ultimately obtain an insulating / conductive multilayer structure.

[0115] The porosity of the layer is a function of the etchant concentration, the doping of the silicon substrate, and the current density across the wafer in SiSE. Embodiments of multi-layered porous and non-porous silicon made by SiSE consist of a porous layer having a porosity of from 30% to 75%, while the non-porous layer has a porosity of less than 10%. The porosity is measured by cross-sectional SEM and TEM images and processed using image processing software such as ImageJ. The porosity of a single layer may be measured using gas adsorption experiments such as the use of Brunauer-Emmett-Teller (BET) theory. Here, CICE is performed on a bulk substrate with a patterned catalyst and exposed to a current density to create a thick layer of porous silicon having a porosity parameter corresponding to an alternating set of porous layers.

[0116] Figures 10A through 10E illustrate an example of a catalyst mesh according to one or more embodiments of the present technology. In Figure 10A, isolated catalyst nanodots 1010 and trenches 1020 are shown. In Figure 10B, the catalyst nanodots 1010 and trenches / slits 1020 can be connected by line 1030 (upper figure), or the diameters and alignment of the dots and trenches can be controlled to ensure connection as shown in the lower figure of Figure 10B. In Figure 10C, staggered-connected catalyst nanodots 1010 and trenches / slits 1020 are shown. In Figure 10D, it is shown that connection link 1040 is patterned into a catalyst feature for a BiCS-type layout having sparse word line trenches / slits 1020. In Figure 10E, it is shown that connection link 1040 is patterned into a catalyst mechanism for a P-BiCS-type layout having word line trenches / slits every two columns of channels.

[0117] In other embodiments, features such as holes for VC 3D NAND or lines for VC 3D NAND are etched into the bulk silicon using plasma etching. Next, catalyst-free electrochemical etching is performed on the etched substrate to create alternating layers of silicon with highly porous and low-porous porous layers having sufficient etching or heat treatment selectivity between the layers. This results in a multilayer stack of high aspect ratio features. Here, some of the plurality of layers are oxidized or selectively replaced to create a 3D NAND device.

[0118] Route I - SiSE with Catalyst and Electrochemical Etching A substrate such as a bulk silicon wafer is patterned with a catalyst and etched with a solution containing fluoride species and (optionally) oxidant species. During SiSE processing, electric field parameters such as current density are modulated to create alternating layers with different porosities. In one embodiment, the current density is modulated using a square wave function having one zero and one non-zero value. Thus, the "zero value" current density etching proceeds only with catalyst etching, while the non-zero value creates porosity in the layer using a combination of catalyst etching and electric field etching. Therefore, the resulting superlattice comprises alternating layers of zero and non-zero porosities along with high aspect ratio etched features corresponding to the inverse of the catalyst pattern. In other embodiments, the current density can be modulated using a square wave function having negative and positive values. Thus, the "negative value" current density etching prevents catalyst fluctuations, and the "positive value" current density etching creates porosity in the layer. This route does not require expensive processes such as deposition and etching of multiple alternating layers of materials.

[0119] Route II - SiSE with Catalyst Etching Path II requires alternating layers of semiconductor materials in which at least one of the material type, doping concentration, and dopant material characteristics changes. These layers can be deposited via epitaxy, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., to create superlattices in SiSE. Table 1 shows an example of various combinations of semiconductor alternating multilayers centered on silicon that can be used in the above-described process flow. In Table 1, the doping of silicon donors and acceptors is indicated by p- and n-Si, and "++" indicates the doping concentration. For example, p++Si means highly doped silicon with a boron concentration of 1e18 cm -3 or higher. Two or more alternating layers can be used to more precisely control doping variations and diffusion (e.g., ABCABC). This embodiment uses atomically thin Ge layers between doped Si layers to reduce the movement of dopants during deposition. The main feature of this alternating stack etching is to create a large difference in processing parameters such as etching rate or oxidation rate between different layers (layer A and layer B in a two-layer stack), and this difference is used to modify the stack and ultimately obtain insulating lines / conductor lines.

[0120] As a result of SiSE processing, an etched stack of alternating materials having alternating forms is post-processed by thermal oxidation and / or ALD to obtain the desired stable configuration of the etched channels and slits. FIG. 11 shows an embodiment of a processing flow 1100 for an alternating stack of highly doped and undoped (or lightly doped) silicon. The highly p-doped silicon becomes porous, and this porosity can be controlled based on the etchant concentration and the doping of the silicon layer. The lightly doped silicon does not change its form after etching. Next, the porous silicon can be oxidized at a much faster rate than the non-porous silicon. Next, a thermal step of transferring dopants from the oxidized porous silicon (OPS) and flowing more dopant gas changes the lightly doped silicon into wordlines in the vertical channel regime. By short-time anisotropic oxide etching followed by ALD of a metal, the wordlines become continuous on both sides of the etched channels, and a low-resistivity silicide WL is formed by annealing. This process is referred to as "dielectric / gate first" because the material stack deposited (or epitaxially grown) before SiSE processing ends up in the etched and heat-treated stack.

[0121] Figure 11 shows a processing flow 1100 for high aspect ratio (HAR) etching of channels and slits having a catalyst mesh pattern similar to that shown in Figure 10. The etched stack of alternating materials having an alternating pattern as a result of SiSE processing is post-processed by sacrificial layer removal and atomic layer deposition (ALD) to obtain the desired stable configuration of the etched channels and trenches / slits. As shown in Figure 11, during processing step 110, the deposition of an alternating multi-layer is performed. This step is not necessary if the system starts with a bulk silicon substrate. During processing step 1120, the catalyst mesh is patterned and then SiSE is performed to obtain alternating layers of porous and non-porous materials. During processing step 1130, the oxidation of the porous layer is performed. The oxidation process may also oxidize the thin ends of the non-porous layer that need to be removed. Process step 1140 is used to remove the oxide using anisotropic etching such as atomic layer etching or plasma etching after lithography on the blocks of materials that should not be etched. Processing steps 1150 to 1160 are composed of a plurality of lithography, deposition, and etching processes necessary to create a 3D NAND flash memory array. In some embodiments, processing step 1150 includes the selective deposition of a metal on the non-porous layer followed by silicide formation. Processing step 1160 includes, for example, lithography and deposition of a memory film that is three layers of silicon oxide, silicon nitride, silicon oxide (ONO), poly-Si in charge trap (CT) 3D NAND, and deposition of core filler and low-k dielectrics using ALD and CVD.

[0122] FIG. 12 shows a sacrificial process flow 1200 of vertical channel 3D NAND according to one or more embodiments of the present technology. This process is similar to the process of FIG. 11, but the big difference is the post-treatment step after CICE. Instead of changing one set of alternating layers, they are etched away and then replaced with a conductive material such as tungsten, cobalt, titanium nitride, tantalum nitride, etc. First, CICE is executed on an alternating stack of highly doped and undoped (or lightly doped) silicon during operation 1210. The highly doped silicon becomes porous, and this porosity can be controlled based on the etchant concentration and the doping of the silicon layer. The lightly doped silicon does not change its morphology after etching. That is, it remains crystalline and non-porous. When creating layers with alternating porosities using bulk Si with a time-varying electric field, an alternating stack is not required. Polysilicon and core filler are deposited in the cylindrical channel in operation 1220 and provide support during the sacrificial etching 1230 of one of the alternating layers. The subsequent deposition of a metal (e.g., tungsten, cobalt, titanium nitride, tantalum nitride) using CVD, ALD, or electroplating in step 1240 creates the word line. This process is referred to as "dielectric / gate last". Because the material stack deposited (or epitaxially grown) before the CICE process is partially (one set of alternating layers is replaced with metal) or completely (the second set is etched away and replaced with a low-k dielectric) replaced during process 1240.

[0123] Table 2 shows some examples of layer changes outlined in FIG. 13. An example of a change where one layer is selectively “etched away” is the sacrificial process flow where the gate and / or dielectric film is replaced. This is similar to the TCAT process flow for 3D NAND manufacturing (processing). Some of these embodiments are the processes shown in paths C, D, E, F, G, and in FIG. 12. In such a process flow, when one set of alternating layers is etched away, it is necessary to fill the vertical channels with material to support the structure. The etched stack of alternating materials having an alternating pattern as a result of the SiSE process is post-processed by removal of the sacrificial layer and / or ALD to obtain the desired stable configuration of the etched channels and slits. In one embodiment, high aspect ratio lines are stabilized by removing them after creating lithography links between the lines. Polysilicon and core filler materials are deposited in the cylindrical channels to provide support during the sacrificial etching of one of the alternating layers. Subsequent deposition of metal (e.g., tungsten, cobalt, nickel, tantalum nitride, titanium nitride, copper) creates the word line. This process is referred to as “dielectric / gate last” because the stack of materials deposited (or epitaxially grown) prior to the SiSE process is partially (one set of alternating layers is replaced with metal) or completely (a second set is etched away and replaced with a low-k dielectric). Table 2: Routes B-G for 3D NAND array manufacturing (processing) by changing materials within superlattices made by SiSE, based on FIG. 13

[0124] [Table 2]

[0125] Figures 14 to 16 show a part of the processing flow for processing an alternating layer of a porous silicon layer and a non-porous silicon layer created by SiSE to create a vertical channel 3D NAND array. Figure 14 includes one substitution step and represents path C in Figure 13. Figures 15 to 16 include two substitution steps. Here, Figure 15 represents path D as shown in Figure 13, and Figure 16 represents path G.

[0126] Figure 14 has a plurality of steps including the following: namely, 1) SiSE to create high aspect ratio channels and slits with alternating layers of non-porous and porous Si, 2) oxidation of the porous layer where the thin ends of the non-porous layer and connection links are also oxidized, 3) lithography to block the slits by depositing a material such as a polymer and etching away the material in the peripheral region of the slits, 4) deposition of a film to form a memory core such as an oxide-nitride-oxide layer, polysilicon, and an oxide core using ALD and CVD, 5) material removal from the slits and lithography to protect the channels (selective removal of materials from the slits such as polymers and oxide connection links is performed using selective etching such as oxygen plasma to remove the polymer and atomic layer etching to remove the oxide link), 6) selective removal of the silicon layer using an etchant such as TMAH without affecting the oxidized porous silicon layer, 7) deposition of a conductive material (e.g., W, Co, TiN) using chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or physical vapor deposition (PVD), and subsequent etchback to isolate the conducting wires, and 8) filling the exposed area with an insulating material (not shown in the image).

[0127] FIG. 15 includes the following steps. That is, 1) SiSE that creates high aspect ratio channels and slits with alternating layers of non-porous and porous Si, 2) oxidation of the porous layer where thin ends and connection links of the non-porous layer are also oxidized, 3) lithography that deposits a material such as a polymer and blocks the slit by etching away the material in the peripheral region of the slit, 4) deposition of a film to form a memory core such as an oxide-nitride-oxide layer, polysilicon, and oxide core using ALD and CVD, 5) material removal and lithography from the slit to protect the channel (selective removal of material from the slit such as a polymer or oxidized connection link is performed using selective etching such as oxygen plasma to remove the polymer or atomic layer etching to remove the oxide link), 6) selective removal of the oxide layer using an etching agent such as HF without affecting the silicon layer, 7) deposition of a thin oxide layer using ALD, and deposition of a conductive material (e.g., W, Co, TiN) using chemical vapor deposition, atomic layer deposition, sputtering, etc., and subsequent etch-back to isolate the conducting wire, 8) selective removal of the silicon layer using an etching agent such as TMAH without affecting the deposited conductive material, 9) deposition of an insulating material such as silicon oxide using ALD.

[0128] FIG. 16 includes the following steps. That is, 1) SiSE that creates high aspect ratio channels and slits with alternating layers of non-porous and porous Si, 2) lithography that deposits a material such as a polymer and blocks the slits by etching away the material in the peripheral region of the slits, 3) deposition of a film that forms a memory core such as an oxide-nitride-oxide layer, polysilicon, and an oxide core, etc., 4) material removal and lithography from the slits to protect the channels (selective removal of materials from the slits such as polymers and silicon connection links is performed using selective etching such as oxygen plasma to remove the polymer and atomic layer etching to remove the silicon link), 5) selective removal of the porous silicon layer using an etchant such as HF or HF + H2O2 without affecting the non-porous silicon layer, 6) deposition of a conductive material (e.g., W, Co, TiN) using chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc., and subsequent etch-back to isolate the conducting wires, 7) selective removal of the silicon layer using an etchant such as TMAH without affecting the deposited conductive material, and 8) deposition of an insulating material such as silicon oxide using ALD.

[0129] FIG. 17 shows an embodiment of a 3D NAND architecture with a vertical gate and a horizontal silicon channel. As shown in FIG. 17, which represents path F of FIG. 13, the steps include the following. That is, 1) SiSE that creates high aspect ratio channels and slits with alternating layers of non-porous and porous Si, 2) oxidation of the porous layer where thin ends of the non-porous layer and connection links are also oxidized, 3) deposition of a film to form a memory core such as an oxide-nitride-oxide layer, polysilicon, and an oxide core using CVD, ALD, etc., 4) lithography to create a mask for subsequent etching of the memory material, 5) etching of the memory material from unpatterned regions using atomic layer etching, plasma etching, etc., 6) deposition of a gate material such as W, polysilicon, Co, TiN, etc. (in other embodiments, the gate material can be patterned by removing the lithographed mask, depositing the gate material over the entire structure, performing lithography, and etching away the gate material in unpatterned regions), 7) removal of excess gate material and the lithographed mask using plasma etching or chemical etching, and 8) filling the exposed regions (not shown in the image) with an insulating material such as silicon oxide.

[0130] The non-sacrificial route is similar to the BiCS 3D NAND manufacturing (processing) flow and does not involve etching removal of any layer such as Route B. As a result of the SiSE process, the etched stack of alternating materials with an alternating pattern is post-processed by oxidation (thermal, anodic, etc.) and / or ALD to obtain the desired stable configuration of the etched channels and slits. For example, highly p-doped silicon becomes porous, and this porosity can be controlled based on the etchant concentration, electric field, and doping of the silicon layer. Low-doped silicon does not change its morphology after etching. Next, the porous silicon can be oxidized at a much faster rate than non-porous silicon. Next, a thermal step of transferring dopants from the oxidized porous silicon (OPS) and flowing more dopant gas changes the low-doped silicon to the word line in the vertical channel regime (region). By any short-time anisotropic oxide etching followed by ALD of a metal, the word line becomes continuous on both sides of the etched channel, and a low-resistivity silicide WL is formed by annealing. This process is referred to as "dielectric / gate first" because the material stack deposited (or epitaxially grown) before the SiSE process ends up in the etched and heat-treated stack.

[0131] Note that the superlattices used in various embodiments start with (porous Si / non-porous Si) in Table 2 and can be manufactured (processed) using Route I or II. Also, Route A, which is described as including staircase etching, can be added to the processing flow of any of the multiple routes. Other embodiments of the superlattice are Ge, Si x Ge 1-xIt can include different materials such as GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, etc. and / or alternating layers with different porosities. All layers of the superlattice are also non-porous, and the alternating layers still have different processing rates such as oxidation, chemical etching, etc. As an example, a p-doped Si / n-doped Si superlattice can be mentioned, where an alkaline etching agent such as TMAH or KOH etches only p-type Si under an electric bias. Route B can also be used to create a vertical gate-based 3D NAND flash architecture with a crystalline horizontal silicon channel.

[0132] Various embodiments of the CICE process use a patterned catalyst that sinks into the substrate as etching progresses and leaves unpatterned regions as high aspect ratio features. The catalyst mesh can be patterned to etch both channels and word line slits (trenches) in one lithography step, and in the CICE process, both of these features can be etched simultaneously. Some examples of the catalyst mesh are shown in FIGS. 18A to 18C. To prevent fluctuations in the catalyst mesh and ensure the transport of the etchant solution, an electric field, a ceiling, and / or a linked continuous pattern can be used. The resulting high aspect ratio features can be prevented from collapsing by relaxation techniques such as using surface tension gradient agents (ethanol, isopropyl alcohol, etc.), supercritical drying, and features connected by lithography. These two constraints can also be met by using a patterning technique using features connected by a link or by converting a high aspect ratio linked structure into a desired 3D NAND configuration using controlled deposition or etching after the CICE process.

[0133] The fabrication (processing) of the SiSE catalyst pattern requires multiple lithography and etching steps. For various layout schemes of 3D NAND flash arrays based on both vertical channel (VC) architecture and vertical gate (VG) architecture, the critical dimension and overlay requirements are shown in FIGS. 18A through 18C. FIGS. 18A through 18C show the etched features. As shown in FIGS. 18A through 18C, "a" represents the width of the memory channel block, "b" represents the width of the lithography link, "c" is the distance between blocks of width a, "d" represents the diameter of the circular channel, "e" is the pitch between lateral holes, "f" is the shortest pitch of the holes arranged in a hexagonal pattern, and "g" is the shortest distance between a block of width "a" and the circular channel. The narrow connection lines of width "b" are referred to as lithography links, which connect isolated semiconductor features and then improve the stability of the internally connected high aspect ratio multi-layer semiconductor structure to be etched. The intended design of the catalyst mesh depends on the layout of the 3D NAND flash array, incorporates lithography links to stabilize the etched structure, optionally improves the diffusion of the etchant, and prevents the variation of the catalyst features.

[0134] FIGS. 18A through 18C show the layout and dimensions of an embodiment of a 3D NAND array. Two sets of dimensions are described below. One is the aggressive scaling limited by lithography constraints, and the other is based on assuming a minimum channel diameter of 50 nm for VC-based devices. Since the lithography pattern mainly requires lines and spaces (L / S) and does not require holes or pillars, VC-based devices have the potential for more aggressive scaling, and the L / S can be made smaller by multiple patterning. can be made.

[0135] Some embodiments of the dimensions of the features of FIG. 18 are as follows. FIG. 18A shows a VC 3D NAND configuration with a staggered pattern of two rows of holes per block. When the half pitch is 20 nm (in the X direction), the dots in the Y direction are 25 nm, and the block is 35 nm, a = 60 nm, b = 10 nm, c = 10 nm, d = 25 nm, e = 40 nm, f = 35 nm, and g = 10 nm. When the half pitch is 35 nm (in the X direction), the dots in the Y direction are 42 nm, and the block is 85 nm, a = 110 nm, b = 10 nm, c = 20 nm, d = 50 nm, e = 70 nm, f = 60 nm, and g = 10 nm. FIG. 18B shows a VC 3D NAND configuration with a staggered pattern of four rows of holes per block. When the half pitch is 20 nm (in the X direction), the dots in the Y direction are 25 nm, and the block is 65 nm, a = 120 nm, b = 10 nm, c = 10 nm, d = 25 nm, e = 40 nm, f = 35 nm, and g = 10 nm. When the half pitch is 35 nm (in the X direction), the dots in the Y direction are 42 nm, and the block is 120 nm, a = 220 nm, b = 10 nm, c = 20 nm, d = 50 nm, e = 70 nm, f = 60 nm, and g = 10 nm. FIG. 18C shows a vertical gate 3D NAND shape. Here, the line of width "a" indicates the silicon channel dimension, and in one embodiment, a = 20 nm, b = 10 nm, and c = 20 nm.

[0136] The example of dimensions described in FIG. 18 is limited by the lithography and electronic characteristics required for the memory array. The VC 3D NAND channel holes must be filled with a memory layer such as, for example, oxide-nitride-oxide (ONO) and polysilicon channel materials. The minimum diameter of the poly-Si channel, which is restricted by the string read current and the allowable enhancement of the electric field, is about 20 nm. The minimum ONO thickness, which is restricted by device performance and reliability, is about 15 nm. Thus, the minimum hole diameter is about 50 nm. In a certain process flow, the oxidation step is performed after SiSE, and alternating layers of porous silicon oxide and non-porous silicon are created. In this oxidation step, a thin layer (less than 5 nm) of non-porous silicon at the end can also be oxidized. This thin layer can be retained as a memory layer or removed. When removed, for example, in oxidation and subsequent 5 nm of material removal, the effective dimension of the pattern, i.e., the diameter of the channel, which involves a two-fold change in the dimension of the oxide, increases by 10 nm, the width of the word line decreases by 10 nm, and then the width of the spacing between the lines increases by 10 nm. Therefore, based on the final desired parameters, the initial dimensions should be adjusted as appropriate.

[0137] Electron beam lithography can write sub-10 nm features but has a large overlay, while photolithography has excellent overlay but low resolution, so it is very difficult to manufacture (process) sub-30 nm features with smaller contacts for structural stability. Some embodiments can use photolithography and imprint lithography to pattern the film.

[0138] The design of the 3D NAND features shown in FIGS. 18A to 18C can be patterned using lithography techniques such as photolithography, imprint lithography, electron beam lithography, directed self-assembly, laser interference lithography, etc., which involve multiple patterning. The process of creating masks for these various lithography techniques will be described below.

[0139] (Pattern formation by imprint lithography) FIG. 19D shows the design of a catalyst having a linked structure to prevent wandering and improve diffusion. In one embodiment, the width of the link pattern is 10 nm, the pitch is 25 nm, and the lines are not in a regular arrangement. To fabricate (process) such a pattern, a grid pattern is created using electron beam lithography. Next, using electron beam lithography, the linked structure is patterned, and the elements of the grid are removed by etching away the selected regions of the grid. Next, the resulting pattern can be etched onto a template substrate to create a master template for imprint lithography.

[0140] Imprint lithography can be used to pattern aperiodic irregular patterns with high resolution and a narrow pitch. In the case of imprint lithography, a template can be made to print the catalyst patterns shown in FIGS. 18A to 18C. The fabrication (processing) of the template is shown in FIGS. 19A to 19C. The master templates 1910 and 1920 shown in FIGS. 19A and 19B can be made using electron beam lithography. In one embodiment, the features in FIG. 19A can be made using two sets of L / S perpendicular to each other, creating 20 nm × 20 nm blocks with a pitch of 100 nm, and the features in FIG. 19B can be made using holes with a diameter of 20 nm and a pitch of 40 nm and lines of 20 nm with a pitch of 80 nm.

[0141] The final master template 1930 shown in FIG. 19C can be made by imprinting with the master template 1910 shown in FIG. 19A. The imprinted features are etched into the hard mask, and then the master template 1920 shown in FIG. 19 can be patterned after being aligned with the features imprinted by the master template 19A. According to various embodiments, the alignment of the templates can be performed using an alignment method. Here, within the lithography field, the template 1920 shown in FIG. 19 has features that are intentionally offset by varying the direction and size from one sub-field to the next. After imprinting, sub-fields with ideal alignment requirements are selected and used to create the final master template 1930 shown in FIG. 19C using a step-and-repeat method. Based on the overlay alignment requirements, the final master template 1930 shown in FIG. 19C can also be made using photolithography. In this case, the second template 1920 shown in FIG. 19B is a photolithography mask with larger dimensions to account for the resolution of photolithography. These larger dimensions can then be reduced using plasma etching techniques. FIG. 19D is an example of a lithographically linked pattern where the lines are made by imprint lithography (the template of which is fabricated by electron beam lithography) and the dots are aligned and printed using imprinting or photolithography, or vice versa.

[0142] In other embodiments, the fabrication (processing) of a pattern such as that in FIG. 19D is performed using photolithography and multiple patterning. Next, the holes in the selected regions are patterned and reduced, and the grid elements are removed by etching away the grid lines, thereby creating a link pattern. Due to the limitations of the minimum pitch of photolithography, the patterning of the holes may involve multiple steps.

[0143] The current method of photolithography is at a wavelength of 193 nm with immersion, but uses a three-layer resist and is limited to a half-pitch of about 38 nm for lines and spaces. Methods such as self-aligned double (SADP) / quadruple (SAQP) patterning and LELE (Litho-Etch-Litho-Etch) are required to make the dimensions smaller and the pitch narrower. This requires multiple deposition and etching steps and is inherently suitable for periodic patterns. However, the minimum resolution and pitch of circles are large. In a VG 3D NAND architecture without circles, photolithography and trim etching can be used to create lines and spaces perpendicular to each other. The process of creating the pattern of VG 3D NAND is more complex.

[0144] Figures 20a through 20j show a method of creating such a pattern using photolithography. In FIG. 20, a catalyst is deposited after the photolithography process, and the exposed area (silicon) is currently covered with the catalyst material. The catalyst deposited on the patterned feature can optionally be lifted off. Other embodiments can be used where photolithography is performed on the catalyst film and then the catalyst is etched away in the exposed areas. In that case, the pattern is the reverse of that shown in FIG. 18.

[0145] Figures 20a through 20e show both a cross-sectional view (top surface) and a top view of a lithography step. Figures 20f through 20j show only the top view. In Figure 20a, a lithography link is made using a square with a side of 40 nm and a pitch of 80 nm (y direction) and 40 nm (x direction) patterned with polysilicon (pink) on a first hard mask, silicon nitride (blue) layer. In Figure 20b, trim etching is performed to obtain a square with a side of 10 nm. In Figure 20c, the features are planarized with spin-on glass, and lines with a width of 40 nm and a pitch of 80 nm are aligned and patterned. In Figure 20d, a spacer material is deposited to increase the line width to 70 nm. In Figure 20e, the lines and squares are etched into a hard mask layer such as silicon nitride. In Figure 20f, LELE is performed. That is, holes of 50 nm are aligned and patterned with a pitch (x direction) of 80 nm and a pitch (y direction) of 80 nm, and the diameter is reduced to 25 nm by trim etching and etched into the underlying silicon nitride. In Figures 20g, 20h, and 20i, step 20F is repeated with a shifted alignment. In Figure 20j, a catalyst material can be deposited.

[0146] Instead of multiple LELE steps in photolithography, direct self-assembly can be used to achieve density doubling. FIG. 21 shows a process flow for creating a catalyst pattern having substantially connected catalyst features using self-assembly and lithography. In FIG. 21a, dots are patterned using photolithography. In FIG. 21b, these dots are used to orient block copolymers to double the density using directed self-assembly. Next, lines are patterned to block regions according to the design of the 3D NAND flash catalyst (FIG. 21c). Subsequent etching transfers the dots not blocked by the lines to a hard mask such as silicon nitride or carbon (FIG. 21d). Other lithography steps are performed to pattern the lines (FIG. 21e), and the hard mask is etched (FIG. 21f). Next, the resist is removed to expose the final features of the hard mask (FIG. 21g). In FIG. 21h, a catalyst material is deposited. This process does not show lithography links but can be incorporated into a process flow similar to that of FIG. 20. Also, an imprint lithography template can be created using patterning with self-assembly.

[0147] In the design of 3D NAND flash, simultaneous etching of circular channels and rectangular slits cannot be reliably achieved with plasma etching that precisely controls sidewalls. Similarly, for features with connection links, sub-10 nm connections between pillars cannot be maintained at high aspect ratios. The dry plasma etching processes used in the semiconductor industry for anisotropically etching highly controlled nanopatterns require expensive vacuum equipment and cannot easily maintain cross-sectional shapes when patterning high aspect ratios (>50:1). These are troubled by etching problems such as aspect ratio dependent etching (ARDE) and etching tapers.

[0148] On the one hand, in SiSE processing, necessary patterns can be anisotropically etched and superlattices can be created without losing resolution. However, there are various issues that need to be addressed to make SiSE a viable technology for commercialization. In this section, these issues and solutions for realizing wafer-scale etching of high aspect ratio nanostructure stacks in semiconductor materials are described.

[0149] Define the step-by-step description of various processes that can be used in this new manufacturing (processing) method. Also, in the next section, mention the parameters that need to be optimized at each step for good electrical performance of the final device, mechanical stability at intermediate steps, CMOS compatibility, cost, and throughput.

[0150] In conventional 3D NAND processing, alternating layers of SiO / SiN or SiO / poly-Si are used. These layers are etched and optionally replaced with a conductive material such as W to obtain a stack of alternating conductive and insulating lines that form the word lines and dielectrics of the 3D NAND cells. In various embodiments, alternating layers of semiconductor material may be used instead of SiO / SiN or SiO / poly-Si. Since SiSE can etch semiconductor material while changing its morphology according to adjustable material properties such as doping concentration and dopant type, the alternating layers are designed to ensure selective removal or oxidation to obtain the final conductive and dielectric lines.

[0151] This is not a problem in Route I (see, for example, FIG. 13) where a bulk silicon substrate is used for SiSE and there is no need to consider the deposition of alternating layers.

[0152] The method adopted for the deposition of the interaction layer or "superlattice" depends on commercial availability, cost, throughput, growth rate, thermal budget, number of layers, layer thickness, mobility and resistivity of the layers before and after etching, availability of crystallographic etching, etc. For example, the poly-Si layer needs to be thicker than epitaxial silicon in order to overcome the problem of grain boundaries and obtain good conductivity of the etched word line. Since the diffusion of dopants is more in poly-Si than in crystalline Si, the poly-Si layer may require a thin diffusion barrier layer between multiple alternately doped layers to suppress the diffusion of dopants between the layers. In the case of epitaxial silicon, taper etching to create a stepped contact can also be performed on the crystal layer by using alkaline etchants such as KOH, TMAH, and EDP.

[0153] The epitaxial (epi) growth of silicon in current production is based on chemical vapor deposition (CVD), a process in which a thin solid film is synthesized from the gas phase by a chemical reaction. High-temperature epi growth of silicon above 1000 °C provides high throughput, in-situ doping, and prevents contamination. On the other hand, molecular beam epitaxy (MBE) allows for sharp steps in the doping profile but has a very low growth rate. Low-temperature epitaxy using CVD at about 650 to 850 °C provides a compromise for the growth of the silicon superlattices described in Table 1. Temperature, pressure, gas flow rate, substrate preparation, surface treatment, and anti-oxidation are the main parameters that determine the quality of the epi superlattice. The partial pressure of the gas used for doping such as B2H6 or PH3 determines the doping concentration of the epi layer. When the total pressure is low during growth, contamination from the gas of the previous layer is reduced, enabling a better junction. All of these parameters play important roles in epi growth, but as will be further explained below, temperature, dopant concentration, and the thickness of the epi layer are the most important because they determine the outcome of the next processing step. ● Temperature: The temperature of epitaxial growth depends on various factors. The crystallinity of the epitaxial film can be achieved at temperatures in the range of 500 °C or higher. At low temperatures, the diffusion of dopants decreases, and in some embodiments, a steep profile can be obtained, but the growth rate is low. Depending on the type of dopant in silicon and its diffusion rate, in some embodiments, the diffusion rate across the high-dope / low-dope interface can be calculated. ● Dopant concentration: Using simulations of Fick's law with appropriately modified electric field effects, concentration values, gradients, etc., determine what the doping material and concentration of each alternating layer are in order to obtain the required final diffusion profile. This depends on the temperature of the reaction chamber, the thermal budget required for subsequent processing steps, the concentration gradient across the layer, and the presence or absence of defects during epitaxial growth. The diffusion coefficient of common dopants in silicon depends exponentially on temperature (D = D0.exp(-E a / kT)). Slow diffusers (As and Sb) are preferred over fast diffusers (P, B, and In), and the choice of dopant also depends on the solid solubility limit of silicon. ● Layer thickness: Depending on the width of the final word line, the thickness of the conductive layer must be adjusted to minimize resistivity, while the thickness of the dielectric layer must be adjusted to reduce parasitic capacitance and maximize resistivity. When the word line layer is composed of polycrystalline silicon, the increase in resistance due to grain boundaries must be considered.

[0154] Consider an example of a P++ / P superlattice where one layer has a boron concentration of 1E18 and the other layer has a boron concentration of 1E15. For epitaxial growth at 650 °C and a pressure of 10 Pa in an ultra-clean environment, the deposition rate is approximately 100 nm / min. At this temperature, the diffusion constant of B is 7.7E-20 cm 2 / s. In some embodiments, to determine the diffusion profile, it is necessary to know the thickness of each layer and the length of time the wafer is in the chamber, i.e., the number of layers that need to be grown. When the boron concentration is 1E18, the resistivity of the word line is 0.04 ohm-cm. This can be further reduced by incorporating a metal to form a silicide or by annealing after subsequent SiSE processing to transfer all dopants from the oxide porous layer to the crystalline silicon layer. When the layer thickness is 100 nm, the total growth time for 256 layers is approximately 5 hours. Next, the maximum diffusion occurs in the first layer grown, and the diffusion length is given by X j = 2 * sqrt(Dt). This gives a maximum diffusion length of 0.8 nm. Thus, since the diffusion rate is very low at 650 °C, the effect of temperature on the diffusion length is minimal. When using simulations, additional factors such as multi-level concentration gradients and electric fields can be considered. A slow deposition rate such as 100 n / min cannot be justified from a cost perspective. At 1000 °C, the deposition rate is 10 microns / min, and 256 layers can be deposited in less than 3 minutes.

[0155] However, the diffusion constant of boron at this temperature is 1.39E-14 cm 2 / s, and the diffusion length is 31 nm. To find a compromise between these two parameters, in some embodiments, a temperature of 800 °C or near it is chosen where a deposition rate of 1 micron / min is obtained. This takes approximately 30 minutes for the deposition process of 256 layers and 10 minutes for 100 layers. Next, the diffusion length of B is approximately 6 nm in the bottom layer (worst case) for 256 layers and 3 nm for 100 layers. For a layer with a thickness of 100 nm, a sub-5 nm junction is sufficient. However, the junction length described above represents the distance from the interface where the concentration changes by 1 / e. This is not sufficient to create a reliable process. Therefore, the SiSE process is adjusted so that the dopant concentration steepens reliably as the morphology changes from solid to porous. This can be achieved by adjusting the etchant concentration.

[0156] In some embodiments, plasma enhanced ALD can be used to plug the pores of the porous layer. ALD of SiO2 is used to fill the holes and slits etched using SiSE. The substrate is then planarized to enable the next processing steps including lithography and plasma etching. According to various embodiments, lithography can be performed to open channels and prevent film deposition into the slits. Next, a memory layer (such as oxide-nitride-oxide), a poly-Si channel, and a core filler material can be deposited into these channels (vertical holes).

[0157] In the case of an epitaxial growth crystal layer of silicon, an alkaline etchant such as KOH or TMAH can be used to anisotropically etch the <100> crystal plane. This reduces the number of etching and lithography steps required for staircase etching and creates contacts to each word line layer within the vertical channel structure. This alkaline wet etching can be performed on the as-grown (as-grown) epitaxial material stack either before or after CICE. If one of the alternating layers is highly p-doped, TMAH can be used instead of KOH depending on the relative etching rate along the crystal plane and at different dopant concentrations.

[0158] FIG. 22 shows an example of 3D NAND staircase etching according to one or more embodiments of the present technology. After doped / undoped Si epitaxial growth, a taper etching process is performed using an alkaline etchant to create a contact region for the word line. The length of the protrusion in the contact region depends on the thickness of the insulating layer. Other embodiments of this process involve using electrochemical etching to create alternating layers of silicon with different porosities based on the doping of individual layers without using CICE. This stack is then etched with plasma etching and tilted etched before electrochemical etching to create the staircase.

[0159] FIG. 23 is similar to FIG. 22, but the main difference is that the tapered etching is performed on bulk Si instead of the alternating semiconductor layers. Next, SiSE is performed on the tapered etched bulk Si, and then after the manufacturing (processing) steps of the 3D NAND memory, selective plasma etching is performed to expose the contact regions on the conducting wires.

[0160] In path I, the bulk silicon is etched, and in path II, the epitaxial growth crystal layer of silicon is etched. To create a taper, crystallographic etchants such as KOH, EDP, TMAH, etc. can be used. For example, 30% KOH or 10% TMAH can be used at a temperature of 60°C.

[0161] Some embodiments use a process of stepped etching or inclined plasma etching on bulk silicon using an alkaline etchant to create the contact regions of the word lines. Since the crystallographic etching creates a taper of 54.74°, the length of the protrusion of the contact pad depends on the thickness of the insulating layer. This reduces the number of etching and lithography steps required for the stepped etching and creates contacts to each word line layer within the vertical channel structure. However, the taper does not create vertical sidewalls of the steps, which may affect the reliability of the placement of the metal contacts to the word lines. This can be corrected by increasing the thickness of the dielectric layer or the width of the word line according to the area consumed by the step tread feature. Alternatively, inclined plasma etching with a Faraday cage can also be used to create a taper.

[0162] As SiSE progresses, the catalytic mesh etches the semiconductor material stack to expose high aspect ratio features with holes and slits for 3D NAND channels and word line isolation. SiSE can be stopped by using an etch stop layer, timed etching, or by monitoring and controlling electric field parameters. Due to the etching agent composition and electron hole generation during processing, alternating films of different morphologies occur based on those materials and doping concentrations. After SiSE, one of the multiple layers can be selectively removed or modified (e.g., oxidized) to create a 3D NAND layer. The volume change during the oxidation of porous silicon can be suppressed by controlling the porosity and pore density of the porous silicon layer, thereby reducing mechanical stress on the structure. The oxidation rate of the porous layer is much higher than that of single crystal silicon and can be carried out at a lower temperature to enhance selectivity. For example, at 700 °C, the surface and bulk of a porous silicon layer (for individual layers thinner than 1 micron) are oxidized in 3 minutes, while the surface of crystalline silicon is oxidized only 3 nm by dry O2.

[0163] The difference in oxidation rate between the porous silicon layer and the crystalline silicon layer, and the difference in etching rate between the porous oxide and silicon or between the porous silicon and the crystalline silicon must be very high. This is to ensure no undercut and to increase the number of memory layers that can be made in the SiSE process. Table 3 lists etching agents that can be used to selectively remove one layer from a superlattice for various superlattice modifications to obtain a 3D NAND flash array with alternating layers of insulating and conductive films. Surfactants and other such chemicals can be added to the etching agent to improve the etching selectivity from layer A to layer B in all applicable crystal orientations. The etching agent may be in liquid or vapor form. Table 3: List of etching agents that can be used to selectively remove one layer from a superlattice with selectivity

[0164] [Table 3]

[0165] Table 4 shows examples of various combinations of semiconductor alternating multilayers and processing steps necessary to reliably and selectively remove or oxidize one of the alternating layers to obtain the final metal line and dielectric layer. The doping of silicon donors and acceptors is indicated by p- and n-Si, and "++" indicates the doping concentration. For example, p++Si means highly doped silicon with a boron concentration of 1e18 cm -3 or higher. Two or more alternating layers can be used to more precisely control the doping variation (e.g., ABCABC). This embodiment uses an atomically thin Ge layer between doped Si layers to prevent the movement of dopants during epitaxial growth. When the layers grow epitaxially to obtain a crystalline form, step etching can also be performed by selectively etching the <100> plane in the micron scale range using alkaline etchants such as KOH, TMAH, and EDP. The main feature of this alternating stack etching is to create a large difference in the etching rate or oxidation rate between different layers (layer A and layer B in a two-layer stack), and this difference is used to modify the stack to finally obtain an insulating line / conductor. Table 4: Examples of various combinations of semiconductor alternating multilayers and processing steps necessary to reliably and selectively remove or oxidize one of the alternating layers to obtain the final metal line and dielectric layer

[0166] [Table 4]

[0167] Using various embodiments of the present technology, 3D NAND VC may be created without a replacement step, similar to BiCS processing. For example, in some embodiments, a substrate may be provided. Next, alternating layers of a semiconductor material (e.g., doped or undoped Si) may be deposited. Next, lithography and taper etching using a crystallographic anisotropic etchant may be performed. Next, the catalyst can be patterned. For example, some embodiments may use deposition of a discontinuous catalyst - Pt, Pd, Ru, CMP / lift-off of the catalyst, or selective electrodeposition of Pt, Pd, or Ru. Next, SiSE processing is performed, and the catalyst may be removed using wet etching (e.g., aqua regia) or isolated with an insulator. The plurality of layers can be selectively processed (e.g., oxidize the porous layer and connection links), and the plurality of holes are plugged with atomic layer deposition (ALD). Using lithography, the region between word lines can be blocked before depositing a memory material such as oxide-nitride-oxide (ONO) together with a polysilicon core and / or an oxide core filler. Next, the material can be removed from the word line slit, and a low-k dielectric can be deposited in the slit. To create a staircase along the etched taper, the taper can be etched using selective plasma etching for one set of alternating layers.

[0168] In some embodiments, similar to the TCAT process, the process of 3D NAND VC involving oxidation and substitution can be utilized. For example, in some embodiments, a substrate may be provided. Next, alternating layers of semiconductor material (e.g., doped or undoped Si) may be deposited. Next, lithography and taper etching using a crystallographic anisotropic etchant may be performed. Next, the catalyst can be patterned. For example, some embodiments may use deposition of discontinuous catalyst - Pt, Pd, Ru, CMP / lift - off of the catalyst, or selective electrodeposition of Pt, Pd or Ru. Next, SiSE treatment is performed, and the catalyst may be removed using wet etching (e.g., aqua regia) or isolated with an insulator. Multiple layers can be selectively processed (e.g., oxidizing the porous layer and connection links), and multiple holes can be plugged with ALD. The region between word lines can be blocked using lithography, and a stabilizing core (e.g., polysilicon core and oxide core filler) can be deposited.

[0169] Material can be removed from the word line slit. Atomic layer etching is used to remove the thin oxide layer surrounding the porous oxide / crystalline Si structure. The next set of processes for making a 3D NAND flash array may include one substitution step (e.g., selectively etching crystalline Si selective to the porous oxide, sealing the holes with ALD, depositing the memory material ONO, depositing W and etch - back to isolate the word line, etc.), or two substitution steps (e.g., etching the porous oxide selective to crystalline Si, depositing the memory material ONO, depositing W and etch - back to separate the word line, etching Si selective to W, depositing SiO2, etc.) or (e.g., etching the porous oxide selective to crystalline Si, depositing SiO2 and etch - back to isolate, etching crystalline Si selective to the deposited SiO2, depositing the memory material ONO, depositing W and etch - back to isolate the word line, etc.) and so on. Next, a low - k dielectric can be deposited in the slit. To create a staircase along the etched taper, the taper can be etched using selective plasma etching for one set of alternating layers.

[0170] In some embodiments, similar to TCAT processing, the processing of 3D NAND VC with replacement can be utilized. For example, in some embodiments, a substrate may be provided. Next, alternating layers of a semiconductor material (e.g., doped or undoped Si, Si / SiGe, Si / Ge, etc.) may be deposited. Next, lithography and taper etching using a crystallographic anisotropic etchant may be performed. Next, the catalyst can be patterned. For example, some embodiments may use deposition of a discontinuous catalyst - Pt, Pd, Ru, CMP / lift-off of the catalyst, or selective electrodeposition of Pt, Pd, or Ru. Next, SiSE processing is performed, and the catalyst may be removed using wet etching (e.g., aqua regia) or isolated with an insulator. The plurality of holes can be plugged by ALD. The region between word lines can be blocked using lithography, and a stabilization core (e.g., a polysilicon core and an oxide core filler) can be deposited. Material can be removed from the word line slit. The next set of processes for making a 3D NAND flash array may include one replacement step (e.g., etching porous silicon selective to crystalline Si, depositing memory material ONO, depositing W and etching back to isolate the word line, etching Si selective to W, depositing SiO2, etc.), or two replacement steps (e.g., etching porous silicon selective to crystalline Si, oxidizing crystalline Si, depositing memory material ONO, depositing W and etching back to isolate the word line, etc.) or (e.g., etching porous silicon selective to crystalline Si, depositing SiO2 and etching back to isolate, etching crystalline Si selective to SiO2, depositing memory material ONO, depositing W and etching back to isolate the word line, etc.), etc. Next, a low-k dielectric can be deposited in the slit. To create a staircase along the etched taper, the taper can be etched using selective plasma etching for one set of alternating layers.

[0171] In some embodiments, the processing of 3D NAND with vertical gates can be utilized. For example, in some embodiments, a substrate may be provided. Next, alternating layers of semiconductor material (e.g., doped or undoped Si, Si / SiGe, Si / Ge, etc.) may be deposited. Next, lithography and taper etching using a crystallographic anisotropic etchant may be performed. Next, the catalyst can be patterned. For example, some embodiments may use deposition of a discontinuous catalyst - Pt, Pd, Ru, CMP / lift-off of the catalyst, or selective electrodeposition of Pt, Pd, or Ru. Next, SiSE processing is performed, and the catalyst may be removed using wet etching (e.g., aqua regia) or isolated with an insulator. The plurality of layers can be selectively processed (e.g., oxidizing the porous layer and connection links). The plurality of holes can be plugged with ALD. Lithography can be used to block the regions between the layers and an ONO memory material can be deposited. The word line can also be arranged perpendicular to the horizontal channel line. Next, a low-k dielectric can be deposited in the slit between the word lines. To create a staircase along the etched taper, the taper can be etched using selective plasma etching for one set of alternating layers.

[0172] In one embodiment, 3D NAND can be fabricated (processed) by using silicon nanowires as the channel material and then depositing alternating layers of conductive and insulating materials. MSP-CICE and the novel connection link or ceiling-based breakdown mitigation techniques are used to pattern an array of NWs instead of using deep reactive ion etching processes. DRIE uses processes such as Bosch process. In this process, scalloped sidewalls that damage the surface and degrade FET performance are created. The various embodiments of the CICE process proposed herein exhibit significantly less damage and provide smooth sidewalls and a more refined cross-sectional shape, thus demonstrating excellent performance. The high aspect ratio vertical NWs created using CICE can be used in vertical 3D NAND flash memories. This involves the deposition of a memory material containing a high-k dielectric with a high trap density for conformal ALD charge storage on the vertical NWs. Next, a series of conductive materials separated by insulating materials are deposited to form word lines and create NAND strings that result in multilayer ultra-high density 3D NAND flash memories.

[0173] In 2D structures, it is very difficult to scale DRAM capacitors and transistors, so DRAM products are approaching fundamental limits. Current mitigation strategies are to use stacked or trench capacitors to increase the capacitance per cell without compromising the (substrate) area. However, this method has limitations in the high aspect ratio trench etching of trench capacitors and the stability of stacked capacitors. Also, reducing the feature size affects the reliability of planar and recess channel or fin-based DRAM transistors. Certain DRAM cell configurations also use a cell size factor of 5-6F 2 instead of the ideal 4F 2 cell. As the feature size decreases from the current 20 nm half-pitch to sub-10 nm by 2025, it is necessary to self-alignedly incorporate vertical cell access transistors with high aspect ratio capacitors.

[0174] FIG. 24 shows an exemplary DRAM design in which transistors, capacitors, and wiring materials are deposited on a nanowire etched by CICE according to one or more embodiments of the present technology. The upper part of FIG. 24 shows a cross-sectional view of the capacitor region. The bit lines run perpendicular to the drawing and connect the upper N+ doped silicon regions. Various embodiments are 4F 2 A vertical nanowire-based DRAM architecture incorporating both gate-all-around transistors and self-aligned capacitors is used to generate a cell size factor. This allows the DRAM to be scaled to a sub-10 nm half-pitch. Since the vertical sidewall angle is greater than 89.5° in the CICE process, the center-to-center distance between the pillars can be made sub-20 nm, sub-15 nm, sub-10 nm, etc. By arranging the pillars in a hexagonal pattern, smaller DRAM cells can be created. The etched pillars can be aligned perpendicular to the substrate or at an angle based on the CICE etchant concentration. The cross-section of the pillars can be optimized to give the maximum surface area depending on whether they can be fabricated (processed) by conventional photolithography and nanoimprint lithography with an acceptable defect level.

[0175] To isolate the nanowires of each DRAM cell, an SOI (silicon-on-insulator) substrate can be used. In this case, the insulator functions as an etching stop for CICE and isolates the individual nanowires. Alternatively, the base of the nanowire can be made porous using an electric field. Next, selective oxidation of the porous base can be performed to electrically insulate the nanowires.

[0176] Figures 25A through 25B show two processing flows of CICE wet anisotropic etching for creating high aspect ratio pillars without collapsing, according to one or more embodiments of the present technology. Figure 25A shows a method of preventing collapse using a ceiling to extend the maximum aspect ratio used. The collapse prevention using a ceiling can be performed by etching the feature to a short and stable height using plasma etching or SiSE, depositing the ceiling, and continuing the SiSE process. The "ceiling" may be at a height along the length of a short pillar such as L / 2, where L is the height of the short and stable pillar. Thereby, as the feature is further etched, additional support is provided, and the maximum aspect ratio becomes larger than the aspect ratio of the ceiling at the top of the short pillar. This imparts structural stability to the high aspect ratio pillar and prevents collapse. The ceiling can be deposited by methods such as inclined electron beam evaporation, filling with a polymer, etch-back and deposition of the ceiling, or spin coating. Materials that can be used for the ceiling include metals and oxides that do not react with CICE etching agents such as polymers, sputtered / deposited semiconductors, Cr, Cr2O3, carbon, silicon, Al2O3, etc. In some embodiments, the ceiling can also be made porous by a further low-resolution lithography step or by a reaction that induces porosity in the ceiling material. For example, the ceiling material can be amorphous or poly-Si that becomes porous in CICE. Once the substrate is etched and the catalyst is removed, a memory film or dielectric filler can be deposited by a method such as atomic layer deposition before removing the porous ceiling. The ceiling material can be adjusted to be removed in a certain region or to be non-selective with respect to atomic layer deposition (ALD) to prevent multiple holes from closing and blocking the deposition path. After filling the feature, the ceiling is etched or polished. Also, ALD can be used to close the high aspect ratio shape after etching to create deep holes (e.g., structural voids, openings, etc. defined by a lithography pattern) without using isolated catalysts.

[0177] Figure 25B shows a link-based method that ensures the stability of an etched nanostructure with a diamond-shaped cross-section. When the catalyst mesh comprises both lithographic links and gaps, the linked structure is created by etching. Figure 26 shows SEM images depicting the collapse of unsupported features vs supported features after CICE on silicon, according to one or more embodiments of the present technology. Electron beam lithography can write sub-10nm features but has a large overlay, while photolithography has an excellent overlay but low resolution, making it very difficult to fabricate (process) sub-30nm features with even smaller link contacts. Photolithography and imprint lithography (whose masks and templates are fabricated by electron beam lithography) may be used to obtain a linked final structure that will later serve as a nanoimprint template.

[0178] In an alternative embodiment, holes can be etched by CICE to create trench capacitor DRAM cells. This architecture has a 4F to minimize the area occupied by the DRAM cells. 2It can also be designed as a layout. In the CICE process, since the vertical sidewall angle is greater than 89.5°, the center-to-center distance between holes can be made sub-20 nm, sub-15 nm, sub-10 nm, etc. By arranging the holes in a hexagonal shape, smaller DRAM cells can be created. To enhance the diffusion of the etching agent within the holes, an electric field can be used to create one or more porous layers along the length of the etched holes, excluding the upper region. A silicon transistor for a DRAM cell can be created using a non-porous upper region. One or more porous layers can be selectively oxidized to electrically isolate the trench capacitor. The holes created in the porous layer can be plugged after the CICE process using atomic layer deposition of insulating materials such as SiO2, SiN, SiON, etc. The trench capacitor can be created within a high aspect ratio hole by depositing capacitor materials such as electrodes (poly-Si, W, TiN, Co, TaN) and high-k dielectrics (HfO2, ZrO2, Al2O3) to form a capacitor with a MOS (metal-oxide-semiconductor), MIM (metal-insulator-metal), or MIMIM configuration, etc.

[0179] (Transistor) In the semiconductor industry, typically, CMOS scaling is adopted to improve chip performance, reduce power consumption, and enhance functionality by increasing transistor density. This scaling is done by releasing new technology nodes every 18 months or two years. Transistor density increases by reducing the dimensions of the transistor, such as the gate length, the thickness of the gate oxide, the thickness of the spacer, etc. With the reduction in feature size, new technologies such as high-k dielectrics, metal gates, strain engineering, low-k spacer dielectrics, etc. have been adopted in planar or recess transistors. However, 3D scaling in the form of FinFETs has been introduced to improve electrostatic characteristics despite reducing the area per transistor. Since the dimensions have decreased to sub-20 nm, it has been difficult to create tall, thin fins with minimal sidewall damage and no collapse. At the sub-10 nm node, innovative methods using horizontal nanosheets and nanowires to improve electrostatic characteristics have been proposed.

[0180] However, for all of these 3D geometries, the combination of structural stability and manufacturing (processing) challenges limits the technological potential. As the fins become taller and / or the number of stacked nanosheets and nanowires increases, the chip performance improves and scaling of many technology nodes becomes possible. However, plasma etching for fin manufacturing (processing) suffers from etching tapers and sidewall damage that affect device performance. In CICE, by eliminating the etching taper and reducing the number of fins required per transistor, high aspect ratio fins with less sidewall damage having sub-10nm critical dimensions can be realized. First-level wafer scale manufacturing (processing) of transistors with optimal cross-sections ranging from rectangular fins to circular and shaped NWs incorporates large area control and in-line metrology. The various embodiments include novel etching techniques, catalytically enhanced chemical etching (CICE) and lithography requirements, enabling the fabrication of high aspect ratio fins with vertical sidewalls free of plasma damage.

[0181] CICE is applicable to Si, Ge, Si x Ge 1-xIt is a catalyst-based etching method that can be used for semiconductors such as GaN, InP, GaAs, InAs, GaP, InGas, InGaP, SiC, and multi-layers of semiconductors. The electric field may or may not be used together with the etching catalyst. An etchant (such as hydrofluoric acid HF), an oxidizing agent (such as hydrogen peroxide H2O2), and optionally a low surface tension liquid (such as ethanol) or deionized water can preferentially etch the semiconductor substrate at the position of the catalyst (such as Ag, Au, Pd, Pt, Ru, Cu, W, TiN, TaN, RuO2, IrO2, graphene, etc.). If necessary, a non-aqueous etchant can also be used. Lithography techniques (such as photolithography, electron beam lithography, double patterning, quadruple patterning, nanoimprint lithography, etc.) can be used to define the catalyst features. The obtained substrate with the catalyst mesh is placed in the etchant solution and precisely etched to a certain depth actively controlled by an optical imaging system and an electric field that can determine the etching depth based on the electrical and optical properties during etching.

[0182] Therefore, the final device is a finFET with high aspect ratio fins having an aspect ratio exceeding 5:1. Here, the fin structure is very vertical and the angle exceeds 89.5°. This angle is measured by using a scanning electron microscope (SEM), TEM, AFM, etc., and then using image analysis software such as ImageJ. The average taper angle is measured using a nearly isometric (conformal) straight line using a linear fitting algorithm between the differences in feature sizes at the top and bottom of the critical feature. The critical dimension can be the width of the fin or the width of the trench between the fins. Since the vertical sidewall angle is greater than 89.5° in the CICE process, the center-to-center distance between important features such as fin pitch and fin width can be sub-20 nm, sub-15 nm, sub-10 nm, etc.

[0183] In the case of a lateral nanowire and nanosheet FET, the fin is composed of alternating layers of materials. Here, one of the multiple layers is selectively removed, and a dielectric and a gate electrode are conformally (isometrically) deposited to surround the suspended lateral nanowire or nanosheet. The taper of the nanosheet and the lateral nanowire FET are also measured in the same way as finFETs.

[0184] Plasma etching for fin manufacturing (processing) has various processing challenges such as precise etching, etching taper, collapse, erosion, and structure preservation, and sidewall damage. This affects the device performance of the transistor. With CICE, a high aspect ratio of fins with a critical dimension of sub-10 nm and low sidewall damage can be achieved. The etching taper angle causes further challenges as it limits the maximum height of the fin at a certain fin width. To increase the height of the fin, it is necessary to increase the width of the fin, which reduces the packing density of the transistor.

[0185] Figure 27A shows a 14 nm FinFET with a taper angle of about 85° and a 24 nm physical half-pitch (HP) used in the industry. The maximum fin height achievable at such a taper angle is calculated by maximum fin height = 0.5 × half-pitch × tan(taper angle). By improving the taper angle, the maximum fin height can be increased for different fin widths and half-pitches (HP). This relationship is plotted in Figure 27B, showing the maximum fin height vs etching taper angle that can be etched for a given HP. This indicates the scaling potential of etching processes without taper such as CICE. This does not consider the structural stability of the fin, which will be discussed later. Since a fin height of 100 nm is used for shallow trench isolation (STI), this fin height is not part of the active finFET.

[0186] High aspect ratio fins are prone to collapse. Once the transistor is fabricated and the fin is embedded in a stabilizing material such as an insulator, the collapse of the fin can be mitigated using connection links that can be changed or removed.

[0187] Figure 28 is a plot showing the maximum height of a fin without a taper before it collapses laterally along the fin length (50 nm in this case) without a support / support function. Figure 28 shows the critical height of a fin not supported by a connection link for a length of 50 nm against its half pitch. This is calculated by equating the bending energy of the fin due to collapse to the surface energy required to separate the fins.

[0188]

Number

[0189]

Number

[0190] Here, E is the elastic modulus of the fin, I is the moment of inertia about the bending axis, w is the deflection of the fin, i.e., half the distance between the collapsed fins, γ sv is the surface energy of the fin material, and a and b are the dimensions of the fin perpendicular to the collapse direction (length direction vs width direction).

[0191] The collapse occurs along the fin length at the shortest height, so the height shown in the graph is obtained. The fins can be much longer based on a specific circuit design, but the shortest length of the fin is determined by the contact gate pitch (CGP) of the finFET. The minimum spacer thickness (t s ) is about 5 nm, and the source / drain (S / D) contact length (L c ) is about 15 nm. In this case, the contact gate pitch CGP = L G + 2t s + L c is. This means that the scaling of the transistor changes with the gate length L between 10 and 25 nm GIt shows dependence. The 50 nm case is considered to determine the maximum height of fins with different widths before the fin collapses laterally onto another fin. In some embodiments, since there is no etching taper, the fin pitch can be reduced, so a fin pitch that is twice the fin width is adopted.

[0192] The main limitation of scaling to smaller fin widths is the structural instability. In FinFETs fabricated with bulk silicon, most of its length is utilized for shallow trench isolation (STI). Assuming the minimum height required for STI is 100 nm, only fins with a width of 10 nm or more can be used. Furthermore, the active part of the fin is much shorter than the initial fin height. This can be partially alleviated by using SOI wafers. However, even in the case of SOI finFETs, there is a limit to the maximum height that can be achieved with fins. The etching taper helps to improve the structural stability of the fin to some extent, but as explained in FIG. 27, it ultimately limits the possible maximum height.

[0193] (FinFET Processing Flow) Various embodiments improve the structural stability of fins by using connection links between fins to stabilize the fins during and after etching. After further processing the device, the stabilization structure is removed or modified. In one embodiment, the connection link can also be used at the circuit design stage to link the sources and drains of adjacent finFETs along the epitaxial S / D contact formation. An example of the finFET processing flow is shown in FIG. 29.

[0194] An embodiment of the CICE finFET process flow is shown in FIG. 29, and the process steps are: a) CICE of the connected fins and subsequent removal of the catalyst material, and b) atomic layer deposition (ALD) of the STI material, and etch-back of the STI material using vapor HF, atomic layer etching (ALE) or reactive ion etching (RIE), STI (shallow trench isolation) filling and etch-back, and c) patterning and deposition of dummy gates and spacers, where polysilicon is used as the dummy gate and silicon nitride is used as the spacers on both sides of the dummy gate, and d) filling of the oxide using ALD and planarization using chemical mechanical polishing (CMP), cutting / etching removal of the connection features (or links). Here, the connection features between the fins are etched and removed using RIE, ALE, selective oxide and vapor HF etching, etc., and the lithography mask for etching and removing the connection features can be designed to retain certain connections based on the number of fins per transistor and the transistor circuit design. e) Oxide filling and etch-back, and f) source / drain deposition using in-situ doping with Si and Ge, or epitaxial growth of Si, and g) replacement of the dummy gate with a high-k dielectric and a metal gate between the spacers to form the final high aspect ratio finFET, replacement of the metal gate and deposition of the high-k dielectric.

[0195] In other embodiments, catalyst connection links may be used in the fin regions, and the missing portions can be joined using epitaxial growth of silicon. In the regions where the connection links are removed, materials such as TiN, W, SiO2, SiN, carbon, Si, Ge, etc. may be deposited based on the required electrical properties of the material, e.g., whether the connection needs to be conductive, insulating, or semiconductive, depending on the location and circuit design.

[0196] The high aspect ratio FinFETs fabricated (processed) by CICE have connection links between the fins to prevent collapse. These links must be removed during the fabrication (processing) process (step (d) of FIG. 29) to obtain the required fin design. In one embodiment, the finFET links are removed by the first patterning after CICE, deposition of dummy gates and spacers, and then deposition of dielectric in all exposed regions. Next, photolithography is performed to isolate the regions of the fin links that need to be removed. The fin links are removed using atomic layer etching, plasma etching, etc. The plasma etching taper created during etching does not affect the fin structure protected by the dummy gates and spacers. The subsequent S / D epitaxy step may replenish the fin material lost by the plasma etching taper. Alternatively, selective oxidation and removal of the exposed fin links can be performed, and the oxidized fin links are removed using vapor HF, plasma etching, wet etching, etc. to remove silicon oxide instead of silicon, thereby protecting the silicon fins by the selective nature of silicon oxide etching.

[0197] This method has the advantage that the overlay is very accurate and less than 2 nm, thereby ensuring that excessive material is not removed from the fins. Using spacer patterning, the width and pitch can be reduced from the photolithography resolution of 35 to 40 nm line / space to 20 to 25 nm line / space. Two photolithography steps can be used with the line / space at 90 degrees to each other to create cuts parallel and perpendicular to the fins. EUV lithography can be used to create the same features without further spacer patterning. Based on the finFET design of logic devices, a catalyst pattern for etching the fins and their connection links is designed. For example, in FIG. 32, the starting CICE catalyst pattern and the pattern after removing the connection links are shown.

[0198] Figures 30A through 30E illustrate an example of FinFET processing after CICE according to one or more embodiments of the technology. More specifically, Figures 30A through 30E show top views of connected fin structures, the design of which depends on the use of finFETs such as SRAM and logic circuits. In Figure 30A, the structure etched by CICE is connected to prevent collapse. Figure 30B shows dummy gates and spacer patterns designed to connect multiple fins as required by the circuit design. In Figure 30C, lithography is used to expose the portion to be etched away (connection link). In Figure 30D, the connection link is then etched away using atomic layer etching or plasma etching. Next, further FinFET processing steps such as source / drain epitaxial deposition and gate replacement (not shown in Figures 30A through 30E) can be performed to obtain the final device circuit. Figure 30E shows a schematic of the fins below part D remaining after all FinFET processing steps.

[0199] A nanosheet FET is created by etching fins comprising alternating layers of semiconductor material and then removing one of the alternating layers, resulting in suspended nanosheets. The nanosheet FET has better electrostatics (electrostatic characteristics) than a finFET due to its gate-all-around configuration, as opposed to the tri-gate structure of a finFET. Similar to the fin height limitation described in the previous section, the critical height of the alternating semiconductor layers within the nanosheet fin limits the number of layers that can be etched using plasma etching. This limitation does not exist in SiSE processing, which is a subset of CICE that produces nanostructures with alternating layers instead of bulk Si. Embodiments of the nanosheet layer are composed of Si and Si x Ge 1-x where the new critical height depends on the changed elastic modulus of the multi-layer stacked fins. Assuming that the thickness of each nanosheet is 5 nm and the lower region of the fin covered by STI is Si, the effective elastic modulus can be calculated using the "slab" model with the inverse rule of mixtures of composite materials.

[0200]

Number

[0201] Here, E is the elastic modulus, V is the volume fraction, and the subscript f represents, for example, a sacrificial nanosheet material such as Si x Ge 1-x or a sacrificial nanosheet material such as porous Si, and m is the remaining nanosheet material such as Si, etc.

[0202] When the volume fraction of Si is about 75% to 95%, the resulting effective elastic modulus is about 100 to 150 GPa, and the critical height of the nanosheet fin is similar to the critical height of the finFET fin. The change in surface energy depends on the material of the surface on top of the contacting fins. In one embodiment, the material is silicon, and the influence of the nanosheet material is the same as that of a silicon finFET.

[0203] Alternatively, by reducing the width of the fin, a lateral nanowire FET can be fabricated in a similar manner. In the SiSE process, the connected fins formed in the finFET using lithography links can also be used on a stack of alternating layers of semiconductors.

[0204] The nanosheet FET is similar to a finFET having fins with alternating layers of materials instead of bulk silicon. One embodiment includes alternating layers of Si and Si x Ge 1-x and the Si x Ge 1-x layers are removed to give silicon nanosheets. Other embodiments consist of alternating layers of Si doped differently, which produce sacrificial porous Si layers and crystalline Si nanosheets. In a further embodiment, a protective layer between the alternating layers is used such that the silicon nanosheets are formed from low-doped Si / Si x Ge 1-x / high-doped Si / Si x Ge 1-xBy using an alternating stack of, for example, low-doped Si / Ge / high-doped Si / Ge, it is ensured that the sacrificial nanosheet etching has no effect. Here, the high-doped Si is converted into porous Si, while the low-doped Si remains crystalline. The SiSE process is adjusted such that the morphology surely changes from porous to non-porous at a specific doping concentration, creating a multi-layer stack of porous and non-porous Si. The porous Si can be selectively removed to obtain suspended nanosheets of Si. Due to the etching agent composition and hole generation during the process, alternating films with different morphologies are produced based on their materials and doping concentrations. In other embodiments, the SiSE process is used with a time-varying electric field on bulk Si to create nanosheet fins with alternating layers of porous and non-porous Si. A typical process flow is described in FIG. 31. FIG. 31 shows an example of a process flow for fabricating a nanosheet FET and a lateral nanowire FET with SiSE according to one or more embodiments of the present technology. The steps are: a) removal of the SiSE and catalyst material of the connected fins, b) dielectric filling for creating STI (shallow trench isolation) using atomic layer deposition (ALD), and c) cutting / etching removal of the connecting features. Here, the connecting features between the fins are etched away using RIE or ALE, and the lithography mask for etching away the connecting features can be designed to retain certain connections based on the number of fins per transistor and the transistor circuit design. d) Deposition of a stress liner such as silicon nitride in the cut-out region using ALD, e) dielectric (STI) etch-back and selective removal of the alternating layers to obtain suspended nanosheets / nanowires, and f) patterning and deposition of dummy gates and spacers. Here, polysilicon is used as the dummy gate and silicon nitride is used as the spacers on both sides of the dummy gate. Spacers can be deposited around the dummy gate, and the excess spacer material can be patterned / etched, and oxide filling and planarization can be performed. g) S / D deposition where source and drain regions are deposited using in-situ doping with Si and Ge, or epitaxial growth of Si, and h) replacement of the metal gate and deposition of a high-k dielectric.

[0205] In other embodiments of the SiSE of the nanosheet FET, by using a time-varying electric field together with catalyst etching and using bulk Si instead of the alternating epitaxial layers of materials as the starting substrate, an alternating layer of porous Si and non-porous Si can be created.

[0206] The selective removal of the alternating layers of the nanosheets is performed using a selective etching process. For example, in a stack of Si / Si x Ge 1-x HCl is used to remove Si x Ge 1-xIt may be selectively removed. In the stack of Si / porous Si, etching agents such as HF, TMAH, vapor HF, and HF, and weak oxidants such as hydrogen peroxide can be used. For low-doped Si / Si x Ge 1-x / high-doped (porous after CICE) Si / Si x Ge 1-x In stacks of multiple alternating materials such as, porous Si can be removed using HF, and then Si x Ge 1-x can be removed.

[0207] The catalyst is designed to prevent collapse such that all fins are connected using lithography links. To further prevent catalyst fluctuations when SiSE and / or an electric field cannot be used to suppress fluctuations, while ensuring that all fins are connected to prevent collapse, a connection link is made with a lithography link that connects all catalyst regions.

[0208] The critical height of the fin before collapse can be increased by using connection links at the ends of the fins near the S / D region. These links can be removed after stabilizing the fins with the gate, spacers, and insulator. Figure 32 plots the critical height before lateral collapse for different numbers of fins along the length and width of the fin structure. For a 50 nm contact gate pitch (CGP), 10 nm wide connection links are used on both sides of the fin to improve stability. As shown in Figure 32, the maximum height of the fins when all fins are interconnected in a square mesh can be simulated as a thin and long plate with three fixed faces.

[0209] Figure 32A is a diagram of the connection link when the number of fins is greater than 1. When N = 1, the length b is equal to the CGP of the finFET, but when N > 1, the length b = CGP + 2 *(link width). In FIG. 32B, the critical height before collapse along the length of the connected fin structure is shown for different fin widths f and numbers of fins in the range from 1 to 10. In FIG. 32C, the critical height before collapse along the width of the connected fin structure is shown for different fin widths f and numbers of fins in the range from 1 to 10. To prevent catalyst wobbling in larger blocks of connected fins, a linked mesh as shown below can be utilized for a 6×4 fin block. Multiple blocks can be completely separated or connected via semiconductor links. FIG. 32D is a plot showing the critical height before collapse along the width of the connected fin structure for different fin widths f and numbers of fins in the range from 1 to 10.

[0210] One of the important steps for creating a device from connected fins etched using CICE is a dielectric etch-back to create a shallow trench isolation (STI) region at the base of the fins. This step is necessary for all embodiments of this process other than those using a silicon-on-insulator (SOI) wafer. Dielectrics such as SiOx can be deposited on high aspect ratio fins with a width of less than 15 nm using a conformal deposition method such as atomic layer deposition. The timed etch-back of the dielectric ideally creates an STI with a thickness of approximately 100 nm at the base of the fins without affecting the fins themselves. Usually, plasma etching is used for this process. However, the physical elements of the plasma etching process can potentially damage the fins. Using vapor HF in a pure chemical process can etch back the dielectric without damaging the fins. In one embodiment, a separate material (such as silicon nitride) can be deposited around the fins using ALD before the oxide dielectric deposition. This creates an etch stop on the fins and prevents damage in selective chemical etching.

[0211] It is necessary to control the uniformity of such etch-back processing from the center to the edge of the wafer. This can be performed using multiple temperature zones in a vapor HF setup. A "pilot" wafer can be used to optimize the timed etching and map various regions with discontinuities in the etching rate and depth. The discontinuities can be smoothed by creating local high and low temperature zones to change the local etching rate and create a uniform etching depth.

[0212] Alternatively, the silicon-containing polymer can be precisely dispensed using an inkjet at locations with a high etching rate, such as the edge of the wafer. The amount to be dispensed can be determined using data from the pilot wafer. Next, the substrate is baked at an optimized temperature, and a material with an intentionally non-uniform height is created on the substrate. This cancels out the non-uniform etching by vapor HF, thus ensuring that the final etching uniformity for creating STI in the fins remains within the specification range.

[0213] In other embodiments, the bulk Si fins of finFETs and the nanosheet fins of nanosheet FETs can be electrically isolated from each other by creating a porous bottom layer during SiSE processing using an electric field, etching agent concentration, and / or doping concentration of the layer to be etched such that the layer becomes porous after etching. The porous bottom layer can be 100 nm thick. Next, the porous layer is selectively oxidized to create oxidized porous Si at the bottom of the fins. Thereby, the oxidized porous Si functions as shallow trench isolation (STI) and electrically isolates the fins. In the case of nanosheet FETs, the alternating porous layers may also be oxidized when the porous bottom layer is oxidized.

[0214] Various embodiments of the present technology provide techniques for manufacturing FinFETs. For example, in some embodiments, the catalyst can be patterned by using lithography to deposit a discontinuous catalyst such as Pt, Pd, Ru, Au, etc., and performing chemical mechanical polishing or lift-off. Alternatively, selective electrodeposition of the catalyst can be performed after lithography. After SiSE treatment, the catalyst material can be removed using wet etching (e.g., aqua regia) or isolated from the device layer using an insulator. To create the STI layer, the insulator can be deposited and planarized. Next, lithography and etching of the excess fin connection structure can be performed. Next, lithography and deposition of the stress liner material can be performed. Optionally, an etch-back can be performed to obtain shallow trench isolation (STI) using a method such as timed vapor HF etching. In the case of a nanosheet transistor, alternating layers are selectively removed to obtain suspended nanosheets. For example, some embodiments may etch Si x Ge 1-x that is selective to Si and / or porous Si that is selective to Si. Next, the dummy gate can be patterned. For example, in some embodiments, lithography of the dummy gate pattern can be performed and a dummy gate material (oxide, polysilicon) can be deposited. Spacers can be deposited around the dummy gate and the excess spacer material can be patterned / etched. Oxide filling and etch-back may be performed. In some embodiments, lithography can be used to expose the S / D regions. Next, S / D deposition (e.g., doped epitaxial growth) may be performed. The polysilicon dummy gate can be etched away and replaced with a high-k dielectric and a metal gate. Next, an insulator such as silicon oxide can be deposited and planarized to complete the manufacture (processing) of the transistor layer. Thereafter, further processing is performed to create the metal layer contacts, thereby creating a working transistor device and completing the filling and planarization of the oxide of the metal layer.

[0215] (Conclusion) Unless clearly required otherwise in context, throughout the description and claims, terms such as "comprise", "comprising", etc. should be construed in an inclusive sense rather than an exclusive or exhaustive sense. That is, in the sense of "including but not limited to". As used herein, the phrases "connected", "coupled", or variations thereof mean a direct or indirect connection or coupling between two or more elements. The connection or coupling between elements can be physical, logical, or a combination thereof. Further, terms such as "herein", "above", "below", and similar terms, when used in this specification, refer to the specification as a whole and not to a particular part of the specification. Where the context permits, phrases used in the above detailed description in the singular or plural may include the plural or singular, respectively. The term "or" in relation to a list of two or more items encompasses all of the following interpretations of the term. That is, any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0216] The above detailed description of the examples of the present technology is not intended to be exhaustive or to limit the present technology to the precise forms disclosed above. Specific examples of the present technology have been described above for illustrative purposes, but as will be recognized by those skilled in the art, various equivalent modifications are possible within the scope of the present technology. For example, although processes or blocks are presented in a given order, in another implementation, routines including steps may be executed in a different order or systems including blocks may be used, and some processes or blocks may be deleted, moved, added, re-divided, combined, and / or modified to provide alternatives or partial combinations. Each of these processes or blocks can be implemented in various ways. Also, although processes or blocks are sometimes shown as being performed sequentially, these processes or blocks may instead be executed or performed simultaneously or at different times. Further, the specific numerical values described herein are merely examples, and different values or ranges may be employed in alternative implementations.

[0217] The teachings of the technology provided in this specification can be applied not necessarily to the systems described above, but to other systems. By combining the elements and operations of the various examples described above, further implementations of the technology can be provided. Some alternative implementations of the technology may include not only more elements but also fewer elements than those of the implementations described above.

[0218] In light of the detailed description above, these and other changes can be made to the technology. The above description illustrates certain examples of the technology and the contemplated best mode, but however detailed the above may appear in text, the technology can be practiced in many ways. Details of the system, while included in the technology disclosed herein, may vary considerably in a particular implementation. As noted above, specific terms used when describing a particular feature or aspect of the technology should not be construed as suggesting that the terms are redefined herein to be limited to a particular feature, characteristic, or aspect in the relevant art. In general, unless such language is clearly defined in the section of the detailed description above, the language used in the claims should not be construed as limiting the technology to the specific examples disclosed in the specification. Accordingly, the actual scope of the technology encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology based on the claims.

[0219] To reduce the number of claims, certain aspects of the present technology are presented below in certain claim forms, but the applicant contemplates various aspects of the present technology in any number of claim forms. For example, only one aspect of the present technology is described as a claim for a computer-readable medium, but other aspects may likewise be embodied as claims for a computer-readable medium or in other forms such as embodied in means-plus-function claims. Claims intended to be treated under 35 U.S.C. § 112(f) begin with the phrase "means for", but the use of the phrase "for" in other contexts is not intended to be treated under the provisions of 35 U.S.C. § 112(f). Accordingly, the applicant reserves the right to pursue such additional claim forms in any subsequent application, whether this application or a continuing application, in order to pursue such additional claim forms after the filing of this application.

Claims

1. 1. An apparatus for catalytically accelerated chemical etching, comprising: a processing chamber for storing a semiconductor wafer including a catalyst on at least one surface thereof and an etchant, the etchant being a gas phase etchant; a plurality of actuators configured to control a plurality of environmental characteristics within the processing chamber; An apparatus comprising:

2. The plurality of environmental characteristics include temperature, vapor pressure, electric field, etchant concentration, etchant composition, and lighting.

2. The apparatus of claim 1.

3. The etching apparatus further includes a plurality of sensors for detecting an etching state.

2. The apparatus of claim 1.

4. The etching conditions include one or more of an etch depth, a material porosity, a number of alternating layers etched, an electrical conductivity of a doped semiconductor material in contact with an etchant, an optical property of a plurality of features, and an electrical property of a plurality of features measured during and / or after the etching process.

4. The apparatus of claim 3.

5. Further comprising a lead wafer being processed through the equipment, and an off-line weighing system for sensing the etching status of the lead wafer.

2. The apparatus of claim 1.

6. The offline metrology estimates process excursions noted on the previous wafer.

6. The apparatus of claim 5.

7. and a drying mechanism configured to prevent collapse of the plurality of high aspect ratio semiconductor structures.

2. The apparatus of claim 1.

8. The local and / or global etch depth is monitored using one or more of local electric field measurements based on voltage, current, capacitance, resistance or inductance, optical metrology and imaging using a camera, optical cable or spectrophotometer, and thermal measurements using multiple thermal chucks or multiple micromirrors.

2. The apparatus of claim 1.

9. The optical measurements are performed in the IR wavelength range, allowing monitoring through silicon.

9. The apparatus of claim 8.

10. The local and global etchant concentrations are monitored during catalytically promoted chemical etching using refractive index measurements of the etchant or the etchant conductance.

2. The apparatus of claim 1.

11. The local and / or global enchantment solution concentration is controlled during catalytically accelerated chemical etching using flow control and circulation of etchant, rotation of the substrate, a sprayer to create a uniform enchantment solution concentration, a temperature gradient for spraying of etchant, localized addition of chemicals for spraying of etchant, air jets, or localized addition of depleted components of etchant.

2. The apparatus of claim 1.

12. a thermal chuck for controlling local temperature; a monitor for monitoring the vapor pressure; The apparatus of claim 1 further comprising:

13. The catalyst is Au, Pt, Pd, Ru, Ag, Cu, Ni, W, TiN, TaN, RuO ２ , IrO ２ and graphene 2. The apparatus of claim 1.

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