Oscillation circuit, oscillator, and method for controlling oscillation circuit

Abstract

To provide an oscillation circuit that can reduce the possibility of abnormal oscillation even if there is a variation in the characteristics of an oscillator to be connected thereto.SOLUTION: An oscillation circuit comprises a circuit for oscillation that is connected to an oscillator, and a control circuit that controls the circuit for oscillation. The circuit for oscillation has a normal operation mode for oscillating in a state where a negative resistance value is a first value, and a start-up mode from a state where the circuit for oscillation stops oscillation until a transition to the normal operation mode. The control circuit performs control, in the start-up mode, so as to increase the negative resistance value from a second value smaller than the first value.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to an oscillation circuit, an oscillator, and a method for controlling an oscillation circuit.

Background Art

[0002] Patent Document 1 describes an oscillation circuit in which a control circuit for increasing the load capacitance of the oscillation circuit only at the time of oscillation startup is provided so that the growth factor of the main oscillation at the time of oscillation startup becomes larger than the growth factor of spurious oscillation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the case of a configuration in which the load capacitance is made different between startup and other times as in the oscillation circuit described in Patent Document 1, there is a risk that normal oscillation cannot be ensured due to variations in the characteristics of the oscillator. That is, when an oscillator is used in which neither the main oscillation nor the sub-oscillation such as spurious oscillation resonates at the load capacitance at the time of oscillation startup, and both the main oscillation and the sub-oscillation resonate at the load capacitance during normal operation, there is a risk of abnormal oscillation.

Means for Solving the Problems

[0005] One aspect of the oscillation circuit according to the present invention is an oscillation circuit connected to an oscillator, a control circuit for controlling the oscillation circuit, and includes the oscillation circuit has a normal operation mode in which oscillation occurs with a negative resistance value being a first value, and a startup mode from a state where the oscillation circuit has stopped oscillating until it shifts to the normal operation mode. The control circuit is, In the startup mode, control is performed so that the negative resistance value increases from a second value smaller than the first value.

[0006] One aspect of the oscillator according to the present invention is, One aspect of the oscillation circuit and, The vibrator, and comprises.

[0007] One aspect of the control method of the oscillation circuit according to the present invention is, An oscillation circuit including an oscillation circuit connected to a vibrator, the oscillation circuit having a normal operation mode in which oscillation occurs with a negative resistance value of a first value, and a startup mode from a state where the oscillation circuit has stopped oscillating until it shifts to the normal operation mode. A control method of the oscillation circuit, In the startup mode, control is performed so that the negative resistance value increases from a second value smaller than the first value.

Brief Description of Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Embodiments for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential components of the present invention.

[0010] 1. First Embodiment 1-1. Configuration of Oscillator FIGS. 1, 2, and 3 are diagrams showing an example of the structure of the oscillator 1 of the present embodiment. FIG. 1 is a perspective view of the oscillator 1. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is a bottom view of the oscillator 1.

[0011] As shown in FIGS. 1, 2, and 3, the oscillator 1 includes an oscillation circuit 2, a vibrator 3, a package 4, a lid 5, and a plurality of external terminals 6. In the present embodiment, the vibrator 3 is a crystal oscillator using crystal as a substrate material, and for example, an AT-cut crystal oscillator, a tuning fork type crystal oscillator, or the like. The vibrator 3 may be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) vibrator. Note that SAW is an abbreviation for Surface Acoustic Wave. Also, MEMS is an abbreviation for Micro Electro Mechanical Systems. As the substrate material of the vibrator 3, in addition to crystal, piezoelectric single crystals such as lithium tantalate and lithium niobate, piezoelectric materials such as piezoelectric ceramics such as lead zirconate titanate, or silicon semiconductor materials can be used. As the excitation means of the vibrator 3, those based on the piezoelectric effect may be used, or electrostatic drive based on Coulomb force may be used. Also, in the present embodiment, the oscillation circuit 2 is realized by a one-chip integrated circuit. However, at least a part of the oscillation circuit 2 may be composed of discrete components.

[0012] Package 4 houses the oscillation circuit 2 and the vibrator 3 within the same space. Specifically, Package 4 is provided with a recess, and by covering the recess with the lid 5, a housing chamber 7 is formed. On the inside of Package 4 or on the surface of the recess, there are provided wirings (not shown) for electrically connecting the two terminals of the oscillation circuit 2, specifically, the XI terminal and the XO terminal shown in FIG. 4 described later, and the two exciting electrodes 3a, 3b of the vibrator 3 respectively. Also, on the inside of Package 4 or on the surface of the recess, there are provided wirings (not shown) for electrically connecting each terminal of the oscillation circuit 2 and each external terminal 6 provided on the bottom surface of Package 4. Note that Package 4 is not limited to the configuration of housing the oscillation circuit 2 and the vibrator 3 within the same space. For example, it may be a so-called H-type package in which the oscillation circuit 2 is mounted on one surface of the package substrate and the vibrator 3 is mounted on the other surface.

[0013] The vibrator 3 has metal exciting electrodes 3a, 3b on its front and back surfaces respectively, and oscillates at a desired frequency according to the shape and mass of the vibrator 3 including the exciting electrodes 3a, 3b.

[0014] As shown in FIG. 3, the oscillator 1 of the present embodiment is provided with four external terminals 6 on its bottom surface, specifically, on the back surface of Package 4, which are an external terminal VDD1 as a power supply terminal, an external terminal VSS1 as a ground terminal, an external terminal VC1 as a terminal to which a signal for controlling the frequency of the oscillation circuit 2 is input, and an external terminal OUT1 as an output terminal from which an oscillation signal is output. A power supply voltage is supplied to the external terminal VDD1, and the external terminal VSS1 is grounded.

[0015] FIG. 4 is a functional block diagram of the oscillator 1 according to the first embodiment. As shown in FIG. 4, the oscillator 1 of the present embodiment includes an oscillation circuit 2 and a vibrator 3. The oscillation circuit 2 has, as external connection terminals, a VDD terminal, a VSS terminal, an OUT terminal, a VC terminal, an XI terminal, and an XO terminal. The VDD terminal, the VSS terminal, the OUT terminal, and the VC terminal are electrically connected to the external terminal VDD1, the external terminal VSS1, the external terminal OUT1, and the external terminal VC1, which are the four external terminals 6 of the oscillator 1 shown in FIG. 3, respectively. The XI terminal is electrically connected to the exciting electrode 3a, which is one end of the vibrator 3, and the XO terminal is electrically connected to the exciting electrode 3b, which is the other end of the vibrator 3.

[0016] In the present embodiment, the oscillation circuit 2 includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generation circuit 50, an output circuit 60, and a memory circuit 70. Note that the oscillation circuit 2 may be configured by omitting or changing some of these elements, or adding other elements.

[0017] The power supply circuit 20 generates various voltages including the power supply voltage Vdd of the logic circuit 42 based on the external power supply voltage input from the external terminal VDD1 and supplied through the VDD terminal, and supplies the generated various voltages to each circuit. In addition, a ground voltage Vss is supplied to each circuit through the VSS terminal.

[0018] When power is turned on for the oscillator 1, the power supply voltage Vdd output from the power supply circuit 20 rises from 0 V to a predetermined voltage value. When the power supply voltage Vdd reaches a predetermined threshold voltage, the power-on reset circuit 30 generates a power-on reset signal POR that becomes high level for a certain period of time. The logic circuit 42 is initialized to a desired state by the power-on reset signal POR. When the power-on reset signal POR changes from high level to low level, the logic circuit 42 starts operating.

[0019] The oscillation circuit 10 is connected to the oscillator 3 via the XI terminal and the XO terminal, amplifies the signal output from the oscillator 3 by an amplification element, supplies it to the oscillator 3, and is a circuit that oscillates the oscillator 3. The amplification element may be, for example, a bipolar transistor, a MOS transistor, or a CMOS inverter. MOS is an abbreviation for Metal Oxide Semiconductor. Also, CMOS is an abbreviation for Complementary Metal Oxide Semiconductor. The oscillation circuit 10 is adjusted so that the oscillation frequency becomes the target frequency based on various setting signals supplied from the logic circuit 42.

[0020] The output circuit 60 buffers and outputs the oscillation signal CK output from the oscillation circuit 10. The oscillation signal CKO output from the output circuit 60 is output to the outside of the oscillator 1 via the OUT terminal and the external terminal OUT1. Note that the output circuit 60 may output a differential oscillation signal. That is, the output circuit 60 may output an oscillation signal XCKO whose polarity is inverted with respect to the oscillation signal CKO together with the oscillation signal CKO. In this case, the oscillation circuit 2 further has an XOUT terminal for outputting the oscillation signal XCKO, and the oscillator 1 further has an external terminal XOUT1 for outputting the oscillation signal XCKO.

[0021] The control circuit 40 controls the oscillation circuit 10. In the present embodiment, the control circuit 40 includes a voltage control circuit 41 and a logic circuit 42.

[0022] The voltage control circuit 41 generates a control voltage for changing the oscillation frequency of the oscillation circuit 10 according to the voltage level of the frequency control signal supplied from the external terminal VC1 via the VC terminal, and supplies it to the oscillation circuit 10. That is, the frequency of the oscillation signal CKO output from the external terminal OUT1 changes according to the voltage level of the frequency control signal input from the external terminal VC1.

[0023] The logic circuit 42 outputs an oscillation enable signal en_osc to the oscillation circuit 10 to control the operation of the oscillation circuit 10. Specifically, the logic circuit 42 oscillates the oscillation circuit 10 by setting the oscillation enable signal en_osc to a high level, and stops the oscillation of the oscillation circuit 10 by setting the oscillation enable signal en_osc to a low level. Also, the logic circuit 42 outputs various setting signals to the oscillation circuit 10 to control the oscillation frequency of the oscillation circuit 10. Further, the logic circuit 42 outputs an output enable signal en_out to the output circuit 60 to control the operation of the output circuit 60. Specifically, the logic circuit 42 controls the output circuit 60 to output the oscillation signal CKO by setting the output enable signal en_out to a high level, and controls the output circuit 60 to stop the output of the oscillation signal CKO by setting the output enable signal en_out to a low level.

[0024] The reference voltage generation circuit 50 generates various reference voltages based on the voltage output from the power supply circuit 20 and outputs them to the oscillation circuit 10.

[0025] The memory circuit 70 is a circuit that stores various types of information and includes a non-volatile memory 71 and a register 72. The non-volatile memory 71 may be, for example, a FAMOS, MONOS type memory, EEPROM, etc. Note that FAMOS is an abbreviation for Floating gate Avalanche injection Metal Oxide Semiconductor. Also, MONOS is an abbreviation for Metal Oxide Nitride Oxide Silicon. Further, EEPROM is an abbreviation for Electrically Erasable Programmable Read-Only Memory. In the manufacturing process of the oscillator 1, various types of information are stored in the non-volatile memory 71. Then, when power is supplied to the oscillator 1, the various types of information stored in the non-volatile memory 71 are transferred to the register 72, and the various types of information stored in the register 72 are appropriately supplied to each circuit. For example, the information for adjusting the oscillation frequency transferred from the non-volatile memory 71 to the register 72 is supplied to the oscillation circuit 10 as various setting signals via the logic circuit 42. The information for adjusting the oscillation frequency is current adjustment data and capacitance adjustment data, which will be described later.

[0026] 1-2. Configuration of the Oscillation Circuit FIG. 5 is a diagram showing a configuration example of the oscillation circuit 10. In the example of FIG. 5, the oscillation circuit 10 includes an amplification element 11, a variable current source 12, a resistor 13, variable capacitance circuits 14, 15, 16, and 17. The oscillation circuit 10 also includes ten CMOS inverters 100, 101, 102, 103, 104, 110, 111, 112, 113, 114.

[0027] The amplification element 11 is an NPN bipolar transistor, with its base terminal connected to the XI terminal, its collector terminal connected to the XO terminal, and its emitter terminal grounded. Also, a resistor 13 is connected between the base terminal and the collector terminal of the amplification element 11. An oscillation-stage current Iosc is supplied from the variable current source 12 to the collector terminal of the amplification element 11, and the signal at the collector terminal is output as an oscillation signal CK. Note that a MOS transistor or a CMOS inverter may be used as the amplification element 11.

[0028] The variable current source 12 generates an oscillation-stage current Iosc having a magnitude corresponding to 5-bit current adjustment data trimI[4:0] as a setting signal supplied from the logic circuit 42 based on the voltage Vreg generated by the reference voltage generation circuit 50. Then, the variable current source 12 supplies the oscillation-stage current Iosc to the amplification element 11. Note that the number of bits of the current adjustment data trimI is not limited to 5.

[0029] FIG. 6 is a diagram showing a configuration example of the variable current source 12. In the example of FIG. 6, the variable current source 12 includes six current sources 120, 121, 122, 123, 124, 130, five switch elements 125, 126, 127, 128, 129, and two P-channel MOS transistors 131, 132.

[0030] For the P-channel MOS transistor 131, the gate and the drain are connected, and the voltage Vreg is supplied to the source. For the P-channel MOS transistor 132, the gate is connected to the gate of the P-channel MOS transistor 131, the voltage Vreg is supplied to the source, and the drain is connected to the collector of the amplification element 11 in FIG. 5.

[0031] One end of the current source 130 is connected to the drain of the P-channel MOS transistor 131, and the other end is grounded, and a constant bias current I bflows. One end of the current source 120 is connected to the drain of the P-channel MOS transistor 131 via the switch element 125, and the other end is grounded. When the switch element 125 is in the conducting state, a constant current I0 flows. One end of the current source 121 is connected to the drain of the P-channel MOS transistor 131 via the switch element 126, and the other end is grounded. When the switch element 126 is in the conducting state, a current twice as large as I0 flows. One end of the current source 122 is connected to the drain of the P-channel MOS transistor 131 via the switch element 127, and the other end is grounded. When the switch element 127 is in the conducting state, a current four times as large as I0 flows. One end of the current source 123 is connected to the drain of the P-channel MOS transistor 131 via the switch element 128, and the other end is grounded. When the switch element 128 is in the conducting state, a current eight times as large as I0 flows. One end of the current source 124 is connected to the drain of the P-channel MOS transistor 131 via the switch element 129, and the other end is grounded. When the switch element 129 is in the conducting state, a current sixteen times as large as I0 flows. For example, the current sources 120, 121, 122, 123, 124, and 130 may be configured using depletion-type N-channel MOS transistors or current mirror circuits.

[0032] The switch element 125 has the data trimI[0] of bit 0 of the current adjustment data trimI[4:0] input to its control terminal, conducts when the data trimI[0] is at a high level, and does not conduct when the data trimI[0] is at a low level. The switch element 126 has the data trimI[1] of bit 1 of the current adjustment data trimI[4:0] input to its control terminal, conducts when the data trimI[1] is at a high level, and does not conduct when the data trimI[1] is at a low level. The switch element 127 has the data trimI[2] of bit 2 of the current adjustment data trimI[4:0] input to its control terminal, conducts when the data trimI[2] is at a high level, and does not conduct when the data trimI[2] is at a low level. The switch element 128 has the data trimI[3] of bit 3 of the current adjustment data trimI[4:0] input to its control terminal, conducts when the data trimI[3] is at a high level, and does not conduct when the data trimI[3] is at a low level. The switch element 129 has the data trimI[4] of bit 4 of the current adjustment data trimI[4:0] input to its control terminal, conducts when the data trimI[4] is at a high level, and does not conduct when the data trimI[4] is at a low level. For example, the switch elements 125, 126, 127, 128, and 129 may be N-channel MOS transistors or transmission gates.

[0033] Figure 7 is a diagram showing the relationship between the value of the current adjustment data trimI[4:0] expressed in decimal and the values of each bit of the current adjustment data trimI[4:0] expressed in binary. 0 of each bit corresponds to a low level, and 1 of each bit corresponds to a high level. For example, if the current adjustment data trimI[4:0] is 1, bit 0 is 1 and bits 1, 2, 3, and 4 are 0. Therefore, the switch element 125 conducts and the current I0 flows to the current source 120. Also, for example, if the current adjustment data trimI[4:0] is 2, bit 1 is 1 and bits 0, 2, 3, and 4 are 0. Therefore, the switch element 126 conducts and a current twice as large as the current I0 flows to the current source 121.

[0034] Between the source and drain of the P-channel MOS transistor 131, a current obtained by adding the currents flowing through each of the current sources 120, 121, 122, 123, and 124 to the bias current I b flows. For example, when the current adjustment data trimI[4:0] is 1, a current I0 flows through the current source 120, and the currents flowing through each of the current sources 121, 122, 123, and 124 are zero. Therefore, between the source and drain of the P-channel MOS transistor 131, a current obtained by adding the current I0 to the bias current I b flows. Also, for example, when the current adjustment data trim I[4:0] is 1, a current twice the current I0 flows through the current source 121, and the currents flowing through each of the current sources 120, 122, 123, and 124 are zero. Therefore, between the source and drain of the P-channel MOS transistor 131, a current obtained by adding a current twice the current I0 to the bias current I b flows. Then, by a current mirror circuit composed of two P-channel MOS transistors 131 and 132, a current having a magnitude that is a predetermined multiple of the current flowing between the source and drain of the P-channel MOS transistor 131 flows between the source and drain of the P-channel MOS transistor 132. This current is supplied to the amplifying element 11 as the oscillation stage current Iosc. Therefore, the magnitude of the oscillation stage current Iosc changes according to the value of the current adjustment data trimI[4:0]. Specifically, the larger the value of the current adjustment data trimI[4:0], the larger the oscillation stage current Iosc becomes. In the manufacturing process of the oscillator 1, the value of the current adjustment data trimI[4:0] for setting the oscillation stage current Iosc to a desired value according to the resonance frequency of the vibrator 3 is written into the non-volatile memory 71.

[0035]

[0036] ​Returning to the description of FIG. 5, the CMOS inverter 100 outputs data trimCN1[0] which is the logical inversion of data trimC1[0] of bit 0 of the 5-bit capacitance adjustment data trimC1[4:0] as the setting signal supplied from the logic circuit 42. The CMOS inverter 101 outputs data trimCN1[1] which is the logical inversion of data trimC1[1] of bit 1 of the capacitance adjustment data trimC1[4:0]. The CMOS inverter 102 outputs data trimCN1[2] which is the logical inversion of data trimC1[2] of bit 2 of the capacitance adjustment data trimC1[4:0]. The CMOS inverter 103 outputs data trimCN1[3] which is the logical inversion of data trimC1[3] of bit 3 of the capacitance adjustment data trimC1[4:0]. The CMOS inverter 104 outputs data trimCN1[4] which is the logical inversion of data trimC1[4] of bit 4 of the capacitance adjustment data trimC1[4:0].

[0037] The variable capacitance circuit 14 is a capacitance circuit having a capacitance value C1 of a magnitude corresponding to the capacitance adjustment data trimCN1[4:0] in which each bit of the capacitance adjustment data trimC1[4:0] is logically inverted by the CMOS inverters 100, 101, 102, 103, 104. The variable capacitance circuit 14 includes five capacitance elements 140, 141, 142, 143, 144 and five switch elements 145, 146, 147, 148, 149.

[0038] The capacitance element 140 has one end connected to the XI terminal and the other end grounded via the switch element 145, and its capacitance value is C0. The capacitance element 141 has one end connected to the XI terminal and the other end grounded via the switch element 146, and its capacitance value is twice that of C0. The capacitance element 142 has one end connected to the XI terminal and the other end grounded via the switch element 147, and its capacitance value is four times that of C0. The capacitance element 143 has one end connected to the XI terminal and the other end grounded via the switch element 148, and its capacitance value is eight times that of C0. The capacitance element 144 has one end connected to the XI terminal and the other end grounded via the switch element 149, and its capacitance value is sixteen times that of C0. For example, the capacitance elements 140, 141, 142, 143, and 144 may be MIM-type capacitance elements using metal for the two electrodes, or PIP-type capacitance elements using polysilicon for the two electrodes. MIM is the abbreviation of Metal Insulator Metal. Also, PIP is the abbreviation of Poly Insulator Poly.

[0039] The switch element 145 has the data trimCN1[0] of bit 0 of the capacitance adjustment data trimCN1[4:0] input to its control terminal, conducts when the data trimCN1[0] is at a high level, and does not conduct when the data trimCN1[0] is at a low level. The switch element 146 has the data trimCN1[1] of bit 1 of the capacitance adjustment data trimCN1[4:0] input to its control terminal, conducts when the data trimCN1[1] is at a high level, and does not conduct when the data trimCN1[1] is at a low level. The switch element 147 has the data trimCN1[2] of bit 2 of the capacitance adjustment data trimCN1[4:0] input to its control terminal, conducts when the data trimCN1[2] is at a high level, and does not conduct when the data trimCN1[2] is at a low level. The switch element 148 has the data trimCN1[3] of bit 3 of the capacitance adjustment data trimCN1[4:0] input to its control terminal, conducts when the data trimCN1[3] is at a high level, and does not conduct when the data trimCN1[3] is at a low level. The switch element 149 has the data trimCN1[4] of bit 4 of the capacitance adjustment data trimCN1[4:0] input to its control terminal, conducts when the data trimCN1[4] is at a high level, and does not conduct when the data trimCN1[4] is at a low level. For example, the switch elements 145, 146, 147, 148, and 149 may be N-channel MOS transistors or transmission gates.

[0040] FIG. 8 is a diagram showing the relationship between the value obtained by expressing the capacitance adjustment data trimC1[4:0] in decimal and the values obtained by expressing each bit of the capacitance adjustment data trimCN1[4:0] in which the capacitance adjustment data trimC1[4:0] is logically inverted in binary. 0 of each bit corresponds to the low level, and 1 of each bit corresponds to the high level. For example, if the capacitance adjustment data trimC1[4:0] is 1, bits 1, 2, 3, 4 of the capacitance adjustment data trimCN1[4:0] are 1 and bit 0 is 0. Therefore, the switching elements 146, 147, 148, 149 are turned on and the other ends of the capacitance elements 141, 142, 143, 144 are grounded. Also, for example, if the capacitance adjustment data trimC1[4:0] is 2, bits 0, 2, 3, 4 of the capacitance adjustment data trimCN1[4:0] are 1 and bit 1 is 0. Therefore, the switching elements 145, 147, 148, 149 are turned on and the other ends of the capacitance elements 140, 142, 143, 144 are grounded.

[0041] The capacitance value C1 of the variable capacitance circuit 14 is the value obtained by adding the capacitance values of the capacitance elements 140, 141, 142, 143, 144 whose other ends are grounded when each of the switching elements 145, 146, 147, 148, 149 is turned on. For example, when the capacitance adjustment data trimC1[4:0] is 1, the other ends of the capacitance elements 141, 142, 143, 144 are grounded and the other end of the capacitance element 140 is not grounded, so the capacitance value C1 of the variable capacitance circuit 14 is 2C0 + 4C0 + 8C0 + 16C0 = 30C0. Also, for example, when the capacitance adjustment data trimC1[4 :0] is 2, the other ends of the capacitance elements 140, 142, 143, 144 are grounded and the other end of the capacitance element 141 is not grounded, so the capacitance value C1 of the variable capacitance circuit 14 is C0 + 4C0 + 8C0 + 16C0 = 29C0. Thus, the capacitance value C1 of the variable capacitance circuit 14 varies according to the value of the capacitance adjustment data trimC1[4:0]. Specifically, the larger the value of the capacitance adjustment data trimC1[4:0], the smaller the capacitance value C1 of the variable capacitance circuit 14.

[0042] The CMOS inverter 110 outputs data trimCN2[0] which is the logical inversion of data trimC2[0] of bit 0 of the 5-bit capacitance adjustment data trimC2[4:0] as the setting signal supplied from the logic circuit 42. The CMOS inverter 111 outputs data trimCN2[1] which is the logical inversion of data trimC2[1] of bit 1 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 112 outputs data trimCN2[2] which is the logical inversion of data trimC2[2] of bit 2 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 113 outputs data trimCN2[3] which is the logical inversion of data trimC2[3] of bit 3 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 114 outputs data trimCN2[4] which is the logical inversion of data trimC2[4] of bit 4 of the capacitance adjustment data trimC2[4:0].

[0043] The variable capacitance circuit 15 is a capacitance circuit having a capacitance value C2 of a magnitude corresponding to the capacitance adjustment data trimCN2[4:0] in which each bit of the capacitance adjustment data trimC2[4:0] is logically inverted by the CMOS inverters 110, 111, 112, 113, 114. The variable capacitance circuit 15 includes five capacitance elements 150, 151, 152, 153, 154 and five switch elements 155, 156, 157, 158, 159.

[0044] The capacitance element 150 has one end connected to the XO terminal and the other end grounded via the switch element 155, and its capacitance value is C0. The capacitance element 151 has one end connected to the XO terminal and the other end grounded via the switch element 156, and its capacitance value is twice that of C0. The capacitance element 152 has one end connected to the XO terminal and the other end grounded via the switch element 157, and its capacitance value is four times that of C0. The capacitance element 153 has one end connected to the XO terminal and the other end grounded via the switch element 158, and its capacitance value is eight times that of C0. The capacitance element 154 has one end connected to the XO terminal and the other end grounded via the switch element 159, and its capacitance value is sixteen times that of C0. For example, the capacitance elements 150, 151, 152, 153, and 154 may be MIM-type capacitance elements using metal for the two electrodes, or PIP-type capacitance elements using polysilicon for the two electrodes. MIM is the abbreviation of Metal Insulator Metal. Also, PIP is the abbreviation of Poly Insulator Poly.

[0045] The switch element 155 has the data trimCN2[0] of bit 0 of the capacitance adjustment data trimCN2[4:0] input to its control terminal, conducts when the data trimCN2[0] is at a high level, and does not conduct when the data trimCN2[0] is at a low level. The switch element 156 has the data trimCN2[1] of bit 1 of the capacitance adjustment data trimCN2[4:0] input to its control terminal, conducts when the data trimCN2[1] is at a high level, and does not conduct when the data trimCN2[1] is at a low level. The switch element 157 has the data trimCN2[2] of bit 2 of the capacitance adjustment data trimCN2[4:0] input to its control terminal, conducts when the data trimCN2[2] is at a high level, and does not conduct when the data trimCN2[2] is at a low level. The switch element 158 has the data trimCN2[3] of bit 3 of the capacitance adjustment data trimCN2[4:0] input to its control terminal, conducts when the data trimCN2[3] is at a high level, and does not conduct when the data trimCN2[3] is at a low level. The switch element 159 has the data trimCN2[4] of bit 4 of the capacitance adjustment data trimCN2[4:0] input to its control terminal, conducts when the data trimCN2[4] is at a high level, and does not conduct when the data trimCN2[4] is at a low level. For example, the switch elements 155, 156, 157, 158, and 159 may be N-channel MOS transistors or transmission gates.

[0046] The relationship between the value obtained by expressing the capacitance adjustment data trimC2[4:0] in decimal and the values obtained by expressing each bit of the capacitance adjustment data trimCN2[4:0] in which the capacitance adjustment data trimC2[4:0] is logically inverted in binary is the same as the relationship between the value obtained by expressing the capacitance adjustment data trimC1[4:0] in decimal and the values obtained by expressing each bit of the capacitance adjustment data trimCN1[4:0] in binary as shown in FIG. 8, so the illustration thereof is omitted. For example, if the capacitance adjustment data trimC2[4:0] is 1, bits 1, 2, 3, 4 of the capacitance adjustment data trimCN2[4:0] are 1 and bit 0 is 0. Therefore, the switch elements 156, 157, 158, 159 conduct and the other ends of the capacitance elements 151, 152, 153, 154 are grounded. Also, for example, if the capacitance adjustment data trimC2[4:0] is 2, bits 0, 2, 3, 4 of the capacitance adjustment data trimCN2[4:0] are 1 and bit 1 is 0. Therefore, the switch elements 155, 157, 158, 159 conduct and the other ends of the capacitance elements 150, 152, 153, 154 are grounded.

[0047] The capacitance value C2 of the variable capacitance circuit 15 is the value obtained by adding the capacitance values of the capacitance elements 150, 151, 152, 153, 154 whose other ends are grounded when the switch elements 155, 156, 157, 158, 159 are conducting respectively. For example, when the capacitance adjustment data trimC2[4:0] is 1, the other ends of the capacitance elements 151, 152, 153, 154 are grounded and the other end of the capacitance element 150 is not grounded, so the capacitance value C2 of the variable capacitance circuit 15 is 2C0 + 4C0 + 8C0 + 16C0 = 30C0. Also, for example, when the capacitance adjustment data trimC2[4 :0] is 2, the other ends of the capacitance elements 150, 152, 153, 154 are grounded and the other end of the capacitance element 151 is not grounded, so the capacitance value C2 of the variable capacitance circuit 15 is C0 + 4C0 + 8C0 + 16C0 = 29C0. Thus, the capacitance value C2 of the variable capacitance circuit 15 varies according to the value of the capacitance adjustment data trimC2[4:0]. Specifically, the larger the value of the capacitance adjustment data trimC2[4:0], the smaller the capacitance value C2 of the variable capacitance circuit 15.

[0048] The variable capacitance circuit 14 is connected to the excitation electrode 3a of the vibrator 3 via the XI terminal, and the variable capacitance circuit 15 is connected to the excitation electrode 3b of the vibrator 3 via the XO terminal. That is, the variable capacitance circuits 14 and 15 are connected to the node connected to the vibrator 3 and form part of the load capacitance of the vibrator 3. In the manufacturing process of the oscillator 1, the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] for setting the frequency of the oscillation signal CK output from the oscillation circuit 10 to the target frequency are written into the non-volatile memory 71.

[0049] The variable capacitance circuit 16 is a capacitance circuit having a capacitance value C3 of a magnitude corresponding to the control voltage Vcnt1 supplied from the voltage control circuit 41. The variable capacitance circuit 16 includes a variable capacitance element 160. For example, the variable capacitance element 160 is a varactor in which the source and drain of an NMOS transistor are connected, the gate of the NMOS transistor is connected to the XI terminal, the ground voltage Vss is supplied to the back gate, and the control voltage Vcnt1 is supplied to the source and drain. The larger the control voltage Vcnt1, the smaller the capacitance value C3 of the variable capacitance circuit 16.

[0050] The variable capacitance circuit 17 is a capacitance circuit having a capacitance value C4 of a magnitude corresponding to the control voltage Vcnt2 supplied from the voltage control circuit 41. The variable capacitance circuit 17 includes a variable capacitance element 170. For example, the variable capacitance element 170 is a varactor in which the source and drain of an NMOS transistor are connected, the gate of the NMOS transistor is connected to the XO terminal, the ground voltage Vss is supplied to the back gate, and the control voltage Vcnt2 is supplied to the source and drain. The larger the control voltage Vcnt2, the smaller the capacitance value C4 of the variable capacitance circuit 17.

[0051] FIG. 9 is a diagram showing another configuration example of the variable capacitance circuits 16 and 17. In the example of FIG. 9, the variable capacitance circuit 16 includes n variable capacitance elements 161-1 to 161-n, n capacitance elements 162-1 to 162-n, and n capacitance elements 163-1 to 163-n. n is an integer of 2 or more. For each integer i from 1 to n, the variable capacitance element 161-i is a varactor in which the source and drain of an NMOS transistor are connected. The source and drain of the NMOS transistor are connected to the XI terminal via the capacitance element 163-i. The ground voltage Vss is supplied to the back gate, and the gate is grounded via the capacitance element 162-i. Further, the reference voltage Vref1-i generated by the reference voltage generation circuit 50 is supplied to the gate of the NMOS transistor, and the control voltage Vcnt1 is supplied to the source and drain. The larger the control voltage Vcnt1, the smaller the capacitance value C3 of the variable capacitance circuit 16.

[0052] Further, the variable capacitance circuit 17 includes n variable capacitance elements 171-1 to 171-n, n capacitance elements 172-1 to 172-n, and n capacitance elements 173-1 to 173-n. n is an integer of 2 or more. For each integer i from 1 to n, the variable capacitance element 171-i is a varactor in which the source and drain of an NMOS transistor are connected. The source and drain of the NMOS transistor are connected to the XI terminal via the capacitance element 173-i. The ground voltage Vss is supplied to the back gate, and the gate is grounded via the capacitance element 172-i. Further, the reference voltage Vref2-i generated by the reference voltage generation circuit 50 is supplied to the gate of the NMOS transistor, and the control voltage Vcnt2 is supplied to the source and drain. The larger the control voltage Vcnt2, the smaller the capacitance value C4 of the variable capacitance circuit 17.

[0053] In both FIG. 5 and FIG. 9, the variable capacitance circuit 16 is connected to the excitation electrode 3a of the vibrator 3 via the XI terminal, and the variable capacitance circuit 17 is connected to the excitation electrode 3b of the vibrator 3 via the XO terminal. That is, the variable capacitance circuits 16 and 17 are connected to the node connected to the vibrator 3 and form part of the load capacitance of the vibrator 3. The capacitance values C3 and C4 of the variable capacitance circuits 16 and 17 each change according to the control voltages Vcnt1 and Vcnt2, and the control voltages Vcnt1 and Vcnt2 change according to the voltage level of the frequency control signal input from the external terminal VC1 via the VC terminal. Therefore, the oscillation frequency of the oscillation circuit 10 can be changed by the frequency control signal input from the external terminal VC1. Thus, in the present embodiment, the voltage control circuit 41 generates the control voltages Vcnt1 and Vcnt2 according to the voltage level of the frequency control signal input from the external terminal VC1. However, the voltage control circuit 41 may be a temperature compensation circuit, and the control voltages Vcnt1 and Vcnt2 may be temperature compensation voltages.

[0054]

[0055] 1-3. Startup Sequence In this embodiment, the oscillation circuit 2 has a plurality of operation modes including a normal operation mode and a startup mode. The normal operation mode is an operation mode in which the oscillation circuit 10 oscillates in a state where the negative resistance value |nR|, which is the absolute value of its negative resistance, becomes a first value |nR1| determined in advance. The startup mode is an operation mode from the state where the oscillation circuit 10 has stopped oscillating until it shifts to the normal operation mode. The startup mode is, for example, the operation mode from when the power is turned on to the oscillator 1 until it shifts to the normal operation mode. Further, when the oscillation circuit 2 has a standby mode as an operation mode in which the oscillation of the oscillation circuit 10 stops while the power is turned on to the oscillator 1, the operation mode until it shifts from the standby mode to the normal operation mode is also the startup mode.

[0056] In this embodiment, the oscillator 3 is a crystal oscillator and can resonate in the main vibration or the sub-vibration. When illustrating the polarization of the vibration in the X-axis, Y-axis, and Z-axis directions, respectively, the Y-axis and Z-axis are cosine waves. Assuming the number of peaks is p, q, and r respectively, the vibration mode is represented as (p.q.r). For example, when the oscillator 3 is an AT-cut crystal oscillator, the main vibration is the thickness main vibration with the vibration mode of (1.0.0). This thickness main vibration is a pure shear vibration with displacement only in the X-axis direction and has a constant polarization in the Z-axis direction. Also, for example, the sub-vibration is the thickness sub-vibration with the vibration mode of (3.1.0), (5.1.0), or (7.1.0). This thickness sub-vibration is a shear vibration only in the X-axis direction, but has an odd number of sinusoidal polarizations in the X-axis direction, and the signs of adjacent extreme values are opposite. Alternatively, the sub-vibration may be the thickness sub-vibration with the vibration mode of (1.1.1) or (1.1.2). This thickness sub-vibration is close to the thickness main vibration and is a vibration intervening between the thickness main vibration and the thickness sub-vibration with the vibration mode of (3.1.0), (5.1.0), or (7.1.0). It has one sinusoidal polarization in the X-axis direction and one or two cosine wave polarizations in the Z-axis direction, and the signs of adjacent extreme values are opposite. Alternatively, the sub-vibration may be the sub-vibration due to the high-order contour vibration with the vibration mode of (21.0.0). This sub-vibration due to the high-order contour vibration has an odd number of sinusoidal polarizations in the X-axis direction, the signs of adjacent extreme values are opposite, and has a substantially constant polarization in the Z-axis direction. Alternatively, the sub-vibration may be the sub-vibration due to the high-order contour vibration with the vibration mode of (0.0.33). This sub-vibration due to the high-order contour vibration has an odd number of sinusoidal polarizations in the Z-axis direction, the signs of adjacent extreme values are opposite, and has a substantially constant polarization in the X-axis direction. Alternatively, the sub-vibration may be the sub-vibration due to the high-order contour vibration with the vibration mode of (40.1.0), (42.1.0), or (12.1.0). This sub-vibration due to the high-order contour vibration has an odd number of sinusoidal polarizations in the X-axis direction, and the signs of adjacent extreme values are opposite.

[0057] The value R of the series resistance under load when the oscillator 3 resonates in the main vibration Lm is the value R of the series resistance under load when the oscillator 3 resonates in the sub-vibrationLs In other words, the load series resistance is The vibration with the smallest value is the primary vibration. In the normal operation mode, if the vibrator 3 resonates with the primary vibration, the oscillation circuit 10 oscillates normally and an oscillation signal CK of the target frequency is obtained, but if the vibrator 3 resonates with the secondary vibration, the oscillation circuit 10 oscillates abnormally and an oscillation signal CK of the target frequency is not obtained. In the normal operation mode, in order to stably oscillate the oscillation circuit 10 with the primary vibration, the negative resistance value |nR| is set to R Lm The nR1 is set to a first value |nR1| that is sufficiently larger than Specifically, the logic circuit 42 of the control circuit 40 supplies the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] transferred from the non-volatile memory 71 to the register 72 to the oscillation circuit 10, and controls the negative resistance value |nR| of the oscillation circuit 10 to become a first value |nR1| determined by the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0].

[0058] However, the first value |nR1| is Lm is sufficiently larger than R L s Then, the first value |nR1| becomes larger than R Ls It was bigger than Therefore, if the negative resistance value |nR| is set to the first value |nR1| immediately after the oscillation of the oscillation circuit 10 has stopped, the vibrator 3 may resonate with the secondary vibration under some conditions, which may cause the oscillation circuit 10 to oscillate abnormally. Therefore, in this embodiment, in order to reduce the possibility of the oscillation circuit 10 oscillating abnormally, the logic circuit 42 of the control circuit 40 controls the negative resistance value |nR| of the oscillation circuit 10 in the startup mode so as to increase from a second value |nR2| that is smaller than the first value |nR1|.

[0059] Here, as described above, the first value |nR1| is the value R of the loaded series resistance when the vibrator 3 resonates with the main vibration. LmLarger than, and when the vibrator 3 resonates in sub-vibration, the series resistance value R at load of the column resistance Ls is a larger value. Also, the second value |nR2| is at least the series resistance value R at load when the vibrator 3 resonates in sub-vibration Ls is a smaller value, that is, it is a negative resistance value at which the vibrator 3 cannot resonate in sub-vibration. The second value |nR2| may be smaller than the series resistance value R at load when the vibrator 3 resonates in main vibration Lm or may be larger. For example, even considering the variation in the characteristics of the vibrator 3 connected to the oscillation circuit 2, the second value |nR2| is surely made Ls smaller than R R Lm as well.

[0060] Thus, in this embodiment, the logic circuit 42 controls, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 to increase from the second value |nR2| at which the vibrator 3 cannot resonate at least in sub-vibration. As a result, there will surely be a state where the negative resistance value |nR| is larger than R Lm and smaller than R Ls . In this state, the vibrator 3 can resonate in main vibration but cannot resonate in sub-vibration. Therefore, the vibrator 3 resonates in main vibration before resonating in sub-vibration, and the oscillation circuit 10 oscillates normally based on the resonance in main vibration. Here, in the oscillation circuit 10 shown in FIG. 5, when the mutual conductance of the amplifying element 11 is g

[0061] , the capacitance value connected to the XI terminal is C m , the capacitance value connected to the XO terminal is C XI , and the oscillation frequency of the oscillation circuit 10 is f = ω / 2π, the theoretical formula for the negative resistance value |nR| of the oscillation circuit 10 is as shown in Equation (1). XO The oscillation

[0062] [Number]

[0063] Also, the mutual conductance of the amplification element 11 is g m which is represented by Equation (2). In Equation (2), q is the charge of an electron, k is the Boltzmann constant, and T is the absolute temperature.

[0064] [Number]

[0065] From Equation (1), the larger the mutual conductance g m of the amplification element 11, the larger the negative resistance value |nR|. In Equation (2), since q, k, and T are constants, the larger the oscillation-stage current Iosc, the larger the mutual conductance g m is. Therefore, the larger the oscillation-stage current Iosc, the larger the negative resistance value |nR|.

[0066] Therefore, in the present embodiment, the logic circuit 42 of the control circuit 40 increases the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2| by increasing the value of the oscillation-stage current Iosc in the startup mode. Specifically, in the startup mode, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] output to the oscillation circuit 10 to increase the value of the oscillation-stage current Iosc step by step, and controls so that the negative resistance value |nR| increases step by step.

[0067] FIG. 10 is a waveform diagram showing an example of a sequence of shifting to the normal operation mode after the oscillation circuit 2 is powered on. In the example of FIG. 10, when the oscillator 1 is powered on, the reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from the low level to the high level, and the logic circuit 42 is initialized. Thereafter, when the power-on reset signal POR changes from the high level to the low level, the reset period T1 ends and the memory load period T2 starts.

[0068] In the memory load period T2, various kinds of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from the low level to the high level, whereby the memory load period T2 ends and the startup period T3 starts.

[0069] In the startup period T3, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] step by step from the start value to the end value by an arbitrary value each time. Along with this, the value of the oscillation stage current Iosc gradually increases. The start value and the end value of the current adjustment data trimI[4:0] may be set to arbitrary values, for example, by being written in advance to the non-volatile memory 71. In the example of FIG. 10, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] step by step from the start value of 0 by 1 each time. Along with this, the value of the oscillation stage current Iosc increases by I b to I0 each time. As a result, in the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases stepwise from the second value |nR2|. When the negative resistance value |nR| is larger than R Lm and smaller than R Ls the vibrator 3 starts to resonate at the main oscillation, and the amplitude of the current I_xtal output from the oscillator 3 increases. Then, when the amplitude of the current I_xtal exceeds a predetermined threshold value, a pulse is generated in the oscillation signal CK. After that, the current adjustment data trimI[4:0] continues to increase, and the negative resistance value |nR| becomes larger than R Ls but at that point, the oscillation of the oscillation circuit 10 due to the resonance at the main oscillation of the oscillator 3 has grown sufficiently, so resonance at the sub - oscillation of the oscillator 3 does not occur. When the current adjustment data trimI[4:0] further increases and reaches 31 of the end value, the value of the oscillation stage current Iosc becomes I +31I0. After that, the logic circuit 42 gradually changes the value of the current adjustment data trimI[4:0] step - by - step by arbitrary values from the end value to the set value in the normal operation mode. In the example of FIG. 10, the logic circuit 42 gradually decreases the value of the current adjustment data trimI[4:0] from 31 of the end value by 1 each time. When the set value of the current adjustment data trimI[4:0] in the normal operation mode reaches 20, which is the value transferred to the register 72 during the memory load period T2, the value of the oscillation stage current Iosc becomes I b +20I0 and the negative resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 20 and changes the output enable signal en_out from the low level to the high level, so that the startup period T3 ends and the normal operation period T4 starts. b +20I0 and the negative resistance value |nR| becomes the first value |nR1|. And the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 20 and changes the output enable signal en_out from the low level to the high level, so that the startup period T3 ends and the normal operation period T4 starts.

[0070] During the normal operation period T4, since the output enable signal en_out is at the high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0071] Note that in the example of FIG. 10, the operation mode during the startup period T3 is the startup mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation modes during the reset period T1, the memory load period T2, and the startup period T3 are the startup mode.

[0072] In the example of FIG. 10, in the startup mode, the logic circuit 42 increases the current adjustment data trimI[4:0] from the minimum value to the maximum value and then decreases it to the set value in the normal operation mode, so the startup period T3 is long. On the other hand, other sequences that shorten the startup period T3 are also conceivable.

[0073] FIG. 11 is a waveform diagram showing another example of the sequence from when the power is turned on to the oscillation circuit 2 until it shifts to the normal operation mode. In the example of FIG. 11, during the startup period T3, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] step by step from the start value to the set value in the normal operation mode. Along with this, the value of the oscillation stage current Iosc increases step by step. The start value of the current adjustment data trimI[4:0] may be set to an arbitrary value, for example, by being written in the non-volatile memory 71 in advance. In the example of FIG. 11, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] from 0, which is the start value, to 20, which is the set value in the normal operation mode, one by one. Along with this, the value of the oscillation stage current Iosc increases by I0 from I b to I b +20I0 one by one. . As a result, during the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases step by step from the second value |nR2| to the first value |nR1|. Then, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 20 and changes the output enable signal en_out from the low level to the high level, so that the startup period T3 ends and the normal operation period T4 starts.

[0074] In the example of FIG. 11, since the logic circuit 42 does not need to increase the current adjustment data trimI[4:0] from the start value to the end value, the startup period T3 is shortened. Also, in the example of FIG. 11, the first value |nR1|, which is the set value of the negative resistance value |nR| in the normal operation mode, is equal to or greater than the maximum value of the negative resistance value |nR| during the startup period T3. That is, during the startup period T3, since the negative resistance value |nR| does not become larger than the first value |nR1|, the time during which the negative resistance value |nR| becomes a value larger than the load series resistance value R when the oscillator 3 resonates in sub-oscillation is short, and resonance in sub-oscillation of the oscillator 3 is less likely to occur. Ls than a larger value, and the time for resonance in sub-oscillation of the oscillator 3 is shorter, making resonance in sub-oscillation of the oscillator 3 less likely to occur.

[0075] Note that also in the example of FIG. 11, the operation mode during the startup period T3 is the startup mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation modes during the reset period T1, the memory load period T2, and the startup period T3 are the startup mode.

[0076] 1-4. Control Method of Oscillation Circuit FIG. 12 is a flowchart showing an example of the procedure of the control method of the oscillation circuit 2. As shown in FIG. 12, when power is supplied to the oscillator 1, first, the oscillation circuit 2 performs a reset step S1. Specifically, in the reset step S1, the power-on reset circuit 30 changes the power-on reset signal POR from a low level to a high level to initialize the logic circuit 42. Then, the power-on reset circuit 30 changes the power-on reset signal POR from a high level to a low level, and the reset step S1 ends. The period of the reset step S1 corresponds to the reset period T1 in FIG. 10 or FIG. 11.

[0077] Next, the oscillation circuit 2 performs the memory load step S2. Specifically, in the memory load step S2, the memory circuit 70 transfers various pieces of information stored in the non-volatile memory 71 to the register 72. After the transfer is completed, the logic circuit 42 sets the oscillation enable signal en_osc to a high level, and the memory load step S2 ends. The period of the memory load step S2 corresponds to the memory load period T2 in FIG. 10 or FIG. 11.

[0078] Next, the oscillation circuit 2 performs the startup step S3. Specifically, in the startup step S3, the logic circuit 42 sets the oscillation enable signal en_osc to a high level, and the negative resistance value |nR| of the oscillation circuit 10 increases from a second value |nR2| that is smaller than a first value |nR1| and is controlled accordingly. Then, the logic circuit 42 changes the output enable signal en_out from a low level to a high level, and the startup step S3 ends. The period of the startup step S3 corresponds to the startup period T3 in FIG. 10 or FIG. 11.

[0079] Finally, the oscillation circuit 2 performs the normal operation step S4. Specifically, in the normal operation step S4, the oscillation circuit 10 oscillates with its negative resistance value |nR| being the second value |nR2|, and the oscillation signal CKO output from the output circuit 60 is output from the external terminal OUT1 of the oscillator 1 via the OUT terminal. The period of the normal operation step S4 corresponds to the normal operation period T4 in FIG. 10 or FIG. 11.

[0080] Note that the operation mode in the startup step S3 is the startup mode, and the operation mode in the normal operation step S4 is the normal operation mode. Alternatively, the operation modes in the reset step S1, the memory load step S2, and the startup step S3 are the startup mode.

[0081] FIG. 13 is a flowchart showing an example of the procedure of the startup process S3 in FIG. 12 in the first embodiment. The procedure shown in FIG. 13 corresponds to the operation during the startup period T3 in FIG. 10. As shown in FIG. 13, first, in step S31, the logic circuit 42 sets the current adjustment data trimI[4:0] to the starting value. In the example of FIG. 10, the starting value is 0. By setting the current adjustment data trimI[4:0] to the starting value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0082] Next, when a predetermined time elapses in step S32, in step S33, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the end value. In the example of FIG. 10, the end value is 20.

[0083] If the value of the current adjustment data trimI[4:0] does not match the end value in step S33, in step S34, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0084] Steps S32, S33, and S34 are repeated until the value of the current adjustment data trimI[4:0] matches the end value. When the value of the current adjustment data trimI[4:0] matches the end value, in step S35, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in the normal operation mode.

[0085] Then, in step S36, the logic circuit 42 sets the output enable signal en_out to the high level, and the startup process S3 ends.

[0086] FIG. 14 is a flowchart showing another example of the procedure of the startup step S3 in FIG. 12 in the first embodiment. The procedure shown in FIG. 14 corresponds to the operation during the startup period T3 in FIG. 11. As shown in FIG. 14, first, in step S101, the logic circuit 42 sets the current adjustment data trimI[4:0] to the starting value. In the example of FIG. 11, the starting value is 0. By setting the current adjustment data trimI[4:0] to the starting value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0087] Next, when a predetermined time elapses in step S102, in step S103, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the set value in the normal operation mode. The set value of the current adjustment data trimI[4:0] in the normal operation mode is the value stored in the non-volatile memory 71.

[0088] If the value of the current adjustment data trimI[4:0] does not match the set value in the normal operation mode in step S103, in step S104, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0089] Then, steps S102, S103, and S104 are repeated until the value of the current adjustment data trimI[4:0] matches the set value in the normal operation mode. When the value of the current adjustment data trimI[4:0] matches the set value in the normal operation mode, in step S105, the logic circuit 42 sets the output enable signal en_out to the high level, and the startup step S3 ends.

[0090] 1-5. Operational Effects In the oscillator 1 of the first embodiment described above, in the oscillation circuit 2, in the startup mode from the state where the oscillation circuit 10 has stopped oscillating until it shifts to the normal operation mode where the oscillation circuit 10 oscillates with the negative resistance value |nR| of the oscillation circuit 10 becoming the first value |nR1|, the negative resistance value |nR| of the oscillation circuit 10 is from the second value |nR2| which is smaller than the first value |nR1| increases. The value R of the series resistance under load when the oscillator 3 resonates at the main vibration Lm is when the oscillator 3 resonates at the sub-vibration, the value R of the series resistance under load Ls is smaller than, so the negative resistance value |nR| of the oscillation circuit 10 increases from the second value |nR2| and becomes larger than R Lm and also R Ls is smaller than. Therefore, in the startup mode, the oscillation based on the main vibration resonance of the oscillator 3 grows earlier than the oscillation based on the resonance of the sub-vibration of the oscillator 3. Therefore, according to the oscillator 1 of the first embodiment, even if there are variations in the characteristics of the oscillator 3, the risk of abnormal oscillation can be reduced.

[0091] In particular, in the oscillator 1 of the first embodiment, in the startup mode, by increasing the value of the oscillation stage current Iosc, the negative resistance value |nR| of the oscillation circuit 10 gradually increases step by step from the second value |nR2|, so it is larger than R Lm and also smaller than R Ls and the time to reach a smaller value becomes longer. Therefore, the oscillation based on the resonance of the main vibration of the oscillator 3 grows earlier than the oscillation based on the resonance of the sub-vibration of the oscillator 3. Therefore, according to the oscillator 1 of the first embodiment, even if there are variations in the characteristics of the oscillator 3, the risk of abnormal oscillation can be reduced.

[0092] Also, according to the oscillator 1 of the first embodiment, the variable current source 12 for setting the oscillation stage current Iosc to a desired value according to the resonance frequency of the oscillator 3 in the normal operation mode can be used also for increasing the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0093] 2. Second Embodiment Hereinafter, for the oscillator 1 of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, the same description as that in the first embodiment is omitted or simplified, and mainly the contents different from those in the first embodiment will be described.

[0094] Since the configuration of the oscillator 1 in the second embodiment is the same as that in FIGS. 1 to 4, the illustration and description thereof are omitted. Also, since the configuration of the oscillation circuit 10 in the second embodiment is the same as that in FIG. 5, the illustration and description thereof are omitted. The oscillator 1 in the second embodiment has different operations in the startup mode from the oscillator 1 in the first embodiment.

[0095] From the above equation (1), the smaller at least one of the capacitance values C XI , C XO is, the larger the negative resistance value |nR| becomes. Therefore, in the second embodiment, the logic circuit 42 of the control circuit 40 increases the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2| by decreasing at least one of the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 in the startup mode. Specifically, in the startup mode, the logic circuit 42 changes at least one of the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] output to the oscillation circuit 10 to increase at least one of the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 in a stepwise manner, so as to control the negative resistance value |nR| to increase in a stepwise manner.

[0096] Since the other configurations of the oscillator 1 in the second embodiment are the same as those in the first embodiment, the illustration and description thereof are omitted.

[0097] FIG. 15 is a waveform diagram showing an example of a sequence in which the oscillation circuit 2 in the second embodiment shifts to the normal operation mode after the power is turned on. In the example of FIG. 15, when the power is turned on to the oscillator 1, the reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from the low level to the high level, and the logic circuit 42 is initialized. Thereafter, when the power-on reset signal POR changes from the high level to the low level, the reset period T1 ends and the memory load period T2 starts.

[0098] During the memory load period T2, various types of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from a low level to a high level, thereby ending the memory load period T2 and starting the startup period T3.

[0099] During the startup period T3, the logic circuit 42 gradually increases the capacitance adjustment data trimC1[4:0], trimC2[4:0] from the starting value to the set value in the normal operation mode by arbitrary values one by one. Along with this, the values of the capacitance values C1, C2 gradually increase. Capacitance adjustment The starting values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] may be set to arbitrary values, for example, by being written in advance to the non-volatile memory 71. In the example of FIG. 15, the logic circuit 42 gradually increases the capacitance adjustment data trimC1[4:0], trimC2[4:0] from the starting value of 0 by 1 one by one in order. Along with this, the capacitance values C1, C2 decrease from 31C0 to C0 respectively. As a result, during the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases step by step from the second value |nR2|. When the negative resistance value |nR| is greater than R Lm and less than Ls R at the smallest, the oscillator 3 starts resonance in the main oscillation, and the amplitude of the current I_xtal output from the oscillator 3 increases. Then, when the amplitude of the current I_xtal exceeds a predetermined threshold value, a pulse is generated in the oscillation signal CK. After that, the capacitance adjustment data trimC1[4:0], trimC2[4:0] continues to increase, and the negative resistance value |nR| becomes greater than R Ls but at that point, since the oscillation of the oscillation circuit 10 due to the resonance of the oscillator 3 in the main oscillation has grown sufficiently, resonance in the sub-oscillation of the oscillator 3 does not occur. When the capacitance adjustment data trimC1[4:0], trimC2[4:0] further increases and reaches 20, which is the value transferred to the register 72 during the memory load period T2, the capacitance values C1, C2 become 11C0 respectively, and the negative The resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 holds the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] at 20, and changes the output enable signal en_out from the low level to the high level, so that the startup period T3 ends and the normal operation period T4 starts.

[0100] During the normal operation period T4, since the output enable signal en_out is at the high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0101] Note that during the startup period T3, both of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are increased to decrease both of the capacitance values C1 and C2. One of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] may be fixed and the other may be increased to fix one of the capacitance values C1 and C2 and decrease the other.

[0102] In the example of FIG. 15, the first value |nR1|, which is the set value of the negative resistance value |nR| in the normal operation mode, is not less than the maximum value of the negative resistance value |nR| during the startup period T3. That is, during the startup period T3, since the negative resistance value |nR| does not become larger than the first value |nR1|, the time when the negative resistance value |nR| becomes larger than the value R of the load series resistance when the oscillator 3 resonates in the sub-oscillation is short, and the resonance in the sub-oscillation of the oscillator 3 is less likely to occur. Ls than the value R, and the resonance in the sub-oscillation of the oscillator 3 is less likely to occur. .

[0103] Note that in the example of FIG. 15, the operation mode during the startup period T3 is the startup mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation modes during the reset period T1, the memory load period T2, and the startup period T3 are the startup mode.

[0104] Although the illustration of the sequence is omitted, during the startup period T3, the logic circuit 42 may gradually increase at arbitrary values from the start value to the end value for at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0], and then gradually decrease to the set value in the normal operation mode at arbitrary values.

[0105] Since the flowchart showing the procedure of the control method of the oscillation circuit 2 in the second embodiment is the same as FIG. 12, the illustration and description thereof are omitted. However, in the second embodiment, the procedure of the startup step S3 in FIG. 12 is different from that in the first embodiment.

[0106] FIG. 16 is a flowchart showing an example of the procedure of the startup step S3 in FIG. 12 in the second embodiment. The procedure shown in FIG. 16 corresponds to the operation during the startup period T3 in FIG. 15. As shown in FIG. 16, first, in step S201, the logic circuit 42 sets the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the start values respectively. In the example of FIG. 15, the start values are both 0. By setting the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the start values respectively, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0107] Next, when a predetermined time elapses in step S202, in step S203, the logic circuit 42 determines whether the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the set values in the normal operation mode respectively. The set values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] in the normal operation mode are the values stored in the non-volatile memory 71.

[0108] If the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] do not match the set values in the normal operation mode in step S203, in step S204, the logic circuit 42 changes the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to decrease the capacitance values C1 and C2.

[0109] Then, steps S202, S203, and S204 are repeated until the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the set values in the normal operation mode. When the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the set values in the normal operation mode, in step S205, the logic circuit 42 sets the output enable signal en_out to the high level, and the startup step S3 ends.

[0110] Note that the logic circuit 42 fixes one of the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and changes the other value, thereby fixing one of the capacitance values C1 and C2 and decreasing the other.

[0111] In the oscillator 1 of the second embodiment described above, in the startup mode, by decreasing the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15, the negative resistance value |nR| of the oscillation circuit 10 gradually increases step by step from the second value |nR2|. Therefore, the value of the series resistance R under load when the vibrator 3 resonates in the main oscillation Lm is larger than R, and when the vibrator 3 resonates in the sub-oscillation the value of the series resistance R under load when it occurs Ls is smaller, and the time for the value to be smaller becomes longer. Therefore, the oscillation based on the resonance of the vibrator 3 in the main oscillation grows earlier than the oscillation based on the resonance of the vibrator 3 in the sub-oscillation. Therefore, according to the oscillator 1 of the second embodiment, even if there are variations in the characteristics of the vibrator 3, the risk of abnormal oscillation can be reduced. Further, according to the oscillator 1 of the second embodiment, the variable capacitance circuits 14 and 15 for setting the oscillation frequency of the oscillation circuit 10 to the target frequency in the normal operation mode can be used also for increasing the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0112] 3. Third Embodiment

[0113] 3. Third Embodiment Hereinafter, regarding the oscillator 1 of the third embodiment, the same components as those in any of the above embodiments are denoted by the same reference numerals, and the description similar to that in any of the above embodiments is omitted or simplified, and mainly the content different from any of the above embodiments will be described.

[0114] Since the configuration of the oscillator 1 of the third embodiment is the same as that in FIGS. 1 to 4, the illustration and description thereof are omitted. Also, since the configuration of the oscillation circuit 10 in the third embodiment is the same as that in FIG. 5, the illustration and description thereof are omitted. The oscillator 1 of the third embodiment has a different operation in the startup mode from the oscillator 1 of each of the above embodiments.

[0115] From the above formula (1), the smaller at least one of the capacitance values C XI , C XO is, the larger the negative resistance value |nR| becomes. Therefore, in the third embodiment, the voltage control circuit 41 of the control circuit 40 increases the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2| by decreasing at least one of the capacitance values C3 and C4 of the variable capacitance circuits 16 and 17 in the startup mode. Specifically, the voltage control circuit 41 changes at least one of the values of the control voltages Vcnt1 and Vcnt2 output to the oscillation circuit 10 in the startup mode to continuously increase at least one of the capacitance values C3 and C4 of the variable capacitance circuits 16 and 17, thereby controlling the negative resistance value |nR| to increase continuously. |nR| to increase continuously. |nR| is controlled to increase continuously.

[0116] FIG. 17 is a diagram showing a configuration example of the voltage control circuit 41 in the third embodiment. As shown in FIG. 17, the voltage control circuit 41 includes a control voltage generation circuit 200, a filter circuit 210, a switch circuit 220, a filter circuit 230, a switch circuit 240, a resistor 250, and a resistor 260.

[0117] In the normal operation mode, the control voltage generation circuit 200 generates control voltages Vcnt1X and Vcnt2X for changing the oscillation frequency of the oscillation circuit 10 according to the voltage level of the frequency control signal supplied from the external terminal VC1 via the VC terminal. Also, in the startup mode, the control voltage generation circuit 200 outputs control voltages Vcnt1X and Vcnt2X according to the control from the logic circuit 42. The control voltage Vcnt1X is input to the filter circuit 210, and the control voltage Vcnt2X is input to the filter circuit 230.

[0118] The filter circuit 210 is a low-pass filter circuit including a resistor 211 and a capacitive element 212, and outputs a control voltage Vcnt1f with a gentle rise or fall of the control voltage Vcnt1.

[0119] The switch circuit 220 selects and outputs the control voltage Vcnt1X in the normal operation mode and the control voltage Vcnt1f in the startup mode according to the control from the logic circuit 42. The voltage output from the switch circuit 220 is supplied as the control voltage Vcnt1 to the variable capacitance circuit 16 in FIG. 5 via the resistor 250.

[0120] The filter circuit 230 is a low-pass filter circuit including a resistor 231 and a capacitive element 232, and outputs a control voltage Vcnt2f with a gentle rise or fall of the control voltage Vcnt2.

[0121] The switch circuit 240 selects and outputs the control voltage Vcnt2X in the normal operation mode and the control voltage Vcnt2f in the startup mode according to the control from the logic circuit 42. The voltage output from the switch circuit 240 is supplied as the control voltage Vcnt2 to the variable capacitance circuit 17 in FIG. 5 via the resistor 260.

[0122] Since the other configurations of the oscillator 1 of the third embodiment are the same as those of the above embodiments, the illustration and description thereof are omitted.

[0123] FIG. 18 is a waveform diagram showing an example of a sequence for shifting to the normal operation mode after the power is turned on in the third embodiment. In the example of FIG. 18, when the power is turned on to the oscillator 1, the reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from the low level to the high level, and the logic circuit 42 is initialized. Thereafter, when the power-on reset signal POR changes from the high level to the low level, the reset period T1 ends and the memory load period T2 starts.

[0124] In the memory load period T2, various pieces of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from the low level to the high level, whereby the memory load period T2 ends and the startup period T3 starts.

[0125] In the startup period T3, under the control of the logic circuit 42, in the voltage control circuit 41, the control voltage generation circuit 200 raises the control voltages Vcnt1X and Vcnt2X from the start value V start to the end value V end and the switch circuits 220 and 240 select and output the control voltages Vcnt1f and Vcnt2f output from the filter circuits 210 and 230. As a result, the rise of the control voltages Vcnt1 and Vcnt2 becomes gentle, the control voltages Vcnt1 and Vcnt2 continuously increase, and accordingly, the capacitance values C3 and C4 continuously decrease. As a result, in the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 continuously increases from the second value |nR2|. When the negative resistance value |nR| is larger than R Lm and smaller than R and smaller than R Ls and smaller than R, the vibrator 3 starts resonance with the main vibration, and the vibrator 3 The amplitude of the output current I_xtal increases. Then, when the amplitude of the current I_xtal exceeds a predetermined threshold value, a pulse is generated in the oscillation signal CK. After that, the control voltages Vcnt1 and Vcnt2 continue to increase, and the negative resistance value |nR| becomes larger than R Ls However, at that time, since the oscillation of the oscillation circuit 10 due to the resonance in the main oscillation of the oscillator 3 has sufficiently grown, the resonance in the sub-oscillation of the oscillator 3 does not occur. When the control voltages Vcnt1 and Vcnt2 further increase and reach the end value V end the capacitance values C3 and C4 respectively become predetermined values, and the negative resistance value |nR| becomes the first value |nR1|. For example, the end value V end may be the voltage value of the frequency control signal input from the VC terminal. Then, the logic circuit 42 changes the output enable signal en_out from the low level to the high level, and the startup period T3 ends and the normal operation period T4 starts. Note that the start value V and the end start value V and the end end value V can be set to arbitrary values, for example, by being written in advance to the non-volatile memory 71

[0126] In the normal operation period T4, since the output enable signal en_out is at the high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0127] Note that in the startup period T3, by increasing both of the control voltages Vcnt1 and Vcnt2, both of the capacitance values C3 and C4 are decreased. However, by fixing one of the control voltages Vcnt1 and Vcnt2 and increasing the other, one of the capacitance values C3 and C4 can be fixed and the other can be decreased.

[0128] ​In the example of Fig. 18, the operation mode during the startup period T3 is the startup mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation modes during the reset period T1, the memory load period T2, and the startup period T3 are the startup mode.

[0129] Although the illustration of the sequence is omitted, during the startup period T3, at least one of the control voltages Vcnt1 and Vcnt2 is continuously increased from the start value V start to the end value V end After that, it may be continuously changed from the end value V to the voltage value of the frequency control signal input from the VC terminal. For example, the minimum value and the maximum value of the variable range of the control voltages Vcnt1 and Vcnt2 may be the start value V end and the end value V and the end value V start and the end value V end respectively.

[0130] Since the flowchart showing the procedure of the control method of the oscillation circuit 2 in the third embodiment is the same as Fig. 12, its illustration and description are omitted. However, in the third embodiment, the procedure of the startup step S3 in Fig. 12 is different from those of the above embodiments.

[0131] Fig. 19 is a flowchart showing an example of the procedure of the startup step S3 in Fig. 12 in the third embodiment. The procedure shown in Fig. 19 corresponds to the operation during the startup period T3 in Fig. 18. As shown in Fig. 19, first, in step S301, the logic circuit 42 sets the switch circuits 220 and 240 of the voltage control circuit 41 to select the output voltages of the filter circuits 210 and 230.

[0132] Next, in step S302, the logic circuit 42 controls the control voltage generation circuit 200 of the voltage control circuit 41 so that the control voltages Vcnt1X and Vcnt2X are changed from the start value V start to the end value V end As a result, the control voltages Vcnt1 and Vcnt2 are continuously changed from the start value to the end value. continuously change from the start value to the end value.

[0133] Then, when a predetermined time has elapsed in step S303, in step S304, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends. For example, the predetermined time is longer than the time during which the control voltages Vcnt1 and Vcnt2 change from the start value V start to the end value V end and is appropriately determined based on the time constants of the filter circuits 210 and 2 30.

[0134] Note that the logic circuit 42 may fix one of the values of the control voltages Vcnt1X and Vcnt2X and change the other value, thereby fixing one of the capacitance values C1 and C2 and decreasing the other as well.

[0135] In the oscillator 1 of the third embodiment described above, in the startup mode, by decreasing the capacitance values C3 and C4 of the variable capacitance circuits 16 and 17, the negative resistance value |nR| of the oscillation circuit 10 continuously and gradually increases from the second value |nR2|. Therefore, the value of the series resistance at load when the vibrator 3 resonates in the main oscillation is larger than the value of R Lm and is smaller than the value of the series resistance at load when the vibrator 3 resonates in the sub-oscillation for a longer time. Therefore, the oscillation based on the resonance of the main oscillation of the vibrator 3 grows earlier than the oscillation based on the resonance of the sub-oscillation of the vibrator 3. Therefore, according to the oscillator 1 of the third embodiment, even if there are variations in the characteristics of the vibrator 3, the risk of abnormal oscillation can be reduced. Ls 3.

[0136] Also, according to the oscillator 1 of the third embodiment, the variable capacitance circuits 16 and 17 for changing the oscillation frequency of the oscillation circuit 10 by the frequency control signal input from the external terminal VC1 in the normal operation mode can be used also for increasing the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0137] ​4. Fourth Embodiment Hereinafter, for the oscillator 1 of the fourth embodiment, the same components as those in any of the above embodiments are denoted by the same reference numerals, and the description similar to that in any of the above embodiments is omitted or simplified, and mainly the content different from any of the above embodiments will be described.

[0138] Since the configuration of the oscillator 1 of the fourth embodiment is the same as that in FIGS. 1 to 4, the illustration and description thereof are omitted. Further, since the configuration of the oscillation circuit 10 in the fourth embodiment is the same as that in FIG. 5, the illustration and description thereof are omitted. The oscillator 1 of the fourth embodiment has a different operation in the startup mode from the oscillator 1 of each of the above embodiments.

[0139] In the fourth embodiment, the logic circuit 42 of the control circuit 40 increases the value of the oscillation stage current Iosc and at least decreases at least one of the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 in the startup mode to increase the negative resistance value |nR| from the second value |nR2|. For example, in the startup mode, the logic circuit 42 increases the value of the oscillation stage current Iosc from the third value to a fourth value larger than the third value without changing the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15, and then decreases at least one of the capacitance values C1 and C2 and changes the value of the oscillation stage current Iosc to the third value, and this control may be repeated. For example, in the startup mode, the logic circuit 42 first holds the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] output to the oscillation circuit 10 at the start value, and changes the value of the current adjustment data trimI[4:0] output to the oscillation circuit 10 from the start value to the end value to increase the value of the oscillation stage current Iosc stepwise from the third value to the fourth value, so as to control the negative resistance value |nR| to increase stepwise. Next, after changing the value of the current adjustment data trimI[4:0] to the start value, the logic circuit 42 changes and holds the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to decrease at least one of the capacitance values C1 and C2 by one step, and the current adjustment data trimI[4:0] is changed to the start value, and the oscillation stage current Iosc is changed to the third value. By changing the value of the entire data trimI[4:0] from the start value to the end value and increasing the value of the oscillation stage current Iosc step by step from the third value to the fourth value, the negative resistance value |nR| is controlled to increase step by step. The logic circuit 42 repeats the same control while changing at least one of the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0]. Finally, after the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to the start value, it changes at least one of the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the end value and holds it, thereby decreasing the capacitance values C1 and C2 by one step. By changing the value of the current adjustment data trimI[4:0] from the start value to the end value and increasing the value of the oscillation stage current Iosc step by step from the third value to the fourth value, the negative resistance value |nR| is controlled to increase step by step.

[0140] Other configurations of the oscillator 1 of the fourth embodiment are the same as those of the above embodiments, and thus the illustration and description thereof are omitted.

[0141] FIG. 20 is a waveform diagram showing another example of a sequence for shifting to the normal operation mode after the power is turned on in the oscillation circuit 2 in the fourth embodiment. In the example of FIG. 20, when the power is turned on to the oscillator 1, the reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from the low level to the high level, and the logic circuit 42 is initialized. Thereafter, when the power-on reset signal POR changes from the high level to the low level, the reset period T1 ends and the memory load period T2 starts.

[0142] During the memory load period T2, various types of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from the low level to the high level, whereby the memory load period T2 ends and the startup period T3 starts.

[0143] During the startup period T3, the logic circuit 42 first sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their initial values, and gradually increases the current adjustment data trimI[4:0] step by step by an arbitrary value from the initial value to the final value. Along with this, the value of the oscillation stage current Iosc gradually increases. The initial values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0], and the initial and final values of the current adjustment data trimI[4:0] may be set to arbitrary values, for example, by being written into the non-volatile memory 71 in advance. In the example of FIG. 20, the logic circuit 42 sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their initial value of 0, and gradually increases the current adjustment data trimI[4:0] step by step by 1 from the initial value of 0 to the final value of 31. As a result, the capacitance values C1 and C2 are in the state of 31C0 respectively, and the oscillation stage current Iosc is the third value I b to the fourth value I b +31I0 in a stepwise manner, and the negative resistance value |nR| of the oscillation circuit 10 increases step by step from the second value |nR2|.

[0144] Next, after the logic circuit 42 changes the current adjustment data trimI[4:0] to the initial value of 0, it increases the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by an arbitrary value respectively. In the example of FIG. 20, the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set and held to 1, which is the value increased by 1 from 0 respectively, and again, the current adjustment data trimI[4:0] is gradually increased step by step by 1 from the initial value of 0 to the final value of 31. As a result, the capacitance values C1 and C2 decrease to 30C0 respectively in the state where, the oscillation stage current Iosc is the third value I b to the fourth value I b +31I0 in a stepwise manner, and the negative resistance value |nR| of the oscillation circuit 10 increases step by step.

[0145] Next, after the logic circuit 42 changes the current adjustment data trimI[4:0] to the starting value of 0, it increases the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by arbitrary values respectively. In the example of FIG. 20, the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set and held at 2, which is the value increased by 1 from 1 respectively, and again, the current adjustment data trimI[4:0] is incremented step by step from the starting value of 0 to the ending value of 31 one by one. As a result, the capacitance values C1 and C2 decrease to 29C0 respectively in a state where the oscillation stage current Iosc is the third value I b to the fourth value I b +31I0 and increases step by step until, and the negative resistance value |nR| of the oscillation circuit 10 increases step by step. When the negative resistance value |nR| is greater than R Lm and less than R Ls at that time, the oscillator 3 starts to resonate in the main oscillation, and the amplitude of the current I_xtal output from the oscillator 3 increases. Then, when the amplitude of the current I_xtal exceeds a predetermined threshold value, a pulse is generated in the oscillation signal CK. After that, the capacitance adjustment data trimC1[4:0] and trimC2[4:0] continue to increase, and the negative resistance value |nR| becomes greater than R Ls but at that time, the oscillation of the oscillation circuit 10 due to the resonance of the oscillator 3 in the main oscillation has grown sufficiently, so resonance in the sub-oscillation of the oscillator 3 does not occur.

[0146] After that, when the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach 31 of the end values respectively, and the value of the current adjustment data trimI[4:0] reaches 31 of the end value, the logic circuit 42 gradually changes the value of the current adjustment data trimI[4:0] step by step by arbitrary values from the end value to the set value in the normal operation mode. The end values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] may be set to arbitrary values, for example, by being written in advance to the non-volatile memory 71. In the example of FIG. 20, the logic circuit 42 gradually decreases the value of the current adjustment data trimI[4:0] by 1 from 31 of the end value. Then, when the value of the current adjustment data trimI[4:0] reaches 24, which is the value transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 24, and the value of the oscillation stage current Iosc becomes I b +24I0. Further, the logic circuit 42 gradually changes the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] step by step by arbitrary values from the end values to the set values in the normal operation mode. In the example of FIG. 20, the logic circuit 42 gradually decreases the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by 1 from 31 of the end values respectively. Then, when the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach 26, which are the values transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] at 26, and the capacitance values C1 and C2 become 5C0 respectively. When the value of the oscillation stage current Iosc becomes I b +24I0 and the capacitance values C1 and C2 become 5C0 respectively, the negative resistance value |nR| becomes the first value |nR1 |. Then, the logic circuit 42 changes the output enable signal en_out from the low level to the high level, so that the startup period T3 ends and the normal operation period T4 starts.

[0147] During the normal operation period T4, since the output enable signal en_out is at a high level, the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0148] Note that during the startup period T3, by increasing both the capacitance adjustment data trimC1[4:0] and trimC2[4:0], both the capacitance values C1 and C2 are decreased. It is also possible to fix one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and increase the other, thereby fixing one of the capacitance values C1 and C2 and decreasing the other.

[0149] Note that in the example of FIG. 20, the operation mode during the startup period T3 is the startup mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation modes during the reset period T1, the memory load period T2, and the startup period T3 are the startup mode.

[0150] Although the illustration of the sequence is omitted, in order to shorten the startup period T3, when the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach arbitrary end values respectively set, and the value of the current adjustment data trimI[4:0] reaches the end value, the logic circuit 42 may decrease the value of the current adjustment data trimI[4:0] to the set value in the normal operation mode to end the startup period T3. For example, the end values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] may be the set values in the normal operation mode.

[0151] The flowchart showing the procedure of the control method of the oscillation circuit 2 in the fourth embodiment is the same as that in FIG. 12, so its illustration and description are omitted. However, in the fourth embodiment, the procedure of the startup step S3 in FIG. 12 is different from those in the above embodiments.

[0152] FIG. 21 is a flowchart showing an example of the procedure of the startup process S3 in FIG. 12 in the fourth embodiment. The procedure shown in FIG. 21 corresponds to the operation during the startup period T3 in FIG. 20. As shown in FIG. 21, first, in step S401, the logic circuit 42 sets the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the starting values. In the example of FIG. 20, the starting value of the current adjustment data trimI[4:0] is 0, and the starting values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are 0. By setting the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the starting values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0153] Next, when a predetermined time has elapsed in step S402, in step S403, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the end value. In the example of FIG. 20, the end value of the current adjustment data trimI[4:0] is 31.

[0154] If the value of the current adjustment data trimI[4:0] does not match the end value in step S403, in step S404, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0155] Steps S402, S403, and S404 are repeated until the value of the current adjustment data trimI[4:0] matches the end value. When the value of the current adjustment data trimI[4:0] matches the end value, in step S405, the logic circuit 42 determines whether the values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] each match the end value. In the example of FIG. 20, the end values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are both 31.

[0156] In step S405, if the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] do not match the end values, in step S406, the logic circuit 42 sets the current adjustment data trimI[4:0] to the start value. Further, in step S407, the logic circuit 42 changes the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to decrease the capacitance values C1 and C2 respectively.

[0157] Steps S402, S403, S404, S405, S406, and S407 are repeated until the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end values. When the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end values, in step S408, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in the normal operation mode. Further, in step S409, the logic circuit 42 changes the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the set values in the normal operation mode.

[0158] Then, in step S410, the logic circuit 42 sets the output enable signal en_out to the high level, and the startup step S3 ends.

[0159] Note that the logic circuit 42 may fix one of the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and change the other value to fix one of the capacitance values C1 and C2 and decrease the other.

[0160] In the oscillator 1 of the fourth embodiment described above, in the startup mode, while increasing the value of the oscillation stage current Iosc, the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 are decreased. In this way, the negative resistance value |nR| of the oscillation circuit 10 gradually increases step by step from the second value |nR2|, so the value of the load series resistance R Lm when the vibrator 3 resonates in the main oscillation is larger than, and when the vibrator 3 resonates in the sub-oscillation, the value of the load series resistance RLs smaller than The time to reach a smaller value becomes longer. Therefore, the oscillation based on the resonance in the main oscillation of the vibrator 3 grows earlier than the oscillation based on the resonance in the sub-oscillation of the vibrator 3. Therefore, according to the oscillator 1 of the fourth embodiment, even if there are variations in the characteristics of the vibrator 3, the risk of abnormal oscillation can be reduced.

[0161] In particular, in the oscillator 1 of the fourth embodiment, the logic circuit 42 repeatedly performs control to increase the value of the oscillation stage current Iosc from a third value to a fourth value while changing the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15. Therefore, according to the oscillator 1 of the fourth embodiment, it is possible to reduce the risk that the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 are too large, or that the value of the oscillation stage current Iosc is too small and the oscillation circuit 10 does not oscillate. Further, after the logic circuit 42 increases the value of the oscillation stage current Iosc from a third value to a fourth value, the logic circuit 42 changes the value of the oscillation stage current Iosc to the third value before decreasing the capacitance values C1 and C2, so that when the capacitance values C1 and C2 are decreased, the risk that the negative resistance value |nR| increases rapidly and the vibrator 3 resonates in the sub-oscillation can be reduced.

[0162] Also, according to the oscillator 1 of the fourth embodiment, the variable current source 12 for setting the oscillation stage current Iosc to a desired value according to the resonance frequency of the vibrator 3 and the variable capacitance circuits 14 and 15 for setting the oscillation frequency of the oscillation circuit 10 to the target frequency in the normal operation mode can be used also for increasing the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0163] 5. Fifth Embodiment Hereinafter, for the oscillator 1 of the fifth embodiment, the same components as those in any of the above embodiments are denoted by the same reference numerals, the description similar to that in any of the above embodiments is omitted or simplified, and mainly the content different from any of the above embodiments will be described.

[0164] Since the structure of the oscillator 1 according to the fifth embodiment is the same as that in FIGS. 1 to 3, its illustration and description are omitted.

[0165] FIG. 22 is a functional block diagram of the oscillator 1 according to the fifth embodiment. As shown in FIG. 22, the oscillator 1 according to the fifth embodiment includes an oscillation circuit 2 and a vibrator 3, similar to each of the above embodiments. The oscillation circuit 2 includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generation circuit 50, an output circuit 60, and a memory circuit 70, similar to each of the above embodiments. However, different from each of the above embodiments, it further includes an oscillation detection circuit 80. Note that the oscillation circuit 2 may be configured by omitting or changing some of these elements, or adding other elements.

[0166] In the startup mode, the oscillation detection circuit 80 detects that the signal output from the vibrator 3 has reached a predetermined amplitude or more, and outputs a detection signal DET.

[0167] Based on the detection signal DET, the logic circuit 42 of the control circuit 40 sets the negative resistance value |nR| of the oscillation circuit 10 to a first value |nR1|.

[0168] FIG. 23 is a diagram showing a configuration example of the oscillation detection circuit 80. In the example of FIG. 23, the oscillation detection circuit 80 includes a current source 300, three capacitor elements 301, 314, 315, three variable resistors 302, 303, 304, six N-channel MOS transistors 305, 306, 307, 308, 309, 313, a comparator 310, and two CMOS inverters 311, 312.

[0169] One end of the current source 300 is supplied with a voltage Vreg, and the other end is connected to the drain of the N-channel MOS transistor 305.

[0170] The gate of N-channel MOS transistor 305 is connected to the gates of N-channel MOS transistor 307 and N-channel MOS transistor 309, and the sources of N-channel MOS transistors 305, 307, and 309 are grounded.

[0171] The drain of N-channel MOS transistor 307 is connected to the source of N-channel MOS transistor 306, and the drain of N-channel MOS transistor 309 is connected to the source of N-channel MOS transistor 308.

[0172] One end of variable resistor 304 is supplied with voltage Vreg, and the other end is connected to one end of variable resistor 303. The other end of variable resistor 303 is connected to one end of variable resistor 302, and the other end of variable resistor 302 is grounded.

[0173] One end of capacitor element 301 is connected to the XI terminal, and the other end is connected to the other end of variable resistor 303, one end of variable resistor 302, and the gate of N-channel MOS transistor 306. A signal output from oscillator 3 is input to the XI terminal.

[0174] The gate of N-channel MOS transistor 308 is connected to the other end of variable resistor 304 and one end of variable resistor 303, and voltage Vreg is supplied to the drains of N-channel MOS transistors 306 and 308.

[0175] The inverting input terminal of comparator 310 is connected to the source of N-channel MOS transistor 308 and one end of capacitor element 315, and the non-inverting input terminal is connected to the source of N-channel MOS transistor 306 and one end of capacitor element 314. The other ends of capacitor element 314 and capacitor element 315 are grounded.

[0176] The output terminal of the comparator 310 is connected to the input terminal of the CMOS inverter 311 and the gate of the N-channel MOS transistor 313, and the output terminal of the CMOS inverter 311 is connected to the input terminal of the CMOS inverter 312. The source and drain of the N-channel MOS transistor 313 are connected to one end and the other end of the variable resistor 303, respectively.

[0177] In the oscillation detection circuit 80 configured as described above, a voltage V2 = Vreg×(R1 + R2) / (R1 + R2 + R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, and 304 is input to the gate of the N-channel MOS transistor 306. R1, R 2, and R3 are the resistance values of the variable resistors 302, 303, and 304, respectively. Also, a voltage Vreg×R1 / (R1 + R2 + R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, and 304 and an AC component obtained by removing the DC component of the signal input from the XI terminal by the capacitive element 3 01 are added to obtain a voltage V1, which is input to the gate of the N-channel MOS transistor 306. Therefore, a voltage V2 - V is input to the inverting input terminal of the comparator 310, and a voltage V1 - V gs2 is input to the non-inverting input terminal of the comparator 310. V gs 1 is input. V gs1 is the voltage between the gate and source of the N-channel MOS transistor 306, and V is the voltage between the gate and source of the N-channel MOS transistor 308. gs2 is the voltage between the gate and source of the N-channel MOS transistor 308. is the voltage between the gate and source of the N-channel MOS transistor 308.

[0178] When the voltage V1 - V gs1 is lower than the voltage V2 - V gs2 the comparator 310 outputs a low-level signal, and when the voltage V1 - V is higher than the voltage V2 - V gs1 the comparator 310 outputs a high-level signal. When the voltage V1 - V gs2 is higher than the voltage V2 - V Outputs a high-level signal. The output signal of the comparator 310 has its logic level inverted by the CMOS inverter 311 and further inverted by the CMOS inverter 312. And since the output signal of the CMOS inverter 312 is output to the logic circuit 42 as the detection signal DET, the logic level of the detection signal DET is the same as that of the output signal of the comparator 310. Therefore, the detection signal DET is at a low level when the voltage V1-V gs1 is lower than the voltage V2-V gs2 and is at a high level when the voltage V1-V gs1 is higher than the voltage V2-V gs2 . At the start point of the startup mode , since the amplitude of the signal output from the oscillator 3 and input from the XI terminal is zero, the voltage V1-V gs1 is lower than the voltage V2-V gs2 , so the detection signal DET is at a low level . As the amplitude of the signal input from the XI terminal increases, the DC level of the voltage V1-V gs1 increases while the instantaneous voltage fluctuation is suppressed by the capacitive elements 314, 315 . And when the voltage V1-V gs1 becomes higher than the voltage V2-V gs2 , the output signal of the comparator -310 changes to a high level, and the detection signal DET also changes to a high level. When the detection signal DET changes from a low level to a high level, the logic circuit 42 sets the negative resistance value |nR| of the oscillation circuit 10 to the first value |nR1|. Also, when the output signal of the comparator 310 becomes high level, the drain-source of the N-channel MOS transistor 313 conducts, the difference between the voltage V1 and the voltage V2 disappears, and the output signal of the comparator 310 maintains a high level, and the detection signal DET also maintains a high level.

[0179] According to this oscillation detection circuit 80, the voltages V1, V2 are those of the variable resistors 302, 303, 304 Since it is determined by the ratio rather than the absolute values of the resistance values R1, R2, and R3 instead of the absolute value, the variable resistor 30 The errors of the voltages V1 and V2 due to the manufacturing errors of 2,303,304 are small, and from the vibrator 3 The amplitude of the signal output can be detected with high accuracy.

[0180] Since the other configurations of the oscillator 1 of the fifth embodiment are the same as those of the above-described embodiments, the illustration and description thereof are omitted.

[0181] FIG. 24 is a waveform diagram showing another example of a sequence of shifting to the normal operation mode after the power is turned on in the oscillation circuit 2 in the fifth embodiment. In the example of FIG. 24, when the power is turned on to the oscillator 1, the reset period T1 starts, the power supply voltage Vdd rises from 0 V to a predetermined voltage value, the power-on reset signal POR changes from the low level to the high level, and the logic circuit 42 is initialized. Thereafter, when the power-on reset signal POR changes from the high level to the low level, the reset period T1 ends and the memory load period T2 starts.

[0182] During the memory load period T2, various types of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from the low level to the high level, whereby the memory load period T2 ends and the startup period T3 starts.

[0183] During the startup period T3, the logic circuit 42 first sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their starting values respectively, and gradually increases the current adjustment data trimI[4:0] step by step by an arbitrary value from the starting value to the ending value. Along with this, the value of the oscillation stage current Iosc gradually increases step by step. The starting values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0], and the starting value and ending value of the current adjustment data trimI[4:0] may be set to arbitrary values, for example, by being written into the non-volatile memory 71 in advance. In the example of FIG. 24, the logic circuit 42 sets and holds the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to 0, which is the starting value respectively, and gradually increases the current adjustment data trimI[4:0] step by step by 1 from the starting value of 0 to the ending value of 31. As a result, with the capacitance values C1 and C2 being in the state of 31C0 respectively, the oscillation stage current Iosc is the third value I b to the fourth value I b +31I0 in a stepwise manner, and the negative resistance value |nR| of the oscillation circuit 10 increases step by step from the second value |nR2|.

[0184] Next, after the logic circuit 42 changes the current adjustment data trimI[4:0] to the starting value of 0, it increases the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by an arbitrary value respectively. In the example of FIG. 24, the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set and held to 1, which is the value increased by 1 from 0 respectively, and again, the current adjustment data trimI[4:0] is gradually increased step by step by 1 from the starting value of 0 to the ending value of 31. As a result, with the capacitance values C1 and C2 decreased to 30C0 respectively in the state, the oscillation stage current Iosc is the third value I b to the fourth value I b +31I0 in a stepwise manner, and the negative resistance value |nR| of the oscillation circuit 10 increases step by step.

[0185] Next, after the logic circuit 42 changes the current adjustment data trimI[4:0] to the starting value of 0, it increases the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by arbitrary values respectively. In the example of FIG. 24, the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set and held at 2, which is the value obtained by increasing each by 1 from 1, and again, the current adjustment data trimI[4:0] is incremented step by step from the starting value of 0 to the ending value of 31. As a result, the capacitance values C1 and C2 decrease to 29C0 respectively in a state where the oscillating stage current Iosc is the third value I b to the fourth value I b +31I0 in a stepwise manner, and the negative resistance value |nR| of the oscillation circuit 10 increases step by step. When the negative resistance value |nR| is greater than R Lm and less than R Ls , the oscillator 3 starts to resonate in the main oscillation, and the amplitude of the current I_xtal output from the oscillator 3 increases. Then, when the amplitude of the current I_xtal exceeds a predetermined threshold value, a pulse is generated in the oscillation signal CK. Also, when the amplitude of the current I_xtal output from the oscillator 3 reaches a predetermined value, for example, when the value of the current adjustment data trimI[4:0] is 9 and the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are both 2, the detection signal DET changes from the low level to the high level.

[0186] Next, in response to the detection signal DET becoming high level, the logic circuit 42 gradually changes the value of the current adjustment data trimI[4:0] by arbitrary values up to the set value in the normal operation mode. In the example of FIG. 24, since the value of the current adjustment data trimI[4:0] when the detection signal DET becomes high level is 9, the logic circuit 42 gradually increases the value of the current adjustment data trimI[4:0] by 1 from 9. Then, when the value of the current adjustment data trimI[4:0] reaches 24, which is the value transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 24, and the value of the oscillation stage current Iosc becomes I b +24I0. Further, the logic circuit 42 gradually changes the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by arbitrary values up to the set values in the normal operation mode. In the example of FIG. 24, since the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] when the detection signal DET becomes high level are both 2, the logic circuit 42 gradually increases the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by 1 from 2 respectively. Then, when the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach 26 respectively, which are the values transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] at 26, and the capacitance values C1 and C2 become 5C0 respectively. The value of the oscillation stage current Iosc becomes I b +24I0, and since the capacitance values C1 and C2 become 5C0 respectively, the negative resistance value |nR| becomes the first value |nR1|. Before the negative resistance value |nR| becomes the first value |nR1|, it becomes larger than R Ls but at that point, the oscillator 3 Since the oscillation of the oscillation circuit 10 due to resonance in the main oscillation has sufficiently grown, resonance in the sub-oscillation of the vibrator 3 does not occur. Then, when the logic circuit 42 changes the output enable signal en_out from the low level to the high level, the startup period T3 ends and the normal operation period T4 starts.

[0187] During the normal operation period T4, since the output enable signal en_out is at the high level, the oscillation signal CK is buffered and pulses are generated in the oscillation signal CKO.

[0188] Note that during the startup period T3, both of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are increased to decrease both of the capacitance values C1 and C2. One of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] may be fixed and the other may be increased to fix one of the capacitance values C1 and C2 and decrease the other.

[0189] Note that in the example of FIG. 24, the operation mode during the startup period T3 is the startup mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation modes during the reset period T1, the memory load period T2, and the startup period T3 are the startup mode.

[0190] Since the flowchart showing the procedure of the control method of the oscillation circuit 2 in the fifth embodiment is the same as that of FIG. 12, its illustration and description are omitted. However, in the fifth embodiment, the procedure of the startup step S3 in FIG. 12 is different from those of the above embodiments.

[0191] FIG. 25 is a flowchart showing an example of the procedure of the startup process S3 in FIG. 12 in the fifth embodiment. The procedure shown in FIG. 25 corresponds to the operation during the startup period T3 in FIG. 24. As shown in FIG. 25, first, in step S501, the logic circuit 42 sets the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the starting values. In the example of FIG. 24, the starting value of the current adjustment data trimI[4:0] is 0, and the starting values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are 0. By setting the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the starting values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0192] Next, when a predetermined time has elapsed in step S502, if the detection signal DET is at a low level in step S503, then in step S504, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the end value. In the example of FIG. 24, the end value of the current adjustment data trimI[4:0] is 31.

[0193] If the value of the current adjustment data trimI[4:0] does not match the end value in step S504, then in step S505, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0194] As long as the detection signal DET is at a low level in step S503, steps S502, S504, and S505 are repeated until the value of the current adjustment data trimI[4:0] matches the end value. When the value of the current adjustment data trimI[4:0] matches the end value, in step S506, the logic circuit 42 determines whether the values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] each match the end value. In the example of FIG. 24, the end values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are both 31.

[0195] In step S506, if the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] do not match the end values, in step S507, the logic circuit 42 sets the current adjustment data trimI[4:0] to the start value. Further, in step S508, the logic circuit 42 changes the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to decrease the capacitance values C1 and C2 respectively.

[0196] As long as the detection signal DET is at the low level in step S503, steps S502, S504, S505, S506, S507, and S508 are repeated until the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end values.

[0197] When the detection signal DET is at the high level in step S503, or when the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end values in step S506, in step S509, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in the normal operation mode. Further, in step S510, the logic circuit 42 changes the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the set values in the normal operation mode.

[0198] Then, in step S511, the logic circuit 42 sets the output enable signal en_out to the high level, and the startup step S3 ends.

[0199] Note that the logic circuit 42 may fix one of the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and change the other value to fix one of the capacitance values C1 and C2 and decrease the other.

[0200] Note that FIGS. 24 and 25 correspond to the sequence and flowchart when the oscillation detection circuit 80 is added to the oscillator 1 of the fourth embodiment. Although the illustration of the sequence and flowchart is omitted, the oscillation detection circuit 80 may be added to the oscillator 1 of the first to third embodiments.

[0201] In the oscillator 1 of the fifth embodiment described above, in the startup mode, when the oscillation detection circuit 80 detects that the signal output from the vibrator 3 has reached a predetermined amplitude or more, the negative resistance value |nR| is set to the first value |nR1| and the normal operation mode is entered, so the startup time can be shortened.

[0202] 6. Sixth Embodiment Hereinafter, regarding the oscillator 1 of the sixth embodiment, the same components as those in any of the above embodiments are denoted by the same reference numerals, and the same explanations as those in any of the above embodiments are omitted or simplified, and mainly the content different from any of the above embodiments will be described.

[0203] Since the configuration of the oscillator 1 of the sixth embodiment is the same as that in FIGS. 1 to 4, the illustration and description thereof are omitted. Also, since the configuration of the oscillation circuit 10 in the fourth embodiment is the same as that in FIG. 5, the illustration and description thereof are omitted.

[0204] In each of the above embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on the weighted multi-bit control data output from the control circuit 40.

[0205] For example, in the first embodiment or the fourth embodiment, in the startup mode, the negative resistance value |nR| is controlled by current adjustment data trimI[4:0] which is control data with a larger weight for larger bits. For example, when the logic level of trimI[0] is inverted, the oscillator stage current Iosc increases or decreases by I0, while when the logic level of trimI[4] is inverted, the oscillator stage current Iosc increases or decreases by 16×I0. Therefore, for example, when the current adjustment data trimI[4:0] changes from 15 to 16, if trimI[4] changes from high level to low level before trimI[0], trimI[1], trimI[2], and trimI[3] each change from high level to low level, the oscillator stage current Iosc will instantaneously increase by 16×I0. As a result, when the negative resistance value |nR| becomes larger than the value R of the series resistance under load when the vibrator 3 resonates in sub-vibration, the risk of abnormal oscillation occurring due to the vibrator 3 resonating in sub-vibration increases. Ls becomes larger than the risk of abnormal oscillation occurring due to the vibrator 3 resonating in sub-vibration increases.

[0206] Also, for example, in the second embodiment or the fourth embodiment, in the startup mode, the negative resistance value |nR| is controlled by capacitance adjustment data trimC1[4:0] and trimC2[4:0] which are control data with a larger weight for larger bits. For example, when the logic levels of trimC1[0] and trimC2[0] are inverted, the capacitance values C1 and C2 increase or decrease by C0 respectively, while when the logic levels of trimC1[4] and trimC2[4] are inverted, the capacitance values C1 and C2 increase or decrease by 16×C0 respectively. Therefore, for example, when the capacitance adjustment data trimC1[4:0] and trimC2[4:0] change from 15 to 16, if trimC1[4] changes from high level to low level before trimC1[0], trimC1[1], trimC1[2], and trimC1[3] each change from high level to low level, the capacitance value C1 will instantaneously increase by 16×C0. As a result of this, when the negative resistance value |nR| becomes larger than the value R of the series resistance under load when the vibrator 3 resonates in sub-vibration, the capacitance value C1 will instantaneously increase by 16×C0. As a result of this, when the negative resistance value |nR| becomes larger than the value R of the series resistance under load when the vibrator 3 resonates in sub-vibration, LsWhen it becomes larger than this, the risk of the resonator 3 resonating in sub-vibration and causing abnormal oscillation increases. The same can be said for the capacitance adjustment data trimC2[4:0].

[0207] Therefore, in the sixth embodiment, in order to reduce the risk of abnormal oscillation, the control circuit 40 is configured such that the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode changes its logic level earlier for bits with smaller weights.

[0208] FIG. 26 is a diagram showing a configuration example of the control circuit 40 in the sixth embodiment. FIG. 26 shows a configuration example of the control circuit 40 when the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode is the current adjustment data trimI[4:0]. In the example of FIG. 26, the control circuit 40 includes a logic circuit 42 and ten delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, 444. Similar to each of the above embodiments, the control circuit 40 also includes a voltage control circuit 41, but it is not shown in FIG. 26.

[0209] The logic circuit 42 outputs the current adjustment data trimIX[4:0]. trimIX[0] is output as trimI[0]. trimIX[1] is output as trimI[1] after propagating through the delay circuit 411. trimIX[2] is output as trimI[2] after propagating through the delay circuits 421, 422. trimIX[3] is output as trimI[3] after propagating through the delay circuits 431, 432, 433. trimIX[4] is output as trimI[4] after propagating through the delay circuits 441, 442, 443, 444.

[0210] The delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, 444 are circuits in which, for example, as shown in FIG. 27, four CMOS inverters 401, 402, 403, 404 are connected in series. Note that the number of CMOS inverters is not limited to four and may be any even number.

[0211] FIG. 28 is a diagram showing an example of waveforms of respective bits of the current adjustment data trimIX[4:0], trimI[4:0]. In the example of FIG. 28, waveforms of respective bits when the current adjustment data trimIX[4:0] changes from 15 to 16 are shown.

[0212] In the example of FIG. 28, the logic levels of respective bits of the current adjustment data trimIX[4:0] change simultaneously at time t1. Specifically, trimIX[0], trimIX[1], trimIX[2], trimIX[3] change from high level to low level, respectively, and trimIX[4] changes from low level to high level.

[0213] Since trimIX[0] is output as trimI[0] without propagating through the delay circuit, at time t1, trimI[0] changes from high level to low level. Also, after time t1, the low level of trimIX[1] propagates through the delay circuit 411, and at time t2, trimI[1] changes from high level to low level. Also, after time t1, the low level of trimIX[2] propagates through the delay circuits 421, 422, and at time t3, trimI[2] changes from high level to low level. Also, after time t1, the low level of trimIX[3] propagates through the delay circuits 431, 432, 433, and at time t4, trimI[3] changes from high level to low level. Also, after time t1, the high level of trimIX[4] propagates through the delay circuits 441, 442, 443, 444, and at time t5, next, trimI[4] changes from low level to high level.

[0214] Thus, the current adjustment data trimI[4:0] output to the oscillation circuit 10 changes its logic level earlier in the order of trimI[0], trimI[1], trimI[2], trimI[3], trimI[4], that is, the bits with smaller weights change their logic levels earlier.

[0215] Although not shown, the control circuit 40 in the case where the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode is the capacitance adjustment data trimC1[4:0] and trimC2[4:0] is also configured in the same manner as in FIG. 26.

[0216] Since other configurations of the oscillator 1 according to the sixth embodiment are the same as those of the above embodiments, the illustration and description thereof are omitted.

[0217] In the oscillator 1 according to the sixth embodiment described above, in the startup mode, when increasing the negative resistance value |nR| of the oscillation circuit 10, the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] change their logic levels earlier for the bits with smaller weights. Therefore, according to the oscillator 1 of the sixth embodiment, when increasing the negative resistance value |nR| of the oscillation circuit 10, the negative resistance value |nR| does not increase rapidly transiently, so the oscillation based on the resonance in the sub-oscillation of the vibrator 3 is less likely to grow and cause abnormal oscillation.

[0218] 7. Seventh Embodiment Hereinafter, for the oscillator 1 according to the seventh embodiment, the same components as those in any of the above embodiments are denoted by the same reference numerals, the same explanations as those in any of the above embodiments are omitted or simplified, and mainly the contents different from any of the above embodiments will be described.

[0219] Since the configuration of the oscillator 1 according to the seventh embodiment is the same as that in FIGS. 1 to 4, the illustration and description thereof are omitted.

[0220] In each of the above embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on a plurality of weighted bits of control data output from the control circuit 40. Therefore, as described above, except for the sixth embodiment, the risk of the vibrator 3 resonating in sub-oscillation and causing abnormal oscillation increases.

[0221] Therefore, in the seventh embodiment, in order to reduce the risk of abnormal oscillation, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on a plurality of unweighted bits of control data output from the control circuit 40. The plurality of unweighted bits of control data may be data represented by a thermometer code.

[0222] For example, in the startup mode, the oscillation stage current Iosc output from the variable current source 12 of the oscillation circuit 10 is controlled based on 32-bit unweighted current adjustment data trimI[31:0], whereby the negative resistance value |nR| may be controlled. Also, for example, in the startup mode, the capacitance values C1, C2 of the variable capacitance circuits 14, 15 of the oscillation circuit 10 are controlled based on 32-bit unweighted capacitance adjustment data trimC1[31:0], trimC2[31:0], whereby the negative resistance value |nR| may be controlled.

[0223] FIG. 29 is a diagram showing a configuration example of the variable current source 12 controlled by 32-bit unweighted current adjustment data trimI[31:0]. In the example of FIG. 29, the variable current source 12 includes a current source 135, 32 current sources 136-0 to 136-31, 32 switch elements 137-0 to 137-31, and two P-channel MOS transistors 133, 134.

[0224] The P-channel MOS transistor 133 has its gate and drain connected, and a voltage Vreg is supplied to the source. The P-channel MOS transistor 134 has its gate connected to the gate of the P-channel MOS transistor 133, a voltage Vreg is supplied to the source, and its drain is connected to the collector of the amplifying element 11 in FIG. 5.

[0225] One end of the current source 135 is connected to the drain of the P-channel MOS transistor 133, and the other end is grounded, and a constant bias current I b flows. For each integer i from 0 to 31, one end of the current source 136-i is connected to the drain of the P-channel MOS transistor 133 via the switch element 137-i, and the other end is grounded. When the switch element 137-i is in the conducting state, a constant current I0 flows. For example, the current sources 135, 136-0 to 136-31 may be configured using depletion-type N-channel MOS transistors or may be configured using a current mirror circuit.

[0226] For each integer i from 0 to 31, the switch element 137-i has the data trimI[i] of bit i of the current adjustment data trimI[31:0] input to its control terminal, conducts when the data trimI[i] is at a high level, and does not conduct when the data trimI[i] is at a low level. For example, the switch elements 137-0 to 137-31 may be N-channel MOS transistors or may be transmission gates.

[0227] FIG. 30 is a diagram showing the relationship between the value of each bit of the current adjustment data trimI[31:0] and the value of the oscillation-stage current Iosc output from the variable current source 12 shown in FIG. 29. 0 of each bit corresponds to a low level, and 1 of each bit corresponds to a high level. For example, when bit 0 of the current adjustment data trimI[31:0] is 1 and bits 1 to 31 are 0, only the switch element 137-0 conducts and the oscillation-stage current Iosc = I b + I0. Also, for example For example, when bits 0 and 1 of the current adjustment data trimI[31:0] are 1 and bits 2 to 31 are 0, only two switch elements 137-0 and 137-1 are turned on, and the oscillation stage current Iosc = I b +2I0. Generally, among the 32 bits of the current adjustment data trimI[31:0 , if the number of bits with a value of 1 is N and the number of bits with a value of 0 is 32 - N, the oscillation stage current Iosc = I b +N×I0. The code shown in FIG. 30 is such that all the values of bits 0 to 31 are 0, all the values of bits 0 to 31 are 1, or for any integer j from 0 to 30, all the values of bits 0 to j are 1 and all the values of bits j + 1 to 31 are 0. Such a code is called a thermometer code. Although not shown, in the startup mode, the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 of the oscillation circuit 10 are also configured in the same manner as in FIGS. 29 and 30 for the variable capacitance circuits 14 and 15 and the capacitance adjustment data trimC1[31:0], trimC2[31:0] when controlled based on the 32-bit capacitance adjustment data trimC1

[0228] [31:0], trimC2[31:0] without weighting. [31:0], trimC2[31:0] are also configured in the same manner as in FIGS. 29 and 30.

[0229] The other configurations of the oscillator 1 of the seventh embodiment are the same as those of the above embodiments, and thus the illustration and description thereof are omitted.

[0230] In the oscillator 1 of the seventh embodiment described above, in the startup mode, when increasing the negative resistance value |nR| of the oscillation circuit 10, the current adjustment data trimI[31:0], the capacitance adjustment data trimC1[31:0], and trimC2[31:0] are data that are not weighted, for example, data represented by a thermometer code. Therefore, according to the oscillator 1 of the seventh embodiment, when increasing the negative resistance value |nR| of the oscillation circuit 10, the negative resistance value |nR| does not increase rapidly transiently, so the oscillation based on the resonance in the sub-oscillation of the vibrator 3 is less likely to grow and cause abnormal oscillation.

[0231] 8. Modification In the oscillator 1 of the first embodiment or the fourth embodiment described above, in the startup mode, the logic circuit 42 controls the negative resistance value |nR| to increase stepwise by increasing the value of the oscillation stage current Iosc stepwise. However, the negative resistance value |nR| may be controlled to increase continuously by increasing the value of the oscillation stage current Iosc continuously.

[0232] Also, in the oscillator 1 of the second embodiment or the fourth embodiment described above, in the startup mode, the logic circuit 42 controls the negative resistance value |nR| to increase stepwise by increasing at least one of the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 stepwise. However, the negative resistance value |nR| may be controlled to increase continuously by increasing at least one of the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 continuously. Increasing at least one of the capacitance values C1 and C2 of the variable capacitance circuits 14 and 15 continuously so that the negative resistance value |nR| increases continuously.

[0233] Also, the oscillator 1 in each of the above embodiments is an oscillator having a frequency control function such as a VCXO (Voltage Controlled Crystal Oscillator), but it may also be an oscillator having a temperature compensation function such as a TCXO (Temperature Compensated Crystal Oscillator), an oscillator having a temperature compensation function and a frequency control function such as a VC-TCXO (Voltage Controlled Temperature Compensated Crystal Oscillator), a simple oscillator having no temperature compensation function and no frequency control function such as an SPXO (Simple Packaged Crystal Oscillator), an oscillator having a temperature control function such as an OCXO (Oven Controlled Crystal Oscillator), etc. VCXO is the abbreviation of Voltage Controlled Crystal Oscillator. TCXO is the abbreviation of Temperature Compensated Crystal Oscillator. VC-TCXO is the abbreviation of Voltage Controlled Temperature Compensated Crystal Oscillator. SPXO is the abbreviation of Simple Packaged Crystal Oscillator. OCXO is the abbreviation of Oven Controlled Crystal Oscillator. When the oscillator 1 is an oscillator having a temperature compensation function or an oscillator having a temperature compensation function and a frequency control function, in the startup mode, the temperature compensation circuit may increase the negative resistance value by decreasing the capacitance value of the variable capacitance circuit.

[0234] The present invention is not limited to this embodiment, and various modifications can be made within the scope of the gist of the present invention.

[0235] The above-described embodiments and modifications are examples and are not necessarily limited thereto. For example, it is also possible to appropriately combine each embodiment and each modification.

[0236] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations having the same functions, methods, and results, or configurations having the same objectives and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that exhibit the same operational effects as the configurations described in the embodiments or configurations that can achieve the same objectives. The present invention also includes configurations in which known techniques are added to the configurations described in the embodiments.

[0237] The following content is derived from the above-described embodiments and variations.

[0238] One aspect of the oscillation circuit is an oscillation circuit connected to an oscillator, and a control circuit that controls the oscillation circuit, and the oscillation circuit has a normal operation mode in which it oscillates with a negative resistance value being a first value, and a startup mode from a state where the oscillation circuit has stopped oscillating until it transitions to the normal operation mode, and the control circuit controls the negative resistance value to increase from a second value smaller than the first value in the startup mode.

[0239] In this oscillation circuit, in the startup mode from a state where the oscillation circuit has stopped oscillating until it transitions to the normal operation mode in which the oscillation circuit oscillates with a negative resistance value being a first value, the negative resistance value of the oscillation circuit increases from a second value smaller than the first value. The value R of the load series resistance when the oscillator resonates at the main vibration Lm is smaller than the value R of the load series resistance when the oscillator resonates at the sub-vibration, Ls so the negative resistance value of the oscillation circuit increases from the second value to a value larger than R Lm and smaller than R Ls Therefore, in the startup mode In this case, the oscillation based on the resonance of the main vibration of the vibrator grows earlier than the oscillation based on the resonance of the sub-vibration of the vibrator. Therefore, according to this oscillation circuit, even if there are variations in the characteristics of the connected vibrator, the risk of abnormal oscillation can be reduced.

[0240] In one aspect of the oscillation circuit, The control circuit In the startup mode, it may be controlled such that the negative resistance value increases stepwise.

[0241] In this oscillation circuit, in the startup mode, since the negative resistance value of the oscillation circuit increases stepwise from the second value, the time when it is Lm greater than R and Ls less than R becomes longer. Therefore, the oscillation based on the resonance of the main vibration of the vibrator grows earlier than the oscillation based on the resonance of the sub-vibration of the vibrator. Therefore, according to this oscillation circuit, even if there are variations in the characteristics of the connected vibrator, the risk of abnormal oscillation can be reduced.

[0242] In one aspect of the oscillation circuit, The control circuit In the startup mode, it may be controlled such that the negative resistance value increases continuously.

[0243] In this oscillation circuit, in the startup mode, since the negative resistance value of the oscillation circuit increases continuously from the second value, the time when it is Lm greater than R and Ls less than R becomes longer. Therefore, the oscillation based on the resonance of the main vibration of the vibrator grows earlier than the oscillation based on the resonance of the sub-vibration of the vibrator. Therefore, according to this oscillation circuit, even if there are variations in the characteristics of the connected vibrator, the risk of abnormal oscillation can be reduced.

[0244] In one aspect of the oscillation circuit, The first value may be equal to or greater than the maximum value of the negative resistance value in the startup mode.

[0245] According to this oscillation circuit, in the startup mode, since the negative resistance value of the oscillation circuit does not become larger than the first value, the time during which the negative resistance value of the oscillation circuit becomes larger than the value R of the series resistance under load when the vibrator resonates in sub-oscillation is short, and resonance in the sub-oscillation of the vibrator is less likely to occur. Ls to occur. to occur.

[0246] In one aspect of the oscillation circuit, the oscillation circuit includes an amplification element and a variable current source that supplies current to the amplification element, and the control circuit may increase the negative resistance value by increasing the value of the current in the startup mode.

[0247] According to this oscillation circuit, for example, a variable current source for setting the current supplied to the amplification element to a desired value according to the resonance frequency of the vibrator in the normal operation mode can be also used for increasing the negative resistance value of the oscillation circuit in the startup mode.

[0248] In one aspect of the oscillation circuit, the oscillation circuit includes a variable capacitance circuit connected to a node connected to the vibrator, and the control circuit may increase the negative resistance value by decreasing the capacitance value of the variable capacitance circuit in the startup mode.

[0249] According to this oscillation circuit, for example, a variable capacitance circuit for setting the oscillation frequency of the oscillation circuit to a target frequency in the normal operation mode can be also used for increasing the negative resistance value of the oscillation circuit in the startup mode.

[0250] In one aspect of the oscillation circuit, the oscillation circuit includes an amplification element, a variable current source that supplies current to the amplification element, and a variable capacitance circuit connected to a node connected to the vibrator. In the startup mode, the control circuit may increase the negative resistance value by increasing the value of the current and decreasing the capacitance value of the variable capacitance circuit.

[0251] According to this oscillation circuit, for example, in the normal operation mode, a variable current source for setting the current supplied to the amplification element to a desired value according to the resonance frequency of the vibrator and a variable capacitance circuit for setting the oscillation frequency of the oscillation circuit to the target frequency are used also for increasing the negative resistance value of the oscillation circuit in the startup mode. Further, according to this oscillation circuit, in the startup mode, since the value of the current supplied to the amplification element is increased and the capacitance value of the variable capacitance circuit is decreased, it is possible to reduce the possibility that the capacitance value of the variable capacitance circuit is too large or the value of the current supplied to the amplification element is too small and the oscillation circuit does not oscillate.

[0252] In one aspect of the oscillation circuit, in the startup mode, the control circuit may repeatedly perform control to increase the value of the current from a third value to a fourth value greater than the third value without changing the capacitance value, and then decrease the capacitance value and change the value of the current to the third value.

[0253] According to this oscillation circuit, in the startup mode, while changing the capacitance value of the variable capacitance circuit, the control of increasing the value of the current supplied to the amplification element from the third value to the upper limit value is repeatedly performed, so that it is possible to reduce the possibility that the capacitance value of the variable capacitance circuit is too large or the value of the current supplied to the amplification element is too small and the oscillation circuit does not oscillate. Further, in this oscillation circuit, after the control circuit increases the value of the current supplied to the amplification element from the third value to the fourth value, by changing the value of the current supplied to the amplification element to the third value before decreasing the capacitance value of the variable capacitance circuit, it is possible to reduce the possibility that the negative resistance value rapidly increases and the vibrator resonates with sub-oscillation when the capacitance value of the variable capacitance circuit is decreased.

[0254] One aspect of the oscillation circuit is In the starting mode, an oscillation detection circuit is provided which detects that a signal output from the vibrator has reached a predetermined amplitude or more and outputs a detection signal. Based on the detection signal, the control circuit may set the negative resistance value to the first value.

[0255] According to this oscillation circuit, when the oscillation circuit for oscillation oscillates in the starting mode, the negative resistance value is set to the first value and the circuit shifts to the normal operation mode, so that the starting time can be shortened.

[0256] In one aspect of the oscillation circuit, the negative resistance value is controlled based on weighted multi-bit control data, and the control data may change its logic level earlier for bits with smaller weighting.

[0257] According to this oscillation circuit, when increasing the negative resistance value of the oscillation circuit, the negative resistance value does not increase rapidly transiently, so the oscillation based on resonance in the sub-vibration of the vibrator is less likely to grow into abnormal oscillation.

[0258] In one aspect of the oscillation circuit, the negative resistance value may be controlled based on unweighted multi-bit control data.

[0259] According to this oscillation circuit, when increasing the negative resistance value of the oscillation circuit, the negative resistance value does not increase rapidly transiently, so the oscillation based on resonance in the sub-vibration of the vibrator is less likely to grow into abnormal oscillation.

[0260] In one aspect of the oscillation circuit, the control data may be data represented by a thermometer code.

[0261] One aspect of the oscillator is one aspect of the oscillation circuit and the vibrator.

[0262] In this oscillator, in the startup mode from the state where the oscillation circuit is stopped to the normal operation mode where the oscillation circuit oscillates with the negative resistance value of the oscillation circuit being the first value, the negative resistance value of the oscillation circuit increases from a second value smaller than the first value. The value R of the series resistance under load when the vibrator resonates in the main oscillation Lm is smaller than the value R of the series resistance under load when the vibrator resonates in the sub-oscillation Therefore, the negative resistance value of the oscillation circuit increases from the second value and becomes larger than R Ls and smaller than R Accordingly, in the startup mode, the oscillation based on the resonance of the main oscillation of the vibrator grows earlier than the oscillation based on the resonance of the sub-oscillation of the vibrator. Therefore, according to this oscillator, even if there are variations in the characteristics of the vibrator, the risk of abnormal oscillation can be reduced. Lm and smaller than R Ls For this reason, in the startup mode, the oscillation based on the resonance of the main oscillation of the vibrator grows earlier than the oscillation based on the resonance of the sub-oscillation of the vibrator. Therefore, according to this oscillator, even if there are variations in the characteristics of the vibrator, the risk of abnormal oscillation can be reduced. For this reason, in the startup mode, the oscillation based on the resonance of the main oscillation of the vibrator grows earlier than the oscillation based on the resonance of the sub-oscillation of the vibrator. Therefore, according to this oscillator, even if there are variations in the characteristics of the vibrator, the risk of abnormal oscillation can be reduced.

[0263] One aspect of the control method of the oscillation circuit is a control method of an oscillation circuit including an oscillation circuit connected to a vibrator, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates with a negative resistance value being a first value and a startup mode from a state where the oscillation circuit is stopped to the normal operation mode, the control method comprising in the startup mode, controlling the negative resistance value to increase from a second value smaller than the first value.

[0264] In this control method of the oscillation circuit, in the startup mode from the state where the oscillation circuit is stopped to the normal operation mode where the oscillation circuit oscillates with the negative resistance value of the oscillation circuit being the first value, the negative resistance value of the oscillation circuit increases from a second value smaller than the first value. The value R of the series resistance under load when the vibrator resonates in the main oscillation Lm is smaller than the value R of the series resistance under load when the vibrator resonates in the sub-oscillation when the vibrator resonates in the sub-oscillation Ls is smaller than the value R of the series resistance under load when the vibrator resonates in the sub-oscillation Therefore, the negative resistance value of the oscillation circuit increases from the second value and becomes larger than R Lmis larger than and R Ls is smaller than that value. Therefore, In the startup mode, oscillation based on resonance in the main vibration of the vibrator grows prior to oscillation based on resonance in the sub-vibration of the vibrator. Therefore, according to this method of controlling the oscillation circuit, even if there are variations in the characteristics of the connected vibrator, the risk of abnormal oscillation can be reduced.

Description of Signs

[0265] 1... Oscillator, 2... Oscillation circuit, 3... Vibrator, 3a... Excitation electrode, 3b... Excitation electrode, 4... Package, 5... Lid, 6... External terminal, 7... Accommodation chamber, 10... Oscillation circuit, 11... Amplifying element, 12... Variable current source, 13... Resistor, 14... Variable capacitance circuit, 15... Variable capacitance circuit, 16... Variable capacitance circuit, 17... Variable capacitance circuit, 20... Power supply circuit, 30... Power-on reset circuit, 40... Control circuit, 41... Voltage control circuit, 42... Logic circuit, 50... Reference voltage generation circuit, 60... Output circuit, 70... Memory circuit, 71... Non-volatile memory, 72... Register, 80... Oscillation detection circuit, 100, 101, 102, 103, 104, 110, 111, 112, 113, 114... CMOS inverter, 120, 121, 122, 123, 124... Current source, 125, 126, 127, 128, 129... Switch element, 130... Current source, 131, 132... P-channel MOS transistor, 133, 134... P-channel MOS transistor, 135... Current source, 136-0 to 136-31... Current source, 137-0 to 137-31... Switch element, 140, 141, 142, 143, 144... Capacitance element, 145, 146, 147, 148, 149... Switch element, 150, 151, 152, 153, 154... Capacitance element, 155, 156, 157, 158, 159... Switch element, 160... Variable capacitance element, 161-1 to 161-n... Variable capacitance element, 162-1 to 162-n... Capacitance element, 163-1 to 163-n... Capacitance element, 170... Variable capacitance element, 171-1 to 171-n... Variable capacitance element, 172-1 to 172-n... Capacitance element, 173-1 to 173-n... Capacitance element, 200... Control voltage generation circuit, 210... Filter circuit, 211... Resistor, 212... Capacitance element, 220... Switch circuit, 230... Filter circuit, 231... Resistor, 232... Capacitance element, 240... Switch circuit, 250... Resistor, 260... Resistor, 300... Current source, 301... Capacitance element, 302, 303, 304... Variable resistor, 305, 306, 307, 308, 309... N-channel MOS transistor, 310... Comparator, 311, 312... CMOS inverter, 313... N-channel MOS transistor, 314, 315... Capacitance element, 401, 402, 403, 404... CMOS inverter, 411, 421, 422, 431, 432, 433, 441, 442, 443, 444... Delay circuit

Claims

1. an oscillation circuit connected to the oscillator; A control circuit for controlling the oscillation circuit, a normal operation mode in which the oscillation circuit oscillates in a state in which the negative resistance value is a first value; a startup mode from a state in which the oscillation circuit stops oscillating to a state in which the normal operation mode is transitioned to; The control circuit includes: In the startup mode, the oscillation circuit controls the negative resistance value so as to increase from a second value smaller than the first value.

2. The control circuit includes:

2. The oscillation circuit according to claim 1, wherein in the start-up mode, the negative resistance value is controlled to increase in a stepwise manner.

3. The control circuit includes:

2. The oscillation circuit according to claim 1, wherein in the startup mode, the negative resistance value is controlled to increase continuously.

4. 4. The oscillation circuit according to claim 1, wherein the first value is equal to or greater than a maximum value of the negative resistance in the startup mode.

5. the oscillation circuit includes an amplifying element and a variable current source that supplies a current to the amplifying element; 5. The oscillation circuit according to claim 1, wherein the control circuit increases the negative resistance value by increasing the value of the current in the startup mode.

6. 5. The oscillation circuit according to claim 1, wherein the oscillation circuit includes a variable capacitance circuit connected to a node connected to the vibrator, and the control circuit increases the negative resistance value by decreasing a capacitance value of the variable capacitance circuit in the startup mode.

7. the oscillation circuit includes an amplifying element, a variable current source that supplies a current to the amplifying element, and a variable capacitance circuit that is connected to a node that is connected to the vibrator; 5. The oscillation circuit according to claim 1, wherein the control circuit increases the negative resistance value by increasing the current value and decreasing the capacitance value of the variable capacitance circuit in the startup mode.

8. 8. The oscillation circuit according to claim 7, wherein in the startup mode, the control circuit repeatedly performs control to increase the value of the current from a third value to a fourth value greater than the third value without changing the capacitance value, and then decrease the capacitance value and change the value of the current to the third value.

9. an oscillation detection circuit that detects when the signal output from the vibrator reaches or exceeds a predetermined amplitude in the startup mode and outputs a detection signal; The oscillation circuit according to claim 1 , wherein the control circuit sets the negative resistance value to the first value based on the detection signal.

10. the negative resistance value is controlled based on weighted multi-bit control data; 10. The oscillation circuit according to claim 1, wherein the control data has a logic level that changes more quickly for a bit with a smaller weight.

11. 10. The oscillator circuit according to claim 1, wherein the negative resistance value is controlled based on unweighted multi-bit control data.

12. 12. The oscillator circuit according to claim 11, wherein the control data is data represented by a thermometer code.

13. An oscillator circuit according to any one of claims 1 to 12; An oscillator comprising the vibrator.

14. A method for controlling an oscillation circuit, comprising: an oscillation circuit connected to a vibrator, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates with a first negative resistance value; and a startup mode in which the oscillation circuit transitions from a state in which oscillation has stopped to the normal operation mode, the method comprising: A method for controlling an oscillation circuit, comprising: in the startup mode, controlling the negative resistance value so as to increase from a second value smaller than the first value.

Images