Semiconductor device and manufacturing method of semiconductor device

Abstract

To suppress an occurrence of short circuits and an increase in a leakage current in a semiconductor device.SOLUTION: A semiconductor device 10 includes: a semiconductor layer 12 having a first surface 12A, a second surface 12B opposite to the first surface 12A, and an outer peripheral surface 12C connecting the first surface 12A and the second surface 12B; and an element structure 20, a portion of which is constituted by the semiconductor layer 12. The semiconductor layer 12 includes a first conductivity-type first semiconductor layer 14 including at least a portion of the first surface 12A, and a second conductivity-type second semiconductor layer 16 located on the first semiconductor layer 14. The outer peripheral surface 12C includes an upper side surface 94 connected to the second surface 12B, a lower side surface 96 connected to the first surface 12A, the lower side surface 96 being recessed from the upper side surface 94 in a direction from an outer peripheral region 24 toward an active region 22, and a connecting surface 98 connecting the upper side surface 94 and the lower side surface 96. The connecting surface 98 is located away from an interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16 towards the first surface 12A.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including an insulated gate bipolar transistor having a trench gate structure. Such a semiconductor device configured as a semiconductor chip is generally mounted on a support substrate via a conductive bonding material.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] When mounting a semiconductor device on a support substrate, a short circuit or an increase in leakage current may occur through the conductive bonding material used.

[0005] A semiconductor device according to an aspect of the present disclosure includes a semiconductor layer having a first surface, a second surface opposite to the first surface, and an outer peripheral surface connecting the first surface and the second surface, the semiconductor layer including a first semiconductor layer of a first conductivity type including at least a part of the first surface, and a second semiconductor layer of a second conductivity type located on the first semiconductor layer, and an element structure partially constituted by the semiconductor layer. The semiconductor layer includes an active region where the element structure is located, and an outer peripheral region surrounding the active region in plan view and including the outer peripheral surface of the semiconductor layer. The outer peripheral surface includes an upper side surface connected to the second surface and a lower side surface connected to the first surface, the lower side surface being recessed from the upper side surface in a direction from the outer peripheral region toward the active region, and a connection surface connecting the upper side surface and the lower side surface. The connection surface is located away from the first surface from an interface between the first semiconductor layer and the second semiconductor layer.

[0006] Other features and aspects will become apparent from the following detailed description, the drawings, and the claims.

Brief Description of the Drawings

[0007]

Figure 1

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Figure 10

Figure 11

[0008] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative sizes, ratios, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0009] The following detailed description provides a comprehensive understanding of the described methods, apparatuses, and / or systems. Modifications and equivalents of the described methods, apparatuses, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is exemplary and can be changed as will be apparent to those skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted.

[0010] Exemplary embodiments may have different forms and are not limited to the examples described. However, the described examples are detailed and complete and convey the full scope of the present disclosure to those skilled in the art.

[0011] Referring to FIGS. 1 to 4, an exemplary semiconductor device 10 according to an embodiment will be described. The semiconductor device 10 may be configured as a semiconductor chip on which an Insulated Gate Bipolar Transistor (IGBT) is formed. FIG. 1 is a schematic plan view of the exemplary semiconductor device 10. FIG. 2 is a schematic plan view of a portion of the semiconductor device 10 in FIG. 1 surrounded by the dashed-dotted line F2. FIG. 3 is a schematic cross-sectional view of the semiconductor device 10 taken along the line F3 - F3 in FIG. 2. FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along the line F4 - F4 in FIG. 1.

[0012] The Z-axis direction of the XYZ axes orthogonal to each other shown in FIGS. 1 to 4 is a direction orthogonal to the first surface 12A of the semiconductor layer 12 (see, for example, FIG. 3). Note that the term "plan view" as used in this specification means viewing the semiconductor device 10 from above along the Z-axis direction (for example, from the side of the second surface 12B of the semiconductor layer 12) unless otherwise explicitly stated.

[0013] <Schematic Structure of Semiconductor Device> As shown in FIGS. 1 to 4, the semiconductor device 10 includes a semiconductor layer 12. The semiconductor layer 12 has a first surface 12A, a second surface 12B opposite to the first surface 12A, and an outer peripheral surface 12C connecting the first surface 12A and the second surface 12B. The semiconductor layer 12 may be rectangular in plan view. The semiconductor layer 12 may contain silicon (Si). In one example, the semiconductor layer 12 may be substantially composed of silicon.

[0014] The semiconductor layer 12 includes a p-type first semiconductor layer 14 and an n-type second semiconductor layer 16 located on the first semiconductor layer 14. In the present disclosure, the p-type may be referred to as the first conductivity type, and the n-type may be referred to as the second conductivity type. The p-type impurity may be, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In), etc. The n-type impurity may be, for example, phosphorus (P), arsenic (As), and / or antimony (Sb), etc.

[0015] The first semiconductor layer 14 includes at least a part of the first surface 12A of the semiconductor layer 12. In one example, the first semiconductor layer 14 may be a p-type semiconductor substrate. More specifically, the first semiconductor layer 14 may be a p-type silicon substrate. In one example, the first semiconductor layer 14 may have a thickness (dimension in the Z-axis direction) of 160 μm to 185 μm.

[0016] The second semiconductor layer 16 may be located between the first semiconductor layer 14 and the second surface 12B of the semiconductor layer 12. In one example, the second semiconductor layer 16 may be an n-type epitaxial layer. More specifically, the second semiconductor layer 16 may be an n-type silicon epitaxial layer. In one example, the second semiconductor layer 16 may have a thickness of 60 μm to 85 μm. An interface 100 may exist between the first semiconductor layer 14 and the second semiconductor layer 16.

[0017] The semiconductor device 10 may include an insulating layer 18 located on the semiconductor layer 12. The insulating layer 18 may cover the second surface 12B of the semiconductor layer 12. The insulating layer 18 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and aluminum oxide (Al2O3). The insulating layer 18 may be composed of a single insulating layer or may include a plurality of different insulating layers.

[0018] The semiconductor device 10 includes an element structure 20 partially constituted by the semiconductor layer 12. The element structure 20 may include an IGBT as described later with reference to FIGS. 2 and 3. Note that the element structure 20 is not limited to only the IGBT. For example, the element structure 20 may include an element other than the IGBT such as a diode.

[0019] As shown in FIG. 1, the semiconductor layer 12 includes an active region 22 where the element structure 20 (see FIGS. 2 and 3) is located and an outer peripheral region 24 surrounding the active region 22 in plan view. The outer peripheral region 24 includes the outer peripheral surface 12C of the semiconductor layer 12. The outer peripheral surface 12C may extend in a rectangular shape in plan view. Accordingly, the outer peripheral region 24 including the outer peripheral surface 12C may extend in a rectangular frame shape in plan view. In FIG. 1, two active regions 22 are shown, but the arrangement of the active region 22 and the outer peripheral region 24 can be appropriately determined according to the desired characteristics of the semiconductor device 10 and is not limited to the illustrated example.

[0020] As shown in FIG. 1, the semiconductor device 10 may include a gate electrode 26 and an emitter electrode 28. The gate electrode 26 and the emitter electrode 28 may be located on the insulating layer 18. The gate electrode 26 and the emitter electrode 28 are separated from each other. The emitter electrode 28 may cover at least the active region 22. In the illustrated example, the gate electrode 26 includes a gate pad portion 30, an inner gate finger portion 32, and an outer peripheral gate finger portion 34. The inner gate finger portion 32 is connected to the gate pad portion 30 and may extend in the X-axis direction through between the two active regions 22. The outer peripheral gate finger portion 34 is connected to the gate pad portion 30 and is located in the outer peripheral region 24. Each active region 22 may be at least partially surrounded in plan view by the inner gate finger portion 32 and the outer peripheral gate finger portion 34. Also, in the illustrated example, the emitter electrode 28 includes an emitter pad portion 36 and an emitter finger portion 38. The emitter pad portion 36 may cover the active region 22. The emitter finger portion 38 is connected to the emitter pad portion 36 and may be located in the outer peripheral region 24. At least a part of the emitter finger portion 38 may surround the outer peripheral gate finger portion 34 in plan view. The outer peripheral gate finger portion 34 may be located between the emitter pad portion 36 and the emitter finger portion 38. Note that the arrangements of the gate electrode 26 and the emitter electrode 28 can be appropriately determined according to the desired characteristics of the semiconductor device 10 and are not limited to the illustrated example.

[0021] The gate electrode 26 may contain at least one of aluminum (Al), copper (Cu), aluminum alloy, copper alloy, tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The gate electrode 26 may be composed of a single metal layer or may include a plurality of different metal layers.

[0022] The emitter electrode 28 may include at least one of aluminum, copper, aluminum alloy, copper alloy, tungsten, molybdenum, nickel, titanium, titanium nitride, tantalum, and tantalum nitride. The emitter electrode 28 may be composed of a single metal layer or may include a plurality of different metal layers.

[0023] As shown in FIG. 1, the semiconductor device 10 may include a plurality of field electrodes 40 and channel stop electrodes 42 located in the outer peripheral region 24. The plurality of field electrodes 40 and channel stop electrodes 42 may be located on the insulating layer 18. The plurality of field electrodes 40 may extend so as to surround the emitter electrode 28 in a plan view. The plurality of field electrodes 40 and the emitter electrode 28 are spaced apart from each other. Also, the plurality of field electrodes 40 are spaced apart from each other. The channel stop electrode 42 may extend so as to surround the plurality of field electrodes 40 in a plan view. The channel stop electrode 42 and the plurality of field electrodes 40 are spaced apart from each other.

[0024] It should be understood that the layout of the semiconductor device 10 shown in FIG. 1 is an example, and different layouts may be adopted according to the desired characteristics of the semiconductor device 10. For example, the position and size of the active region 22 may be different from the example shown in FIG. 1.

[0025] As shown in FIGS. 3 and 4, the semiconductor device 10 may include a collector electrode 44 formed on the first surface 12A of the semiconductor layer 12. The collector electrode 44 may include at least one of titanium, nickel, palladium (Pd), gold (Au), silver (Ag), and aluminum. The collector electrode 44 may be composed of a single metal layer or may include a plurality of different metal layers.

[0026] The collector electrode 44 is in contact with the first semiconductor layer 14. In the illustrated example, the p-type first semiconductor layer 14 can also be referred to as the collector region of the IGBT. The collector electrode 44 can form an ohmic contact with the first semiconductor layer 14 (collector region). In one example, the p-type impurity concentration of the first semiconductor layer 14 is 1×10 15 cm -3 or more and 1×10 18 cm -3 or less.

[0027] The second semiconductor layer 16 may include an n-type buffer region 46 located on the first semiconductor layer 14 and an n-type drift region 48 located on the buffer region 46. The drift region 48 has a lower n-type impurity concentration than the buffer region 46. In one example, the n-type impurity concentration of the buffer region 46 is 1×10 15 cm -3 or more and 1×10 17 cm -3 or less. Also, in one example, the n-type impurity concentration of the drift region 48 is 1×10 13 cm -3 or more and 1×10 15 cm -3 or less.

[0028] In the illustrated example, the interface 100 corresponds to the interface between the p-type collector region (first semiconductor layer 14) and the n-type buffer region 46. Note that the second semiconductor layer 16 does not necessarily include the buffer region 46, and in that case, the interface 100 may correspond to the interface between the p-type collector region (first semiconductor layer 14) and the n-type drift region 48.

[0029] <Active region> Figures 2 and 3 show an example of the semiconductor device 10 in the active region 22. Hereinafter, with reference to Figures 2 and 3, an example in the case where the element structure 20 formed in the active region 22 is an IGBT will be described.

[0030] As shown in FIGS. 2 and 3, in the active region 22, the semiconductor device 10 may include a plurality of gate trenches 50 extending from the second surface 12B into the semiconductor layer 12. In the illustrated example, each of the plurality of gate trenches 50 extends in the Y-axis direction in plan view. The plurality of gate trenches 50 are spaced apart from each other in the X-axis direction in plan view.

[0031] The semiconductor device 10 includes an embedded electrode 52 located within the gate trench 50 and separated from the semiconductor layer 12 by an insulating layer 18. The embedded electrode 52 may be formed of conductive polysilicon. In another example, the embedded electrode 52 may be formed of any other conductive material.

[0032] The insulating layer 18 may include a first insulating layer 54 and a second insulating layer 56 located on the first insulating layer 54. The first insulating layer 54 can cover the second surface 12B of the semiconductor layer 12 and the walls of the gate trench 50. The embedded electrode 52 may be embedded within the gate trench 50 via the first insulating layer 54. The second insulating layer 56 may cover the embedded electrode 52 within the gate trench 50.

[0033] In one example, the gate trench 50 may have a depth (dimension in the Z-axis direction) of 1 μm or more and 30 μm or less. Also, in one example, the gate trench 50 may have a width (dimension in the X-axis direction) of 0.1 μm or more and 1 μm or less. In the illustrated example, the side walls of the gate trench 50 extend in the Z-axis direction, but in another example, they may be inclined with respect to the Z-axis direction.

[0034] As shown in FIG. 3, in the active region 22, the semiconductor layer 12 may include an n-type carrier storage region 58 located on the drift region 48, a p-type base region 60 located on the carrier storage region 58, and an n-type emitter region 62 located on the base region 60 and including a part of the second surface 12B of the semiconductor layer 12.

[0035] The carrier storage region 58 may have an n-type impurity concentration higher than that of the drift region 48. The n-type impurity concentration of the carrier storage region 58 may be 1×10 15 cm -3 or more and 1×10 17 cm -3 or less. By providing the carrier storage region 58, the discharge of carriers (holes) to the base region 60 can be suppressed, and the accumulation of carriers (holes) in the region directly below the gate trench 50 can be promoted. Therefore, the carrier storage region 58 can reduce the on-resistance and on-voltage of the IGBT.

[0036] The p-type impurity concentration of the base region 60 may be 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The emitter region 62 may have an n-type impurity concentration higher than that of the carrier storage region 58. The n-type impurity concentration of the emitter region 62 may be 1×10 19 cm -3 or more and 1×10 20 cm -3 or less.

[0037] The gate trench 50 may penetrate the emitter region 62, the base region 60, and the carrier storage region 58 and reach the drift region 48. That is, the bottom of the gate trench 50 may be adjacent to the drift region 48.

[0038] The semiconductor device 10 may include a plurality of contact openings 64 that penetrate the insulating layer 18 and expose the semiconductor layer 12, and a plurality of contact plugs 66 embedded in the plurality of contact openings 64, respectively. Each contact opening 64 may penetrate the emitter region 62 and reach the base region 60. Each contact opening 64 may be disposed between two adjacent gate trenches 50 among the plurality of gate trenches 50. In the illustrated example, each of the contact openings 64 may extend in the Y-axis direction in plan view.

[0039] The contact plug 66 may be composed of a single metal layer or may include a plurality of different metal layers. The contact plug 66 may include at least one of tungsten, molybdenum, nickel, aluminum, copper, aluminum alloy, copper alloy, titanium, titanium nitride, tantalum, and tantalum nitride.

[0040] The semiconductor layer 12 may include a plurality of p-type contact regions 68 respectively exposed by the plurality of contact openings 64. Each contact region 68 is formed along the bottom of the corresponding contact plug 66. The contact region 68 may be adjacent to the base region 60. In one example, the p-type impurity concentration of the plurality of contact regions 68 is 1×10 19 cm -3 or more and 1×10 20 cm -3 or less.

[0041] The upper surfaces of the plurality of contact plugs 66 are covered by an emitter electrode 28 (emitter pad portion 36) formed on the insulating layer 18. The plurality of contact plugs 66 are connected to the emitter electrode 28.

[0042] <Peripheral region> Next, with reference to FIGS. 1 and 4, the peripheral region 24 of the semiconductor device 10 will be described. Note that in FIG. 4, an outer peripheral surface 12C extending in the Y-axis direction is shown in plan view, but it should be noted that the outer peripheral surface 12C extending in the X-axis direction may be the same as FIG. 4 except for the direction.

[0043] The semiconductor layer 12 may include a p-type outer peripheral well region 70 extending into the peripheral region 24. The outer peripheral well region 70 may be formed so as to surround the active region 22 in plan view. The outer peripheral well region 70 may include a part of the second surface 12B of the semiconductor layer 12. The outer peripheral well region 70 may extend from the second surface 12B of the semiconductor layer 12 to a position deeper than the base region 60.

[0044] In one example, the p-type impurity concentration in the outer peripheral well region 70 may be higher than the p-type impurity concentration in the base region 60. In another example, the p-type impurity concentration in the outer peripheral well region 70 may be approximately the same as the p-type impurity concentration in the base region 60.

[0045] The insulating layer 18 may include a first well opening 72 and a second well opening 74 that expose the outer peripheral well region 70. The emitter pad portion 36 can contact the outer peripheral well region 70 through the first well opening 72. Also, the emitter finger portion 38 can contact the outer peripheral well region 70 through the second well opening 74.

[0046] The insulating layer 18 may further include a gate opening 76 between the first well opening 72 and the second well opening 74. Also, the semiconductor device 10 may further include an outer peripheral gate wiring 78 located on the first insulating layer 54. The outer peripheral gate wiring 78 may be located below the outer peripheral gate finger portion 34 and above the outer peripheral well region 70. The outer peripheral gate finger portion 34 can contact the outer peripheral gate wiring 78 through the gate opening 76. The outer peripheral gate wiring 78 may be formed of conductive polysilicon. In another example, the outer peripheral gate wiring 78 may be formed of any other conductive material.

[0047] The semiconductor layer 12 may include a plurality of p-type field regions 80 extending in the outer peripheral region 24. The plurality of field regions 80 may be arranged so as to surround the outer peripheral well region 70 in plan view. The plurality of field regions 80 may be arranged between the outer peripheral well region 70 and the outer peripheral surface 12C of the semiconductor layer 12. The plurality of field regions 80 are arranged at intervals from each other. The interval between the plurality of field regions 80 may be larger as it is closer to the outer peripheral surface 12C of the semiconductor layer 12. The field region 80 (the outermost field region 80) at the position closest to the outer peripheral surface 12C of the semiconductor layer 12 may have a larger width (dimension in the direction orthogonal to the outer peripheral surface 12C) than the other field regions 80. Each field region 80 may include a part of the second surface 12B of the semiconductor layer 12. Each field region 80 may extend from the second surface 12B of the semiconductor layer 12 to a position deeper than the base region 60.

[0048] The insulating layer 18 may include a field opening 82 that exposes each field region 80. Each of the plurality of field electrodes 40 can contact the field region 80 through the field opening 82. Each field electrode 40 may include at least one of aluminum, copper, an aluminum alloy, a copper alloy, tungsten, molybdenum, nickel, titanium, titanium nitride, tantalum, and tantalum nitride. Each field electrode 40 may be composed of a single metal layer or may include a plurality of different metal layers. The field region 80 and the field electrode 40 may be electrically floating.

[0049] In one example, the p-type impurity concentration of the plurality of field regions 80 may be higher than the p-type impurity concentration of the base region 60. Also, the p-type impurity concentration of the plurality of field regions 80 may be higher than the p-type impurity concentration of the outer peripheral well region 70. In another example, the p-type impurity concentration of the plurality of field regions 80 may be substantially the same as the p-type impurity concentration of the base region 60 and / or the outer peripheral well region 70.

[0050] The semiconductor layer 12 may include an n-type channel stop region 86 that extends into the outer peripheral region 24. The channel stop region 86 may be arranged to surround a plurality of field regions 80 in plan view. The channel stop region 86 may be disposed between the plurality of field regions 80 and the outer peripheral surface 12C of the semiconductor layer 12. The channel stop region 86 may include a part of the second surface 12B of the semiconductor layer 12. Also, the channel stop region 86 may include a part of the outer peripheral surface 12C of the semiconductor layer 12.

[0051] The insulating layer 18 may partially cover the channel stop region 86. The end portion 88 of the insulating layer 18 may be located above the channel stop region 86. The channel stop electrode 42 may cover the end portion 88 of the insulating layer 18 and may be in contact with the channel stop region 86. The channel stop electrode 42 may cover a part of the channel stop region 86. The channel stop electrode 42 may include at least one of aluminum, copper, an aluminum alloy, a copper alloy, tungsten, molybdenum, nickel, titanium, titanium nitride, tantalum, and tantalum nitride. The channel stop electrode 42 may be composed of a single metal layer or may include a plurality of different metal layers. The channel stop region 86 and the channel stop electrode 42 may be electrically floating.

[0052] In one example, the n-type impurity concentration of the channel stop region 86 may be higher than the n-type impurity concentration of the drift region 48. The semiconductor layer 12 may include an n-type dicing region 92 extending in the outer peripheral region 24. The dicing region 92 may include a part of the first surface 12A and a part of the outer peripheral surface 12C of the semiconductor layer 12. The dicing region 92 may be located between the collector electrode 44 and the first semiconductor layer 14. The dicing region 92 may be adjacent to the collector electrode 44. The dicing region 92 may have a thickness smaller than that of the first semiconductor layer 14. In one example, the dicing region 92 may have a thickness (dimension in the Z-axis direction) of 5 μm or more and 50 μm or less. The dicing region 92 may face the channel stop region 86 through the first semiconductor layer 14, the buffer region 46, and the drift region 48.

[0053] As shown in FIG. 1, the dicing region 92 may extend along the outer peripheral surface 12C of the semiconductor layer 12 in a plan view. That is, the dicing region 92 may be formed in a rectangular frame shape along the outer peripheral surface 12C of the semiconductor layer 12. The width of the dicing region 92 may be smaller than the width of the channel stop region 86. Here, the width of the dicing region 92 is a dimension in a direction orthogonal to the outer peripheral surface 12C along which the dicing region 92 extends. For example, the width of a portion of the dicing region 92 extending in the Y-axis direction in a plan view corresponds to the dimension in the X-axis direction of that portion. In one example, the width of the dicing region 92 may be 30 μm or more and 100 μm or less.

[0054] In one example, the n-type impurity concentration of the dicing region 92 may be higher than the n-type impurity concentration of the drift region 48. <Details of the outer peripheral surface of the semiconductor layer> As shown in FIG. 4, the outer peripheral surface 12C of the semiconductor layer 12 includes an upper side surface 94 connected to the second surface 12B, a lower side surface 96 connected to the first surface 12A, and a connection surface 98 connecting the upper side surface 94 and the lower side surface 96. The lower side surface 96 is recessed from the upper side surface 94 in a direction from the outer peripheral region 24 toward the active region 22. The direction from the outer peripheral region 24 toward the active region 22 may be along an axis orthogonal to the upper side surface 94. For example, in the case of the outer peripheral surface 12C extending in the Y-axis direction in a plan view as shown in FIG. 4, the lower side surface 96 may be recessed from the upper side surface 94 in a direction from the outer peripheral region 24 toward the active region 22 along the X-axis.

[0055] In one example, the lower side surface 96 may be recessed from the upper side surface 94 by 5 μm or more and 15 μm or less in a direction from the outer peripheral region 24 toward the active region 22. The amount of recess R1 of the lower side surface 96 with respect to the upper side surface 94 may be the distance between the upper side surface 94 and the lower side surface 96 in a direction orthogonal to the upper side surface 94.

[0056] In one example, the upper side surface 94 may be a flat surface that intersects (for example, is orthogonal to) the second surface 12B. Also, the lower side surface 96 may be a flat surface that intersects (for example, is orthogonal to) the first surface 12A. The connection surface 98 may be inclined with respect to the upper side surface 94 and the lower side surface 96. In the example of FIG. 4, the connection surface 98 is at least partially curved.

[0057] The connection surface 98 is located away from the first surface 12A from the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16. That is, the connection surface 98 may be located between the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16 and the first surface 12A in the thickness direction of the semiconductor layer 12. The thickness direction of the semiconductor layer 12 may be a direction that intersects (for example, is orthogonal to) the first surface 12A. In the illustrated example, the thickness direction of the semiconductor layer 12 corresponds to the Z-axis direction. In one example, the connection surface 98 may be located closer to the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16 than the first surface 12A in the Z-axis direction. Preferably, the distance D1 between the connection surface 98 and the interface 100 may be at least 5 μm.

[0058] Since the connection surface 98 is located below the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16, from the upper side surface 94, the second semiconductor layer 16 and a part of the first semiconductor layer 14 (the part indicated by the distance D1 in FIG. 4) may be exposed. From the connection surface 98 and the lower side surface 96, the remaining part of the first semiconductor layer 14 may be exposed.

[0059] More specifically, from the upper side surface 94, the n-type channel stop region 86, the n-type drift region 48, and the n-type buffer region 46, and a part of the p-type collector region (the first semiconductor layer 14) may be exposed. From the connection surface 98 and the lower side surface 96, the remaining part of the p-type collector region (the first semiconductor layer 14) may be exposed.

[0060] In other words, the second semiconductor layer 16 may include the upper part of the upper side surface 94, and the first semiconductor layer 14 may include the lower part of the upper side surface 94 (the part indicated by the distance D1 in FIG. 4), the connection surface 98, and the lower side surface 96.

[0061] The ratio of the lower side surface 96 to the entire outer peripheral surface 12C may be larger than the ratio of the upper side surface 94. Also, as shown in FIG. 4, the ratio of the lower side surface 96 to the entire outer peripheral surface 12C may be larger than the ratio of the upper side surface 94, and the ratio of the upper side surface 94 may be larger than the ratio of the connection surface 98.

[0062] <Method for manufacturing a semiconductor device> Next, with reference to FIGS. 5 to 10, a method for manufacturing the semiconductor device 10 will be described. FIG. 5 is a schematic view of a semiconductor wafer 102 used in the manufacture of the semiconductor device 10. FIGS. 6 to 10 are schematic cross-sectional views showing exemplary manufacturing steps of the semiconductor device 10.

[0063] The manufacturing method of the semiconductor device 10 includes a step of dicing the semiconductor wafer 102. FIG. 5 is a schematic diagram of an exemplary semiconductor wafer 102 before dicing. The semiconductor wafer 102 has chip regions 104 arranged in a matrix in a plan view and lattice-shaped dicing lines 106 that define the boundaries of the chip regions 104. By dicing the semiconductor wafer 102 along the dicing lines 106, the semiconductor device 10, which is a semiconductor chip separated from the semiconductor wafer 102, can be obtained. Note that the size of the chip region 104 and the arrangement of the dicing lines 106 shown in FIG. 5 are examples, and those skilled in the art will understand that different layouts can be used.

[0064] The front surface of the semiconductor wafer 102 shown in FIG. 5 corresponds to the first surface 12A of the semiconductor layer 12. A part of the dicing line 106 corresponds to the dicing region 92 shown in FIG. 4. As shown in FIG. 4, since the collector electrode 44 is formed on the first surface 12A of the semiconductor layer 12, the dicing line 106 is covered by the collector electrode 44 during dicing. The dicing line 106 may be visible through the collector electrode 44 so that the semiconductor wafer 102 can be appropriately diced from the side of the collector electrode 44 (the first surface 12A of the semiconductor layer 12).

[0065] Hereinafter, the manufacturing process of the semiconductor device 10 including the formation of the dicing lines 106 and the dicing of the semiconductor wafer 102 will be described in more detail. FIGS. 6 to 10 correspond to enlarged cross-sectional views near the boundary between two chip regions 104. In FIGS. 6 to 10, the boundary between the two chip regions 104 is indicated by a two-dot chain line.

[0066] As shown in FIG. 6, a method for manufacturing a semiconductor device 10 includes forming a semiconductor layer 12 including a p-type first semiconductor layer 14 and an n-type second semiconductor layer 16 located on the first semiconductor layer 14, and forming an element structure 20 in the semiconductor layer 12. The semiconductor layer 12 includes an active region 22 where the element structure 20 is located and an outer peripheral region 24 surrounding the active region 22 in a plan view. Before dicing, the outer peripheral region 24 may be located along the boundary of the chip region 104.

[0067] FIG. 7 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 6. As shown in FIG. 7, a method for manufacturing a semiconductor device 10 includes forming a dicing line 106 in the outer peripheral region 24 of the semiconductor layer 12. The dicing line 106 may be formed along the boundary of the chip region 104. The dicing line 106 extends across two outer peripheral regions 24 respectively included in two adjacent chip regions 104. Forming the dicing line 106 may include forming the dicing line 106 by implanting n-type impurities into the semiconductor layer 12.

[0068] FIG. 8 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 7. As shown in FIG. 8, a method for manufacturing a semiconductor device 10 may include forming a collector electrode 44 on the first surface 12A of the semiconductor layer 12. The collector electrode 44 may cover the first surface 12A of the semiconductor layer 12 and the dicing line 106. The dicing line 106 covered by the collector electrode 44 may be visible through the collector electrode 44.

[0069] FIG. 9 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 8. As shown in FIG. 9, the method of manufacturing the semiconductor device 10 may include forming a groove 110 from the first surface 12A of the semiconductor layer 12 along the dicing line 106 using a first blade 108 having a first width W1. In one example, the first width W1 may be 40 μm or more and 60 μm or less. The first blade 108 can form the groove 110 in the semiconductor layer 12 by penetrating the collector electrode 44 and the dicing line 106. The groove 110 is formed so as not to penetrate the first semiconductor layer 14. The groove 110 is located away from the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16 toward the first surface 12A. The lower side surface 96 and the connection surface 98 as shown in FIG. 4 may be formed from a part of the groove 110. The remaining part of the dicing line 106 cut by the first blade 108 corresponds to the dicing region 92 shown in FIG. 4.

[0070] FIG. 10 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 9. As shown in FIG. 10, the method of manufacturing the semiconductor device 10 may include cutting the semiconductor layer 12 through the groove 110 using a second blade 112 having a second width W2 smaller than the first width W1. Thereby, separated semiconductor chips (semiconductor device 10) can be formed. In one example, the second width W2 may be 10 μm or more and 30 μm or less. The second width W2 of the second blade 112 is smaller than the width of the groove 110 formed by the first blade 108. Thereby, the outer peripheral surface 12C of the cut semiconductor layer 12 can include the upper side surface 94, the lower side surface 96, and the connection surface 98 as described above with reference to FIG. 4.

[0071] As described above, the method of manufacturing the semiconductor device 10 includes cutting the semiconductor layer 12 along the dicing line 106 to form separated semiconductor chips (semiconductor device 10). Cutting the semiconductor layer 12 along the dicing line 106 to form separated semiconductor chips may include forming a groove 110 from the first surface 12A of the semiconductor layer 12 along the dicing line 106 using a first blade 108 having a first width W1, and cutting the semiconductor layer 12 through the groove 110 using a second blade 112 having a second width W2 smaller than the first width W1.

[0072] <Operation and Effect of Semiconductor Device According to the Present Embodiment> Hereinafter, the operation of the semiconductor device 10 according to the present embodiment will be described. The semiconductor device 10 includes a semiconductor layer 12 having a first surface 12A, a second surface 12B opposite to the first surface 12A, and an outer peripheral surface 12C connecting the first surface 12A and the second surface 12B, and an element structure 20 partially constituted by the semiconductor layer 12. The semiconductor layer 12 includes a first semiconductor layer 14 of a first conductivity type including at least a part of the first surface 12A, and a second semiconductor layer 16 of a second conductivity type located on the first semiconductor layer 14. The outer peripheral surface 12C includes an upper side surface 94 connected to the second surface 12B, a lower side surface 96 connected to the first surface 12A, and a connection surface 98 connecting the upper side surface 94 and the lower side surface 96.

[0073] The lower side surface 96 is recessed from the upper side surface 94 in a direction from the outer peripheral region 24 toward the active region 22, and the connection surface 98 connecting the upper side surface 94 and the lower side surface 96 is located away from the first surface 12A from the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16.

[0074] Generally, when mounting a semiconductor chip on a support substrate or the like using a conductive bonding material (such as solder), extra bonding material may be generated. The extra bonding material may climb up the outer peripheral surface of the semiconductor chip, which may cause short circuits and leakage currents.

[0075] According to the semiconductor device 10 of the present embodiment, such an extra bonding material can be received in a space formed by the connection surface 98 and the lower side surface 96, which is recessed from the upper side surface 94. Further, due to the presence of the connection surface 98, the upward creep of the bonding material onto the upper side surface 94 can be suppressed. As a result, the extra bonding material can be prevented from reaching the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16, thereby suppressing the occurrence of a short circuit and an increase in leakage current in the semiconductor device 10.

[0076] The semiconductor device 10 and the method of manufacturing the semiconductor device 10 of the present embodiment have the following advantages. (1) The lower side surface 96 is recessed from the upper side surface 94 in a direction from the outer peripheral region 24 toward the active region 22, and the connection surface 98 connecting the upper side surface 94 and the lower side surface 96 is located away from the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16 toward the first surface 12A.

[0077] According to this configuration, when the semiconductor device 10 is mounted on a support substrate or the like using a bonding material, an extra bonding material can be received in the space formed by the connection surface 98 and the lower side surface 96. As a result, the extra bonding material can be prevented from reaching the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16, thereby suppressing the occurrence of a short circuit and an increase in leakage current in the semiconductor device 10.

[0078] (2) The connection surface 98 may be inclined with respect to the upper side surface 94 and the lower side surface 96. Therefore, even if an extra bonding material is generated during mounting, the presence of the connection surface 98 can prevent the bonding material from creeping onto the upper side surface 94.

[0079] (3) The ratio of the lower side surface 96 to the entire outer peripheral surface 12C may be larger than the ratio of the upper side surface 94. Thereby, a sufficient space for receiving an extra bonding material can be formed by the connection surface 98 and the lower side surface 96.

[0080] (4) The distance D1 between the connection surface 98 and the interface 100 may be at least 5 μm. Thereby, even if extra bonding material is generated during mounting, the distance between the bonding material and the interface 100 can be made sufficient, so that the occurrence of a short circuit and an increase in leakage current in the semiconductor device 10 can be suppressed.

[0081] (5) The lower side surface 96 may be recessed from the upper side surface 94 by 5 μm to 15 μm in the direction from the outer peripheral region 24 toward the active region 22. Thereby, a sufficient space for receiving extra bonding material is formed by the connection surface 98 and the lower side surface 96, and a sufficient size of the first surface 12A of the semiconductor layer 12 for mounting can be ensured.

[0082] (6) The first semiconductor layer 14 may be a collector region of the IGBT, and the second semiconductor layer 16 may include a drift region 48 of the IGBT. Since the connection surface 98 is located away from the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16, the occurrence of a short circuit and an increase in leakage current in the semiconductor device 10 including the IGBT as the element structure 20 can be suppressed.

[0083] (7) The method for manufacturing the semiconductor device 10 includes cutting the semiconductor layer 12 along the dicing line 106 to form separated semiconductor chips. The cut semiconductor layer 12 has a first surface 12A, a second surface 12B opposite to the first surface 12A, and an outer peripheral surface 12C connecting the first surface 12A and the second surface 12B. The outer peripheral surface 12C includes an upper side surface 94 connected to the second surface 12B, a lower side surface 96 connected to the first surface 12A, and a connection surface 98 connecting the upper side surface 94 and the lower side surface 96. The lower side surface 96 is recessed from the upper side surface 94 in the direction from the outer peripheral region 24 toward the active region 22, and the connection surface 98 connecting the upper side surface 94 and the lower side surface 96 is located away from the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16 toward the first surface 12A.

[0084] According to the manufacturing method of this semiconductor device 10, when the semiconductor device 10 is mounted on a support substrate or the like using a bonding material, a space for receiving the excess bonding material can be formed by the connection surface 98 and the lower side surface 96. As a result, it is possible to prevent the excess bonding material from reaching the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16. Therefore, it is possible to provide a semiconductor device 10 that can suppress the occurrence of short circuits and the increase of leakage current.

[0085] (8) The manufacturing method of the semiconductor device 10 may include forming a collector electrode 44 on the first semiconductor layer 14, and the collector electrode 44 is adjacent to the dicing line 106. Thereby, when cutting the semiconductor layer 12 through the collector electrode 44, the dicing line 106 can be easily visually recognized.

[0086] (9) Forming a semiconductor chip separated by cutting the semiconductor layer 12 along the dicing line 106 may include forming a groove 110 from the first surface 12A of the semiconductor layer 12 along the dicing line 106 using a first blade 108 having a first width W1, and using a second blade 112 having a second width W2 smaller than the first width W1 to cut the semiconductor layer 12 through the groove 110. Thereby, the outer peripheral surface 12C can be formed to include an upper side surface 94, a lower side surface 96 recessed from the upper side surface 94, and a connection surface 98 connecting the upper side surface 94 and the lower side surface 96.

[0087] (10) Forming the groove 110 from the first surface 12A of the semiconductor layer 12 along the dicing line 106 may include forming the groove 110 so as to be located away from the first surface 12A from the interface 100 between the first semiconductor layer 14 and the second semiconductor layer 16. Thereby, the lower side surface 96 and the connection surface 98 formed from a part of the groove 110 can be located away from the interface 100.

[0088] [Modification Example] The above embodiment can be implemented with the following modifications. · In the example shown in FIG. 4, the connection surface 98 is at least partially curved, but in another example, the connection surface 98 may alternatively or additionally be at least partially flat. FIG. 11 is a schematic cross-sectional view of a semiconductor device 200 according to such a modified example.

[0089] As shown in FIG. 11, in the semiconductor device 200, the outer peripheral surface 12C of the semiconductor layer 12 includes an upper side surface 94 connected to the second surface 12B, a lower side surface 96 connected to the first surface 12A, and a connection surface 202 connecting the upper side surface 94 and the lower side surface 96. The upper side surface 94 and the lower side surface 96 may be the same as those in the example shown in FIG. 4.

[0090] The connection surface 202 may be at least partially flat. In the example of FIG. 11, the flat connection surface 202 is orthogonal to the upper side surface 94 and the lower side surface 96. In this case, the connection surface 202 may be parallel to the first surface 12A or the second surface 12B.

[0091] Not limited to the illustrated example, the connection surface 202 may intersect the upper side surface 94 and the lower side surface 96 at any angle. Also, the connection surface 202 may include both a flat portion and a curved portion.

[0092] · In the example shown in FIG. 4, the ratio of the connection surface 98 to the entire outer peripheral surface 12C is smaller than the ratio of the lower side surface 96. However, the ratio of the connection surface 98 to the entire outer peripheral surface 12C may be equal to or greater than the ratio of the lower side surface 96. For example, when the thickness of the first semiconductor layer 14 is relatively thin, the ratio of the connection surface 98 to the entire outer peripheral surface 12C may be larger than the ratio of the lower side surface 96.

[0093] One or more of the various examples described herein can be combined within a technically non - conflicting range. In this specification, "at least one of A and B" should be understood to mean "only A, or only B, or both A and B".

[0094] As used in this disclosure, the term "on" can include both the meanings of "on" and "above", unless the context clearly indicates otherwise. Thus, the expression "the first layer is formed on the second layer" is intended that in some embodiments, the first layer can be directly disposed on the second layer in contact with the second layer, while in other embodiments, the first layer can be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which other layers are formed between the first layer and the second layer.

[0095] Directional terms such as "vertical", "horizontal", "above", "below", "upper", "lower", "front", "rear", "longitudinal", "lateral", "left", "right", "forward", "backward" used in this disclosure depend on the specific orientation of the device being described and illustrated. In this disclosure, various alternative orientations can be assumed, and thus these directional terms should not be construed narrowly.

[0096] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction and does not have to exactly coincide with the vertical direction. Thus, various structures according to this disclosure (e.g., the structure shown in FIG. 1) are not limited to the "upper" and "lower" in the Z-axis direction described herein being the "upper" and "lower" in the vertical direction. For example, the X-axis direction can be the vertical direction, or the Y-axis direction can be the vertical direction.

[0097] <Appendix> The technical ideas that can be grasped from this disclosure are described below. Note that, for the purpose of assisting understanding rather than limiting, the components described in the appendix are assigned the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples for assisting understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0098] (Appendix 1) A semiconductor layer (12) having a first surface (12A), a second surface (12B) opposite to the first surface (12A), and an outer peripheral surface (12C) connecting the first surface (12A) and the second surface (12B), the semiconductor layer (12) including a first semiconductor layer (14) of a first conductivity type including at least a part of the first surface (12A), and a second semiconductor layer (16) of a second conductivity type located on the first semiconductor layer (14). An element structure (20) partially constituted by the semiconductor layer (12). And comprising The semiconductor layer (12) includes an active region (22) where the element structure (20) is located, and an outer peripheral region (24) surrounding the active region (22) in a plan view and including the outer peripheral surface (12C) of the semiconductor layer (12). The outer peripheral surface (12C) is An upper side surface (94) connected to the second surface (12B), A lower side surface (96) connected to the first surface (12A), the lower side surface (96) being recessed from the upper side surface (94) in a direction from the outer peripheral region (24) toward the active region (22). And a connection surface (98) connecting the upper side surface (94) and the lower side surface (96). Including The connection surface (98) is located away from the first surface (12A) from an interface (100) between the first semiconductor layer (14) and the second semiconductor layer (16). A semiconductor device.

[0099] (Appendix 2) The semiconductor device according to Appendix 1, wherein the first semiconductor layer (14) is composed of a p-type semiconductor substrate, and the second semiconductor layer (16) is composed of an n-type epitaxial layer.

[0100] (Appendix 3) The semiconductor device according to Appendix 1 or 2, wherein the direction from the outer peripheral region (24) toward the active region (22) is along an axis orthogonal to the upper side surface (94).

[0101] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein the connection surface (98) is inclined with respect to the upper side surface (94) and the lower side surface (96).

[0102] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, wherein the semiconductor layer (12) includes a dicing region (92) of a second conductivity type extending in the outer peripheral region (24).

[0103] (Appendix 6) The semiconductor device according to Appendix 5, further comprising a collector electrode (44) formed on the first surface (12A) of the semiconductor layer (12), wherein the collector electrode (44) is adjacent to the dicing region (92).

[0104] (Appendix 7) The semiconductor device according to any one of Appendices 1 to 6, wherein the ratio of the lower side surface (96) to the entire outer peripheral surface (12C) is larger than the ratio of the upper side surface (94).

[0105] (Appendix 8) The semiconductor device according to any one of Appendices 1 to 7, wherein the connection surface (98) is at least partially curved.

[0106] (Appendix 9) The semiconductor device according to any one of Appendices 1 to 8, wherein the connection surface (202) is at least partially flat.

[0107] (Appendix 10) The semiconductor device according to any one of Appendices 1 to 9, wherein the first semiconductor layer (14) has a thickness of 160 μm to 185 μm, and the second semiconductor layer (16) has a thickness of 60 μm to 85 μm.

[0108] (Appendix 11) The semiconductor device according to any one of Appendices 1 to 10, wherein the distance (D1) between the connection surface (98) and the interface (100) is at least 5 μm.

[0109] (Appendix 12) The lower side surface (96) is recessed by 5 μm to 15 μm from the upper side surface (94) in a direction from the outer peripheral region (24) toward the active region (22), and the semiconductor device according to any one of Appendices 1 to 11.

[0110] (Appendix 13) The element structure (20) includes an IGBT, and the semiconductor device according to any one of Appendices 1 to 12.

[0111] (Appendix 14) The first semiconductor layer (14) is the collector region of the IGBT, and the second semiconductor layer (16) includes the drift region (48) of the IGBT, and the semiconductor device according to Appendix 13.

[0112] (Appendix 15) Forming a semiconductor layer (12) including a first semiconductor layer (14) of a first conductivity type and a second semiconductor layer (16) of a second conductivity type located on the first semiconductor layer (14), Forming an element structure (20) in the semiconductor layer (12), wherein the semiconductor layer (12) includes an active region (22) where the element structure (20) is located and an outer peripheral region (24) surrounding the active region (22) in a plan view, and forming the element structure (20), Forming a dicing line (106) in the outer peripheral region (24) of the semiconductor layer (12), Cutting the semiconductor layer (12) along the dicing line (106) to form a separated semiconductor chip (10), wherein the cut semiconductor layer (12) has a first surface (12A), a second surface (12B) opposite to the first surface (12A), and an outer peripheral surface (12C) connecting the first surface (12A) and the second surface (12B), and forming the semiconductor chip (10) including, The first semiconductor layer (14) includes at least a part of the first surface (12A), The outer peripheral surface (12C) is an upper side surface (94) connected to the second surface (12B), and A lower side surface (96) connected to the first surface (12A), the lower side surface (96) being recessed from the upper side surface (94) in a direction from the outer peripheral region (24) toward the active region (22), and a connection surface (98) connecting the upper side surface (94) and the lower side surface (96), comprising, wherein the connection surface (98) is located away from the first surface (12A) from an interface (100) between the first semiconductor layer (14) and the second semiconductor layer (16), a method of manufacturing a semiconductor device.

[0113] (Appendix 16) Further comprising forming a collector electrode (44) on the first semiconductor layer (14), the collector electrode (44) being adjacent to the dicing line (106), a method of manufacturing a semiconductor device according to Appendix 15.

[0114] (Appendix 17) Cutting the semiconductor layer (12) along the dicing line (106) to form the separated semiconductor chip (10) is forming a groove (110) from the first surface (12A) of the semiconductor layer (12) along the dicing line (106) using a first blade having a first width, and cutting the semiconductor layer (12) through the groove (110) using a second blade having a second width smaller than the first width, comprising, a method of manufacturing a semiconductor device according to Appendix 15 or 16.

[0115] (Appendix 18) Forming a groove (110) from the first surface (12A) of the semiconductor layer (12) along the dicing line (106) includes forming the groove (110) so as to be located away from the first surface (12A) from the interface (100) between the first semiconductor layer (14) and the second semiconductor layer (16), a method of manufacturing a semiconductor device according to Appendix 17.

[0116] (Appendix 19) The manufacturing method of the semiconductor device according to any one of Appendices 15 to 18, wherein the first semiconductor layer (14) is composed of a p-type semiconductor substrate and the second semiconductor layer (16) is composed of an n-type epitaxial layer.

[0117] (Appendix 20) Forming the dicing line (106) includes forming the dicing line (106) by implanting n-type impurities into the semiconductor layer (12). The manufacturing method of the semiconductor device according to any one of Appendices 15 to 19.

[0118] Various changes in form and detail can be made without departing from the scope of the claims and their equivalents for the examples described above. The above examples are for illustrative purposes and not for purposes of limitation. The description of the features in each example should be considered applicable to similar features or aspects in other examples. Suitable results can be achieved if consecutive events are performed in a different order and / or if the components within the described system, architecture, device, or circuit are combined in different manners and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description but by the claims and their equivalents. All modifications of the claims and their equivalents are included in the present disclosure.

Explanation of Reference Numerals

[0119] 10,200... Semiconductor device 12... Semiconductor layer 12A... First surface 12B... Second surface 12C... Outer peripheral surface 14... First semiconductor layer 16... Second semiconductor layer 18... Insulating layer 20... Element structure 22... Active region 24... Outer peripheral region 26... Gate electrode 28... Emitter electrode 30…Gate pad section 32…Inner gate finger section 34…Peripheral gate finger section 36…Emitter pad section 38…Emitter finger section 40…Field electrode 42…Channel stop electrode 44…Collector electrode 46…Buffer region 48…Drift region 50…Gate trench 52…Embedded electrode 54…First insulating layer 56…Second insulating layer 58…Carrier storage region 60…Base region 62…Emitter region 64…Contact opening 66…Contact plug 68…Contact region 70…Peripheral well region 72…First well opening 74…Second well opening 76…Gate opening 78…Peripheral gate wiring 80…Field region 82…Field opening 86…Channel stop region 88…End portion 92…Dicing region 94…Upper side surface 96…Lower side surface 98, 202…Connection surface 100…Interface 102…Semiconductor wafer 104…Chip region 106…Dicing line 108…First blade 110…Groove 112…Second blade

Claims

1. A semiconductor layer having a first surface, a second surface opposite to the first surface, and an outer peripheral surface connecting the first surface and the second surface, the semiconductor layer including a first semiconductor layer of a first conductivity type including at least a part of the first surface, and a second semiconductor layer of a second conductivity type positioned on the first semiconductor layer, an element structure partially constituted by the semiconductor layer, comprising: the semiconductor layer including an active region where the element structure is located, and an outer peripheral region surrounding the active region in a plan view and including the outer peripheral surface of the semiconductor layer, the outer peripheral surface including an upper side surface connected to the second surface, and a lower side surface connected to the first surface, the lower side surface being recessed from the upper side surface in a direction from the outer peripheral region toward the active region, and a connecting surface connecting the upper side surface and the lower side surface, wherein the connecting surface is located away from the first surface from an interface between the first semiconductor layer and the second semiconductor layer. A semiconductor device.

2. The semiconductor device according to claim 1, wherein the first semiconductor layer is constituted by a p-type semiconductor substrate, and the second semiconductor layer is constituted by an n-type epitaxial layer.

3. The semiconductor device according to claim 1, wherein the direction from the outer peripheral region toward the active region is along an axis orthogonal to the upper side surface.

4. The semiconductor device according to claim 1, wherein the connecting surface is inclined with respect to the upper side surface and the lower side surface.

5. The semiconductor device according to claim 1, wherein the semiconductor layer includes a dicing region of a second conductivity type extending in the outer peripheral region.

6. The semiconductor device according to claim 5, further comprising a collector electrode formed on the first surface of the semiconductor layer, the collector electrode being adjacent to the dicing region.

7. The semiconductor device according to any one of claims 1 to 6, wherein a ratio of the lower side surface to an entirety of the outer peripheral surface is larger than a ratio of the upper side surface.

8. The semiconductor device according to any one of claims 1 to 6, wherein the connecting surface is at least partially curved.

9. The semiconductor device according to any one of claims 1 to 6, wherein the connecting surface is at least partially flat.

10. The semiconductor device according to any one of claims 1 to 6, wherein the first semiconductor layer has a thickness of 160 μm to 185 μm, and the second semiconductor layer has a thickness of 60 μm to 85 μm.

11. The semiconductor device according to any one of claims 1 to 6, wherein the distance between the connection surface and the interface is at least 5 μm.

12. The semiconductor device according to any one of claims 1 to 6, wherein the lower side surface is recessed from the upper side surface by 5 μm to 15 μm in a direction from the outer peripheral region toward the active region.

13. The semiconductor device according to any one of claims 1 to 6, wherein the element structure includes an IGBT.

14. The semiconductor device according to claim 13, wherein the first semiconductor layer is a collector region of the IGBT, and the second semiconductor layer includes a drift region of the IGBT.

15. Forming a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type located on the first semiconductor layer, Forming an element structure in the semiconductor layer, wherein the semiconductor layer includes an active region where the element structure is located and an outer peripheral region surrounding the active region in a plan view, forming the element structure, Forming a dicing line in the outer peripheral region of the semiconductor layer, Cutting the semiconductor layer along the dicing line to form separated semiconductor chips, wherein the cut semiconductor layer has a first surface, a second surface opposite to the first surface, and an outer peripheral surface connecting the first surface and the second surface, forming the semiconductor chips including, The first semiconductor layer includes at least a part of the first surface, The outer peripheral surface is, an upper side surface connected to the second surface, a lower side surface connected to the first surface, the lower side surface being recessed from the upper side surface in a direction from the outer peripheral region toward the active region, and a connection surface connecting the upper side surface and the lower side surface including, The connection surface is located away from the first surface from an interface between the first semiconductor layer and the second semiconductor layer, a method of manufacturing a semiconductor device.

16. The method of manufacturing a semiconductor device according to claim 15, further including forming a collector electrode on the first semiconductor layer, wherein the collector electrode is adjacent to the dicing line.

17. Cutting the semiconductor layer along the dicing line to form the separated semiconductor chips includes, using a first blade having a first width to form a groove from the first surface of the semiconductor layer along the dicing line, Cutting the semiconductor layer through the groove using a second blade having a second width smaller than the first width The method of manufacturing a semiconductor device according to claim 15, comprising:

18. Forming a groove from the first surface of the semiconductor layer along the dicing line includes forming the groove so as to be located away from the first surface from the interface between the first semiconductor layer and the second semiconductor layer. The method of manufacturing a semiconductor device according to claim 17.

19. The method of manufacturing a semiconductor device according to any one of claims 15 to 18, wherein the first semiconductor layer is composed of a p-type semiconductor substrate, and the second semiconductor layer is composed of an n-type epitaxial layer.

20. The method of manufacturing a semiconductor device according to any one of claims 15 to 18, wherein forming the dicing line includes forming the dicing line by implanting n-type impurities into the semiconductor layer.

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