Semiconductor device

Abstract

To provide a silicon carbide semiconductor device with improved reliability.SOLUTION: A silicon carbide semiconductor device includes a silicon carbide substrate 2 formed of silicon carbide of a first conductivity type, a drift layer 3 formed of silicon carbide of the first conductivity type, a plurality of body layers 4 formed of silicon carbide of a second conductivity type on the drift layer, a plurality of source layers 5 formed of silicon carbide of the first conductivity type with higher impurity concentration than that of the drift layer on each of the body layers, a gate insulating film 7 formed in contact with the body layer and the source layer, a gate electrode 8 formed on the gate insulating film, and an interlayer insulating film 9 covering the gate electrode. The interlayer insulating film includes a first layer 9a, a second layer 9b, and a third layer 9c from a side farther from the gate electrode. The material of the first layer and the third layer is BPSG. The first layer has a glass transition temperature of 350°C or more and 500°C or less.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device. In particular, it relates to a silicon carbide semiconductor device that improves reliability by using a multilayer structure for the interlayer insulating film.

Background Art

[0002] Semiconductor devices using silicon carbide (SiC) for the substrate and the drift layer (epitaxial layer) can achieve higher breakdown voltage, lower loss, and higher speed than semiconductor devices using silicon (Si) for the substrate, and are thus used, for example, as power semiconductor devices.

[0003] For example, in the SiC-MOSFET as a silicon carbide semiconductor device described in Patent Document 1, a TEOS (Tetra Ethyl Ortho Silicate) oxide film is deposited as an interlayer insulating film for insulating the gate electrode and the source wiring, etc., a BPSG (Boro Phospho Silicate Glass) film is deposited on the TEOS oxide film, and it is disclosed that a three-layer insulating film is formed by further depositing a TEOS oxide film on the BPSG. Non-Patent Document 1 shows that in a trench-type power SiC-MOSFET, when hydrogen ions (H+) enter the device, it has an effect of impairing the reliability of the HTRB (High-Temperature Reverse Bias) test, and as a countermeasure, by adopting a material with a high phosphorus concentration in the interlayer insulating film, hydrogen ions can be adsorbed to prevent hydrogen ions from entering the inside of the semiconductor device and improve the reliability of the semiconductor device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Silicon carbide semiconductor devices such as SiC-MOSFETs are often encapsulated with resin. Hydrogen ions precipitated from the resin pass through the source wiring electrode, gate electrode, and gate insulating film and reach the channel area of the body layer, which impairs the reliability in the HTRB (High Temperature Reverse Bias) test and causes fluctuations in the gate (Vth) threshold voltage and an increase in leakage current of the semiconductor device. For this reason, it is required not to allow hydrogen ions to permeate through the interlayer insulating film. Also, in the process of forming the source electrode wiring, since the thermal expansion coefficients of the members of the semiconductor device are different, stress is generated due to the expansion of the members caused by the temperature rise. When the interlayer insulating film is damaged such as cracked due to this thermal stress, there is a problem that hydrogen ions may easily permeate. In view of these problems, an object of the present invention is to provide a silicon carbide semiconductor device having an interlayer insulating film through which hydrogen ions hardly permeate and in which the interlayer insulating film is hardly damaged even in the process of forming the source electrode wiring.

Means for Solving the Problems

[0007] One aspect of the silicon carbide semiconductor device of the present invention includes a silicon carbide substrate formed of silicon carbide of a first conductivity type, A drift layer formed of silicon carbide of a first conductivity type on a first surface of the silicon carbide substrate, A plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, A plurality of source layers respectively formed of silicon carbide of a first conductivity type having an impurity concentration higher than that of the drift layer on each of the plurality of body layers, A gate insulating film formed so as to be in contact with the body layer and the source layer, A gate electrode formed on the gate insulating film, An interlayer insulating film formed so as to cover the gate electrode together with the gate insulating film comprising, The interlayer insulating film includes a first layer, a second layer, and a third layer from the side far from the gate electrode, The materials of the first layer and the third layer are BPSG, The first layer has a glass transition temperature of 350 °C or higher and 500 °C or lower.

[0008] Thus, since the glass transition temperature of BPSG of the outermost first layer of the interlayer insulating film is lowered to 350 °C or higher and 500 °C or lower, the BPSG of the first layer softens due to the temperature rise during the process of forming the source electrode wiring. Therefore, even if stress is generated due to the expansion of the member caused by the temperature rise during the process of forming the source electrode wiring, the first layer deforms thermally and absorbs the stress. Thereby, it is possible to prevent performance deterioration due to breakage or cracking of the second layer and the third layer.

[0009] Further, since the outermost first layer and the third layer of the interlayer insulating film are made of BPSG, hydrogen ions (H + ) are adsorbed by the phosphorus contained in BPSG, so that it is possible to suppress H+ from reaching the channel area via the insulating oxide film. Therefore, it is possible to suppress an increase in the change in the gate threshold voltage (Vth) and the leakage current of the device due to hydrogen ions. Thereby, it is possible to improve the reliability of the silicon carbide semiconductor device.

[0010] In the silicon carbide semiconductor device of the present invention, it is preferable that the glass transition temperature of BPSG, which is the material of the third layer, is 600°C or higher and 1000°C or lower.

[0011] Thus, since the glass transition temperature of BPSG, which is the material of the third layer, is 600°C or higher and 1000°C or lower, even when the temperature rises to about 500°C in the process of forming the source electrode wiring, the shape is maintained without deforming like the first layer.

[0012] As a specific aspect of the above-described aspect, in the silicon carbide semiconductor device of the present invention, the second layer may be a TEOS oxide film.

[0013] Thus, by using a TEOS oxide film for the second layer, the TEOS oxide film of the second layer is less permeable to hydrogen ions, and by using BPSG, which can absorb hydrogen ions, for the materials of the first layer and the second layer, the passage of hydrogen ions can be prevented more effectively.

[0014] As a specific aspect of the above-described aspect, in the silicon carbide semiconductor device of the present invention, a fourth layer made of at least one of silicon dioxide and silicon nitride may be provided between the third layer and the gate electrode.

[0015] Thus, since the fourth layer made of at least one of silicon dioxide and silicon nitride is provided, phosphorus contained in the BPSG film of the third layer is prevented from diffusing into the gate electrode, and a decrease in the phosphorus concentration of the third layer and a decrease in the ability to absorb hydrogen ions are prevented. Therefore, it is possible to prevent hydrogen ions from reaching the channel area through the gate electrode and the gate insulating film, and the reliability of the silicon carbide semiconductor device can be improved.

[0016] In a specific embodiment of the above-described aspect, the silicon carbide semiconductor device of the present invention is characterized in that the gate electrodes are provided in two separated positions on the gate insulating film, and a fourth layer made of at least one of silicon dioxide and silicon nitride is provided to cover each of the two gate electrodes, and it is preferable that BPSG of the third layer is formed between the two gate electrodes and the second layer. The gate insulating film may be single or provided separately in two parts.

[0017] As described above, since the two gate electrodes are provided separately on the gate insulating film, there is no parasitic capacitor between the gate electrodes and the drift layer because there is no gate electrode between them, which enables the silicon carbide semiconductor device to operate at high speed.

Advantages of the Invention

[0018] According to the present invention, when the temperature rises during the formation of the source electrode wiring, the BPSG of the first layer softens due to the temperature rise. Therefore, even if stress is generated due to the expansion of each member of the silicon carbide semiconductor device, the softened first layer deforms to absorb the stress. As a result, it is possible to prevent performance degradation due to breakage or cracking of the second layer and the third layer. In addition, by using BPSG for the outermost first layer and the third layer of the interlayer insulating film, hydrogen ions (H + ) are adsorbed by the phosphorus contained in BPSG, so that it is possible to suppress hydrogen ions from reaching the channel area via the gate insulating film. Therefore, the reliability of the silicon carbide semiconductor device can be improved.

Brief Description of the Drawings

[0019]

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Mode for Carrying Out the Invention

[0020] <Regarding Definitions in the Description> In the embodiments described hereinafter, the first conductivity type is n-type and the second conductivity type is p-type for the sake of explanation, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0021] Also, regarding words indicating directions such as up and down, left and right, side, inside, and outside, for the sake of convenience and for reference to FIG. 2, they may be different from the actual orientation of the product. Also, the drawings are schematic, and include parts where the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of each layer, etc. are different from the actual ones. Also, there are parts where the dimensional relationships and ratios are different between the drawings.

[0022] <Configuration of the First Embodiment> A first embodiment of a silicon carbide semiconductor device according to the present invention will be described. FIG. 1 is a plan view of a semiconductor chip 50 including a silicon carbide semiconductor device 1 according to the present embodiment. The shape of the semiconductor chip 50 is, for example, rectangular in plan view. On the plane of the semiconductor chip, a gate pad 51 and a source pad 52 are provided, and below these, a plurality of element regions (not shown) are arranged side by side in plan view. In these element regions, a plurality of silicon carbide semiconductor devices 1 are arranged as unit cells each serving as a minimum unit structure of a MOS-FET. The gate pad 51 is electrically connected to the gate electrode of each silicon carbide semiconductor device 1. The source pad 52 is electrically connected to the source electrode of each silicon carbide semiconductor device 1. Note that a drain pad is provided on the bottom surface (back surface) of the semiconductor chip (not shown), and the drain pad is electrically connected to the drain electrode of each silicon carbide semiconductor device 1.

[0023] FIG. 2 is a cross-sectional view of a main part of a planar SiC-MOSFET as the silicon carbide semiconductor device of the present embodiment. In FIG. 2, the silicon carbide semiconductor device 1 includes a silicon carbide substrate 2, a drift layer 3, two body layers 4, two source layers 5, two body contact layers 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, two source electrodes 10, a source wiring electrode 11, and a drain electrode 12.

[0024] As shown in FIG. 2, a planar MOSFET is formed on an n + -type silicon carbide substrate 2 of the first conductivity type. The silicon carbide substrate 2 has a first surface 30 on the upper main surface side and a second surface 31 on the lower main surface side in the drawing of FIG. 2. The thickness of the silicon carbide substrate 2 is about 350 μm if the wafer is 6 inches and about 500 μm if the wafer is 8 inches, but before the step of forming the drain electrode 12 described later, it may be thinned to about 100 to 200 μm for improving heat dissipation.

[0025] An n-type drift layer 3 made of silicon carbide epitaxially grown on the first surface 30 (the upper surface in FIG. 2) of the silicon carbide substrate 2 is formed. The impurity concentration of the n-type drift layer 3 is lower than that of the silicon carbide substrate 2, and the thickness is 5 to 20 μm. For example, nitrogen is used as the n-type impurity in the n-type drift layer 3.

[0026] On the upper surface of the n-type drift layer 3 (the side opposite to the silicon carbide substrate 2), two p-type body layers 4 of the second conductivity type are formed so as to be arranged at intervals from each other. The thickness of the body layer 4 is about 1 μm. The p-type body layer 4 is formed, for example, by ion implantation of aluminum.

[0027] On each p-type body layer 4, an n + -type source layer 5 with a high impurity concentration is provided. n + The impurity concentration of the -type source layer 5 is configured to be higher than that of the n-type drift layer 3. n + The thickness of the -type source layer 5 is, for example, about 0.3 to 0.4 μm. Above the p-type body layer 4 and outside the n + -type source layer 5, a p + -type body contact layer 6 is provided. p + The impurity concentration of the -type body contact layer 6 is configured to be higher than that of the p-type body layer 4.

[0028] Also, the body layer 4 is located between the n + -type source layer 5 and the drift layer 3 and is formed to be in contact with the gate insulating film 7. The gate insulating film 7 is disposed on the drift layer 3, the body layer 4, and the source layer 5, and a gate electrode 8 is provided on the upper surface of the gate insulating film 7. This gate electrode 8 is made of, for example, polysilicon doped with an n-type impurity (for example, phosphorus [P]) in order to enhance conductivity. Further, the gate electrode 8 is provided with a contact hole (not shown in a different cross section from FIG. 2) provided in the interlayer insulating film 9 and is electrically connected to the gate pad 51 via an external wiring.

[0029] An interlayer insulating film 9 is formed so as to cover the gate electrode 8 and a part of the gate insulating film 7. This interlayer insulating film 9 is composed of a plurality of layers of different types. In the present embodiment, specifically, a BPSG film 9c as the third layer formed to cover the gate electrode 8, a TEOS oxide film 9b as the second layer formed to cover this BPSG film 9c, and a BPSG film 9a as the outermost (the side farthest from the gate electrode 8) first layer formed to cover the TEOS oxide film 9b as the second layer constitute the interlayer insulating film 9. The interlayer insulating film 9 is formed up to the contact surface 17 with the source electrode 10 so as to completely cover the gate insulating film 7. Thereby, since the gate insulating film 7 is covered with the interlayer insulating film 9, it is possible to prevent hydrogen ions from reaching the channel area from the source wiring electrode 11 via the gate insulating film 7.

[0030] The BPSG film 9c as the third layer from the outside has a glass transition temperature of its material of 600 °C or higher and 1000 °C or lower. The glass transition temperature of the BPSG film 9a as the first layer from the outside is lower than that of the BPSG film 9c as the third layer, and is 350 °C or higher and 500 °C or lower. The melting point of the TEOS oxide film 9b as the second layer from the outside is preferably 600 °C or higher.

[0031] The source electrode 10 is formed on the source layer 5 and the body contact layer 6. The source electrode 10 is made of, for example, nickel silicide (NiSi). The source wiring electrode 11 is in contact with and electrically connected to the source electrode 10, and is provided on the source electrode 10 and the interlayer insulating film 9 (the BPSG film 9a as the first layer). The source wiring electrode 11 is made of, for example, aluminum, but may be an alloy of aluminum and copper (Al-Cu) or an alloy of aluminum and silicon (Al-Si).

[0032] As shown in FIG. 7, a wiring (bonding wire) 13 is provided on the source wiring electrode 11 via a ball bond 13a. As the material of the wiring 13, for example, aluminum or an alloy of aluminum and copper (Al-Cu) is used.

[0033] The planar SiC-MOSFET as the silicon carbide semiconductor device 1 configured as described above has a channel area in the vicinity of the region in the body layer 4 that is in contact with the gate insulating film 7. Using this channel region as a current path, an electron current flows from the source electrode 10 through the source layer 5 and the drift layer 3 to the drain electrode 12. Also, by controlling the applied voltage of the gate electrode 8 and controlling the width of the depletion layer formed in the channel area, the current flowing through the channel area is controlled, and thus the current flowing between the source electrode 10 and the drain electrode 12 can be controlled.

[0034] In the step of providing the source wiring electrode 11 (for example, a sputtering step), when the temperature of the film reaches about 500°C, thermal stress is generated due to the different coefficients of thermal expansion of the respective members of the semiconductor device 1 as they thermally expand. Conventionally, insulating films with a multilayer structure such as the TEOS oxide film 9b of the second layer and the BPSG film 9c of the third layer of the interlayer insulating film 9 each thermally expand and come into contact with the source wiring electrode 11, which may lead to damage such as the occurrence of cracks. In view of this problem, in the present embodiment, since the outermost first layer insulating film of the interlayer insulating film 9 is a BPSG film 9a with a glass transition temperature of 350°C or higher and 500°C or lower, even if the temperature rises during the step of providing the source wiring electrode 11, the BPSG film 9a as the first layer softens due to heat and becomes easily deformable, absorbing the thermal expansion of the second layer TEOS oxide film 9b and the members around the interlayer insulating film 9 due to heat, thereby preventing damage to the interlayer insulating film 9. Therefore, fluctuations in characteristics due to damage to the interlayer insulating film 9 can be prevented, and the reliability of the silicon carbide semiconductor device 1 can be ensured.

[0035] In addition, since the outermost first layer and the innermost third layer of the interlayer insulating film 9 are made of BPSG film, hydrogen ions (H+) are adsorbed by phosphorus contained in BPSG, so that it is possible to suppress hydrogen ions from reaching the channel area via the interlayer insulating film 9. For this reason, it is possible to suppress an increase in fluctuations in the gate threshold voltage (Vth) and leakage current of the device due to hydrogen ions. As a result, it becomes possible to improve the reliability of the silicon carbide semiconductor device. Further, since the TEOS oxide film 9b of the second layer is less permeable to hydrogen ions, the reliability of the silicon carbide semiconductor device can be improved by the multilayer structure in which the second layer is added to the first layer and the third layer.

[0036] <Manufacturing Process of the First Embodiment> The manufacturing process of the silicon carbide semiconductor device 1 of the present embodiment will be described with reference to FIGS. 3 to 5. As shown in FIG. 3(A), an n-type silicon carbide substrate 2 of the first conductivity type is prepared. Thereafter, an n-type drift layer 3 is epitaxially grown on the first surface 30 (the upper surface in FIG. 1) of the silicon carbide substrate 2. + Then, a mask such as SiO2 is formed on the surface of the n-type drift layer 3, and a mask 20 is formed through a photolithography process so that the upper part of the formation planned region of the p-type body layer 4 of the second conductivity type is exposed. Thereafter, ion implantation of p-type impurity aluminum (Al) is performed from above the mask 20. The thickness of the body layer 4 is, for example, 1 μm. In this embodiment, p-type impurities such as Al are used, but B (boron) or BF2 (boron difluoride) may also be used.

[0037]

[0038] ​Next, as shown in FIG. 3(B), a layer of the same material as the mask 20 (e.g., SiO2) is laminated on the main surface of the silicon carbide substrate 2, and then, by a self-alignment method formed by anisotropic etching, a mask 21 that is widely formed from the mask 20 is formed. The formed mask 21 exposes the upper part of the planned formation region of the n-type source layer 5. Then, for example, nitrogen (N) is ion-implanted as an n-type impurity from above the mask 21. In this embodiment, nitrogen (N) is used as the n-type impurity, but phosphorus (P) may also be used.

[0039] Next, as shown in FIG. 3(C), after removing the mask 21, a mask 23 such as SiO2 is formed, and then, through a photolithography process, the mask 23 is formed so that the upper part of the planned formation region of the P + type body contact layer 6 is exposed. Then, for example, aluminum (Al) is ion-implanted as a p-type impurity into the planned formation region of the body contact layer 6 to form the body contact layer 6.

[0040] Next, after removing the mask 23, for example, annealing at 1600 °C is performed. By this annealing, the p-type body layer 4, the n + type source layer 5, and the body contact layer 6 are activated.

[0041] Next, as shown in FIG. 4(A), a gate insulating film 7 such as SiO2 is formed. Specifically, by heating the region including the upper parts of the body layer 4, the n + type source layer 5, and the body contact layer 6 at 900 to 1350 °C for thermal oxidation to form SiO2, and patterning the gate insulating film 7 using the resist formed by photolithography and etching as a mask to form the gate insulating film 7.

[0042] Next, as shown in FIG. 4(B), a gate electrode 8 is formed on the surface of the gate insulating film 7. Specifically, in order to enhance conductivity, for example, after forming a polysilicon layer doped with an n-type impurity, patterning is performed using the resist formed by photolithography and etching as a mask.

[0043] Next, as shown in FIG. 4(C), a third-layer BPSG film 9c that forms the interlayer insulating film 9 so as to cover the gate electrode 8 is formed. Specifically, by CVD, a BPSG film is deposited over the entire main surface of the wafer including the gate electrode 8, and the BPSG film is patterned using the resist formed by photolithography and etching as a mask, thereby forming the third-layer BPSG film 9c. The BPSG film 9c is subjected to reflow to perform planarization of the upper portion and to round the corners in the cross sections such as those shown in FIGS. 1, 4(A), and 4(B). Rounding can prevent the concentration of electrolysis at the corners in the interlayer insulating film 9. As described above, the third-layer BPSG film 9c has a glass transition temperature higher than 600°C. The glass transition temperature of BPSG can be adjusted by changing the ratio of phosphorus (P) and boron (B) in CVD.

[0044] Next, as shown in FIG. 5(A), a second-layer TEOS oxide film 9b is formed. A TEOS oxide film is deposited over the entire main surface of the wafer including the first interlayer insulating film made of BPSG, and the TEOS oxide film is patterned using the resist formed by photolithography and etching as a mask, thereby forming the second-layer TEOS oxide film 9b.

[0045] Next, as shown in FIG. 5(A), a source electrode 10 made of, for example, nickel silicide (NiSi) is formed. Specifically, first, by sputtering, nickel (Ni) is deposited on the main surface side of the substrate 2 including the upper portions of the source layer 5 and the body contact layer 6. Thereafter, an annealing process for alloying is performed. Specifically, for the silicon carbide substrate 2 on which nickel (Ni) is deposited, heat treatment at 900°C or higher and 1100°C or lower is performed for about 5 minutes, for example, by laser. As a result, at least a part of the source electrode 10 (the portion where the Ni film is in contact with the source layer 5 and the body contact layer 6) is silicided to become nickel silicide. Thereafter, the non-silicided nickel (Ni) portion is removed. Thereby, the source electrode 10 that makes an ohmic contact with the source layer 5 and the body contact layer 6 is formed.

[0046] Next, as shown in FIG. 5(B), the BPSG film 9a of the first layer is formed. Specifically, by CVD, a BPSG film is formed over the entire main surface of the wafer including the upper surface of the TEOS oxide film 9b of the second layer, and the BPSG film is patterned using the resist formed by photolithography and etching as a mask, thereby forming the BPSG film 9a of the first layer. As described above, the BPSG film 9a of the first layer is configured to have a glass transition temperature lower than that of the third layer. The BPSG film 9a, similar to the BPSG film 9c, is subjected to reflow to perform planarization of the upper portion and to make the corners rounded.

[0047] Next, as shown in FIG. 6(A), the source wiring electrode 11 is formed. Specifically, the source wiring electrode 11 is formed, for example, by sputtering so as to cover the source electrode 10, the interlayer insulating film 9, and the barrier layer 15. The material of the source wiring electrode 11 is, for example, aluminum (Al), but may also be an alloy of aluminum and copper (Al-Cu) or a compound of aluminum and silicon (Al-Si). Also, the thickness of the source wiring electrode 11 is about 5 μm. Next, as shown in FIG. 6(A), a drain electrode 12 made of, for example, NiSi is formed on the second surface 31 of the silicon carbide substrate 2. The drain electrode 12 is formed, for example, by depositing Ni by sputtering, and then the deposited Ni is heated, for example, by laser annealing. As a result, at least a part of the Ni is silicided. Thereafter, the Ni that has not been silicided is removed. Thereby, the drain electrode 12 is formed.

[0048] Next, as shown in FIG. 6(B), a wiring (bonding wire) 13 is attached to the source wiring electrode 11 via a ball bond 13a. This wiring 13 is composed of, for example, an alloy of aluminum (Al) and copper (Cu).

[0049] Next, as shown in FIG. 7, the silicon carbide semiconductor device 1 and the wiring 13 are encapsulated (molded) with a mold resin 14. Specifically, the mold resin 14 is provided on the main surface so as to cover the source wiring electrode 11 side. <Second Embodiment> A second embodiment according to the present invention is shown in FIG. 8. Parts that perform the same role as those in the first embodiment are denoted by the same reference numerals and their description is omitted. The silicon carbide semiconductor device 1a in FIG. 8 is configured as a planar SiC-MOSFET. In the silicon carbide semiconductor device 1 showing the first embodiment, as shown in FIG. 2, the lower end of the interlayer insulating film 9 (BPSG film 9a as the first layer) abuts on the contact surface 17 with the source electrode 10. However, in the silicon carbide semiconductor device 1a in FIG. 8, the difference is that the lower end of the interlayer insulating film 9 (BPSG film 9a as the first layer) abuts on the gate insulating film 7. Similar to the first embodiment, the BPSG film 9a with a low glass transition temperature of the first layer that absorbs thermal expansion when the source wiring electrode 11 is provided can prevent the interlayer insulating film 9 from being damaged. Further, the BPSG film 9a of the first layer and the BPSG film 9c of the third layer can make it difficult for hydrogen ions to pass through and improve the reliability of the silicon carbide semiconductor device. <Third Embodiment> A third embodiment of the present invention is shown in FIG. 9. Parts that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and their description is omitted. The silicon carbide semiconductor device 1b in FIG. 9 is configured as a planar SiC-MOSFET as shown in FIG. 9. The silicon carbide semiconductor device 1b in FIG. 9 includes a BPSG film 9a having a low glass transition temperature in the first layer of the interlayer insulating film, a TEOS oxide film 9b in the second layer, and a BPSG having a high glass transition temperature in the third layer. In addition, between the BPSG film 9c in the third layer and the gate electrode 8, a layer having at least one of silicon dioxide (SiO2) and silicon nitride (SiN) is provided as a fourth layer 9d. The fourth layer 9d prevents phosphorus contained in the BPSG film 9c in the third layer from diffusing into the gate electrode 8, and prevents the phosphorus concentration of the BPSG film 9c in the third layer from decreasing. For this reason, it is possible to prevent the phosphorus concentration of the BPSG film 9c in the third layer from decreasing and the ability to absorb hydrogen ions from decreasing, and to prevent hydrogen ions from reaching the gate electrode 8. Therefore, it is possible to prevent hydrogen ions from reaching the channel area through the gate electrode 8 and the gate insulating film 7, and the reliability of the silicon carbide semiconductor device 1b can be improved. When the fourth layer 9d is made of silicon nitride (SiN), the silicon nitride is formed by, for example, CVD, and patterned using a resist formed by photolithography and etching as a mask to form the fourth layer 9d. When the fourth layer 9d is made of silicon dioxide (SiO2), the silicon dioxide (SiO2) is formed by, for example, CVD, and patterned using a resist formed by photolithography and etching as a mask to form the fourth layer 9d. <Fourth Embodiment> A fourth embodiment of the present invention is shown in FIG. 10. The silicon carbide semiconductor device 1c in this embodiment is configured as a planar SiC-MOSFET as shown in FIG. 10. In the silicon carbide semiconductor device 1c of this embodiment, two gate electrodes 8a and 8b are provided separately on the gate insulating film 7, and fourth layers 9d1 and 9d2 made of at least one of silicon dioxide and silicon nitride are provided so as to cover the two gate electrodes respectively. A third layer 9c made of BPSG is formed between the fourth layers 9d1 and 9d2 covering the gate electrodes 8a and 8b and the second layer.

[0050] Thus, since there is no gate electrode between the two gate electrodes 8a and 8b and BPSG of the insulator exists there, the parasitic capacitor between the gate electrode and the drift layer 3 does not exist in that portion. Therefore, the silicon carbide semiconductor device 1c according to the present embodiment can operate faster than the silicon carbide semiconductor device 1 of FIG. 2. Moreover, similar to the third embodiment, the fourth layers 9d1 and 9d2 prevent hydrogen ions from reaching the gate electrodes 8a and 8b, and a highly reliable silicon carbide semiconductor device can be realized. Further, the BPSG film 9a having a low glass transition temperature of the first layer can prevent the interlayer insulating film 9 from being damaged when the temperature rises. Further, the BPSG film 9a of the first layer and the BPSG film 9c of the third layer can make it difficult for hydrogen ions to pass through and improve the reliability of the silicon carbide semiconductor device. <Fifth Embodiment> The fifth embodiment of the present invention is shown in FIG. 11. The silicon carbide semiconductor device 1d in the present embodiment is configured as a planar SiC-MOSFET as shown in FIG. 11. In the present embodiment, the gate electrode 8a and the gate electrode 8b are provided separately from each other on the gate insulating films 7a and 7b provided with a space therebetween, and fourth layers 9d1 and 9d2 made of at least one of silicon dioxide and silicon nitride are provided so as to cover the two gate electrodes respectively. A third layer 9c made of BPSG is formed between the fourth layers 9d1 and 9d2 covering the gate electrodes 8a and 8b respectively and the second layer. The difference from the aforementioned fourth embodiment is that the gate insulating films 7a and 7b are separated into two. The silicon carbide semiconductor device 1d of the present embodiment can achieve the same effects as the fourth embodiment.

[0051] In the above embodiment, an example of applying the silicon carbide semiconductor device of the present invention to a planar SiC-MOSFET has been described, but it is also applicable to an IGBT.

[0052] As described above, the present invention has been described. However, when implementing the present invention, various modifications and additions are possible without departing from the gist of the present invention, not limited to the above-described examples.

Description of Symbols

[0053] 1 Semiconductor device 2 Silicon carbide substrate 3 Drift layer 4 Body layer 5 Source layer 6 Body contact layer 7 Gate insulating film 8 Gate electrode 9 Interlayer insulating film 9a First layer (BPSG film) 9b Second layer (TEOS oxide film) 9c Third layer (BPSG film) 10 Source electrode 11 Source wiring electrode 12 Drain electrode 13 Wiring 13a Ball bond 14 Mold resin

Claims

1. A silicon carbide substrate formed of silicon carbide of a first conductivity type, A drift layer formed of silicon carbide of a first conductivity type on a first surface of the silicon carbide substrate, A plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, A plurality of source layers respectively formed of silicon carbide of a first conductivity type having a higher impurity concentration than the drift layer on each of the plurality of body layers, A gate insulating film formed to be in contact with the body layer and the source layer, A gate electrode formed on the gate insulating film, An interlayer insulating film formed to cover the gate electrode together with the gate insulating film and comprising, The interlayer insulating film includes a first layer, a second layer, and a third layer from a side far from the gate electrode, The materials of the first layer and the third layer are BPSG, The first layer has a glass transition temperature of 350°C or higher and 500°C or lower A silicon carbide semiconductor device.

2. The glass transition temperature of the BPSG of the third layer is 600°C or higher and 1000°C or lower The silicon carbide semiconductor device according to Claim 1.

3. The second layer is made of a TEOS oxide film The silicon carbide semiconductor device according to Claim 1 or Claim 2.

4. A fourth layer made of at least one of silicon dioxide and silicon nitride is provided between the third layer and the gate electrode The silicon carbide semiconductor device according to Claim 1.

5. The gate electrodes are provided two apart from each other on the gate insulating film, and the fourth layer made of at least one of silicon dioxide and silicon nitride is provided to cover each of the two gate electrodes, and BPSG of the third layer is formed between the two gate electrodes and the second layer The silicon carbide semiconductor device according to Claim 4

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