Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suitably bonding substrates together, and the manufacturing method thereof.SOLUTION: According to one embodiment, a semiconductor device comprises a lower insulating film and a plurality of lower pads provided in the lower insulating film. The device further comprises an upper insulating film provided on the lower insulating film, and a plurality of upper pads provided on the plurality of lower pads in the lower insulating film. Furthermore, a second pad included in the plurality of upper pads is arranged on a first pad included in the plurality of lower pads, and the structure of the second pad differs from the structure of the first pad.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] When manufacturing a semiconductor device by bonding substrates together, there is a possibility that the substrates cannot be properly bonded due to warping or magnification of at least one of the substrates.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a semiconductor device and a method for manufacturing the same that can properly bond substrates together.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor device includes a lower insulating film and a plurality of lower pads provided in the lower insulating film. The device further includes an upper insulating film provided on the lower insulating film and a plurality of upper pads provided on the plurality of lower pads within the upper insulating film. Further, a second pad included in the plurality of upper pads is disposed on a first pad included in the plurality of lower pads, and the structure of the second pad is different from the structure of the first pad.

Brief Description of the Drawings

[0006]

Figure 1

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 16, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. The semiconductor device of FIG. 1 is, for example, a three-dimensional memory. The semiconductor device of FIG. 1 is manufactured by bonding an array wafer including an array region (array chip) 1 and a circuit wafer including a circuit region (circuit chip) 2 as will be described later.

[0009] The array region 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 provided on the memory cell array 11, and an interlayer insulating film 13 provided under the memory cell array 11. The memory cell array 11 is provided in the interlayer insulating film 13 under the insulating film 12. The insulating film 12 is, for example, a silicon oxide film (SiO2 film) or a silicon nitride film (SiN film). The interlayer insulating film 13 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and other insulating films. The interlayer insulating film 13 is an example of an upper insulating film.

[0010] The circuit region 2 is provided under the array region 1. The symbol S indicates the boundary surface (bonding surface) between the array region 1 and the circuit region 2. The circuit region 2 includes an interlayer insulating film 14 disposed under the interlayer insulating film 13 and a substrate 15 disposed under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a silicon (Si) substrate. The interlayer insulating film 14 is an example of a lower insulating film. The substrate 15 is an example of a lower substrate.

[0011] FIG. 1 shows the X direction and the Y direction that are parallel to the surface of the substrate 15 and perpendicular to each other, and the Z direction that is perpendicular to the surface of the substrate 15. These X direction, Y direction, and Z direction intersect with each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0012] The array region 1 includes a plurality of word lines WL and a source line SL as a plurality of electrode layers in the memory cell array 11. FIG. 1 shows the stepped portion 21 of the memory cell array 11. Each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to the bit line BL via a via plug 24 and is also electrically connected to the source line SL. The source line SL includes a lower layer SL1 that is a semiconductor layer and an upper layer SL2 that is a metal layer.

[0013] The circuit region 2 includes a plurality of transistors 31 in the interlayer insulating film 14. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 with a gate insulating film interposed therebetween, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 15. Further, the circuit region 2 includes a plurality of contact plugs 33 provided on the gate electrode 32, the source diffusion layer, or the drain diffusion layer of these transistors 31, a wiring layer 34 provided on these contact plugs 33 and including a plurality of wirings, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wirings.

[0014] The circuit region 2 is further provided on the wiring layer 35 and includes a wiring layer 36 including a plurality of wirings, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37. The metal pads 38 are arranged near the bonding surface S within the interlayer insulating film 14. The metal pad 38 is, for example, a metal layer including a Cu (copper) layer. The circuit region 2 functions as a control circuit (logic circuit) for controlling the operation of the array region 1. This control circuit is composed of transistors 31 etc. and is electrically connected to the metal pad 38. The metal pad 38 is an example of a lower pad.

[0015] The array region 1 includes a plurality of metal pads 41 provided on the above plurality of metal pads 38 and a plurality of via plugs 42 provided on these metal pads 41. Further, the array region 1 includes a wiring layer 43 provided on these via plugs 42 and including a plurality of wirings, and a wiring layer 44 provided on the wiring layer 43 and including a plurality of wirings. The metal pads 41 are arranged near the bonding surface S within the interlayer insulating film 13. The metal pad 41 is, for example, a metal layer including a Cu layer. The above bit line BL is included in the wiring layer 44. Also, the above control circuit is electrically connected to the memory cell array 11 via the metal pads 41, 38 etc. and controls the operation of the memory cell array 11 via the metal pads 41, 38 etc. The metal pad 41 is an example of an upper pad.

[0016] The array region 1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on these via plugs 45 and on the insulating film 12, and a passivation film 47 provided on the metal pads 46 and on the insulating film 12. The metal pad 46 is, for example, a metal layer including a Cu layer and functions as an external connection pad (bonding pad) of the semiconductor device in FIG. 1. The passivation film 47 is, for example, a laminated insulating film including a silicon oxide film and a silicon nitride film and has an opening P for exposing the upper surface of the metal pad 46. The metal pad 46 can be connected to a mounting substrate or other device via a bonding wire, solder ball, metal bump etc. through the opening P.

[0017] Note that the metal pads 38 and 41 of the present embodiment have a structure shown in FIG. 7 described later in more detail. Further details of the metal pads 38 and 41 of the present embodiment will be described later.

[0018] FIG. 2 is a cross-sectional view showing the structure of the columnar portion CL of the first embodiment. FIG. 2 shows one of the plurality of columnar portions CL shown in FIG. 1.

[0019] As shown in FIG. 2, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on an interlayer insulating film 13 (see FIG. 1). The word line WL is, for example, a metal layer including a W (tungsten) layer. The insulating layer 51 is, for example, a silicon oxide film.

[0020] The columnar portion CL sequentially includes a block insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is, for example, an insulating film such as a silicon nitride film, and is formed on the side surfaces of the word line WL and the insulating layer 51 via the block insulating film 52. The charge storage layer 53 may be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer, and is formed on the side surface of the charge storage layer 53 via the tunnel insulating film 54. The block insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, a silicon oxide film or a metal insulating film.

[0021] FIGS. 3 and 4 are cross-sectional views showing a method of manufacturing the semiconductor device of the first embodiment.

[0022] FIG. 3 shows an array wafer W1 including a plurality of array regions 1 and a circuit wafer W2 including a plurality of circuit regions 2. The orientation of the array wafer W1 in FIG. 3 is opposite to that of the array region 1 in FIG. 1. In the present embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2. FIG. 3 shows the array wafer W1 before the orientation is reversed for bonding, and FIG. 1 shows the array region 1 after the orientation is reversed, bonded, and diced for bonding. The array wafer W1 is an example of an upper wafer. The circuit wafer W2 is an example of a lower wafer.

[0023] In FIG. 3, reference sign S1 indicates the upper surface of the array wafer W1, and reference sign S2 indicates the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 16 disposed under the insulating film 12. The substrate 16 is a semiconductor substrate such as a silicon substrate, for example. The substrate 16 is an example of an upper substrate.

[0024] In the present embodiment, first, as shown in FIG. 3, a memory cell array 11, an insulating film 12, an interlayer insulating film 13, a stepped portion 21, a metal pad 41, etc. are formed on the substrate 16 of the array wafer W1, and an interlayer insulating film 14, a transistor 31, a metal pad 38, etc. are formed on the substrate 15 of the circuit wafer W2. For example, a via plug 45, a wiring layer 44, a wiring layer 43, a via plug 42, and a metal pad 41 are sequentially formed on the substrate 16. Also, a contact plug 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a via plug 37, and a metal pad 38 are sequentially formed on the substrate 15. Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded by mechanical pressure so that the surface S1 and the surface S2 face each other. Thereby, the interlayer insulating film 13 and the interlayer insulating film 14 are adhered. Specifically, the interlayer insulating film 13 is disposed on the interlayer insulating film 14, and each metal pad 41 is disposed on the corresponding metal pad 38. Next, the array wafer W1 and the circuit wafer W2 are annealed. Thereby, the metal pad 41 and the metal pad 38 are joined. In this way, the substrate 16 and the substrate 15 are bonded via the interlayer insulating films 13 and 14.

[0025] Thereafter, the substrate 15 is thinned by CMP (Chemical Mechanical Polishing), the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are diced into a plurality of chips. In this way, the semiconductor device of FIG. 1 is manufactured. Note that the metal pad 46 and the passivation film 47 are formed on the insulating film 12, for example, after the thinning of the substrate 15 and the removal of the substrate 16.

[0026] In this embodiment, the array wafer W1 and the circuit wafer W2 are bonded together. However, the array wafers W1 may be bonded together instead. The content described above with reference to FIGS. 1 to 4 and the content described below with reference to FIGS. 5 to 16 are also applicable to the bonding of the array wafers W1.

[0027] Further, FIG. 1 shows the interface between the interlayer insulating film 13 and the interlayer insulating film 14 and the interface between the metal pad 41 and the metal pad 38. However, it is common that these interfaces are not observed after the annealing. However, the positions where these interfaces were present can be estimated by detecting, for example, the inclination of the side surface of the metal pad 41 or the metal pad 38 and the misalignment between the side surface of the metal pad 41 and the side surface of the metal pad 38.

[0028] Also, the semiconductor device of this embodiment may be the subject of a transaction in the state of FIG. 1 after being diced into a plurality of chips, or may be the subject of a transaction in the state of FIG. 4 before being diced into a plurality of chips. FIG. 1 shows the semiconductor device in the state of a chip, and FIG. 4 shows the semiconductor device in the state of a wafer. In this embodiment, a plurality of chip-shaped semiconductor devices (FIG. 1) are manufactured from one wafer-shaped semiconductor device (FIG. 4).

[0029] FIG. 5 is a perspective view schematically showing the shapes of the array wafer W1 and the circuit wafer W2 of the first embodiment.

[0030] In this embodiment, when a memory cell array 11, an insulating film 12, an interlayer insulating film 13, etc. are formed on a substrate 16 (see FIG. 3), the substrate 16 warps due to the influence of the memory cell array 11, the insulating film 12, the interlayer insulating film 13, etc. As a result, the array wafer W1 warps as shown in FIG. 5(a). However, FIG. 5(a) shows the warp that occurs in the array wafer W1 exaggeratedly larger than the actual warp for ease of viewing the drawing.

[0031] In FIG. 5(a), the warp of the array wafer W1 (substrate 16) occurs such that the direction of the warp in the cross-section along the X direction and the direction of the warp in the cross-section along the Y direction are opposite. For example, in the XZ cross-section passing through the center of the array wafer W1, the array wafer W1 warps into a shape convex downward. On the other hand, in the YZ cross-section passing through the center of the array wafer W1, the array wafer W1 warps into a shape convex upward. Therefore, the warp of the array wafer W1 in FIG. 5(a) occurs such that the direction of the warp in the XZ cross-section and the direction of the warp in the YZ cross-section are opposite.

[0032] Such a warp of the array wafer W1 is caused, for example, by the influence of the word line WL. FIG. 5(a) schematically shows the word line WL extending in the X direction. Since the shape of the word line WL has a large anisotropy between the X direction and the Y direction, it causes such a warp of the array wafer W1.

[0033] Similarly, when an interlayer insulating film 14, etc. are formed on a substrate 15 (see FIG. 3), the substrate 15 warps due to the influence of the interlayer insulating film 14, etc. As a result, the circuit wafer W2 warps as shown in FIG. 5(b). However, FIG. 5(b) shows the warp that occurs in the circuit wafer W2 exaggeratedly larger than the actual warp for ease of viewing the drawing.

[0034] In FIG. 5(b), the warp of the circuit wafer W2 (substrate 15) occurs such that the direction of warp in the cross section along the X direction and the direction of warp in the cross section along the Y direction are the same. For example, in the XZ cross section passing through the center of the circuit wafer W2, the circuit wafer W2 is warped into a shape convex upward. Also, in the YZ cross section passing through the center of the circuit wafer W1, the circuit wafer W2 is warped into a shape convex upward. Therefore, the warp of the circuit wafer W2 in FIG. 5(b) occurs such that the direction of warp in the XZ cross section and the direction of warp in the YZ cross section are the same.

[0035] The circuit wafer W2 does not include components having a large shape anisotropy between the X direction and the Y direction, such as the word line WL. Therefore, while the warp of the array wafer W1 occurs anisotropically, the warp of the circuit wafer W2 occurs isotropically. That is, the state of the warp of the circuit wafer W2 is different from the state of the warp of the array wafer W1. Generally, since the array wafer W1 warps more than the circuit wafer W2, the warp of the array wafer W1 often becomes a problem.

[0036] Furthermore, when the memory cell array 11, the insulating film 12, the interlayer insulating film 13, etc. are formed on the substrate 16, not only does the substrate 16 warp due to the influence of the memory cell array 11, the insulating film 12, the interlayer insulating film 13, etc., but also the magnification of the substrate 16 changes. The change in the magnification of the substrate 16 means that the substrate 16 expands or contracts in a plan view due to the stress of the interlayer insulating film 13 or the like. Similarly, when the interlayer insulating film 14, etc. are formed on the substrate 15, not only does the substrate 15 warp due to the influence of the interlayer insulating film 14, etc., but also the magnification of the substrate 15 changes. Generally, since the magnitude and direction of the stress of the interlayer insulating film 14 are different from the magnitude and direction of the stress of the interlayer insulating film 13, the state of the magnification of the circuit wafer W2 is different from the state of the magnification of the array wafer W1.

[0037] The warpage state of the wafer can be detected, for example, by measuring the amount of warpage of the wafer or the value of the differential of the warpage of the wafer. On the other hand, the magnification state of the wafer can be detected, for example, by measuring the value of the magnification of the wafer or the magnification difference of the wafer. Details of these measurements will be described later.

[0038] Hereinafter, with reference to FIGS. 6 to 9, the semiconductor device of the present embodiment and the semiconductor device of the comparative example of the present embodiment will be compared.

[0039] FIG. 6 is a cross-sectional view showing a state in which the array wafer W1 and the circuit wafer W2 of the comparative example of the first embodiment are bonded together.

[0040] FIG. 6 corresponds to an enlarged view of FIG. 4. FIG. 6 shows the substrate 16, the interlayer insulating film 13, and the plurality of metal pads 41 of the array wafer W1, and the substrate 15, the interlayer insulating film 14, and the plurality of metal pads 38 of the circuit wafer W2, and illustration of other components shown in FIG. 4 is omitted.

[0041] FIG. 6 further shows the metal pads 38a to 38e included in the plurality of metal pads 38 and the metal pads 41a to 41e included in the plurality of metal pads 41. The metal pads 41a to 41e respectively correspond to the metal pads 38a to 38e. Therefore, the metal pads 41a to 41e are respectively disposed on the metal pads 38a to 38e and are electrically connected to the metal pads 38a to 38e. In FIG. 6, the metal pad 41c is located on the central axis of the array wafer W1, and the metal pad 38c is located on the central axis of the circuit wafer W2. Each of the metal pads 38a to 38e is an example of a first pad. Each of the metal pads 41a to 41e is an example of a second pad.

[0042] In this comparative example, the structure of the metal pad 41a is the same as that of the metal pad 38a. Specifically, the shape of the metal pad 41a in plan view is congruent to the shape of the metal pad 38a in plan view, the orientation of the metal pad 41a in plan view is the same as the orientation of the metal pad 38a in plan view, and the thickness of the metal pad 41a is the same as the thickness of the metal pad 38a.

[0043] In this comparative example, the shape of the metal pad 38a in plan view is the shape of the upper surface of the metal pad 38a (square), and the shape of the metal pad 41a in plan view is the shape of the lower surface of the metal pad 41a (square). Therefore, the shape of the metal pad 38a in plan view and the shape of the metal pad 41a in plan view are congruent squares. Also, the shape of the upper surface of the metal pad 38a is a square having four sides parallel to the X direction or the Y direction, and the shape of the lower surface of the metal pad 41a is also a square having four sides parallel to the X direction or the Y direction. Therefore, the orientation of the metal pad 41a in plan view and the orientation of the metal pad 38a in plan view are the same. The above relationship also holds between the metal pads 38b and 41b, between the metal pads 38c and 41c, between the metal pads 38d and 41d, and between the metal pads 38e and 41e.

[0044] Therefore, the metal pads 38a and 41a of this comparative example should be arranged such that the metal pad 41a and the metal pad 38a completely overlap in plan view if there is no misalignment between the metal pad 38a and the metal pad 41a.

[0045] However, in this comparative example, due to the difference in the warpage and magnification states between the circuit wafer W2 and the array wafer W1, misalignment occurs between the metal pad 38a and the metal pad 41a. As a result, the metal pads 38a and 41a in this comparative example are arranged such that the metal pad 41a and the metal pad 38a partially overlap in plan view. This may deteriorate the electrical characteristics of the metal pads 38a and 41a, such as an increase in the electrical resistance between the metal pad 38a and the metal pad 41a. The same applies to the metal pads 38b and 41b, the metal pads 38d and 41d, and the metal pads 38e and 41e. On the other hand, since the metal pads 38c and 41c are arranged on the central axis, such problems do not occur in the metal pads 38c and 41c. Generally, the greater the distance between the central axis of the array wafer W1 and the metal pad 41, the greater the misalignment between the metal pad 38 and the metal pad 41.

[0046] FIG. 6 shows the area A1 of each metal pad 41 in plan view, the area A2 of each metal pad 38 in plan view, and the joint area A between the metal pad 41 and the metal pad 38 corresponding to each other. The joint area A is the area of the joint portion between the upper surface of the metal pad 38 and the lower surface of the metal pad 41.

[0047] In this comparative example, the shape of the metal pad 41a in a plan view is congruent with the shape of the metal pad 38a in a plan view. Therefore, the area A1 of the metal pad 41a is the same as the area A2 of the metal pad 38a (A1 = A2). Also, in this comparative example, the orientation of the metal pad 41a in a plan view is the same as the orientation of the metal pad 38a in a plan view. Therefore, if there is no misalignment between the metal pads 38a and 41a, the metal pad 41a is arranged so as to completely overlap the metal pad 38a in a plan view, and the bonding area A of the metal pads 41a and 38a should be the same as the area A1 of the metal pad 41a and the area A2 of the metal pad 38a (A = A1, A2). However, in this comparative example, since misalignment occurs between the metal pads 38a and 41a, the bonding area A of the metal pads 41a and 38a is smaller than the area A1 of the metal pad 41a and the area A2 of the metal pad 38a (A < A1, A2). This is the same for the metal pads 38b and 41b, the metal pads 38d and 41d, and the metal pads 38e and 41e.

[0048] The dashed lines shown in FIG. 6 indicate the central axes of the metal pads 38a to 38e. Therefore, the distance between these dashed lines represents the pitch between the metal pads 38a to 38e. Similarly, the pitch between the metal pads 41a to 41e is represented by the distance between the central axes of the metal pads 41a to 41e. In this comparative example, the pitch between the metal pads 41a to 41e is different from the pitch between the metal pads 38a to 38e due to the warping and magnification effects of the array wafer W1 and the circuit wafer W2.

[0049] FIG. 7 is a cross-sectional view showing a state in which the array wafer W1 and the circuit wafer W2 of the first embodiment are bonded together.

[0050] FIG. 7 is an enlarged view similar to FIG. 6. Similar to FIG. 6, FIG. 7 shows the metal pads 38a to 38e included in the plurality of metal pads 38 and the metal pads 41a to 41e included in the plurality of metal pads 41. Hereinafter, the differences between this embodiment and the above comparative example regarding the metal pads 38a to 38e and the metal pads 41a to 41e will be described.

[0051] In this embodiment, the structure of the metal pad 41a is different from that of the metal pad 38a. Specifically, the shape of the metal pad 41a in plan view is incongruent with the shape of the metal pad 38a in plan view. The thickness of the metal pad 41a is the same as that of the metal pad 38a in this embodiment, but it may be different from the thickness of the metal pad 38a. On the other hand, as will be described later, when the shape of the metal pad 41a in plan view is congruent with the shape of the metal pad 38a in plan view, the orientation of the metal pad 41a in plan view may be different from the orientation of the metal pad 38a in plan view. Thus, the metal pads 38a and 41a with different structures from each other can be realized in various forms.

[0052] In this embodiment, the shape of the metal pad 38a in plan view is the shape of the upper surface of the metal pad 38a (rectangle), and the shape of the metal pad 41a in plan view is the shape of the lower surface of the metal pad 41a (square). Therefore, the shape of the metal pad 38a in plan view and the shape of the metal pad 41a in plan view are incongruent. Also, the shape of the upper surface of the metal pad 38a is a rectangle having two long sides parallel to the X direction and two short sides parallel to the Y direction, and the shape of the lower surface of the metal pad 41a is a square having four sides parallel to the X direction or the Y direction. Therefore, both the metal pad 41a in plan view and the metal pad 38a in plan view have sides parallel to the X direction and sides parallel to the Y direction. The above relationship also holds between the metal pads 38b and 41b, between the metal pads 38d and 41d, and between the metal pads 38e and 41e. On the other hand, the relationship between the metal pads 38c and 41c is the same as the relationship in the above comparative example.

[0053] In this embodiment, when forming the metal pad 38a in the interlayer insulating film 14, the structure of the metal pad 38a is corrected. Specifically, when forming the metal pad 38a in the interlayer insulating film 14, the shape of the metal pad 38a in plan view is changed from a square as shown in FIG. 6 to a rectangle as shown in FIG. 7. As a result, the metal pad 38a having the shape shown in FIG. 7 is formed. If such correction is not performed, the metal pad 38a having the shape shown in FIG. 6 is formed. According to this embodiment, by performing such correction, it is possible to make the bonding area A of the corrected metal pads 41a and 38a larger than the bonding area A of the metal pads 41a and 38a before correction (see FIGS. 6 and 7).

[0054] As described above, if the warpage and magnification states of the circuit wafer W2 are different from those of the array wafer W1, misalignment of the metal pads 38a and 41a occurs. Therefore, in this embodiment, before forming the metal pad 38a in the interlayer insulating film 14, a value representing the state of the array wafer W1 is measured. Examples of such values are values related to the warpage of the array wafer W1 and values related to the magnification of the array wafer W1. In this embodiment, based on the measurement result of the value representing the state of the array wafer W1, the structure of the metal pad 38a is corrected. For example, the larger the amount of warpage of the array wafer W1, the larger the increase amount (correction amount) of the area A2 of the metal pad 38a. Thereby, the bonding area A of the metal pads 41a and 38a can be increased, and deterioration of the electrical characteristics of the metal pads 38a and 41a can be suppressed. This is the same for the metal pads 38b and 41b, the metal pads 38d and 41d, and the metal pads 38e and 41e. On the other hand, in this embodiment, since the misalignment of the metal pads 38c and 41c does not pose a problem, correction of the structure of the metal pad 38a is unnecessary.

[0055] In this embodiment, the shape of the metal pad 41a in plan view is incongruent with the shape of the metal pad 38a in plan view. Therefore, the area A1 of the metal pad 41a is different from the area A2 of the metal pad 38a (A1≠A2). Specifically, since the area A2 of the metal pad 38a has increased due to correction, the area A1 of the metal pad 41a is smaller than the area A2 of the metal pad 38a (A1<A2). In this embodiment, in order to ensure a large bonding area A between the metal pads 41a and 38a, it is desirable that the bonding area A between the metal pads 41a and 38a be set to 40% or more of the area A1 of the metal pad 41a and / or be set to 40% or more of the area A2 of the metal pad 38a (A≧0.4×A1 and / or A≧0.4×A2). In the metal pads 41a and 38a in FIG. 7, the bonding area A is 40% or more of the area A1 and less than 40% of the area A2. The same applies to the metal pads 38b and 41b, the metal pads 38d and 41d, and the metal pads 38e and 41e. On the other hand, for the metal pads 38c and 41c, A=A1=A2 holds.

[0056] The dashed lines shown in FIG. 7 indicate the central axes of the metal pads 38a to 38e. Therefore, the distance between these dashed lines represents the pitch between the metal pads 38a to 38e. Similarly, the pitch between the metal pads 41a to 41e is represented by the distance between the central axes of the metal pads 41a to 41e. In this embodiment, similar to the above comparative example, the pitch between the metal pads 41a to 41e is different from the pitch between the metal pads 38a to 38e due to the warpage and magnification of the array wafer W1 and the circuit wafer W2. Also, the pitch between the metal pads 38a to 38e shown in FIG. 7 is different from the pitch between the metal pads 38a to 38e shown in FIG. 6. This indicates that the pitch between the metal pads 38a to 38e has changed due to correction.

[0057] Note that instead of performing the above correction based on the value representing the state of the array wafer W1, it may be performed based on the value representing the state of the circuit wafer W2, or it may be performed based on both the value representing the state of the array wafer W1 and the value representing the state of the circuit wafer W2. In the present embodiment, assuming that the warp of the circuit wafer W2 is smaller than that of the array wafer W1, the above correction is performed based only on the value representing the state of the array wafer W1. Similarly, instead of performing the above correction on the metal pad 38, it may be performed on the metal pad 41, or it may be performed on both the metal pad 38 and the metal pad 41.

[0058] FIG. 8 is a schematic diagram showing a method of manufacturing a semiconductor device according to a comparative example of the first embodiment.

[0059] In this comparative example, when forming the metal pad 41 in the interlayer insulating film 13 of the array wafer W1, a resist layer is formed on the interlayer insulating film 13, and the resist layer is patterned using the exposure apparatus 61. Next, a plurality of pad grooves are formed in the interlayer insulating film 13 by etching using the resist layer, and the metal pad 41 is formed in these pad grooves. Therefore, the shape and orientation of the metal pad 41 in plan view are mainly determined by the patterning of the resist layer, and the thickness of the metal pad 41 is mainly determined by the etching of the pad grooves.

[0060] Similarly, when forming the metal pad 38 in the interlayer insulating film 14 of the circuit wafer W2, a resist layer is formed on the interlayer insulating film 14, and the resist layer is patterned using the exposure apparatus 62. Next, a plurality of pad grooves are formed in the interlayer insulating film 14 by etching using the resist layer, and the metal pad 38 is formed in these pad grooves. Therefore, the shape and orientation of the metal pad 38 in plan view are mainly determined by the patterning of the resist layer, and the thickness of the metal pad 38 is mainly determined by the etching of the pad grooves. Note that the exposure apparatus 62 may be the same as the exposure apparatus 61 or may be different from the exposure apparatus 61.

[0061] Thereafter, the array wafer W1 and the circuit wafer W2 are bonded to each other using a bonding apparatus 63. In this way, the structure shown in FIG. 6 is realized.

[0062] FIG. 9 is a schematic diagram showing a method of manufacturing a semiconductor device according to the first embodiment.

[0063] Also in this embodiment, when forming the metal pads 41 in the interlayer insulating film 13 of the array wafer W1, a resist layer is formed on the interlayer insulating film 13, and the resist layer is patterned using an exposure apparatus 61. Next, a plurality of pad grooves are formed in the interlayer insulating film 13 by etching using the resist layer, and the metal pads 41 are formed in these pad grooves. In this embodiment, further, a value related to the warp of the array wafer W1 is measured by a warp measuring device 64, and a value related to the magnification of the array wafer W1 is measured by the exposure apparatus 61. The value measured by the warp measuring device 64 and the value measured by the exposure apparatus 61 are provided from the warp measuring device 64 and the exposure apparatus 61 to the exposure apparatus 62.

[0064] Similarly, when forming the metal pads 38 in the interlayer insulating film 14 of the circuit wafer W2, a resist layer is formed on the interlayer insulating film 14, and the resist layer is patterned using the exposure apparatus 62. At this time, the exposure apparatus 62 corrects the shape and orientation of the resist pattern for the metal pads 38 (feed-forward correction) based on the values provided from the warp measuring device 64 and the exposure apparatus 61. Next, a plurality of pad grooves are formed in the interlayer insulating film 14 by etching using the resist layer, and the metal pads 38 are formed in these pad grooves. As a result, due to the influence of the correction of the resist pattern, the shape and orientation of the metal pads 38 are corrected. When correcting the thickness of the metal pads 38, the depth of the pad grooves is corrected (feed-forward correction) based on the values provided from the warp measuring device 64 and the exposure apparatus 61.

[0065] Thereafter, the array wafer W1 and the circuit wafer W2 are bonded to each other using a bonding apparatus 63. In this way, the structure shown in FIG. 7 is realized.

[0066] Note that according to the correction of the shape of the metal pad 38, the shape of each metal pad 38 in a plan view is changed from the shape shown in FIG. 6 to the shape shown in FIG. 7, for example. In this case, in the correction performed by the exposure apparatus 62, the exposure data used for exposing the resist layer is changed from the exposure data for forming the metal pad 38 in FIG. 6 to the exposure data for forming the metal pad 38 in FIG. 7. Thereby, the shape of the resist pattern for the metal pad 38 is corrected, and as a result, the shape of the metal pad 38 is corrected.

[0067] FIG. 10 is a cross-sectional view for explaining the warpage of the array wafer W1 and the circuit wafer W2 of the first embodiment.

[0068] FIGS. 10(a) to 10(e) show five states of the array wafer W1 and the circuit wafer W2. The array wafer W1 in FIG. 10(a) is greatly warped so as to have a convex shape upward, and the array wafer W1 in FIG. 10(b) is slightly warped so as to have a convex shape upward. The array wafer W1 in FIG. 10(c) is not warped. The array wafer W1 in FIG. 10(d) is slightly warped so as to have a concave shape downward, and the array wafer W1 in FIG. 10(e) is greatly warped so as to have a concave shape downward. Note that the circuit wafer W2 is not warped in any of FIGS. 10(a) to 10(e).

[0069] Each of FIGS. 10(a), 10(b), 10(d), and 10(e) shows the warpage amount W of the array wafer W1. Here, the magnitude of the warpage amount W is the maximum protruding amount of the array wafer W1 with respect to the edge of the array wafer W1. Further, the value of the warpage amount W is defined to be negative in FIGS. 10(a) and 10(b), zero in FIG. 10(c), and positive in FIGS. 10(d) and 10(e). Therefore, in FIGS. 10(a) to 10(e), the warpage amount W in FIG. 10(a) is the smallest, and the warpage amount W in FIG. 10(e) is the largest. Also, the magnitude (absolute value) of the warpage amount W is large in FIGS. 10(a) and 10(e), and small in FIGS. 10(b) and 10(d).

[0070] FIG. 11 is a table for explaining a method of correcting the metal pad 38 of the first embodiment.

[0071] FIG. 11 shows an example of correcting the structure of the metal pad 38 of the circuit wafer W2 based on the value of the warp derivative of the array wafer W1. The center portion, intermediate portion, and edge portion of each wafer correspond to the portion near the central axis of each wafer, the portion near the edge of each wafer, and the portion between the center portion and the edge portion of each wafer, respectively. The warp derivative in the X direction of the array wafer W1 represents the gradient of the surface of the wafer W1 in the XZ cross section of the array wafer W1. The warp derivative in the Y direction of the array wafer W1 represents the gradient of the surface of the wafer W1 in the YZ cross section of the array wafer W1.

[0072] In FIG. 11, since the warp derivatives in the X direction and the Y direction of the center portion of the array wafer W1 are small, the structure of the metal pad 38 of the center portion of the circuit wafer W2 is corrected to be small. On the other hand, since the warp derivatives in the X direction and the Y direction of the edge portion of the array wafer W1 are large, the structure of the metal pad 38 of the edge portion of the circuit wafer W2 is corrected to be large. Such a correction state is illustrated in FIG. 7.

[0073] The exposure apparatus 62 (FIG. 9) of the present embodiment stores in advance, as a library, the relationship between the values measured by the exposure apparatus 61 and the warp measurement apparatus 64 and the exposure conditions of the exposure apparatus 62. Then, when the exposure apparatus 62 of the present embodiment receives the values measured by the exposure apparatus 61 and the warp measurement apparatus 64, it determines the exposure conditions based on the received values and the library. Thereby, it becomes possible to perform the correction as shown in FIG. 7.

[0074] FIG. 12 is a schematic plan view for explaining a method of correcting the metal pad 38 of the first embodiment.

[0075] FIG. 12(a) shows a state in which the array wafer W1 and the circuit wafer W2 of the above comparative example are bonded together, similar to FIG. 6. In this comparative example, the shape of each metal pad 41 in plan view is square, and the shape of each metal pad 38 in plan view is also square. Further, in each pair of the metal pads 38 and 41, the shape of the metal pad 41 in plan view is congruent with the shape of the metal pad 38 in plan view, and the orientation of the metal pad 41 in plan view is the same as the orientation of the metal pad 38 in plan view.

[0076] FIG. 12(b) shows a state in which the array wafer W1 and the circuit wafer W2 of this embodiment are bonded together, similar to FIG. 7. In this embodiment, the shape of each metal pad 41 in plan view is square, and the shape of each metal pad 38 in plan view is square or rectangular. Further, in each pair of the metal pads 38 and 41, the shape of the metal pad 41 in plan view is non-congruent with the shape of the metal pad 38 in plan view (however, the pair of the central metal pads 38 and 41 is excluded). In each pair of the metal pads 38 and 41 shown in FIG. 12(b), the bonding area A is 40% or more of the area A1.

[0077] FIG. 13 is a cross-sectional view showing a method of manufacturing the array wafer W1 of the first embodiment.

[0078] FIG. 13(a) shows a substrate 16, an interlayer insulating film 13 formed on the substrate 16, and a resist layer 71 formed on the interlayer insulating film 13. When forming the metal pad 41 in the interlayer insulating film 13 of the array wafer W1, the resist layer 71 is formed on the interlayer insulating film 13 (FIG. 13(a)). The resist layer 71 may be formed on the interlayer insulating film 13 via a hard mask layer. Next, the resist layer 71 is patterned using an exposure apparatus 61 (FIG. 9) (FIG. 13(b)). FIG. 13(b) shows a plurality of openings H1 formed in the resist layer 71.

[0079] Next, a plurality of pad grooves H2 are formed in the interlayer insulating film 13 by etching using the resist layer 71 (FIG. 13(c)). Next, after removing the resist layer 71, metal pads 41 are formed in these pad grooves H2 (FIG. 13(d)). In the present embodiment, further, a value related to the warp of the array wafer W1 is measured by a warp measuring device 64 (FIG. 9), and a value related to the magnification of the array wafer W1 is measured by an exposure device 61. The timing of this measurement may be a timing other than the timing of the process of FIG. 13(d). The value measured by the warp measuring device 64 and the value measured by the exposure device 61 are provided from the warp measuring device 64 and the exposure device 61 to the exposure device 62.

[0080] FIG. 14 is a cross-sectional view showing a method of manufacturing the circuit wafer W2 of the first embodiment.

[0081] FIG. 14(a) shows a substrate 15, an interlayer insulating film 14 formed on the substrate 15, and a resist layer 72 formed on the interlayer insulating film 14. When forming the metal pads 38 in the interlayer insulating film 14 of the circuit wafer W2, a resist layer 72 is formed on the interlayer insulating film 14 (FIG. 14(a)). The resist layer 72 may be formed on the interlayer insulating film 14 via a hard mask layer. Next, the resist layer 72 is patterned using an exposure device 62 (FIG. 9) (FIG. 14(b)). FIG. 14(b) shows a plurality of openings H3 formed in the resist layer 72. In the process of FIG. 14(b), the exposure device 62 corrects the shape and orientation of these openings H3 based on the values provided from the warp measuring device 64 and the exposure device 61.

[0082] Next, a plurality of pad grooves H4 are formed in the interlayer insulating film 14 by etching using the resist layer 72 (FIG. 14(c)). Next, after removing the resist layer 72, metal pads 38 are formed in these pad grooves H4 (FIG. 14(d)). As a result, due to the influence of the correction of the openings H3, the shape and orientation of the metal pads 38 are corrected.

[0083] Thereafter, the array wafer W1 and the circuit wafer W2 are bonded to each other using a bonding device 63 (FIG. 9). In this way, the structure shown in FIG. 7 is realized.

[0084] Note that FIGS. 13(a) to 14(b) omit illustration of the via plugs 42 and wiring layers 43 under the metal pads 41, and the via plugs 37 and wiring layers 36 under the metal pads 38. If the shape and orientation of the metal pads 38 are corrected, some of the metal pads 38 may be short-circuited with any of the via plugs 37 or any of the wirings in the wiring layer 36. In this case, short-circuiting may be avoided by correcting the thickness of the metal pads 38.

[0085] FIG. 15 is a plan view for explaining a method of correcting the metal pads 38 of the first embodiment.

[0086] FIG. 15(a) shows an example of the metal pads 38 before correction. The planar shape of the metal pads 38 in FIG. 15(a) is rectangular. FIGS. 15(b) to 15(f) show examples of the metal pads 38 after correction.

[0087] FIG. 15(b) shows an example in which the planar shape of the metal pads 38 in FIG. 15(a) is enlarged in the X direction and the Y direction. FIG. 15(c) shows an example in which the planar shape of the metal pads 38 in FIG. 15(a) is enlarged in the X direction. FIG. 15(d) shows an example in which the orientation of the metal pads 38 in FIG. 15(c) is rotated by 45 degrees. FIG. 15(e) shows an example in which the orientation of the metal pads 38 in FIG. 15(c) is rotated by 90 degrees. FIG. 15(f) shows an example in which the orientation of the metal pads 38 in FIG. 15(a) is rotated by 45 degrees.

[0088] In FIGS. 15(b) to 15(e), the shape of the metal pads 38 in plan view is corrected from FIG. 15(a). On the other hand, in FIG. 15(f), the orientation of the metal pads 38 in plan view is corrected from FIG. 15(a).

[0089] FIG. 16 is another plan view for explaining a method of correcting the metal pads 38 of the first embodiment.

[0090] FIG. 16(a) shows an example of the metal pad 38 before correction. The planar shape of the metal pad 38 in FIG. 16(a) is a circle. FIGS. 16(b) to 16(e) show examples of the metal pad 38 after correction.

[0091] FIG. 16(b) shows an example in which the planar shape of the metal pad 38 in FIG. 16(a) is enlarged in the X direction and the Y direction. FIG. 16(c) shows an example in which the planar shape of the metal pad 38 in FIG. 16(a) is enlarged in the X direction. FIG. 16(d) shows an example in which the orientation of the metal pad 38 in FIG. 16(c) is rotated by 45 degrees. FIG. 16(e) shows an example in which the orientation of the metal pad 38 in FIG. 16(c) is rotated by 90 degrees.

[0092] In FIGS. 16(b) to 16(e), the shape of the metal pad 38 in plan view is corrected from FIG. 16(a).

[0093] As described above, the semiconductor device of the present embodiment includes a combination of metal pads 38 and 41 in which the structure of a certain metal pad 38 and the structure of the corresponding metal pad 41 are different from each other. Therefore, according to the present embodiment, even when the array wafer W1 and / or the circuit wafer W2 is warped, or when the magnification of the array wafer W1 and / or the circuit wafer W2 changes, the array wafer W1 and the circuit wafer W2 can be suitably bonded together.

[0094] As described above, several embodiments have been described, but these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices and methods described in this specification can be implemented in various other forms. Also, various omissions, substitutions, and changes can be made to the forms of the devices and methods described in this specification without departing from the gist of the invention. The appended claims and equivalents thereof are intended to include such forms and modifications within the scope and gist of the invention.

Explanation of Reference Numerals

[0095] 1: Array region, 2: Circuit region, 11: Memory cell array, 12: Insulating film, 13: Interlayer insulating film, 14: Interlayer insulating film, 15: Substrate, 16: Substrate, 21: Staircase structure part, 22: Contact plug, 23: Word wiring layer, 24: Via plug, 31: Transistor, 32: Gate electrode, 33: Contact plug, 34: Wiring layer, 35: Wiring layer, 36: Wiring layer, 37: Via plug, 38, 38a, 38b, 38c, 38d, 38e: Metal pad, 41, 41a, 41b, 41c, 41d, 41e: Metal pad, 42: Via plug, 43: Wiring layer, 44: Wiring layer, 45: Via plug, 46: Metal pad, 47: Passivation film, 51: Insulating layer, 52: Block insulating film, 53: Charge storage layer, 54: Tunnel insulating film, 55: Channel semiconductor layer, 56: Core insulating film, 61: Exposure device, 62: Exposure device, 63: Bonding device, 64: Warpage measurement device, 71: Resist layer, 72: Resist layer

Claims

1. A lower insulating film, a plurality of lower pads provided in the lower insulating film, an upper insulating film provided on the lower insulating film, and a plurality of upper pads provided on the plurality of lower pads within the upper insulating film, wherein a second pad included in the plurality of upper pads is disposed on a first pad included in the plurality of lower pads, and a structure of the second pad is different from a structure of the first pad, a semiconductor device.

2. The semiconductor device according to claim 1, wherein a shape of the second pad in a plan view is incongruent with a shape of the first pad in the plan view.

3. The semiconductor device according to claim 1, wherein an area of the second pad in a plan view is different from an area of the first pad in the plan view.

4. The semiconductor device according to claim 1, wherein a shape of the second pad in a plan view is congruent with a shape of the first pad in the plan view, and an orientation of the second pad in the plan view is different from an orientation of the first pad in the plan view.

5. The semiconductor device according to claim 1, wherein a thickness of the second pad is different from a thickness of the first pad.

6. The semiconductor device according to claim 1, wherein a bonding area between the first pad and the second pad is 40% or more of an area of the first pad in a plan view and / or 40% or more of an area of the second pad in a plan view.

7. The semiconductor device according to claim 1, wherein a pitch between the upper pads is different from a pitch between the lower pads.

8. a memory cell array provided in the upper insulating film, and a control circuit provided in the lower insulating film and configured to control the memory cell array, the semiconductor device according to claim 1 further comprising the same.

9. a lower wafer including a lower insulating film and a plurality of lower pads provided in the lower insulating film, and an upper wafer including an upper insulating film provided on the lower insulating film and a plurality of upper pads provided on the plurality of lower pads within the upper insulating film, the semiconductor device comprising the same, wherein a second pad included in the plurality of upper pads is disposed on a first pad included in the plurality of lower pads, and a structure of the second pad is different from a structure of the first pad, a semiconductor device.

10. wherein the lower wafer further includes a lower substrate provided under the lower insulating film, and the upper wafer further includes an upper substrate provided on the upper insulating film, the semiconductor device according to claim 9.

11. The semiconductor device according to claim 10, wherein the state of warpage of the upper substrate is different from the state of warpage of the lower substrate.

12. The semiconductor device according to claim 10, wherein the magnification state of the upper substrate is different from the magnification state of the lower substrate.

13. Forming a lower insulating film on the lower substrate of the lower wafer, Forming a plurality of lower pads in the lower insulating film, Forming an upper insulating film on the upper substrate of the upper wafer, Forming a plurality of upper pads in the upper insulating film, By bonding the lower wafer and the upper wafer, the upper insulating film is disposed on the lower insulating film, and the plurality of upper pads are disposed on the plurality of lower pads. including The second pad included in the plurality of upper pads is disposed on the first pad included in the plurality of lower pads, The structure of the second pad is different from the structure of the first pad. A method of manufacturing a semiconductor device.

14. The first pad and the second pad are formed such that the bonding area between the first pad and the second pad is 40% or more of the area of the first pad in plan view and / or 40% or more of the area of the second pad in plan view. The method of manufacturing a semiconductor device according to claim 13.

15. Further including measuring a value representing the state of the lower substrate or the upper substrate, The first pad and the second pad are formed such that the structure of the second pad is different from the structure of the first pad based on the value. The method of manufacturing a semiconductor device according to claim 13.

16. The method of manufacturing a semiconductor device according to claim 15, wherein the value is a value related to the warpage of the lower substrate or the upper substrate.

17. The method of manufacturing a semiconductor device according to claim 15, wherein the value is a value related to the magnification of the lower substrate or the upper substrate.

18. Further including correcting the structure of the lower pad or the upper pad when forming the lower pad or the upper pad based on the value, The first pad and the second pad are formed such that the structure of the second pad before correction is the same as the structure of the first pad before correction, and the structure of the second pad after correction is different from the structure of the first pad after correction. The method of manufacturing a semiconductor device according to claim 15.

19. The correction is performed such that a joint area between the first pad and the second pad after correction is larger than a joint area between the first pad and the second pad before correction, the method for manufacturing a semiconductor device according to claim 18.

20. The correction is performed such that a pitch between the lower pads or between the upper pads after correction is different from a pitch between the lower pads or between the upper pads before correction, the method for manufacturing a semiconductor device according to claim 18.

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