Power semiconductor element

Abstract

To provide a power semiconductor element with improved electric characteristics.SOLUTION: A power semiconductor element 100 includes a substrate 101 of a first conductivity type, a drift layer 102 of the first conductivity type on the substrate, a well region 105 of a second conductivity type on the drift layer, a source region 150 of the first conductivity type on the well region, a gate electrode 130 disposed in a gate trench GT penetrating the source region and the well region, a gate insulating layer 120 disposed between the gate electrode and the well region, a dielectric layer 140 on the gate electrode, and a drain electrode 160 on a lower surface of the substrate. The gate electrode has a first width W1 on a lower surface, a second width W2 larger than the first width on an upper surface, and a step part BR with the width changing on a side surface. The step part exists at a level lower than a lower surface of the source region.SELECTED DRAWING: Figure 1a

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) power semiconductor device.

Background Art

[0002] A power semiconductor device is a semiconductor device that operates in an environment of high voltage and high current, and is used in fields that require high power switching such as power conversion, power converters, and inverters. A power semiconductor device is basically required to have a breakdown voltage characteristic against high voltage, and recently, a high-speed switching operation has additionally been required. Therefore, power semiconductor devices using SiC, which have better breakdown voltage characteristics than silicon (Si), have been studied.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the technical problems to be achieved by the present invention is to provide a power semiconductor device with improved electrical characteristics.

Means for Solving the Problems

[0004] The power semiconductor device according to an exemplary embodiment includes a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type on the drift layer, a source region of the first conductivity type on the well region, a gate electrode disposed in a gate trench penetrating the source region and the well region, a gate insulating layer disposed between the gate electrode and the well region, a dielectric layer on the gate electrode, and a drain electrode on the lower surface of the substrate. The gate electrode has a first width at the lower surface, a second width larger than the first width at the upper surface, and a stepped portion with a changed width on the side surface, and the stepped portion can be located at a level lower than the lower surface of the source region.

[0005] The power semiconductor device according to an exemplary embodiment includes a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type on the drift layer, a source region of the first conductivity type on the well region, a gate electrode disposed in a gate trench penetrating the source region and the well region, a gate insulating layer disposed between the gate electrode and the well region, and a drain electrode on the lower surface of the substrate. The gate electrode includes a first region and a second region on the first region. The maximum width of the first region is a first width, and the second region has a second width larger than the first width. The well region includes a channel region adjacent to the gate electrode, and the channel region can include a region overlapping with the first region in the horizontal direction and overlapping with the second region in the vertical direction.

[0006] The power semiconductor device according to an exemplary embodiment includes a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type on the drift layer, a source region of the first conductivity type on the well region, a gate electrode disposed in a gate trench penetrating the source region and the well region, a gate insulating layer covering the inner surface of the gate trench, a field relaxation region of the second conductivity type covering a part of the outer surface of the gate insulating layer, and a drain electrode on the lower surface of the substrate. The gate electrode has a maximum width on the upper surface and has an asymmetric shape in the vertical direction. The well region can include a region bent so as to face the gate electrode.

Advantages of the Invention

[0007] Since the gate electrode has a stepped portion, a power semiconductor device with improved electrical characteristics can be provided by allowing the channel region to be affected through two or more surfaces of the gate electrode.

[0008] The various and beneficial advantages and effects of the present invention are not limited to the above-described content and can be more easily understood in the process of describing specific embodiments of the present invention.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described as follows. In the following, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface", "side surface", etc. are represented by reference numerals in the drawings, and can be understood to be referred to based on the drawings unless otherwise specified.

[0011] FIG. 1a and FIG. 1b are a cross-sectional view and a partial enlarged view showing a power semiconductor device according to an exemplary embodiment, and FIG. 1b shows an enlarged view of the "A" region in FIG. 1a.

[0012] Referring to FIGS. 1a and 1b, the power semiconductor device 100 can include a substrate 101, a drift layer 102 on the substrate 101, a well region 105 disposed on the drift layer 102, a source region 107 disposed on the well region 105, a well contact region 109 on one side of the source region 107, a gate electrode 130 disposed within a gate trench GT that penetrates the source region 107 and the well region 105, a gate insulating layer 120 between the gate electrode 130 and the well region 105, a field relaxation region 104 outside the gate trench GT, a dielectric layer 140 covering the gate electrode 130, a source electrode 150 on the dielectric layer 140, and a drain electrode 160 on the lower surface of the substrate 101.

[0013] The substrate 101 can have an upper surface extending in the X and Y directions. The substrate 101 can include a semiconductor material, for example, it can include SiC. However, in some embodiments, the substrate 101 can also include a Group IV semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, GaAs, InAs, or InP.

[0014] The substrate 101 can be provided as a bulk wafer or an epitaxial layer. The substrate 101 can include an impurity of a first conductivity type, whereby it can have the first conductivity type. In some embodiments, the first conductivity type can be, for example, N-type, and the impurity of the first conductivity type can be, for example, an N-type impurity such as nitrogen (N) and / or phosphorus (P). In some embodiments, the first conductivity type can be, for example, P-type, and the impurity of the first conductivity type can be, for example, a P-type impurity such as aluminum (Al).

[0015] The drift layer 102 can be disposed on the substrate 101. The drift layer 102 can contain a semiconductor material, for example, it can contain SiC. The drift layer 102 may be an epitaxial layer grown on the substrate 101. The drift layer 102 can contain impurities of a first conductivity type, whereby it can have the above-mentioned first conductivity type. The concentration of the impurities of the first conductivity type in the drift layer 102 may be lower than the concentration of the impurities of the first conductivity type in the substrate 101. In an embodiment, the impurities of the first conductivity type in the substrate 101 and the drift layer 102 can contain the same or different elements from each other.

[0016] The well region 105 can be disposed at a predetermined depth from the upper surface of the drift layer 102 and can be spaced apart from each other by a gate trench GT in the horizontal direction, for example, the X direction. The well region 105 can contain a semiconductor material, for example, it can contain SiC. The well region 105 can be a region having a second conductivity type and can contain impurities of the second conductivity type. The above-mentioned second conductivity type may be, for example, a P type, and the above-mentioned impurities of the second conductivity type may be, for example, P type impurities such as aluminum (Al). In some embodiments, the well region 105 can contain a plurality of regions having different doping concentrations from each other.

[0017] The well contact region 109 can be disposed on the well region 105 between adjacent source regions 107. The well contact region 109 can be disposed between the well region 105 and the source electrode 150 so that a voltage from the source electrode 150 can be applied to the well region 105. The well contact region 109 can include a semiconductor material, for example, it can include SiC. The well contact region 109 can be a region having the second conductivity type and can include the second conductivity type impurities described above. The concentration of the second conductivity type impurities in the well contact region 109 may be higher than the concentration of the second conductivity type impurities in the well region 105. In an embodiment, the arrangement position, arrangement period, etc. of the well contact region 109 can be changed in various ways. In some embodiments, the well contact region 109 may not be disposed between some of the source regions 107.

[0018] The field relaxation region 104 can be disposed along a part of the outer surface of the gate trench GT and can cover a part of the outer surface. The field relaxation region 104 can extend along the gate trench GT at the bottom surface of the gate trench GT and an adjacent region thereof. The field relaxation region 104 can be located in the drift layer 102 under the gate electrode 130 and can be located between the gate insulating layer 120 and the drift layer 102.

[0019] The field relaxation region 104 can contain a semiconductor material, for example, it can contain SiC. The field relaxation region 104 may be a doped region formed by doping a part of the drift layer 102. The field relaxation region 104 can be a region having the same conductivity type as the well region 105, for example, the second conductivity type, and can contain second conductivity type impurities. The concentration of the second conductivity type impurities in the field relaxation region 104 may be higher than the concentration of the second conductivity type impurities in the well region 105. The field relaxation region 104 can relax the electric field formed in the drift layer 102 by the gate electrode 130, thereby preventing breakdown of the gate insulating layer 120.

[0020] The source region 107 can be disposed at a predetermined depth from the upper surface of the well region 105. The thickness of the source region 107 may be smaller than the thickness of the well region 105. The source region 107 can contain a semiconductor material, for example, it can contain SiC. The source region 107 can be a region having the first conductivity type, and can contain the first conductivity type impurities described above. The concentration of the first conductivity type impurities in the source region 107 may be higher than the concentration of the first conductivity type impurities in the drift layer 102, but is not limited thereto.

[0021] The gate trench GT can extend from the upper surface of the source region 107 through the source region 107 and the well region 105 into the drift layer 102. The gate trench GT can completely penetrate the well region 105, and the lower end of the gate trench GT can be located within the drift layer 102. However, the length that the gate trench GT extends into the drift layer 102 may be variously changed in embodiments. For example, in some embodiments, the lower end of the gate trench GT may be located on the upper surface of the drift layer 102.

[0022] The gate trench GT corresponds to the step portion BR of the gate electrode 130 and can have a step portion with a discontinuously changing width, whereby the width of the upper region can be wider than the width of the lower region. The step portion can be located within the well region 105. The gate trench GT can include a region where the width increases non-linearly upward from the step portion, and can include a region having a substantially constant width downward from the step portion. A gate insulating layer 120 and a gate electrode 130 can be disposed within the gate trench GT.

[0023] The gate electrodes 130 can be respectively disposed within the gate trench GT. The gate electrodes 130 can be disposed on the gate insulating layer 120 within the gate trench GT. The gate electrodes 130 can overlap the drift layer 102, the well region 105, and the source region 107 in the horizontal direction, for example, the X direction. The lower surface of the gate electrode 130 can be located within the drift layer 102. The lower surface of the gate electrode 130 can be located at a level lower than the lower surface of the well region 105, and the upper surface of the gate electrode 130 can be located at a level lower than the upper surface of the source region 107. However, in some embodiments, the level of the upper surface of the gate electrode 130 can also be located at the same level as or higher than the upper surface of the source region 107.

[0024] The gate electrode 130 can have a first width W1 at the lower surface and a second width W2 larger than the first width W1 at the upper surface. The gate electrode 130 can, for example, have a maximum width at the upper surface. The gate electrode 130 can have a shape corresponding to the shape of the gate trench GT and can have a step portion BR on the side surface. The step portion BR can face the well region 105 with the gate insulating layer 120 interposed therebetween. The step portion BR can be spaced apart from the source region 107 and can be located at a level lower than the lower surface of the source region 107. The gate electrode 130 can have a symmetric shape in the left-right direction and can have an asymmetric shape in the up-down direction.

[0025] The gate electrode 130 can have a dual gate structure including a first region G1 and a second region G2 on the first region G1. The first region G1 and the second region G2 can be arranged vertically with respect to the step portion BR. For example, the first region G1 can have a substantially constant first width W1, but is not limited thereto. For example, the second region G2 can have the first width W1 on the lower surface in contact with the first region G1, and can have a width larger than the first width W1 otherwise. The second region G2 can have a width larger than the maximum width of the first region G1. In the Z direction, the length of the first region G1 may be longer than the length of the second region G2, but the relative lengths of the first region G1 and the second region G2 may be variously changed in the embodiment. The gate electrode 130 can have a recessed portion DP recessed downward toward the substrate 101 on the upper surface. However, in the embodiment, the presence, shape, depth, etc. of the recessed portion DP may be variously changed.

[0026] The gate electrode 130 can include a conductive material, for example, a semiconductor material such as doped polycrystalline silicon, a metal nitride such as titanium nitride film (TiN), tantalum nitride film (TaN), or tungsten nitride film (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). Depending on the embodiment, the gate electrode 130 may be composed of two or more multilayers.

[0027] As shown in FIG. 1b, the well region 105 can include a region that is bent so as to face the gate electrode 130 and the gate insulating layer 120. The above region can correspond to the step portion BR. The side surface of the well region 105 facing the gate electrode 130 can include a first surface having a curved surface shape and a second surface that is bent and extends from the first surface. The above side surface can have a non-linear shape, for example, a non-linear shape, and the second surface can extend from the first surface in a discontinuous form. The first surface is a curved surface extending along the source region 107 and the well region 105, and the second surface can be a straight surface extending downward through the well region 105. In the present embodiment, the angle between the first surface and the second surface may be an obtuse angle.

[0028] During the operation of the power semiconductor device 100, in the well region 105, in the region adjacent to the gate electrode 130 and facing the gate electrode 130, a channel region CR of the transistor can be formed. The channel region CR may be a region including or adjacent to the above side surface of the well region 105. The channel region CR can face the gate electrode 130 with the gate insulating layer 120 interposed therebetween. The channel region CR is a part of the well region 105 and can extend downward from the source region 107 along the drift layer 102. The channel region CR can be bent along the shapes of the gate electrode 130 and the gate insulating layer 120 and extend downward. The channel region CR can extend in a non-linear shape, and the surface facing the gate electrode 130 can be composed of at least two surfaces. The channel region CR can overlap the gate electrode 130 in the horizontal direction. The length of the channel region CR may be, for example, in the range of about 0.2 μm to about 0.8 μm.

[0029] In this embodiment, since the gate electrode 130 has a step portion BR and is bent between the first region G1 and the second region G2, a part of the channel region CR can be affected by both the first region G1 and the second region G2. A part of the channel region CR can overlap with the first region G1 in the horizontal direction and overlap with the second region G2 in the vertical direction. For example, a part of the channel region CR can be affected by two surfaces of the gate electrode 130 at the same time. As a result, the threshold voltage becomes lower and the mobility is improved, and the generation of leakage current before turn-on can be reduced. Therefore, even when the power semiconductor device 100 has a decrease in mobility based on SiC, the electrical characteristics of the power semiconductor device 100 can be ensured.

[0030] The gate insulating layer 120 can be disposed in the gate trench GT respectively. The gate insulating layer 120 can be disposed on the side surface and the lower surface of the gate electrode 130. The gate insulating layer 120 can be disposed between the source region 107, the well region 105, and the drift layer 102 and the gate electrode 130.

[0031] The gate insulating layer 120 can have a non-uniform thickness. As shown in FIG. 1b, the gate insulating layer 120 can have a first thickness T1 on the bottom surface of the gate trench GT and a second thickness T2 smaller than the first thickness T1 on the side wall of the gate trench GT. In the lower region of the gate trench GT, the gate insulating layer 120 can have a lower surface bulging downward along the shape of the gate trench GT and an upper surface substantially flat relative to the gate electrode 130. Below the gate electrode 130, the gate insulating layer 120 can include a region where the thickness in the Z direction gradually decreases from the center of the gate trench GT toward both sides. Since the gate insulating layer 120 has a relatively large thickness on the bottom surface of the gate trench GT, the electric field formed in the drift layer 102 by the gate electrode 130 can be relaxed, and the breakdown of the gate insulating layer 120 can be prevented.

[0032] The gate insulating layer 120 can include an oxide, a nitride, or a high-k (high-dielectric constant) material. The high-k material can mean a dielectric material having a higher dielectric constant than a silicon oxide film (SiO2). The high-k material can be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), or praseodymium oxide (Pr2O3).

[0033] The dielectric layer 140 can cover the gate electrode 130 and can be arranged to expose a part of each of the source regions 107 and the well contact regions 109. The dielectric layer 140 can fill the gate trench GT and can cover the upper surface of the gate electrode 130 and the upper surface of the gate insulating layer 120. The dielectric layer 140 can include an insulating material and can include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0034] The source electrode 150 is disposed on the dielectric layer 140 and can be electrically connected to the source region 107 and the well contact region 109. The source electrode 150 can include a metal-semiconductor compound layer 152 and a conductive layer 154. The metal-semiconductor compound layer 152 can include a metal element and a semiconductor element, and can include, for example, at least one of TiSi, CoSi, MoSi, LaSi, NiSi, TaSi, or WSi. The conductive layer 154 can include a metal substance, for example, at least one of nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), and ruthenium (Ru).

[0035] The drain electrode 160 is disposed on the lower surface of the substrate 101 and can be electrically connected to the substrate 101. The drain electrode 160 can include a metal substance, for example, at least one of nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), and tungsten (W). In some embodiments, the drain electrode 160 can also include a metal-semiconductor compound layer and a conductive layer similar to the source electrode 150.

[0036] In the following description of the embodiments, descriptions that overlap with the above description with reference to FIGS. 1a and 1b are omitted.

[0037] FIGS. 2a to 2c are cross-sectional views showing a power semiconductor device according to an exemplary embodiment. FIGS. 2a to 2c respectively show regions corresponding to the cross-section of FIG. 1a.

[0038] Referring to FIG. 2a, in the power semiconductor device 100a, the gate trench GTa and the gate electrode 130a can have an angular shape instead of a curved shape. The step portion BR may be bent at a right angle or an angle close to a right angle. Thereby, in the gate electrode 130, the second region G2 can have a side surface that extends substantially linearly and can have a substantially constant width. The side surface of the well region 105 opposite to the gate electrode 130 can include a first surface from the upper part, a second surface connected to the first surface and extending horizontally, and a third surface extending vertically downward from the second surface. Thus, in the embodiment, the specific shapes of the gate trench GTa and the gate electrode 130a may be variously changed.

[0039] Referring to FIG. 2b, the power semiconductor device 100b may not include the field relaxation region 104 of FIG. 1a. Thereby, at the lower end of the gate trench GT, the gate insulating layer 120 can be in contact with the drift layer 102. However, even in this case, due to the non-uniform thickness of the gate insulating layer 120, the electric field formed in the drift layer 102 can be relaxed.

[0040] Referring to FIG. 2c, in the power semiconductor device 100c, the gate insulating layer 120c can have a substantially constant thickness. The gate insulating layer 120c can conformally extend along the inner surface of the gate trench GT. However, even in this case, the electric field formed in the drift layer 102 can be relaxed by the field relaxation region 104.

[0041] FIGS. 3a and 3b are a cross-sectional view and a partial enlarged view showing a power semiconductor device according to an exemplary embodiment. FIG. 3b shows an enlargement of the "A" region in FIG. 3a.

[0042] Referring to FIGS. 3a and 3b, in the power semiconductor device 100d, the shape of the gate trench GTd and the shape of the gate electrode 130d can be different from those of the embodiments of FIGS. 1a to 2c. The gate trench GTd can extend along the Z direction so as to penetrate the well region 105 from the upper surface of the well region 105. Thereby, the gate trench GTd can have no step portion.

[0043] The gate electrode 130d can extend into the gate trench GTd from above the upper surface of the well region 105. In the gate electrode 130d, the first region G1 can have a substantially constant first width W1d, and the second region G2 can have a second width W2d that is substantially constant and larger than the first width W1d, but is not limited thereto. In the Z direction, the length of the first region G1 may be longer than the length of the second region G2. The step portion BR of the gate electrode 130d can be located at a level higher than the upper surface of the source region 107 and the upper surface of the well region 105. In some embodiments, the gate electrode 130d can have a recessed portion that is recessed downward toward the substrate 101 on the upper surface.

[0044] The source region 107 can be disposed horizontally separated from the gate trench GTd by a first length L1. The first length L1 may be, for example, in the range of about 20% to about 40% of the length of the channel region CR. However, the relative size of the first length L1 may be variously changed in the embodiment.

[0045] As shown in FIG. 3b, the surface of the well region 105 facing the gate electrode 130d can include a first surface corresponding to the upper surface and a second surface extending vertically from the first surface. The second surface may be a surface that penetrates the well region 105 and extends downward. In the present embodiment, the angle between the first surface and the second surface may be a right angle or an angle close to a right angle.

[0046] During the operation of the power semiconductor device 100d, in the well region 105, a channel region CR of the transistor can be formed in the region opposite to the gate electrode 130d. The channel region CR may include the above surface of the well region 105 or a region adjacent to the above surface. The channel region CR can have an upside-down "L" shape. The channel region CR can overlap with the gate electrode 130d in the vertical and horizontal directions. At least a part of the channel region CR can be affected by both the first region G1 and the second region G2. At least a part of the channel region CR can overlap with the first region G1 in the horizontal direction and with the second region G2 in the vertical direction. For example, a part of the channel region CR can be simultaneously affected and controlled by two surfaces of the gate electrode 130. Thereby, the threshold voltage is lowered, the mobility is improved, and the generation of leakage current before turn-on can be reduced. Therefore, even when the mobility of the power semiconductor device 100d based on SiC decreases, the electrical characteristics of the power semiconductor device 100d can be ensured.

[0047] Figures 4a and 4b are cross-sectional views showing a power semiconductor device according to an exemplary embodiment. Figures 4a and 4b respectively show regions corresponding to the cross-section of Figure 3a.

[0048] Referring to Figure 4a, the power semiconductor device 100e may not include the field relaxation region 104 of Figure 3a. Thereby, at the lower end of the gate trench GTd, the gate insulating layer 120 can contact the drift layer 102. However, even in this case, due to the non-uniform thickness of the gate insulating layer 120, the electric field formed in the drift layer 102 can be relaxed.

[0049] Referring to Figure 4b, in the power semiconductor device 100f, the gate insulating layer 120f can have a substantially constant thickness. The gate insulating layer 120f can conformally extend along the inner surface of the gate trench GTd. However, even in this case, the electric field formed in the drift layer 102 can be relaxed by the field relaxation region 104.

[0050] FIG. 5 is a cross-sectional view showing a power semiconductor device according to an exemplary embodiment.

[0051] Referring to FIG. 5, in the power semiconductor device 100g, the shape of the gate trench GTg and the shape of the gate electrode 130g can be different from those of the embodiments of FIGS. 1a to 2c. The gate trench GTg may have a width in the upper region that is narrower than the width in the lower region. The gate trench GT can have a substantially constant width upward from the stepped portion on the side wall, and can include a region where the width increases non-linearly and a region where the width decreases downward from the stepped portion.

[0052] In the gate electrode 130g, for example, the first region G1 can have a circular or circular-like cross-section and can have a first width W1g that is the maximum width on the lower surface. The second region G2 can have a substantially constant second width W2g. For example, the first region G1 can have a width that is the same as or larger than the maximum width of the second region G2. In the Z direction, the length of the first region G1 may be shorter than the length of the second region G2, but the relative lengths of the first region G1 and the second region G2 may be variously changed in the embodiment. In some embodiments, the gate electrode 130g can have a recessed portion that is recessed downward toward the substrate 101 on the upper surface.

[0053] FIGS. 6a to 6h are diagrams shown in the order of steps to explain a method of manufacturing a power semiconductor device according to an exemplary embodiment. In FIGS. 6a to 6h, an embodiment of a method of manufacturing the power semiconductor device of FIG. 1a will be described.

[0054] Referring to FIG. 6a, a drift layer 102 can be formed on a substrate 101, and a well region 105, a source region 107, and a well contact region 109 can be formed.

[0055] The substrate 101 can be provided, for example, as a SiC wafer. The drift layer 102 can be formed by epitaxial growth from the substrate 101. The drift layer 102 can be formed to contain impurities of a first conductivity type.

[0056] The well region 105, the source region 107, and the well contact region 109 can be sequentially formed in the drift layer 102 by an ion implantation process. Impurities of a second conductivity type can be implanted into the well region 105 and the well contact region 109, and impurities of the first conductivity type can be implanted into the source region 107. After the above ion implantation process, an annealing process can be performed at a high temperature, for example, a temperature of about 1600°C to about 1800°C.

[0057] Referring to FIG. 6b, a preliminary gate trench GT' can be formed by partially removing the source region 107 and the well region 105.

[0058] Using the first mask layer ML1, a preliminary gate trench GT' can be formed by partially removing the source region 107 and the well region 105. The first mask layer ML1 can be, for example, a hard mask layer. The preliminary gate trenches GT' can be formed to be spaced apart from each other along the horizontal direction, for example, the X direction. The preliminary gate trench GT' can be formed to penetrate the source region 107, and the well region 105 can be exposed through the bottom surface.

[0059] Referring to FIG. 6c, a gate trench GT can be formed by partially removing the well region 105 and the drift layer 102.

[0060] By using the second mask layer ML2 to expose a part of the preliminary gate trench GT' and partially removing the well region 105 and the drift layer 102, the gate trench GT can be formed. The second mask layer ML2 may be, for example, a hard mask layer. The gate trench GT can be formed to completely penetrate the well region 105, and the drift layer 102 can be exposed through the bottom surface.

[0061] Referring to FIG. 6d, a field relaxation region 104 can be formed along a part of the outer surface of the gate trench GT.

[0062] The field relaxation region 104 can be formed with a predetermined thickness from the surface of the drift layer 102 exposed from the second mask layer ML2. The field relaxation region 104 can be formed by implanting impurities of the second conductivity type through an ion implantation process. In an exemplary embodiment, the range and thickness of the field relaxation region 104 may be variously changed. However, in some embodiments, the formation process of the field relaxation region 104 may be omitted.

[0063] Referring to FIG. 6e, an annealing process can be performed to form a preliminary gate insulating layer 120P on the inner surface of the gate trench GT.

[0064] First, the second mask layer ML2 can be removed and an annealing process can be performed. The annealing process can include, for example, a hydrogen (H2) annealing process performed in a hydrogen (H2) atmosphere and a high-temperature annealing process. By the hydrogen (H2) annealing process, the gate trench GT can be smoothed, the angle of the inner surface can be relaxed, and it can have a curved shape.

[0065] The preliminary gate insulating layer 120P can be formed, for example, by an oxidation process, such as a thermal oxidation process. In some embodiments, the preliminary gate insulating layer 120P can be formed by a deposition process.

[0066] Referring to FIG. 6f, an insulating material can be further formed on the bottom surface of the gate trench GT to form the gate insulating layer 120.

[0067] The insulating material can be additionally formed only on the preliminary gate insulating layer 120P on the bottom surface of the gate trench GT. The insulating material can be formed, for example, by a Spin-On Glass (SOG) process or a High Temperature Oxide (HTO) process. However, in some embodiments, this step may be omitted.

[0068] Referring to FIG. 6g, the gate electrode 130 can be formed on the gate insulating layer 120.

[0069] The gate electrode 130 may be formed, for example, by depositing doped polycrystalline silicon and performing an etch-back process. The gate electrode 130 can be formed so as to be located only within the gate trench GT. In some embodiments, in this step, a part of the gate insulating layer 120 may also be removed so as to be located only within the gate trench GT. The gate electrode 130 can be formed to have a step portion BR according to the shape of the gate trench GT and can have a double gate structure. The gate electrode 130 can have a depression DP on the upper surface according to the aspect ratio of the gate trench GT, the deposition conditions of the gate electrode 130, etc. However, in some embodiments, the upper surface of the gate electrode 130 may be flat.

[0070] Referring to FIG. 6h, a dielectric layer 140 and a metal-semiconductor compound layer 152 covering the gate electrode 130 can be formed.

[0071] After the dielectric layer 140 is deposited over the entire upper surface of the structure during manufacturing, a part of the dielectric layer 140 can be removed by an etching process so as to expose a respective part of each of the source regions 107 and the well contact regions 109. For example, the dielectric layer 140 may be formed by being patterned together with the gate insulating layer 120. However, in some embodiments, the gate insulating layer 120 can also be patterned in a separate process. The dielectric layer 140 can be formed to cover the upper surface of the gate electrode 130 and the upper surface of the gate insulating layer 120 and expose a part of the upper surface of the source region 107.

[0072] The metal-semiconductor compound layer 152 can be formed over the upper surfaces of the source regions 107 and the well contact regions 109. The metal-semiconductor compound layer 152 may be formed, for example, by a silicidation process.

[0073] Next, referring to FIG. 1a together, a conductive layer 154 can be formed over the metal-semiconductor compound layer 152, and a drain electrode 160 can be formed on the lower surface of the substrate 101.

[0074] The conductive layer 154 can be formed to cover the metal-semiconductor compound layer 152 and the dielectric layer 140, whereby a source electrode 150 can be formed.

[0075] Next, a metal material can be deposited on the lower surface of the substrate 101 to form the drain electrode 160. In some embodiments, the drain electrode 160 may be formed in other process steps. Thereby, the power semiconductor device 100 of FIG. 1a can be manufactured.

[0076] FIGS. 7a to 7g are diagrams shown in the order of processes to explain a method of manufacturing a power semiconductor device according to an exemplary embodiment. In FIGS. 7a to 7g, an embodiment of a manufacturing method for manufacturing the power semiconductor device of FIG. 3a will be described.

[0077] Referring to FIG. 7a, a drift layer 102 can be formed on a substrate 101, and a well region 105, a source region 107, and a well contact region 109 can be formed. This step can be performed in the same manner as described above with reference to FIG. 6a. However, in this step, the source regions 107 may be formed to be spaced apart from each other in the horizontal direction.

[0078] Referring to FIG. 7b, a part of the well region 105 and the drift layer 102 can be removed to form a gate trench GTd.

[0079] Using a mask layer ML, a part of the well region 105 can be exposed between the source regions 107, and by removing a part of the well region 105 and the drift layer 102, a gate trench GTd can be formed. The mask layer ML may be, for example, a hard mask layer. The gate trenches GTd may be formed to be spaced apart from each other along the horizontal direction, for example, the X direction. The gate trench GTd can be formed to completely penetrate the well region 105, and the drift layer 102 can be exposed through the bottom surface.

[0080] Referring to FIG. 7c, a field relaxation region 104 can be formed along a part of the outer surface of the gate trench GTd.

[0081] The field relaxation region 104 can be formed with a predetermined thickness from the surface of the drift layer 102 exposed from the mask layer ML. The field relaxation region 104 can be formed by implanting second-conductivity-type impurities through an ion implantation process. In an exemplary embodiment, the level of the upper end of the field relaxation region 104 may be variously changed.

[0082] Referring to FIG. 7d, an annealing process can be performed to form a preliminary gate insulating layer 120P on the inner surface of the gate trench GTd.

[0083] First, the mask layer ML can be removed, and an annealing process can be performed. The annealing process can be carried out at a high temperature. The preliminary gate insulating layer 120P can be formed in the same manner as described above with reference to FIG. 6e.

[0084] Referring to FIG. 7e, an insulating material can be further formed on the bottom surface of the gate trench GTd to form the gate insulating layer 120. The gate insulating layer 120 can be formed in the same manner as described above with reference to FIG. 6f.

[0085] Referring to FIG. 7f, the gate electrode 130d can be formed on the gate insulating layer 120.

[0086] The gate electrode 130d can be formed, for example, by depositing doped polycrystalline silicon and performing a patterning process together with the gate insulating layer 120. The gate electrode 130d may be formed to have a step portion BR according to the shape of the gate trench GTd. The gate electrode 130d can have, for example, a "T" shape.

[0087] Referring to FIG. 7g, the dielectric layer 140 and the metal-semiconductor compound layer 152 covering the gate electrode 130d can be formed. This step can be performed in the same manner as described above with reference to FIG. 6h.

[0088] Next, referring to FIG. 3a, the conductive layer 154 can be formed, and the drain electrode 160 can be formed on the lower surface of the substrate 101. Thereby, the power semiconductor device 100d in FIG. 3a can be manufactured.

[0089] FIGS. 8a to 8i are diagrams shown in the order of steps to explain a method for manufacturing a power semiconductor device according to an exemplary embodiment. In FIGS. 8a to 8i, an embodiment of a manufacturing method for manufacturing the power semiconductor device in FIG. 5 will be described.

[0090] Referring to FIG. 8a, after forming a drift layer 102 on a substrate 101 and forming a well region 105, a source region 107, and a well contact region 109, a part of the source region 107 and the well region 105 can be removed to form a preliminary gate trench GT'. This step can be performed in the same manner as the steps described above with reference to FIGS. 6a and 6b.

[0091] Referring to FIG. 8b, a preliminary spacer layer SL' can be formed on the inner surface of the preliminary gate trench GT' and the upper surface of the source region 107. The preliminary spacer layer SL' can include, for example, silicon nitride. The preliminary spacer layer SL' can be formed by conformally depositing it over the entire upper surface of the structure being manufactured.

[0092] Referring to FIG. 8c, a part of the preliminary spacer layer SL' can be removed to form a spacer SL. The horizontally extending region of the preliminary spacer layer SL' is selectively removed, and the spacer SL can remain only on the inner sidewall of the preliminary gate trench GT'.

[0093] Referring to FIG. 8d, a gate trench GTg can be formed by removing a part of the well region 105 and the drift layer 102 exposed through the preliminary gate trench GT' and the spacer SL.

[0094] The well region 105 and the drift layer 102 may be removed, for example, by an isotropic etching process. As a result, the region etched in this step can have a circular, elliptical, or similar shape in cross-section. Each of the gate trenches GTg can have a bulb shape.

[0095] Referring to FIG. 8e, a field relaxation region 104 can be formed along a part of the outer surface of the gate trench GTg. The field relaxation region 104 can be formed with a predetermined thickness from the surface of the drift layer 102 in a region adjacent to the bottom surface of the gate trench GTg exposed through the second mask layer ML2.

[0096] Referring to FIG. 8f, an annealing process can be performed to form a preliminary gate insulating layer 120P on the inner surface of the gate trench GTg. First, the second mask layer ML2 can be removed and the annealing process can be performed. The annealing process can be performed at a high temperature. The preliminary gate insulating layer 120P can be formed in the same manner as described above with reference to FIG. 6e.

[0097] Referring to FIG. 8g, an insulating material can be further formed on the bottom surface of the gate trench GTg to form the gate insulating layer 120. This step can be formed in the same manner as described above with reference to FIG. 6f.

[0098] Referring to FIG. 8h, a gate electrode 130g can be formed on the gate insulating layer 120. The gate electrode 130g can be formed, for example, by depositing doped polycrystalline silicon and performing an etch-back process. The gate electrode 130g may be formed to have a step portion BR according to the shape of the gate trench GTg. In some embodiments, in this step, a part of the gate insulating layer 120 may also be removed so that it is only located within the gate trench GTg.

[0099] Referring to FIG. 8i, a dielectric layer 140 and a metal-semiconductor compound layer 152 covering the gate electrode 130g can be formed. This step can be performed in the same manner as described above with reference to FIG. 6h.

[0100] Next, referring to FIG. 5 together, a conductive layer 154 can be formed and a drain electrode 160 can be formed on the lower surface of the substrate 101. Thereby, the power semiconductor device 100g in FIG. 5 can be manufactured.

[0101] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the appended claims. Therefore, various forms of substitution, modification, and change are possible by those having ordinary knowledge in the technical field within the scope not departing from the technical idea of the present invention described in the claims, and combinations of embodiments are also possible, and it can be said that these also belong to the scope of the present invention.

Description of Reference Numerals

[0102] 101: Substrate 102: Drift layer 104: Field relaxation region 105: Well region 107: Source region 109: Well contact region 120: Gate insulating layer 130: Gate electrode 140: Dielectric layer 150: Source electrode 152: Metal-semiconductor compound layer 154: Conductive layer 160: Drain electrode

Claims

1. a substrate of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate electrode disposed in a gate trench penetrating the source region and the well region; a gate insulating layer disposed between the gate electrode and the well region; a dielectric layer on the gate electrode; a drain electrode on a lower surface of the substrate; the gate electrode has a first width at a lower surface, a second width at an upper surface which is greater than the first width, and a step portion at a side surface where the width is changed; The step portion is located at a level lower than a lower surface of the source region.

2. The power semiconductor device according to claim 1 , wherein a surface of the well region facing the gate electrode includes a first surface and a second surface bent and extending from the first surface.

3. 3. The power semiconductor device according to claim 2, wherein the first surface is a curved surface extending along the source region and the well region, and the second surface is a surface extending downward through the well region.

4. The power semiconductor device according to claim 2 , wherein an angle between the first surface and the second surface is a right angle or an obtuse angle.

5. 2. The power semiconductor device of claim 1, wherein the gate insulating layer has a first thickness on a bottom surface of the gate trench and a second thickness on a sidewall of the gate trench that is less than the first thickness.

6. The power semiconductor device of claim 1 , wherein the substrate, the drift layer, and the well region comprise SiC.

7. The power semiconductor device of claim 1 , further comprising a field relief region of the second conductivity type located between the gate insulating layer and the drift layer.

8. a substrate of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate electrode disposed in a gate trench penetrating the source region and the well region; a gate insulating layer disposed between the gate electrode and the well region; a drain electrode on a lower surface of the substrate; the gate electrode includes a first region and a second region on the first region, the first region having a maximum width of a first width, and the second region having a second width greater than the first width; the well region includes a channel region adjacent to the gate electrode; The channel region includes a region that overlaps the first region in a horizontal direction and overlaps the second region in a vertical direction.

9. The power semiconductor device according to claim 8 , wherein the channel region extends in a folded manner along the gate electrode.

10. a substrate of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a source region of the first conductivity type on the well region; a gate electrode disposed in a gate trench penetrating the source region and the well region; a gate insulating layer covering an inner surface of the gate trench; a field relief region of the second conductivity type covering a portion of an outer surface of the gate insulating layer; a drain electrode on a lower surface of the substrate; the gate electrode has a maximum width at an upper surface and has an asymmetric shape vertically; The well region includes a region that is bent to face the gate electrode.

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