Printed circuit board

Abstract

To provide a printed circuit board on which a pad and a metal post having a fine pitch may be mounted as the printed circuit board for mounting an electronic component, a semiconductor chip, or the like.SOLUTION: A present invention relates to a printed circuit board including: an insulating portion; a first pad disposed on the bottom of the insulating portion; a first solder resist layer disposed on the bottom of the insulating portion to cover at least a portion of the first pad and having a first opening on at least a portion of the first pad; a first barrier layer disposed on a portion of the first pad corresponding to the first opening; a first surface treatment layer disposed on the first barrier layer; a second pad disposed on the top of the insulating portion; a second solder resist layer disposed on the top of the insulating portion to cover at least a portion of the second pad and having a second opening on at least a portion of the second pad; a metal post disposed on the second pad and having at least a portion disposed in the second opening; and a second barrier layer disposed between the second pad and the metal post.SELECTED DRAWING: Figure 3a

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] Recently, due to the development of technologies such as Artificial Intelligence (AI), multi-chip packages including memory chips such as High Bandwidth Memory (HBM) for geometrically increasing data processing, and processor chips such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC), and Field Programmable Gate Array (FPGA) have been used. In particular, the number of cores of CPUs and GPUs in server products has increased rapidly, and it is necessary to cope with a finer chip metal post pitch. In particular, research continues on methods for forming pads on the substrate more finely for connecting the chip and the substrate, methods for forming a configuration for smoothly connecting the pads and the chip, and methods for increasing the yield while improving the reliability of the connection between the chip and the substrate.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of several objects of the present invention is to provide a printed circuit board capable of realizing pads and metal posts having a fine pitch in a printed circuit board for mounting electronic components, semiconductor chips, etc.

[0004] Another one of several objects of the present invention is to provide a printed circuit board in which no defect due to galvanic corrosion occurs in the pads and the surface treatment layer on the lower surface when forming the metal posts on the upper surface.

[0005] Another one of several objects of the present invention is to provide a printed circuit board capable of improving reliability.

Means for Solving the Problems

[0006] One of several solutions proposed through the present invention is an insulating part, a first pad disposed below the insulating part, a first solder resist layer disposed below the insulating part and covering at least a part of the first pad and having a first opening on at least a part of the first pad, a first barrier layer disposed on a part of the first pad corresponding to the first opening, a first surface treatment layer disposed on the first barrier layer, a second pad disposed above the insulating part, a second solder resist layer disposed above the insulating part and covering at least a part of the second pad and having a second opening on at least a part of the second pad, a metal post disposed on the second pad with at least a part thereof disposed within the second opening, and a second barrier layer disposed between the second pad and the metal post, to provide a printed circuit board.

[0007] Another one of several solutions proposed through the present invention is an insulating part, a pad disposed above the insulating part, a solder resist layer disposed above the insulating part and covering at least a part of the pad and having an opening on at least a part of the pad, a barrier layer disposed in contact with the pad and extending to an inner wall of the opening and a part of an upper surface of the solder resist, a seed layer disposed on the barrier layer and extending along the barrier layer, and a metal post disposed on the seed layer, the pad contains a first metal, and the barrier layer contains a material different from the first metal of the pad, to provide a printed circuit board.

Advantages of the Invention

[0008] As one of various advantages of the present invention, it is possible to provide a printed circuit board capable of realizing pads and metal posts having a fine pitch in a printed circuit board for mounting electronic components, semiconductor chips, etc.

[0009] Among various effects of the present invention, as another effect, it is possible to provide a printed circuit board in which no defect due to galvanic corrosion occurs in the pad on the lower surface and the surface treatment layer when forming the metal post on the upper surface.

[0010] Among various effects of the present invention, as another effect, it is possible to provide a printed circuit board capable of improving reliability.

Brief Description of the Drawings

[0011]

Figure 1

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Figure 3a

Figure 3b

Figure 3c

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Figure 15

Embodiments for Carrying Out the Invention

[0012] Hereinafter, the present invention will be described with reference to the accompanying drawings. The shape, size, etc. of the elements in the drawings can be exaggerated or reduced for a clearer explanation.

[0013] Electronic device FIG. 1 is a block diagram schematically showing an example of an electronic device system.

[0014] Referring to the drawings, the electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040, etc. are physically and / or electrically connected to the main board 1010. These are also combined with other electronic components described later to form various signal lines 1090.

[0015] Examples of chip-related components 1020 include, but are not limited to, memory chips such as volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), and flash memories; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, other different forms of chip-related electronic components may also be included. Also, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in a package form including the above-mentioned chips and electronic components.

[0016] Examples of network-related components 1030 include, but are not limited to, Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth (registered trademark), 3G, 4G, 5G, and any other arbitrary wireless and wired protocols designated as such and later. Needless to say, the network-related components 1030 may be combined with the chip-related components 1020 and with each other.

[0017] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condensers), etc. However, it is not limited to these, and in addition to these, passive elements in the form of chip components used for other different applications may also be included. Needless to say, other components 1040 may also be combined with chip-related components 1020 and / or network-related components 1030 with each other.

[0018] Depending on the type of the electronic device 1000, the electronic device 1000 can include other electronic components that are physically and / or electrically connected or not connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited to these, and it may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a large-capacity storage device (e.g., a hard disk drive), a CD (compact disk), a DVD (digital versatile disk), etc. Needless to say, in addition to these, other electronic components used for various applications according to the type of the electronic device 1000 may also be included.

[0019] The electronic device 1000 may be, for example, a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, it is not limited to these, and needless to say, it may be any other electronic device that processes data other than these.

[0020] FIG. 2 is a perspective view schematically showing an example of an electronic device.

[0021] Referring to the drawings, the electronic device may be, for example, a smart phone 1100. Inside the smart phone 1100, a motherboard 1110 is housed, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Also, other components that are or are not physically and / or electrically connected to the motherboard 1110, such as a camera module 1130 and / or a speaker 1140, are housed inside. Some of the components 1120 may be the chip-related components described above, for example, a component package 1121, but it is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with active components and / or passive components built therein. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and needless to say, it may be other electronic devices as described above.

[0022] Printed Circuit Board FIG. 3a is a cross-sectional view schematically showing a printed circuit board according to an example, and FIG. 3b is a cross-sectional view showing enlarged parts of the upper and lower sides of the printed circuit board according to an example. Specifically, FIG. 3b shows enlarged views of regions A and B of the printed circuit board according to an example, respectively, and with reference to FIG. 3b, the specific arrangement relationship between regions A and B in FIG. 3a can be understood.

[0023] Referring to FIG. 3a, a printed circuit board according to an example may include an insulating portion 110, a first pad 141 disposed below the insulating portion 110, a first solder resist layer 171 disposed below the insulating portion 110 and covering at least a part of the first pad 141 and having a first opening 171O on at least a part of the first pad 141, a barrier layer 180 disposed on a part of the first pad 141 corresponding to the first opening 171O, a first surface treatment layer 161 disposed on the barrier layer 180, a second pad 142 disposed above the insulating portion 110, a second solder resist layer 172 disposed above the insulating portion 110 and covering at least a part of the second pad 142 and having a second opening 172O on at least a part of the second pad 142, and a metal post 150 disposed on the second pad 142 and at least a part of which is disposed within the second opening 172O.

[0024] Also, the barrier layer 180 of the printed circuit board according to an example may be disposed to be in contact with the second pad 142 and may extend to an inner wall of the second opening 172O and a part of an upper surface of the second solder resist layer 172, may include a seed layer 190 disposed on the barrier layer 180 and extending along the barrier layer 180, the metal post 150 may be disposed on the seed layer 190, and the barrier layer 180 may include a metal different from that of the seed layer 190.

[0025] The printed circuit board according to one example includes a barrier layer 180 between the first pad 141 and the first surface treatment layer 161. Therefore, the first pad 141 does not directly contact the first surface treatment layer 161, and the first pad 141 can be covered by the barrier layer 180. Since the first pad 141 is covered by the barrier layer 180, galvanic corrosion due to etching does not occur when forming the metal post 150 on the second pad 142.

[0026] Also, the printed circuit board according to one example includes a barrier layer 180 between the second pad 142 and the metal post 150. Therefore, the second pad 142 can be covered by the barrier layer 180. Before forming the metal post 150 on the second pad 142, since the second pad 142 is covered by the barrier layer 180, galvanic corrosion due to etching does not occur when forming the metal post 150 on the second pad 142.

[0027] Galvanic Corrosion refers to a phenomenon that may occur when two metals with different electrochemical properties, such as standard reduction potential, are electrically connected and exposed to a corrosive solution. Among the two metals, corrosion occurs in the more active metal or the metal with a lower standard reduction potential value. The third metal layer 167 disposed on the outermost side of the first surface treatment layer 161 can preferably contain gold (Au) on the outermost side. The second pad 142 and the metal post 150 can preferably contain copper (Cu). In order to form the metal post 150 on the second pad 142, in the step of pretreating the second pad 142 through the second opening 172O of the second solder resist layer 172 or the step of removing the seed layer to form the metal post 150, the second pad 142 and the first surface treatment layer 161 may be simultaneously exposed on an etching solution for soft etching or the like. As a result, the second pad 142 containing copper (Cu) with a relatively low standard reduction potential acts as the negative electrode, and the third metal layer 167 of the first surface treatment layer 161 containing gold (Au) with a relatively high standard reduction potential acts as the positive electrode, causing galvanic corrosion to occur between the second pad 142 and the first surface treatment layer 161. Therefore, there is a possibility that galvanic corrosion occurs in the second pad 142, resulting in defects in the second pad 142, and there is also a risk of defects occurring in the metal post 150 disposed on the second pad 142. On the other hand, the metal substances of the third metal layer 167 of the first surface treatment layer 161 and the second pad 142 are not necessarily limited to this, and all cases where the standard reduction potentials are different from each other and there is a possibility of galvanic corrosion occurring between the third metal layer 167 disposed on the outermost side of the first surface treatment layer 161 and the second pad 142 can be included.

[0028] As described above, in the printed circuit board according to an example, after the barrier layer 180 is formed on the first pad 141 and the second pad 142, the seed layer 190 is formed. Therefore, the first pad 141 and the second pad 142 can be covered by the barrier layer 180 respectively. Accordingly, at the stage of forming the seed layer 190, it is possible to prevent the second pad 142 and the first surface treatment layer 161 from being simultaneously exposed to the etching solution. Therefore, even at the stage of realizing the metal post 150 on the second pad 142, the occurrence of galvanic corrosion can be prevented. More specifically, since the barrier layer 180 is conformally disposed along at least a part of the inner wall of the first opening 171O formed in the lower surface of the first pad 141 and the first solder resist layer 171, the galvanic corrosion of the second pad 142 can be prevented. On the other hand, since a part of the barrier layer 180 disposed on the lower side can be removed at the last stage of the subsequent manufacturing method, the barrier layer 180 can be disposed on the lower surface of the first pad 141 and at least a part of the inner wall of the first opening 171O.

[0029] Also, in the printed circuit board according to an example, since a barrier layer can be disposed on the second pad 142 as well, even at the stage of removing a part of the seed layer 190 during the stage of forming the metal post 150, the occurrence of galvanic corrosion on the second pad 142 can be prevented.

[0030] The barrier layer 180 may be a substance having electrical conductivity and may have a material different from the metal substances included in the first pad 141 and the second pad 142.

[0031] In the printed circuit board according to an example, since the galvanic corrosion of the second pad 142 can be prevented, even if the second pad 142 and the metal post 150 are designed to have a fine pitch, no defect will occur. Therefore, it may be advantageous for connecting a configuration having a fine pitch such as a semiconductor chip to the upper side of the printed circuit board.

[0032] The insulating portion 110 may be composed of one or more insulating layers, and may include a first insulating layer 111 that is a core layer and a second insulating layer 112 that is a build-up insulating layer, but is not necessarily limited thereto, and the first insulating layer 111 that is a core layer may be omitted. The insulating portion 110 can contain an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, and / or Glass Fabric) together with such a resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the insulating portion 110 may be an insulating material of ABF (Ajinomoto Build-up Film), but is not limited thereto, and may include PPG (Prepreg), RCC (Resin Coated Copper), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc. However, it is not limited thereto, and other materials with excellent rigidity such as glass materials may be used as necessary. As a non-limiting example, the first insulating layer 111 that is a core layer can include a glass substrate, etc., and the materials of the first insulating layer 111 and the second insulating layer 112 constituting the insulating portion 110 may not be limited. The first insulating layer 111 and the second insulating layer 112 can contain the same insulating material, but can also contain different insulating materials from each other.

[0033] The first wiring layer 121 and the second wiring layer 122 can each be composed of one or more wiring layers, and can include the first wiring layer 121 disposed on the first insulating layer 111 and the second wiring layer 122 as a build-up wiring layer disposed on or within the second insulating layer 112.

[0034] Each of the first wiring layer 121 and the second wiring layer 122 can contain a metallic substance. As the metallic substance, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof can be used. The metallic substance can preferably contain copper (Cu), but is not limited thereto, and the first wiring layer 121 and the second wiring layer 122 can also contain different metallic substances from each other. Each wiring layer can perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc., and is not limited thereto, and can also function as a pad for mounting electronic components and chips, etc., or can also function as a stopper for forming a cavity. These patterns can each have various forms such as a line, a plane, a pad, etc. Each wiring layer can have a different pitch from each other according to its function. For example, when at least a part of the second wiring layer 122 requires a high-density fine pitch for connection with a connection structure or a semiconductor chip, etc., the interval between the second wiring layers 122 and the interval between the patterns can be narrowed, and when performing other signal connections, etc., the interval between the patterns of the wiring layer can be widened.

[0035] The first wiring layer 121 and the second wiring layer 122 may each be formed by any one of the SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive processes, but are not limited thereto. The first wiring layer 121 and the second wiring layer 122 can each contain an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electro copper) as a plating layer, but are not limited thereto. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. If necessary, a copper foil can be further included.

[0036] A printed circuit board according to an example can include a first via layer 131 that connects between the first wiring layers 121 to each other and a second via layer 132 that connects between the second wiring layers 122 to each other. The second via layer 132 may be composed of one or more via layers. The first via layer 131 can be arranged as a through via that penetrates the first insulating layer 111, and the second via layer 132 can be arranged as a build-up via layer that penetrates at least a part of the second insulating layer 112. At this time, the second via layer 132 may connect the second wiring layer 122 and the first pad 141 to each other, or may connect the second wiring layer 122 and the second pad 142 to each other.

[0037] The first via layer 131 can include a metal layer formed on the wall surface of a through hole that penetrates the first insulating layer 111 and a plug that fills the metal layer. The metal layer can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, etc., and preferably can include copper (Cu), but is not limited thereto. The plug may contain an insulating material ink. The metal layer can include an electroless plating layer (or electroless copper) and an electrolytic plating layer (or electroplated copper), but is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The first via layer 131 can perform various functions according to the design. For example, it can include a ground via, a power via, a signal via, etc.

[0038] The second via layer 132 can include microvias. The microvias may be filled vias that fill via holes, or may be conformal vias arranged along the wall surfaces of the via holes. The microvias can be arranged in a stacked type and / or a staggered type. Each of the second via layers 132 can include a metal, and the metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, etc., and preferably can include copper (Cu), but is not limited thereto. Each of the second via layers 132 can include an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper), but is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The second via layer 132 can perform various functions according to the design of the layer. For example, it can include ground vias, power vias, signal vias, etc.

[0039] A printed circuit board according to an example includes a first pad 141 below the insulating portion 110. The first pad 141 can be arranged on or within the insulating layer arranged at the lowermost side of the second insulating layer 112. In FIG. 3a, the first pad 141 is shown as being arranged on the second insulating layer 112 and protruding from the lower side of the second insulating layer 112, but is not necessarily limited thereto, and may have a so-called coreless structure in which the first pad 141 is embedded in the lower side of the second insulating layer 112. The first pad 141 can be connected to at least a part of the second wiring layer 122 through one of the via layers of the second via layer 132.

[0040] The first pad 141 can include a metallic substance, and examples of the metallic substance can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can include copper (Cu), but is not limited thereto. The first pad 141 is disposed on the lowermost side of the printed circuit board and can function as a connection pad so that the lower surface of the printed circuit board can be connected to other components such as a main board. However, it is not limited thereto, and the first pad 141 can also function as a means for connecting to a component having a fine pitch such as a semiconductor chip, and of course, the pitch can be designed in various ways according to the function. The first pad 141 can perform various functions according to the respective design. For example, it can include a ground pad, a power pad, a signal pad, etc. Here, the signal pad can include pads for electrical connection of various signals excluding ground, power, etc., for example, data signals.

[0041] A printed circuit board according to an example can include a second pad 142 on the upper side of the insulating portion 110. The second pad 142 can be disposed on or within the insulating layer disposed on the uppermost side of the second insulating layer 112. In FIG. 3a, the first pad 141 is shown as being disposed on the second insulating layer 112 and protruding above the second insulating layer 112, but it is not necessarily limited thereto, and of course, the second pad 142 may also have a coreless structure embedded within the second insulating layer 112. At this time, since the second pad 142 can have a pad structure with a finer pitch than the first pad 141, as a non-limiting example, the structure in which the second pad 142 is embedded within the second insulating layer 112 may be more preferable than the structure in which the first pad 141 is embedded within the second insulating layer 112. The second pad 142 can be connected to at least a part of the second wiring layer 122 through one via layer 130 of the second via layer 132.

[0042] The second pad 142 can contain a metallic substance, and the metallic substance can include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain copper (Cu), but is not limited thereto. The second pad 142 is disposed on the uppermost side of the printed circuit board and can be an area for mounting electronic components and chips, etc., or can be connected to a circuit pattern for signal connection with other pads. The second pad 142 can perform various functions according to the design. For example, it can include a ground pad, a power pad, a signal pad, etc. Here, the signal pad can include pads for electrical connection of various signals excluding ground, power, etc., such as data signals. When the second pad 142 requires a high-density fine pitch for mounting a semiconductor chip or the like, the interval between the second pads 142 can be narrowed, and for mounting an electronic component, the interval between the second pads 142 can be widened. Also, the second pad 142 in the area where a semiconductor chip or the like is mounted via another configuration such as the connection structure 200 can be formed with a narrower interval.

[0043] The first pad 141 and the second pad 142 can each be formed by any one of the SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive processes, but are not limited thereto, and can be formed using methods available to those with ordinary knowledge in the technical field.

[0044] A printed circuit board according to an example can include a first solder resist layer 171 and a second solder resist layer 172 disposed on the lower side and the upper side of the insulating portion 100, respectively. The first solder resist layer 171 is disposed on the insulating layer disposed at the lowermost side of the second insulating layer 112, and the second solder resist layer 172 can be disposed on the insulating layer disposed at the uppermost side of the second insulating layer 112.

[0045] The first solder resist layer 171 and the second solder resist layer 172 are respectively disposed on the outermost side of the printed circuit board and can protect the printed circuit board from the outside. Known solder resists can be used for the first solder resist layer 171 and the second solder resist layer 172. Each of the first solder resist layer 171 and the second solder resist layer 172 contains a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, but may not contain glass fibers. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but is not limited thereto, and other polymer materials may be used as necessary. When a photosensitive insulating resin is used as the solder resist layer, it may be advantageous for forming fine openings, but is not limited thereto, and fine openings can also be formed by including a non-photosensitive insulating resin and forming fine openings with a UV laser.

[0046] The first solder resist layer 171 can have a first opening 171O, and at least a part of the first pad 141 can be exposed by the first opening 171O. That the first opening 171O can expose a part of the first pad 141 means that the first solder resist layer 171 covers the first pad 141, but in the region where the first opening 171O is formed, the first solder resist layer 171 does not cover the first pad 141. That is, it can be meant to include the case where not only the first pad 141 is exposed outside the printed circuit board, but also a part of the first pad 141 can be connected to other components because the first solder resist layer 171 does not cover a part of the first pad 141.

[0047] On one hand, in FIG. 3a, the first opening 171O of the first solder resist layer 171 is shown as exposing a part of the upper surface of the first pad 141. However, the first solder resist layer 171, the first opening 171O, and the first pad are not limited to being aligned in the form of SMD (Solder Mask Defined), and may be aligned in the form of NSMD (Non-Solder Mask Defined). For example, the relationship between the first pad 141 and the first solder resist layer 171 is not limited to that shown in the drawing. When aligned in the form of NSMD, the width of the first opening 171O of the first solder resist layer 171 can be formed wider than the width of the first pad 141. Of course, the upper surface of the first pad 141 can be exposed by the first solder resist layer 171, and the side surface of the first pad 141 can also have a form exposed by the first solder resist layer 171.

[0048] The second solder resist layer 172 can cover at least a part of the second pad 142. Also, the metal post 150 can penetrate a part of the second solder resist layer 172 and can have a structure protruding from the second solder resist layer 172. That the metal post 150 protrudes more than the second solder resist layer 172 can mean that the upper surface of the metal post 150 can be positioned higher than the upper surface of the solder resist layer 172.

[0049] The second solder resist layer 172 can further expose at least a part of the second pad 142 through the second opening, and the second opening can be filled by the metal post 150. At this time, the width of the lower end portion of the metal post 150 in the region where the metal post 150 is in contact with the second pad 142 can be formed smaller than the width of the second pad 142. On the other hand, as described above, since the width of the second opening formed in the second solder resist layer 172 can also have various widths like the width of the first opening 171O, the width of the metal post 150 can be formed wider than the width of the second pad 142.

[0050] A printed circuit board according to an example can include a barrier layer 180 disposed on at least a part of the first pad 141. The barrier layer 180 can be disposed on at least a part of the first pad 141 and extend to a part of the first solder resist layer 171, such as extending to the inner wall of the first opening 171O. That is, the barrier layer 180 can cover at least a part of the first pad 141 and prevent the first pad 141 from being exposed to the outside.

[0051] On the other hand, the barrier layer 180 can also be disposed on at least a part of the second pad 142, extend to the inner wall of the second opening 172O, and extend onto at least a part of the upper surface of the second solder resist layer 172. That is, the barrier layer 180 can cover at least a part of the second pad 142 and prevent the second pad 142 from being exposed to the outside.

[0052] The barrier layer 180 can include a material having electrical conductivity. The barrier layer 180 can include a metallic material, but is not limited thereto. As the material having electrical conductivity, any material that can be arranged between the metal post 150 and the second pad 142 to conduct electricity is acceptable. Any material that can be arranged between the first pad 141 and the first surface treatment layer 161 and conduct electricity to enable connection to the outside can be used without limitation. That is, the material of the barrier layer is not limited. Copper (Cu) used as the metallic material of the first pad 141 and the second pad 142 can have a function of preventing the first surface treatment layer 161 and the second surface treatment layer 162 from being simultaneously exposed to an aqueous solution environment. As long as it does not contain substantially the same metallic material as the first pad 141 and the second pad 142. The barrier layer 180 can include a metal having a standard reduction potential value lower than that of the metal contained in the first pad 141 and the second pad 142. As a non-limiting example, it can include titanium (Ti), nickel (Ni), aluminum (Al), tin (Sn), lead (Pb), or an alloy thereof, which are metals having a standard reduction potential value lower than that of copper (Cu). On the other hand, without being limited thereto, the barrier layer 180 may not be a metallic material and may include a conductive inorganic carbon-based material or a conductive organic carbon-based material. As long as the material of the barrier layer 180 includes a material substantially different from the first pad 141 and the second pad 142.

[0053] The barrier layer 180 may be a coating layer formed using a thin film deposition method, such as an ALD (Atomic Layer Deposition) or MVD (Molecular Vapor Deposition) method. At this time, a thin film-like barrier layer can be formed by the deposition method. Note that it is not necessarily limited thereto, and the barrier layer 180 may be formed by deposition such as sputtering. On the other hand, the method of forming the barrier layer 180 may vary depending on the material of the barrier layer 180 and does not necessarily have to be limited to the deposition method. The barrier layer 180 may be thinner than the thickness of the first pad 141 and the second pad 142, and may also be thinner than the thickness of the first surface treatment layer 161.

[0054] The printed circuit board according to one example can further include a seed layer 190 on the barrier layer 180. The seed layer 190 can function as a plating seed for forming the metal posts 150. The seed layer 190 can be disposed on the barrier layer 180 and extend along the barrier layer. After forming the metal posts 150 and the second surface treatment layer 162 during the manufacturing stage of the printed circuit board, in order to remove unnecessary portions, the seed layer 190 and the barrier layer 180 can be disposed under the metal posts 150 and the second surface treatment layer 162. The seed layer 190 can also be disposed on the barrier layer 180 on the lower side of the printed circuit board. By forming the seed layer 190 also on the lower side of the printed circuit board, unlike the case where the seed layer 190 is formed only on the upper side of the printed circuit board, the potential difference between the upper side and the lower side of the printed circuit board can be adjusted. However, it is not limited to what is shown in FIGS. 3a and 3b, and the seed layer 190 disposed on the lower side of the printed circuit board may be omitted, or the seed layer 190 may be disposed only on the upper side of the printed circuit board where the metal posts 150 are disposed.

[0055] The seed layer 190 can contain a metallic substance, and as the metallic substance, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof, etc. can be used. The metallic substance can preferably contain copper (Cu), but is not limited thereto. The seed layer 190 can contain an electroless plating layer (or electroless copper) formed by electroless plating, but is not limited thereto, and may contain a sputtering layer formed by sputtering instead of electroless plating, or may contain both an electroless plating layer and a sputtering layer. Without being limited thereto, if necessary, a copper foil may be included, etc., and any metal that can function as a seed for electroplating can be used without limitation.

[0056] A printed circuit board according to an example may further include a first surface treatment layer 161 disposed on at least a part of the first pad 141. The surface treatment layer may be disposed on the first pad 141 within the first opening 171O of the first solder resist layer 171. The first surface treatment layer 161 may be disposed on the first pad 141, on the barrier layer 180, and on the seed layer 190. On the other hand, as described above, since the seed layer 190 may not be disposed on the lower side of the printed circuit board, in this case, the first surface treatment layer 161 may be disposed on the barrier layer 180. The first surface treatment layer 161 can improve the adhesion force and signal transmission force between the first pad 141 and the connecting member.

[0057] The first surface treatment layer 161 may include a first metal layer 165, a second metal layer 166, and a third metal layer 167, and may have a structure in which the first metal layer 165, the second metal layer 166, and the third metal layer 167 are sequentially disposed. On the other hand, it is not necessarily limited to this, and the boundaries of the respective metal layers may not be clearly distinguished.

[0058] The first metal layer 165 may contain nickel (Ni), the second metal layer 166 may contain palladium (Pd), and the third metal layer 167 may contain gold (Au). That is, the first surface treatment layer 161 may be at least a part of an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) structure. On the other hand, without being limited thereto, the second metal layer 166 may be omitted from the first surface treatment layer 161. In this case, the first surface treatment layer 161 may be at least a part of an ENIG (Electroless Nickel Immersion Gold) structure. Alternatively, the first metal layer 165 may also be omitted from the first surface treatment layer 161, and only gold (Au) plating may be included on the outermost side. The first surface treatment layer 161 may include the third metal layer 167 on the outermost side, and the third metal layer 167 containing gold (Au) may be disposed on the outermost side of the printed circuit board. The third metal layer 167 may include a plating layer, may be formed by electroless plating, and preferably may be formed by displacement plating. Since the third metal layer 167, which is the outermost side of the first surface treatment layer 161, may include a gold (Au) plating layer, there is a possibility that galvanic corrosion may occur in the second pad 142 that can contain copper (Cu).

[0059] A barrier layer 180 is formed on the first pad 141, and after a seed layer 190 is formed, a first surface treatment layer 161 is formed. As a result, the first surface treatment layer 161 can be formed to contact a barrier layer 180 and a seed layer 190 that are conformally disposed in a first opening 171O of the first solder resist layer 171. More specifically, the barrier layer 180 and the seed layer 190 can each extend at least partially along an inner wall of the first opening 171O on the first pad 141, and the first surface treatment layer 161 can be formed up to a height at which the first surface treatment layer 161 is formed. This is the result of forming the first surface treatment layer 161 after forming the barrier layer 180 and the seed layer 190 in a method of manufacturing a printed circuit board, and can be the result of removing a part of the seed layer 190 and a part of the barrier layer 180 thereafter. On the other hand, the arrangement relationship of the barrier layer 180, the seed layer 190, and the first surface treatment layer 161 is not necessarily limited to that shown in FIGS. 3A and 3B. As long as the barrier layer 180, the seed layer 190, and the first surface treatment layer 161 are sequentially stacked on the first pad 141, the specific height and the degree of arrangement can be changed without limitation.

[0060] The printed circuit board according to one example may further include a metal post 150 disposed on at least a part of the second pad 142. The metal post 150 can be disposed on the second pad 142 and penetrate at least a part of the second solder resist layer 172. The metal post 150 can include a metallic substance. As the metallic substance, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof can be used. The metallic substance can preferably include copper (Cu), but is not limited thereto. The metal post 150 may be formed by any one of SAM (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive process, but is not limited thereto, and can be formed using a method available to those having ordinary knowledge in the technical field. The metal post 150 can be formed by performing electroplating using the seed layer 190 as a plating seed, and the metal post 150 can include an electroplated layer (electrolytic copper).

[0061] The metal post 150 may be an area for mounting electronic components and chips, etc., and may be configured to protrude to facilitate connection when the electronic components and chips, etc. are mounted on the second pad 142. The metal post 150 can perform various functions according to the design of the second pad 142. The metal post 150 can transmit and receive signals electrically with the second pad 142.

[0062] When the second pad 142 requires a high-density fine pitch for mounting a semiconductor chip or the like, not only the interval between the second pads 142 but also the interval between the metal posts 150 may become narrow. By arranging the metal posts 150 on the second pad 142, even when a semiconductor chip with a fine pitch is mounted, the possibility of a short circuit of the connecting member 170 disposed between the semiconductor chip and the metal post 150 is reduced, and the possibility of a defect in which the semiconductor chip detaches may also be reduced. Further, by arranging the metal posts 150 on the second pad 142, it is possible to secure an adhesive force via the metal posts 150 rather than a structure in which a connecting member such as solder is directly disposed on the second pad 142, so that the reliability of the printed circuit board can be improved.

[0063] The printed circuit board according to an example may further include a second surface treatment layer 162 disposed on at least a part of the metal post 150. The second surface treatment layer 162 may also have a structure in which a first metal layer 165, a second metal layer 166, and a third metal layer 167 are sequentially arranged. However, as described above with respect to the first surface treatment layer 161, the metal layer may be omitted or further added. As described above, it is possible that the boundaries of the respective metal layers may not be clearly distinguished. Since the description of the first surface treatment layer 161 can be applied to the description of the first metal layer 165, the second metal layer 166, and the third metal layer 167, redundant description is omitted.

[0064] Since the metal post 150 has a structure protruding from the second solder resist layer 172, the second surface treatment layer 162 can be formed along the exposed surface of the metal post 150. That is, the second surface treatment layer 162 can be arranged to cover the upper surface and the side surface of the metal post 150, respectively. Since the second surface treatment layer 162 can be arranged to cover the side surface of the metal post 150, the side surface of the metal post 150 is not exposed to the outside. By not exposing the side surface of the metal post 150 to the outside, galvanic corrosion occurring between the first surface treatment layer 161 and / or the second surface treatment layer 162 and the metal post 150 can be prevented in the step of removing a part of the seed layer 190 in the method for manufacturing a printed circuit board. Further, galvanic corrosion occurring between the first surface treatment layer 161 and / or the second surface treatment layer 162 and the second pad 142 can be prevented.

[0065] On the one hand, in the region where the metal post 150 of the printed circuit board according to an example is in contact with the second surface treatment layer 162, the surface roughness of the upper surface and the surface roughness of the side surface can be substantially the same. This can be the result of using the second resist in the step of forming the second surface treatment layer 162 in the manufacturing method of the printed circuit board according to an example. When the second surface treatment layer 162 is formed by performing additional processing on the resist used in the step of forming the metal post 150 so that the resist has an opening wider than the width of the metal post 150, the side surface of the metal post 150 may be damaged in the step of performing additional processing on the resist. In this case, unevenness may occur on the side surface of the metal post 150, and the roughness of the side surface of the metal post 150 may be greater than the surface roughness of the upper surface. In contrast, in the printed circuit board according to an example, after removing the first resist for forming the metal post 150, a second resist for forming the second surface treatment layer 162 is separately formed, so the side surface of the metal post 150 may not be damaged, and the side surface of the metal post 150 can have substantially the same roughness as the upper surface. The surface roughness can be measured by photographing a cross-section cut in the stacking direction of the printed circuit board with a scanning microscope or the like, and the surface roughness can be measured using a known method for calculating the roughness. For example, the arithmetic mean roughness (Ra) may be used, or the ten-point mean roughness (Rz) may be used. However, it is preferable that the method for measuring the roughness of the upper surface and the method for measuring the roughness of the side surface of the metal post 150 are performed according to the same standard and method. The fact that the roughness of the side surface and the upper surface of the metal post 150 are substantially the same may be the result of the difference in the manufacturing method described above, but is not limited thereto, and the surface of the second surface treatment layer 162 that contacts the metal post 150 can also have a substantially uniform surface roughness. Also, instead of further processing the opening in the resist, since the second surface treatment layer 162 is formed using a separate second resist, the opening region of the second resist can also have a flat surface with no unevenness in surface roughness. Therefore, the third metal layer 167 of the second surface treatment layer 162 can also be formed such that the surface roughness of the side surface and the surface roughness of the upper surface are substantially the same or almost the same.On the one hand, since the seed layer 190 disposed in the region where the second surface treatment layer 162 is formed may not be damaged by not processing the resist, the surface roughness of the region in contact with the metal post 150 of the seed layer 190 and the surface roughness in the region in contact with the second surface treatment layer 162 of the seed layer 190 can be substantially the same. On the other hand, without being limited thereto, as long as it can be confirmed when the first resist is removed after forming the metal post 150 and the second surface treatment layer 162 is formed using the second resist, it can be applied without limitation to the description of the printed circuit board according to an example.

[0066] The printed circuit board according to an example may further include a connection structure 200 and an adhesive layer 210. The connection structure 200 can be connected to an electronic component such as a semiconductor chip. For example, the connection structure 200 can have a bridge structure. The connection structure 200 can include a main body on which a pattern is realized on an insulating material, and can include a connection portion 201 for connection to a wiring layer. The connection structure 200 may be composed of an organic substrate, or may be a silicon bridge in which a circuit is realized on a silicon wafer or the like. Without being limited thereto, the connection structure 200 may be such that one semiconductor chip is embedded in the insulating portion 110 of the printed circuit board.

[0067] The connection structure 200 is disposed in a cavity penetrating at least a part of the second insulating layer 112 and can be embedded by the second insulating layer 112. In order for the connection structure 200 to be mounted in the cavity, an adhesive layer 210 can be further included. Regarding the structure and mounting of the connection structure 200, those having ordinary knowledge in the technical field can form it using available structures and methods.

[0068] In FIGS. 3a and 3b, the first metal layer 165, the second metal layer 166, the third metal layer 167, the seed layer 190, and the barrier layer 180 are shown as having similar thicknesses, but this is an element for assisting the understanding of the arrangement relationship, and it is of course not necessarily limited thereto.

[0069] On the one hand, the printed circuit board according to an example is not limited to the configuration shown in FIGS. 3a and 3b, and other configurations may be further included and, in some cases, may be omitted. That is, it may further include or omit configurations that can be utilized by those having ordinary knowledge in the technical field.

[0070] FIG. 3c is a cross-sectional view schematically showing a printed circuit board according to another example.

[0071] Referring to FIG. 3c, the printed circuit board according to another example can further include semiconductor chips 301 and 302 disposed on the metal posts 150, and can further include a connecting member 400 that connects the metal posts 150 and the semiconductor chips 301 and 302 to each other.

[0072] The semiconductor chips 301 and 302 may be integrated circuits (ICs) in which hundreds to millions or more elements are integrated within a single chip. Each of these may be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, specifically, an application processor (AP), but is not limited thereto, and may also be a logic chip such as an analog-digital converter, an ASIC (application-specific IC) memory controller (MC) chip, or may be a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, a flash memory chip, a PRAM (Phase-change Random Access Memory) chip, an MRAM (Magnetic Random Access Memory) chip, an RRAM (Resistive Random Access Memory) chip, an EEPROM (Electrically Erasable and Programmable Read-Only Memory) chip, or an HBM (High Bandwidth Memory), and it goes without saying that these may be arranged in combination with each other.

[0073] The semiconductor chips 301 and 302 can be composed of a main body and connection pads. The surface on which connection pads for connecting to the metal posts 150 are arranged can be the active surface, and the opposite surface can be the non-active surface, but it is not limited thereto. Dual-sided connection may also be possible, and in some cases, it can also have a three-dimensional structure. The semiconductor chips 301 and 302 can be formed based on an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. can be used as the base material forming the main body. Various circuits may be formed in the semiconductor chips 301 and 302, and at least a part of these circuits may be connected to the connection pads.

[0074] The connecting member 400 may be formed of a conductive material, for example, solder, etc., but the material of the connecting member 400 is not particularly limited thereto. Note that the connection method of the connecting member 400 is not limited thereto, and it may be composed of land, ball, pin, etc. Also, the connecting member 400 may be formed in multiple layers or a single layer. When formed in multiple layers, it can include copper pillars and solder, and when formed in a single layer, it can include solder composed of tin-silver or copper, but it is not limited thereto.

[0075] On the other hand, in FIG. 3c, two semiconductor chips 301 and 302 are shown as being arranged on a printed circuit board, but it is not limited thereto. In particular, although the semiconductor chips 301 and 302 are shown as being die-to-die connected with the connection structure 200 interposed therebetween, it is not necessarily limited thereto. The number and arrangement form of the semiconductor chips 301 and 302, and the number, interval, arrangement form, etc. of the connecting member 400 are not particularly limited and can be sufficiently deformed according to the design matters for an ordinary engineer.

[0076] Among the configurations other than the descriptions of the first semiconductor chip and the second semiconductor chip and the content regarding the connecting member, the configuration similar to that of the printed circuit board according to one example is applicable to the printed circuit board according to another example. Therefore, duplicate descriptions thereof are omitted.

[0077] Method for manufacturing a printed circuit board Figs. 4 to 15 are cross-sectional views schematically showing a method for manufacturing a printed circuit board according to one example.

[0078] The method for manufacturing a printed circuit board according to one example may include steps of forming a first pad 141 on the lower side of the insulating portion 110, forming a second pad 142 on the upper side of the insulating portion 110, forming a first solder resist layer 171 and a second solder resist layer 172 on the lower side and the upper side of the insulating portion 110 respectively, forming a barrier layer 180 on each of the first pad 141 and the second pad 142, forming a seed layer 190 on the barrier layer 180, forming a first surface treatment layer 161 on the seed layer 190 on the first pad 141 side, forming a metal post 150 on the seed layer 190 on the second pad 142 side, forming a second surface treatment layer 162 on the metal post 150, and removing a part of each of the seed layer 190 and the barrier layer 180.

[0079] Referring to FIG. 4, a wiring portion of a printed circuit board is prepared. The wiring portion can include an insulating portion 110 including a first insulating layer 111 and / or one or more second insulating layers 112, and can include a first wiring layer 121 disposed on the first insulating layer 111, and a second wiring layer 122 disposed on or within the second insulating layer 112. The wiring portion can include a first pad 141 disposed on the lowermost second insulating layer 112 and a second pad 142 disposed on the uppermost second insulating layer 112. The step of preparing the wiring portion can include the step of forming the first wiring layer 121 on the first insulating layer 111, and can include the steps of forming the second insulating layer 112 on the first insulating layer 111 and forming the second wiring layer 122. The steps of forming the first pad 141 and the second pad 142 on the outermost second insulating layer 112 can be included. At this time, the steps of forming the insulating layer and the wiring layer can be performed by a known build-up process.

[0080] On the other hand, a method for manufacturing a printed circuit board according to an example can further include the steps of forming a cavity penetrating at least a part of the second insulating layer 112, attaching and mounting a connection structure 200 with an adhesive layer 210, and embedding it in the second insulating layer 112, but is not necessarily limited thereto.

[0081] The method can include the step of forming a first solder resist layer 171 below the wiring portion and the step of forming a second solder resist layer 172 above the wiring portion. Each solder resist layer may be formed simultaneously, but is not necessarily limited thereto. The method of forming the first solder resist layer 171 and the second solder resist layer 172 can be used without limitation as long as it is a known method of forming a solder resist.

[0082] Next, referring to FIG. 5, a method for manufacturing a printed circuit board according to an example may include forming a first opening 171O in a first solder resist layer 171 and forming a second opening 172O in a second solder resist layer 172. The first opening 171O can be formed on the first pad 141, and at least a part of the first pad 141 can be exposed by the first opening 171O. The second opening 172O can be formed on the second pad 142, and at least a part of the second pad 142 can be exposed by the second opening 172O. The method of forming the first opening 171O and the second opening 172O in each of the first solder resist layer 171 and the second solder resist layer 172 can be used without limitation as long as it is a known method for forming an opening.

[0083] At this time, pretreatment for forming the metal post 150 can be performed. As the pretreatment, a desmear process for removing residues formed in the second solder resist layer 172 can be performed, and soft etching for processing the surface of the exposed second pad 142 can be performed.

[0084] Next, referring to FIG. 6, a method for manufacturing a printed circuit board according to an example may include forming a barrier layer 180. The barrier layer 180 can be formed on the first solder resist layer 171 and the second solder resist layer 172, respectively. Since the barrier layer 180 can have a thin film shape, the barrier layer 180 can be conformally disposed along the shapes of the first solder resist layer 171 and the second solder resist layer 172. The barrier layer 180 is disposed on the inner walls of the first opening 171O and the second opening 172O, and can be disposed so as to extend to the lower surface of the first solder resist layer 171 and the upper surface of the second solder resist layer 172, respectively.

[0085] The method of forming the barrier layer 180 may vary depending on the material of the barrier layer 180 and may be formed by vapor deposition, but is not limited thereto, as described above in the description of the printed circuit board, and any method capable of forming a thin film can be used without limitation.

[0086] Next, referring to FIG. 7, a method of manufacturing a printed circuit board according to an example may include a step of forming a seed layer 190. The seed layer 190 can be formed on the barrier layer 180, and can be formed not only on the barrier layer 180 disposed above the second pad 142, but also on the barrier layer 180 disposed below the first pad 141. Since the seed layer 190 is also formed on the lower side, uniform plating can be formed by adjusting the potential difference between the upper and lower sides. The seed layer 190 can be formed by electroless plating and can be performed by electroless copper plating, but is not limited thereto, and can also be performed by a sputtering method. The seed layer 190 can be formed along the barrier layer 180 and can be conformally formed along the first solder resist layer 171 and the second solder resist layer 172.

[0087] Next, referring to FIG. 8, a method for manufacturing a printed circuit board according to an example can include a step of forming a first resist 501. The first resist 501 may be a known plating resist. The first resist 501 can be disposed on the seed layer 190 to form an opening that partially penetrates therethrough, and can open an area where plating is to be performed. The first resist 501 may be a resist for forming the metal posts 150, or may be a resist for forming the first surface treatment layer 161. The first resist 501 disposed on the lower side is formed on the seed layer 190 disposed on the first solder resist layer 171, and an area where the first surface treatment layer 161 is to be formed can be opened. The first resist 501 can be opened so as to correspond to the first opening 171O of the first solder resist layer 171. The first resist 501 disposed on the upper side is formed on the seed layer 190 disposed on the second solder resist layer 172, and an area where the metal posts 150 are to be formed can be opened. That is, it can include an opening in an area wider than the second opening 172O of the second solder resist layer 172.

[0088] Next, referring to FIG. 9, a method for manufacturing a printed circuit board according to an example can include a step of forming a first surface treatment layer 161. The first surface treatment layer 161 can be formed on the first pad 141, and can be disposed on the barrier layer 180 and the seed layer 190 disposed on the first pad 141. As described above, the first surface treatment layer 161 may include a first metal layer 165, a second metal layer 166, and a third metal layer 167. The first surface treatment layer 161 can be formed within the first opening.

[0089] Next, referring to FIG. 10, a method for manufacturing a printed circuit board according to an example can include a step of forming metal posts 150. The metal posts 150 can be formed by electrolytic plating using the seed layer 190 as a plating seed and the first resist 501 as a plating resist. The step of forming the metal posts 150 is not limited thereto, and may be formed using a method available to those having ordinary knowledge in the art.

[0090] On the other hand, referring to FIGS. 4 to 10, although the manufacturing method of the printed circuit board according to an example is shown such that the upper and lower side processing is performed at the same stage, it is not necessarily limited thereto, and after processing the lower side of the printed circuit board first to form the first surface treatment layer 161, the upper side may be processed to form the metal post 150.

[0091] Next, referring to FIG. 11, the manufacturing method of the printed circuit board according to an example may include a step of removing the first resist 501. The method of removing the first resist 501 can be performed by a known method of removing a plating resist.

[0092] Next, referring to FIG. 12, the manufacturing method of the printed circuit board according to an example may include a step of forming the second resist 502. The second resist 502 can function as a plating resist and can include an opening for forming the second surface treatment layer 162. The second resist 502 can use a known resist and can include the same material as the first resist 501, but is not limited thereto, and the material of the second resist 502 can be selected according to the form and substance of the plating. The opening formed in the second resist 502 may be formed wider than the width of the metal post 150. By forming the opening wider than the metal post 150, the second surface treatment layer 162 can be formed so as to cover the side surface of the metal post 150.

[0093] On the other hand, the printed circuit board according to one example does not further process the first resist 501 to have an opening wider than the metal post 150. Instead, after removing the first resist 501, a step of forming the second resist 502 is separately performed. That is, instead of expanding the opening of the cured first resist 501 by mechanical / chemical processing, the second resist 502 may be separately formed and the exposure and development steps may be performed to form the opening. That is, since it is different from the case where mechanical / chemical processing is performed targeting only a part of the first resist 501, there is a possibility that the region adjacent to the opening of the first resist 501 is not processed and damaged. That is, the seed layer 190 in the region where the metal post 150 is formed and the seed layer 190 in the region exposed by the opening of the second resist 502 for forming the second surface treatment layer 162 can have substantially the same characteristics as each other. Since the side surface of the metal post 150 is not damaged, the relationship between the upper surface and the side surface of the metal post 150 can also be the same as this.

[0094] Next, referring to FIG. 13, the manufacturing method of the printed circuit board according to one example may include a step of forming the second surface treatment layer 162. The second surface treatment layer 162 can be formed in the opening region of the second resist 502 and can be formed so as to cover the upper surface and the side surface of the metal post 150. That is, the second surface treatment layer 162 can be formed on the metal post 150 exposed by the opening of the second resist 502. The second surface treatment layer 162 can include a first metal layer 165, a second metal layer 166, and a third metal layer 167. Since the content and method of forming the second surface treatment layer 162 overlap with the content regarding the first surface treatment layer 161, they are omitted.

[0095] By covering the side surfaces of the metal posts 150 with the second surface treatment layer 162, the metal posts 150 are not exposed to the outside in the subsequent step of removing a part of the seed layer 190 and the barrier layer 180. Therefore, galvanic corrosion may not occur between the metal posts 150 and the third metal layer 167. That is, the first metal layer 165 formed to contact the metal posts 150 can also function as a barrier to prevent the exposure of the metal posts 150.

[0096] Next, referring to FIG. 14, a method for manufacturing a printed circuit board according to an example may include a step of removing the second resist 502. The method of removing the second resist 502 can be performed using a known resist removal method.

[0097] Next, referring to FIG. 15, a method for manufacturing a printed circuit board according to an example may include a step of removing a part of the seed layer 190 and a part of the barrier layer 180. Since the seed layer 190 and the barrier layer 180 can include different materials from each other, after the step of removing a part of the seed layer 190, the step of removing a part of the barrier layer 180 may be sequentially performed, but it is not limited thereto, and they may be performed simultaneously.

[0098] Even if an etching solution or the like is used to remove a part of the seed layer 190, since the barrier layer 180, which is a different material, is included under the seed layer 190 and the first metal layer 165 of the second surface treatment layer 162 is disposed on the side surfaces of the metal posts 150, galvanic corrosion may not occur on the metal posts 150 and the second pads 142 during the removal step of the seed layer 190.

[0099] By performing the step of removing a part of the barrier layer 180, the short - circuit state in which the metal posts 150 are connected to each other can be opened, and the metal posts 150 and the second pads 142 can function. On the other hand, also on the lower side of the printed circuit board, a part of the seed layer 190 and a part of the barrier layer 180 are removed, and the first pads 141 can function.

[0100] In the present invention, the meaning in the cross-section can mean the cross-sectional shape when the object is vertically cut, or the cross-sectional shape when the object is viewed in a side view. Also, the meaning on the plane can mean the shape when the object is horizontally cut, or the planar shape when the object is viewed in a top view or a bottom view.

[0101] In the present invention, "upper side, upper part, upper surface", etc. are used for convenience to mean the direction toward the surface on which electronic components can be mounted with reference to the cross-section of the drawing, and "lower side, lower part, lower surface", etc. are used to mean the opposite direction. However, this is for convenience of explanation and defines the direction, and it goes without saying that the scope of rights in the claims is not particularly limited by the description of such a direction.

[0102] In the present invention, "connected" includes not only being directly connected but also being indirectly connected via an adhesive layer or the like. Also, "electrically connected" includes both the case of being physically connected and the case of not being connected. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the said component. In some cases, within the scope not departing from the scope of rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0103] In the present invention, it can be judged including substantially process errors, position deviations, errors during measurement, etc. that occur in the manufacturing process. For example, "substantially vertical" can include not only the case of being completely vertical but also the case of being almost vertical. Also, "substantially coplanar" can include not only the case of existing on exactly the same plane but also the case of existing on almost the same plane.

[0104] In the present invention, the "same material" can mean not only when the materials are completely identical, but also when they include the same type of materials. Therefore, although the compositions of the materials are substantially the same, their specific composition ratios may differ slightly from each other.

[0105] The expression "an example" used in the present invention does not mean the same embodiments as each other, but is provided to emphasize and explain their respective unique features. However, it does not exclude that the above-presented example can be realized in combination with the features of other examples. For example, even if a matter described in a specific example is not described in another example, in the other example, as long as there is no description contrary to or conflicting with that matter, it can be understood as an explanation related to the other example.

[0106] The terms used in the present invention are merely used to explain an example and are not intended to limit the present invention. At this time, the singular expression includes plural expressions unless the context clearly indicates a different meaning.

Explanation of Reference Numerals

[0107] 110: Insulating portion 111, 112: First and second insulating layers 121, 122: First and second wiring layers 131, 132: First and second via layers 141: First pad 142: Second pad 150: Metal post 161: First surface treatment layer 162: First surface treatment layer 165, 166, 167: First, second, and third metal layers 171: First solder resist layer 171O: First opening 172: Second solder resist layer 172O: Second opening 180: Barrier layer 190: Seed layer 200: Connecting structure 201: Connection portion 210: Next layer 301, 302: Semiconductor chips 400: Connecting member 501, 502: First and second resists 1000: Electronic device 1010: Main board 1020: Chip-related components 1030: Network-related components 1040: Other components 1050: Camera module 1060: Antenna module 1070: Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Main board inside the smartphone 1120: Electronic components inside the smartphone 1121: Antenna module inside the smartphone 1130: Camera module inside the smartphone 1140: Speaker inside the smartphone

Claims

1. An insulating portion; A first pad disposed under the insulating portion; a first solder resist layer disposed under the insulating portion, covering at least a portion of the first pad, and having a first opening over at least a portion of the first pad; a first barrier layer disposed on a portion of the first pad corresponding to the first opening; a first surface treatment layer disposed on the first barrier layer; A second pad disposed on an upper side of the insulating portion; a second solder resist layer disposed on the insulating portion, covering at least a portion of the second pad, and having a second opening on at least a portion of the second pad; a metal post disposed on the second pad and at least a portion of the metal post disposed within the second opening; a second barrier layer disposed between the second pad and the metal post.

2. The printed circuit board of claim 1 , wherein the first barrier layer extends over a portion of an inner wall of the first opening.

3. The printed circuit board of claim 1 , wherein the first barrier layer is disposed along at least a portion of a side surface of the first surface treatment layer.

4. 2. The printed circuit board of claim 1, wherein the first surface treatment layer includes a first metal layer disposed on the barrier layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer.

5. The printed circuit board of claim 1 , further comprising a first seed layer disposed between the first barrier layer and the surface treatment layer.

6. the first barrier layer extends over a portion of an inner wall of the first opening; The printed circuit board of claim 5 , wherein the first seed layer extends along the first barrier layer.

7. The printed circuit board of claim 6 , wherein one side of each of the first barrier layer, the first seed layer, and the first surface treatment layer are substantially coplanar.

8. The printed circuit board according to claim 1 , wherein one surface of the first surface treatment layer forms a step with a lower surface of the first solder resist layer.

9. The printed circuit board of claim 1 , wherein the barrier layer comprises a different metal than the first pad.

10. The printed circuit board of claim 1 , wherein the second barrier layer is disposed on the second pad and extends onto an inner wall of the second opening and a portion of an upper surface of the second solder resist.

11. 11. The printed circuit board of claim 10, further comprising a second seed layer disposed between the second barrier layer and the metal post and extending onto the second barrier layer.

12. The printed circuit board of claim 11 , further comprising a second surface treatment layer disposed on the metal posts.

13. The printed circuit board of claim 12 , wherein a surface of each of the second surface treatment layer, the second barrier layer, and the second seed layer are substantially coplanar with each other.

14. 13. The printed circuit board of claim 12, wherein the second surface treatment layer includes a first metal layer disposed on the metal post, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer.

15. The insulating portion includes a plurality of insulating layers, The printed circuit board according to claim 1 , further comprising a plurality of wiring layers disposed on one or more of the insulating layers, respectively, and connected to the first pad and the second pad.

16. An insulating portion; A pad disposed on an upper side of the insulating portion; a solder resist layer disposed on the insulating portion to cover at least a portion of the pad and having an opening above at least a portion of the pad; a barrier layer disposed in contact with the pad and extending over an inner wall of the opening and a portion of an upper surface of the solder resist layer; a metal post disposed on the barrier layer; the pad comprises a first metal; The barrier layer comprises a material different from the first metal of the pad.

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