Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a technology that can suppress interdiffusion between silicon and aluminum.SOLUTION: A semiconductor device includes a semiconductor substrate, an electrode, and a first silicon nodule. The semiconductor substrate includes a drift layer of a first conductivity type and an anode layer of a second conductivity type, and the anode layer is provided on at least part of the drift layer. The electrode is located above the anode layer and contains aluminum. The first silicon nodule is located between the anode layer and the electrode and contains oxygen.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In recent years, in an RC-IGBT provided with an IGBT region and a diode region, a configuration has been proposed in which an electrode containing aluminum is provided near the anode layer of the diode region (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a configuration in which an electrode containing aluminum is provided near the anode layer as in Patent Document 1, aluminum having a high diffusion coefficient contained in the electrode causes a growth rate diffusion effect in the anode layer containing silicon. For this reason, there has been a problem that the variation in the diffusion profile of the anode layer becomes large.

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of suppressing the mutual diffusion of silicon and aluminum.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate including a drift layer of a first conductivity type and a second conductivity type anode layer provided on at least a part of the drift layer, an electrode containing aluminum provided above the anode layer, and a first silicon module containing oxygen provided between the anode layer and the electrode.

Effects of the Invention

[0007] According to the present disclosure, a first silicon module containing oxygen is provided between an anode layer and an electrode containing aluminum. According to such a configuration, the mutual diffusion between silicon and aluminum can be suppressed.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. The features described in the following embodiments are examples, and not all features are necessarily essential. Also, in the descriptions shown below, the same or similar reference numerals are given to the same or similar components in a plurality of embodiments, and different components will be mainly described. Further, in the descriptions described below, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily have to match the positions and directions during actual implementation. Also, the fact that a certain part has a higher density than another part means, for example, that the average density of a certain part is higher than the average density of another part. Conversely, the fact that a certain part has a lower density than another part means, for example, that the average density of a certain part is lower than the average density of another part. Also, hereinafter, it will be described assuming that the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. Note that n - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0010] <Embodiment 1> FIG. 1 is a plan view showing a semiconductor device that is an RC-IGBT (Reverse Conducting IGBT). Further, FIG. 2 is a plan view showing another configuration of the semiconductor device that is an RC-IGBT according to Embodiment 1. The semiconductor device 100 shown in FIG. 1 has an IGBT region 10 and a diode region 20 provided side by side in a stripe shape, and may be simply referred to as a "stripe type" in the following description. The semiconductor device 100 shown in FIG. 2 has a plurality of diode regions 20 provided in the vertical and horizontal directions, and the IGBT region 10 is provided around the diode region 20, and may be simply referred to as an "island type" in the following description.

[0011] <Overall planar structure of the stripe type> In FIG. 1, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 in one semiconductor device. Each of the IGBT region 10 and the diode region 20 extends from one end side to the other end side of the semiconductor device 100, and is provided alternately in a stripe shape in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. In FIG. 1, three IGBT regions 10 and two diode regions 20 are shown, and a configuration in which all the diode regions 20 are sandwiched by the IGBT regions 10 is shown. However, the numbers of the IGBT region 10 and the diode region 20 are not limited to this, the number of the IGBT region 10 may be three or more or three or less, and the number of the diode region 20 may also be two or more or two or less. Also, a configuration in which the positions of the IGBT region 10 and the diode region 20 in FIG. 1 are interchanged may be used, or a configuration in which all the IGBT regions 10 are sandwiched by the diode regions 20 may be used. Also, a configuration in which the IGBT region 10 and the diode region 20 are provided adjacent to each other one by one may be used.

[0012] As shown in FIG. 1, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the paper surface. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. In the following description, the IGBT region 10 and the diode region 20 may also be collectively referred to as a cell region. A termination region 30 is provided around the region combining the cell region and the pad region 40 for maintaining the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintaining structure may be appropriately provided in the termination region 30. For the breakdown voltage maintaining structure, for example, on the front side of the semiconductor device 100, an FLR (Field Limiting Ring) surrounding the cell region with a p-type terminal well layer of a p-type semiconductor or a VLD (Variation of Lateral Doping) surrounding the cell region with a p-type well layer having a concentration gradient may be provided. Note that the number of ring-shaped p-type terminal well layers used for the FLR and the concentration distribution used for the VLD may be appropriately selected according to the breakdown voltage design of the semiconductor device 100. Also, a p-type terminal well layer may be provided over almost the entire area of the pad region 40, or IGBT cells or diode cells may be provided in the pad region 40.

[0013] The control pad 41 includes, for example, at least any one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e. In this specification, for example, at least any one of A, B, C, …, and Z means any one of all combinations extracted from one or more types in the group of A, B, C, …, and Z.

[0014] The current sense pad 41a is a control pad for detecting the current flowing through the cell region of the semiconductor device 100. When a current flows through the cell region of the semiconductor device 100, the current sense pad 41a is electrically connected to the cell region such that a current of one fraction to one ten-thousandth of the current flowing through the entire cell region flows through a part of the IGBT cells or diode cells in the cell region.

[0015] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on / off control of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p + type contact layer. The temperature sense diode pads 41d, 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided in the semiconductor device 100. The voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region is measured via the temperature sense diode pads 41d, 41e, and the temperature of the semiconductor device 100 is measured based on the voltage.

[0016] <Island-type overall planar structure> In FIG. 2, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 in one semiconductor device. The diode regions 20 are arranged in a plurality in each of the vertical and horizontal directions in the semiconductor device 100, and the periphery of the diode region 20 is surrounded by the IGBT region 10. That is, a plurality of diode regions 20 are provided in an island shape within the IGBT region 10. In FIG. 2, the diode regions 20 are shown in a matrix configuration of 4 columns in the left-right direction of the drawing sheet and 2 rows in the up-down direction of the drawing sheet. However, the number and arrangement of the diode regions 20 are not limited to this, and one or a plurality of diode regions 20 may be scattered within the IGBT region 10 as long as the periphery of each diode region 20 is surrounded by the IGBT region 10.

[0017] As shown in FIG. 2, a pad region 40 is provided adjacent to the lower side of the IGBT region 10 in the plane of the drawing. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. In the description here, the IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the region combining the cell region and the pad region 40 for maintaining the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintaining structure may be appropriately provided in the termination region 30. For the breakdown voltage maintaining structure, for example, on the front side of the semiconductor device 100, an FLR surrounding the region combining the cell region and the pad region 40 with a p-type terminal well layer of a p-type semiconductor or a VLD surrounding the cell region with a p-type well layer having a concentration gradient may be provided. Note that the number of ring-shaped p-type terminal well layers used for the FLR and the concentration distribution used for the VLD may be appropriately selected according to the breakdown voltage design of the semiconductor device 100. Also, a p-type terminal well layer may be provided over substantially the entire area of the pad region 40, or IGBT cells or diode cells may be provided in the pad region 40.

[0018] The control pad 41 includes, for example, at least any one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e.

[0019] The current sense pad 41a is a control pad for detecting the current flowing through the cell region of the semiconductor device 100. When a current flows through the cell region of the semiconductor device 100, the current sense pad 41a is electrically connected to the cell region so that a current of one fraction to one ten-thousandth of the current flowing through the entire cell region flows through a part of the IGBT cells or diode cells in the cell region.

[0020] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on / off controlling the semiconductor device 100 is applied. The Kelvin emitter pad 41b is connected to the p-type base layer and n +It is electrically connected to the p-type source layer. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p + -type contact layer. The temperature sense diode pads 41d, 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided in the semiconductor device 100. The voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region is measured via the temperature sense diode pads 41d, 41e, and the temperature of the semiconductor device 100 is measured based on the voltage.

[0021] <IGBT region 10> FIG. 3 is a partially enlarged plan view showing the configuration of the IGBT region 10 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 3 is a view showing an enlarged view of the region surrounded by the broken line 82 in the semiconductor device 100 shown in FIGS. 1 and 2.

[0022] Also, FIGS. 4 and 5 are cross-sectional views showing the configuration of the IGBT region 10 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 4 is a cross-sectional view taken along the dashed-dotted line A-A of the semiconductor device 100 shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the dashed-dotted line B-B of the semiconductor device 100 shown in FIG. 3.

[0023] As shown in FIG. 3, an active trench gate 11 and a dummy trench gate 12 are provided in the IGBT region 10 in a stripe shape. In the semiconductor device 100 of FIG. 1, the active trench gate 11 and the dummy trench gate 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to the longitudinal direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, in the semiconductor device 100 of FIG. 2, there is no particular distinction between the longitudinal direction and the lateral direction in the IGBT region 10, and the left-right direction on the paper surface may correspond to the longitudinal direction of the active trench gate 11 and the dummy trench gate 12, or the up-down direction on the paper surface may correspond to the longitudinal direction of the active trench gate 11 and the dummy trench gate 12.

[0024] The active trench gate 11 is configured such that a gate trench electrode 11a is provided in a trench of a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is configured such that a dummy trench electrode 12a is provided in a trench of the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c in FIGS. 1 and 2. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the front surface of the semiconductor device 100.

[0025] As shown in FIG. 3, an n + -type source layer 13 is provided in contact with the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. The n + -type source layer 13 is also called an n + -type emitter layer in some semiconductor devices. The n + -type source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+17 / cm 3 ~1.0E+20 / cm 3 . The n + -type source layer 13 is provided alternately with a p + -type contact layer 14 along the extending direction of the active trench gate 11. The p + -type contact layer 14 is provided in contact with the dummy trench insulating film 12b between two adjacent dummy trench gates 12. The p + -type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 .

[0026] As shown in FIG. 3, in the IGBT region 10 of the semiconductor device 100, three dummy trench gates 12 are arranged adjacent to three active trench gates 11 arranged side by side. And, adjacent to the three dummy trench gates 12 arranged side by side, there is a configuration in which three active trench gates 11 different from the above are arranged side by side. The IGBT region 10 has a configuration in which a set of active trench gates 11 and a set of dummy trench gates 12 are arranged alternately in this way. In FIG. 3, the number of active trench gates 11 included in one set of active trench gates 11 is set to 3, but it may be 1 or more. Also, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be 1 or more, and the number of dummy trench gates 12 may be 0. That is, all of the trench gates provided in the IGBT region 10 may be active trench gates 11.

[0027] FIG. 4 is a cross-sectional view taken along the dashed-dotted line A-A in FIG. 3 of the semiconductor device 100, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 has an n - -type drift layer 1 made of a semiconductor substrate. The n - -type drift layer 1 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+15 / cm 3 . Note that the concentration of the n-type impurity in the above-described n + -type source layer 13 is higher than the concentration of the n-type impurity in the n - -type drift layer 1.

[0028] The range of the semiconductor substrate is, in FIG. 4, from the n + -type source layer 13 and the p + -type contact layer 14 to the p-type collector layer 16. The p-type collector layer 16 is also called a p-type drain layer in some semiconductor devices. In FIG. 4, the n + -type source layer 13 and the p +The upper end of the p-type contact layer 14 on the paper surface is called the front surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is called the back surface of the semiconductor substrate. In the IGBT region 10 of the cell region, the semiconductor device 100 has an n - type drift layer 1 between the front surface and the back surface opposite to the front surface. Note that the semiconductor substrate may be configured to include at least one of, for example, a wafer and an epitaxial growth layer. Further, the semiconductor substrate may include a wide bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), diamond) capable of stable operation at high temperatures.

[0029] As shown in FIG. 4, in the IGBT region 10, on the front surface side of the n - type drift layer 1, an n - type carrier accumulation layer 2 having a higher concentration of n-type impurities than the n-type drift layer 1 is provided. The n-type carrier accumulation layer 2 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+13 / cm 3 ~1.0E+17 / cm 3 . Note that the semiconductor device 100 may be configured such that the n-type carrier accumulation layer 2 is not provided and the n - type drift layer 1 is also provided in the region of the n-type carrier accumulation layer 2 shown in FIG. 4. By providing the n-type carrier accumulation layer 2, the conduction loss when current flows through the IGBT region 10 can be reduced. The n-type carrier accumulation layer 2 and the n - type drift layer 1 may be collectively referred to as a drift layer.

[0030] The n-type carrier accumulation layer 2 is formed by ion-implanting n-type impurities into the semiconductor substrate constituting the n - type drift layer 1 and then diffusing the implanted n-type impurities into the semiconductor substrate, which is the n - type drift layer 1, by annealing.

[0031] A p-type base layer 15 is provided on the front surface side of the n-type carrier accumulation layer 2. In the example of FIG. 4, the p-type base layer 15 is separated from the n-type carrier accumulation layer 2 by n -Although it is selectively and indirectly provided on the n-type drift layer 1, n - It may be selectively and directly provided on the n-type drift layer 1. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 It is. The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. In the example of FIG. 4, the p-type base layer 15 is also in contact with the dummy trench insulating film 12b of the dummy trench gate 12.

[0032] In a part of the front surface side region of the p-type base layer 15, an n + type source layer 13 in contact with the gate trench insulating film 11b of the active trench gate 11 is selectively provided, and in the remaining region of the front surface side of the p-type base layer 15, a p + type contact layer 14 is selectively provided. The n + type source layer 13 and the p + type contact layer 14 constitute the front surface of the semiconductor substrate. Note that the p + type contact layer 14 is a region where the concentration of the p-type impurity is higher than that of the p-type base layer 15. When it is necessary to distinguish between the p + type contact layer 14 and the p-type base layer 15, they may be individually called, and when there is no need to distinguish, the p + type contact layer 14 and the p-type base layer 15 may be collectively called the p-type base layer.

[0033] Also, on the back surface side of the n-type drift layer 1 of the semiconductor device 100, an n - type buffer layer 3 having a higher concentration of n-type impurity than the n-type drift layer 1 is provided. The n-type buffer layer 3 is provided to suppress the punch-through of the depletion layer extending from the p-type base layer 15 to the back surface side when the semiconductor device 100 is in the off state. The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) or proton (H - type buffer layer 3 having a higher concentration of n-type impurity than the n-type drift layer 1 is provided. The n-type buffer layer 3 is provided to suppress the punch-through of the depletion layer extending from the p-type base layer 15 to the back surface side when the semiconductor device 100 is in the off state. The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) or proton (H + ) and proton (H +It may be formed by injecting both of them. The concentration of the n-type impurity in the n-type buffer layer 3 is, for example, 1.0E+12 / cm 3 ~1.0E+18 / cm 3 is. Note that the semiconductor device 100 may have a configuration in which the n-type buffer layer 3 is not provided and an n - type drift layer 1 is provided in the region of the n-type buffer layer 3 shown in FIG. 4. The n-type buffer layer 3 and the n - type drift layer 1 may be collectively referred to as a drift layer.

[0034] On the back side of the n-type buffer layer 3 of the semiconductor device 100, a p-type collector layer 16 is provided. That is, the p-type collector layer 16 is provided between the n - type drift layer 1 and the back surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+16 / cm 3 ~1.0E+20 / cm 3 is. The p-type collector layer 16 constitutes the back surface of the semiconductor substrate. The p-type collector layer 16 may be provided as a p-type terminal collector layer 16a described later not only in the IGBT region 10 but also in the terminal region 30. Further, the p-type collector layer 16 may be provided so as to partially protrude from the IGBT region 10 to the diode region 20.

[0035] As shown in FIG. 4, in the IGBT region 10 of the semiconductor device 100, a trench is provided that penetrates the p-type base layer 15 from the front surface of the semiconductor substrate and reaches the n - type drift layer 1. By providing gate trench electrodes 11a in some of the trenches via gate trench insulating films 11b, an active trench gate 11 is formed. The gate trench electrode 11a faces the n - type drift layer 1 via the gate trench insulating film 11b. Also, by providing dummy trench electrodes 12a in some of the trenches via dummy trench insulating films 12b, a dummy trench gate 12 is formed. The dummy trench electrode 12a faces the n - type drift layer 1 via the dummy trench insulating film 12b.

[0036] The gate trench insulating film 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n + type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a of the active trench gate 11, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0037] As shown in FIG. 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is provided on the region where the interlayer insulating film 4 on the front surface of the semiconductor substrate is not provided and on the interlayer insulating film 4. The barrier metal 5 may be a conductor containing, for example, titanium (Ti), and specifically, may be titanium nitride, or may be TiSi obtained by alloying titanium and silicon (Si). As shown in FIG. 4, the barrier metal 5 is in ohmic contact with the n + type source layer 13, p + type contact layer 14 and the dummy trench electrode 12a, and is electrically connected to the n + type source layer 13, p + type contact layer 14 and the dummy trench electrode 12a. On the other hand, the barrier metal 5 is electrically insulated from the gate trench electrode 11a by the interlayer insulating film 4.

[0038] An emitter electrode 6, which is an electrode containing aluminum, is provided on the barrier metal 5. The emitter electrode 6 may be formed of, for example, an aluminum alloy such as an aluminum silicon alloy (Al—Si alloy), or may be an electrode composed of a plurality of metal films formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. Note that the emitter electrode 6 may be provided on the n + type source layer 13, p + type contact layer 14 and the dummy trench electrode 12a without providing the barrier metal 5. Also, n +The barrier metal 5 may be provided only on the n-type semiconductor layer such as the p-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as the emitter electrode.

[0039] In FIG. 4, a configuration is shown in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12. However, in the cross-sectional portion of FIG. 4, the interlayer insulating film 4 may be provided on the dummy trench electrode 12a of the dummy trench gate 12. In the cross-sectional portion of FIG. 4, when the interlayer insulating film 4 is provided on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross-sectional portion.

[0040] A collector electrode 7 is provided on the back side of the p-type collector layer 16. Similar to the emitter electrode 6, the collector electrode 7 may be composed of a plurality of layers of an aluminum alloy or an aluminum alloy and a plating film. The collector electrode 7 may have a configuration different from that of the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0041] FIG. 5 is a cross-sectional view taken along the chain double-dashed line B-B in FIG. 3 of the semiconductor device 100 and is a cross-sectional view of the IGBT region 10. Different from the cross-sectional portion taken along the chain double-dashed line A-A shown in FIG. 4, in the cross-sectional portion taken along the chain double-dashed line B-B in FIG. 5, there is no n + -type source layer 13 in contact with the active trench gate 11 and provided on the front side of the semiconductor substrate. That is, the n + -type source layer 13 shown in FIG. 3 is selectively provided on the front side of the p-type base layer. Here, the p-type base layer may include the p-type base layer 15 and the p + -type contact layer 14.

[0042] <Diode region 20> FIG. 6 is a partially enlarged plan view showing the configuration of the diode region 20 of the semiconductor device which is an RC-IGBT. Specifically, FIG. 6 is a view showing an enlarged view of the region surrounded by the broken line 83 in the semiconductor device 100 shown in FIGS. 1 and 2.

[0043] FIG. 7 and FIG. 8 are cross-sectional views showing the configuration of the diode region 20 of the semiconductor device that is an RC-IGBT. Specifically, FIG. 7 is a cross-sectional view taken along the dashed-dotted line C-C of the semiconductor device 100 shown in FIG. 6, and FIG. 8 is a cross-sectional view taken along the dashed-dotted line D-D of the semiconductor device 100 shown in FIG. 6.

[0044] The diode trench gate 21 extends from one end side to the opposite end side of the diode region 20 in the cell region along the front surface of the semiconductor device 100. The diode trench gate 21 is configured by providing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a faces the n - type drift layer 1 via the diode trench insulating film 21b.

[0045] Between two adjacent diode trench gates 21, a p + type contact layer 24a and a p-type anode layer 25 having a lower p-type impurity concentration than that are provided. The p + type contact layer 24a is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 . The p-type anode layer 25 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 . The p + type contact layer 24a and the p-type anode layer 25 are alternately provided in the longitudinal direction of the diode trench gate 21.

[0046] FIG. 7 is a cross-sectional view taken along the dashed-dotted line C-C in FIG. 6 of the semiconductor device 100 and is a cross-sectional view of the diode region 20. The semiconductor device 100 is an n made of a semiconductor substrate also in the diode region 20, similar to the IGBT region 10. -It has a drift layer 1 of the n-type. The n-type drift layer 1 of the diode region 20 and the n-type drift layer 1 of the IGBT region 10 are continuously and integrally formed and are formed on the same semiconductor substrate. - The n-type drift layer 1 of the diode region 20 and the n-type drift layer 1 of the IGBT region 10 are continuously and integrally formed and are formed on the same semiconductor substrate. - The n-type drift layer 1 of the diode region 20 and the n-type drift layer 1 of the IGBT region 10 are continuously and integrally formed and are formed on the same semiconductor substrate.

[0047] In FIG. 7, the range of the semiconductor substrate is from the p-type contact layer 24a to the n-type cathode layer 26. In FIG. 7, the upper end of the p-type contact layer 24a on the paper surface is called the front surface of the semiconductor substrate, and the lower end of the n-type cathode layer 26 on the paper surface is called the back surface of the semiconductor substrate. The front surface of the diode region 20 and the front surface of the IGBT region 10 are included in the same plane, and the back surface of the diode region 20 and the back surface of the IGBT region 10 are included in the same plane. + In FIG. 7, the range of the semiconductor substrate is from the p-type contact layer 24a to the n-type cathode layer 26. In FIG. 7, the upper end of the p-type contact layer 24a on the paper surface is called the front surface of the semiconductor substrate, and the lower end of the n-type cathode layer 26 on the paper surface is called the back surface of the semiconductor substrate. The front surface of the diode region 20 and the front surface of the IGBT region 10 are included in the same plane, and the back surface of the diode region 20 and the back surface of the IGBT region 10 are included in the same plane. + In FIG. 7, the range of the semiconductor substrate is from the p-type contact layer 24a to the n-type cathode layer 26. In FIG. 7, the upper end of the p-type contact layer 24a on the paper surface is called the front surface of the semiconductor substrate, and the lower end of the n-type cathode layer 26 on the paper surface is called the back surface of the semiconductor substrate. The front surface of the diode region 20 and the front surface of the IGBT region 10 are included in the same plane, and the back surface of the diode region 20 and the back surface of the IGBT region 10 are included in the same plane. + In FIG. 7, the upper end of the p-type contact layer 24a on the paper surface is called the front surface of the semiconductor substrate, and the lower end of the n-type cathode layer 26 on the paper surface is called the back surface of the semiconductor substrate. The front surface of the diode region 20 and the front surface of the IGBT region 10 are included in the same plane, and the back surface of the diode region 20 and the back surface of the IGBT region 10 are included in the same plane. + In FIG. 7, the upper end of the p-type contact layer 24a on the paper surface is called the front surface of the semiconductor substrate, and the lower end of the n-type cathode layer 26 on the paper surface is called the back surface of the semiconductor substrate. The front surface of the diode region 20 and the front surface of the IGBT region 10 are included in the same plane, and the back surface of the diode region 20 and the back surface of the IGBT region 10 are included in the same plane.

[0048] As shown in FIG. 7, in the diode region 20 as well as in the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the front surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the back surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 may have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily have to be provided in the IGBT region 10 and the diode region 20. For example, the n-type carrier accumulation layer 2 may be provided in the IGBT region 10 but not in the diode region 20. Also, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as the drift layer. - As shown in FIG. 7, in the diode region 20 as well as in the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the front surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the back surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 may have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily have to be provided in the IGBT region 10 and the diode region 20. For example, the n-type carrier accumulation layer 2 may be provided in the IGBT region 10 but not in the diode region 20. Also, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as the drift layer. - As shown in FIG. 7, in the diode region 20 as well as in the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the front surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the back surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 may have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily have to be provided in the IGBT region 10 and the diode region 20. For example, the n-type carrier accumulation layer 2 may be provided in the IGBT region 10 but not in the diode region 20. Also, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as the drift layer. - As shown in FIG. 7, in the diode region 20 as well as in the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the front surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the back surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 may have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily have to be provided in the IGBT region 10 and the diode region 20. For example, the n-type carrier accumulation layer 2 may be provided in the IGBT region 10 but not in the diode region 20. Also, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as the drift layer.

[0049] A p-type anode layer 25 is provided on the front surface side of the n-type carrier accumulation layer 2. In the example of FIG. 7, the p-type anode layer 25 is selectively and indirectly provided on the n-type drift layer 1 by the n-type carrier accumulation layer 2. - A p-type anode layer 25 is provided on the front surface side of the n-type carrier accumulation layer 2. In the example of FIG. 7, the p-type anode layer 25 is selectively and indirectly provided on the n-type drift layer 1 by the n-type carrier accumulation layer 2. -Alternatively, the p-type anode layer 25 may be provided directly on the n-type drift layer 1. - The p-type anode layer 25 is provided between the first drift layer 1 and the front surface. The p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously by making the concentration of p-type impurities in the p-type anode layer 25 the same as the concentration of p-type impurities in the p-type base layer 15 of the IGBT region 10. The concentration of p-type impurities in the p-type anode layer 25 may be made lower than the concentration of p-type impurities in the p-type base layer 15 of the IGBT region 10 to reduce the amount of holes injected into the diode region 20 during diode operation. Reducing the amount of holes injected during diode operation can reduce recovery loss during diode operation.

[0050] On the front surface side of the p-type anode layer 25, a first contact layer p + A contact layer 24a is provided. + The p-type contact layer 24a is provided on at least a portion of the p-type anode layer 25. + The concentration of the p-type impurity in the p-type contact layer 24a is + The concentration of the p-type impurity in the p-type contact layer 14 may be the same as or different from that in the p-type contact layer 14. + The p-type contact layer 24a constitutes the front surface of the semiconductor substrate. + The p-type contact layer 24a is a region having a higher concentration of p-type impurities than the p-type anode layer 25. + When it is necessary to distinguish between the p-type contact layer 24a and the p-type anode layer 25, they may be referred to individually. + The p-type contact layer 24a and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0051] The back surface side of the n-type buffer layer 3 of the semiconductor device 100 is + A type cathode layer 26 is provided. + The cathode layer 26 is - The n-type drift layer 1 is disposed between the rear surface. +The type - cathode layer 26 is a semiconductor layer having, for example, arsenic or phosphorus as an n - type impurity, and the concentration of the n - type impurity is, for example, 1.0E+16 / cm 3 ~1.0E+21 / cm 3 is. The n + - type cathode layer 26 is provided in part or all of the diode region 20. The n + - type cathode layer 26 constitutes the back surface of the semiconductor substrate. Although not shown, in part of the region where the n + - type cathode layer 26 is formed, a p - type impurity may be selectively implanted further to provide a p - type cathode layer which is a p - type semiconductor.

[0052] As shown in FIG. 7, in the diode region 20 of the semiconductor device 100, a trench is provided which penetrates the p - type anode layer 25 from the front surface of the semiconductor substrate and reaches the n - - type drift layer 1. By providing a diode - trench electrode 21a in the trench of the diode region 20 via a diode - trench insulating film 21b, a diode - trench gate 21 is formed. The diode - trench electrode 21a faces the n - - type drift layer 1 via the diode - trench insulating film 21b.

[0053] As shown in FIG. 7, a first silicon module 52 containing oxygen is provided between the p - type anode layer 25 and the emitter electrode 6. In the example of FIG. 7, the first silicon module 52 is provided in contact with the p + - type contact layer 24a and the emitter electrode 6. Also, a silicon layer 51 containing oxygen is provided between the p - type anode layer 25 and the emitter electrode 6, and in the example of FIG. 7, it is provided on the diode - trench electrode 21a and the p + - type contact layer 24a. The first silicon module 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51 and protrudes toward the emitter electrode 6.

[0054] Above the p-type anode layer 25 and on the silicon layer 51, an emitter electrode 6 is provided. The emitter electrode 6 provided in the diode region 20 is configured to be continuous with the emitter electrode 6 provided in the IGBT region 10. Note that, without providing the silicon layer 51, the diode trench electrode 21a and the p + type contact layer 24a may be in ohmic contact with the emitter electrode 6.

[0055] Note that, in FIG. 7, a configuration is shown in which the interlayer insulating film 4 as shown in FIG. 4 is not provided on the diode trench electrode 21a of the diode trench gate 21. However, in the cross-sectional portion of FIG. 7, the interlayer insulating film 4 may be provided on the diode trench electrode 21a. In the cross-sectional portion of FIG. 7, when the interlayer insulating film 4 is provided on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross-sectional portion.

[0056] n + On the back side of the n-type cathode layer 26, a collector electrode 7 is provided. Similar to the emitter electrode 6, the collector electrode 7 in the diode region 20 is configured to be continuous with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is in ohmic contact with the n + type cathode layer 26 and is electrically connected to the n + type cathode layer 26.

[0057] FIG. 8 is a cross-sectional view taken along the dashed-dotted line D-D in FIG. 6 of the semiconductor device 100 and is a cross-sectional view of the diode region 20. Different from the cross-sectional portion taken along the dashed-dotted line C-C shown in FIG. 7, in the cross-sectional portion taken along the dashed-dotted line D-D in FIG. 8, a p + type contact layer 24a is not provided between the p-type anode layer 25 and the silicon layer 51, and the p-type anode layer 25 is the front surface of the semiconductor substrate. That is, the p + type contact layer 24a shown in FIG. 7 is selectively provided on the front surface side of the p-type anode layer 25.

[0058] <Configuration of the boundary region between the IGBT region 10 and the diode region 20> FIG. 9 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 9 is a cross-sectional view taken along the dashed-dotted line E-E in the semiconductor device 100 shown in FIGS. 1 and 2.

[0059] As shown in FIG. 9, the p-type collector layer 16 provided on the back side of the IGBT region 10 and the n + type cathode layer 26 provided on the back side of the diode region 20 are adjacent to each other in the in-plane direction of the semiconductor substrate. And the p-type collector layer 16 is provided so as to protrude toward the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20.

[0060] In this way, by providing the p-type collector layer 16 to protrude into the diode region 20, the distance between the n + type cathode layer 26 of the diode region 20 and the active trench gate 11 can be increased. Therefore, even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, current flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n + type cathode layer 26 can be suppressed. The distance U1 may be, for example, 100 μm. Note that depending on the application of the semiconductor device 100 that is an RC-IGBT, the distance U1 may be zero or a distance smaller than 100 μm.

[0061] As shown in FIG. 9, the first silicon module 52 and the silicon layer 51 are also provided in the boundary region. The first silicon module 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51 and protrudes toward the emitter electrode 6.

[0062] <Terminal region 30> FIG. 10 and FIG. 11 are cross-sectional views showing the configuration of the termination region of the semiconductor device 100 which is an RC-IGBT. Specifically, FIG. 10 is a cross-sectional view taken along the dashed-dotted line F-F shown in FIGS. 1 and 2, and is a cross-sectional view from the IGBT region 10 to the termination region 30. Further, FIG. 11 is a cross-sectional view taken along the dashed-dotted line G-G shown in FIG. 1, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0063] As shown in FIGS. 10 and 11, the termination region 30 of the semiconductor device 100 has an n - -type drift layer 1 between the front surface and the back surface of the semiconductor substrate. The front surface and the back surface of the termination region 30 are included in the same plane as the front surface and the back surface of the IGBT region 10 and the diode region 20, respectively. Also, the n - -type drift layer 1 of the termination region 30 has the same configuration as the n - -type drift layers 1 of the IGBT region 10 and the diode region 20, respectively, and is continuously and integrally formed.

[0064] n - On the front surface side of the -type drift layer 1, that is, between the front surface of the semiconductor substrate and the n - -type drift layer 1, a p-type termination well layer 31 is selectively provided. The p-type termination well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+14 / cm 3 ~1.0E+19 / cm 3 . The p-type termination well layer 31 is provided so as to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a plurality of ring shapes, and the number of the p-type termination well layers 31 provided is appropriately selected according to the breakdown voltage design of the semiconductor device 100. Further, an n + -type channel stopper layer 32 is provided on the further outer edge side of the p-type termination well layer 31, and the n + -type channel stopper layer 32 surrounds the p-type termination well layer 31 in plan view.

[0065] The n -A p-type terminal collector layer 16a is provided between the type drift layer 1 and the back surface of the semiconductor substrate. The p-type terminal collector layer 16a is continuously and integrally formed with the p-type collector layer 16 provided in the IGBT region 10 of the cell region. Therefore, it may be called a p-type collector layer including the p-type terminal collector layer 16a.

[0066] In a configuration where the diode region 20 is provided adjacent to the terminal region 30 as in the semiconductor device 100 shown in FIG. 1, as shown in FIG. 11, the p-type terminal collector layer 16a has an end on the diode region 20 side protruding into the diode region 20 by a distance U2. According to such a configuration, the distance between the n + type cathode layer 26 and the p-type terminal well layer 31 can be increased, so that the operation of the p-type terminal well layer 31 as an anode of the diode can be suppressed. The distance U2 may be, for example, 100 μm.

[0067] A collector electrode 7 is provided on the back surface of the semiconductor substrate. The collector electrode 7 is continuously and integrally formed from the cell region including the IGBT region 10 and the diode region 20 to the terminal region 30.

[0068] On the front surface of the semiconductor substrate in the terminal region 30, an emitter electrode 6 continuous from the cell region and a terminal electrode 6a structurally separated from the emitter electrode 6 are provided. The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating Silicon Nitride). The terminal electrode 6a and the p-type terminal well layer 31 and n + type channel stopper layer 32 are each electrically connected via a contact hole of the interlayer insulating film 4 provided on the front surface of the terminal region 30. Further, in the terminal region 30, a terminal protection film 34 covering the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33 is provided. The terminal protection film 34 is, for example, polyimide.

[0069] As shown in Fig. 9, the first silicon module 52 and the silicon layer 51 are also provided in the boundary region. The first silicon module 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51 and protrudes into the emitter electrode 6. Note that the barrier metal 5 may not be provided in the IGBT region 10 or the like, similar to the diode region 20.

[0070] <Manufacturing method of RC-IGBT> Figs. 12 to 18 are cross-sectional views showing a method of manufacturing a semiconductor device that is an RC-IGBT. Figs. 12 to 16 are views showing steps mainly for forming the front surface side structure of the boundary region of Fig. 9 of the semiconductor device 100, and Figs. 17 and 18 are views showing steps mainly for forming the back surface side structure of the boundary region of Fig. 9 of the semiconductor device 100.

[0071] First, as shown in Fig. 12(a), an n - type semiconductor substrate constituting the drift layer 1 is prepared. The semiconductor substrate may be, for example, an FZ wafer manufactured by the FZ (Floating Zone) method or an MCZ wafer manufactured by the MCZ (Magnetic-field applied CZochralski) method, or may be an n-type wafer containing an n-type impurity. The concentration of the n-type impurity contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device to be manufactured. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurity is adjusted so that the resistivity of the n - type drift layer 1 constituting the semiconductor substrate is about 40 to 120 Ω·cm. As shown in Fig. 12(a), in the step of preparing the semiconductor substrate, the entire semiconductor substrate is an n - type drift layer 1. By implanting p-type or n-type impurity ions from the front surface side or the back surface side of such a semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment or the like, a p-type or n-type semiconductor layer is appropriately formed, and the semiconductor device 100 is manufactured.

[0072] As shown in Fig. 12(a), n -The semiconductor substrate constituting the type drift layer 1 has regions that will become the IGBT region 10 and the diode region 20. Although not shown, regions such as the termination region 30 are provided around the regions that will become the IGBT region 10 and the diode region 20. Hereinafter, the manufacturing method of the configurations of the IGBT region 10 and the diode region 20 of the semiconductor device 100 will be mainly described, but the termination region 30 and the like of the semiconductor device 100 may be fabricated by a well-known manufacturing method. For example, when forming an FLR having a p-type termination well layer 31 as a breakdown voltage holding structure in the termination region 30, p-type impurity ions may be implanted to form the FLR before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100. Alternatively, p-type impurity ions may be implanted simultaneously when implanting p-type impurities into the IGBT region 10 or the diode region 20 of the semiconductor device 100 to form the FLR.

[0073] Next, as shown in FIG. 12(b), n-type impurities such as phosphorus (P) are implanted from the front surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. Also, p-type impurities such as boron (B) are implanted from the front surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by diffusing impurity ions by heat treatment after implanting impurity ions into the semiconductor substrate. Since the ion implantation of the n-type impurities and the p-type impurities is performed after performing a mask treatment on the front surface of the semiconductor substrate, the various layers are selectively formed on the front surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to the p-type termination well layer 31 in the termination region 30.

[0074] The mask process is a process of forming a mask on a semiconductor substrate in order to apply a resist on the semiconductor substrate, form an opening in a predetermined region of the resist using photolithography technology, and perform ion implantation or etching on a predetermined region of the semiconductor substrate through the opening. By the above mask process and ion implantation, an n-type carrier accumulation layer 2, a p-type base layer 15, and a p-type anode layer 25 are selectively formed on the front side of the IGBT region 10 and the diode region 20. Similarly, a p-type termination well layer 31 is selectively formed in the termination region 30.

[0075] The p-type impurities of the p-type base layer 15 and the p-type anode layer 25 may be ion-implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 are the same as each other. Also, by ion-implanting the p-type impurities of the p-type base layer 15 and the p-type anode layer 25 separately by the mask process, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 may be made different from each other.

[0076] The p-type impurities of the p-type termination well layer 31 and the p-type anode layer 25 in the termination region 30 not shown in FIG. 12(b) may be ion-implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 are the same as each other. Alternatively, by ion-implanting the p-type impurities of the p-type termination well layer 31 and the p-type anode layer 25 separately by the mask process, the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 may be made different from each other. Alternatively, by using masks with different aperture ratios, the p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 can be made different from each other by simultaneously ion-implanting the p-type impurities. In this case, either one or both of the masks may be a mesh-shaped mask, and the aperture ratios of the masks may be made different.

[0077] Similarly, by using masks with different aperture ratios and simultaneously ion-implanting p-type impurities in the p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25, it is also possible to make the p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 different from each other. The p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be formed by simultaneously ion-implanting p-type impurities.

[0078] Next, as shown in FIG. 13(a), an n + -type source layer 13 is selectively formed on the front surface side of the p-type base layer 15 in the IGBT region 10 by mask processing and n-type impurity implantation. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Also, a p + -type contact layer 14 is selectively formed on the front surface side of the p-type base layer 15 in the IGBT region 10 by mask processing and p-type impurity implantation, and a p + -type contact layer 24a is selectively formed on the front surface side of the p-type anode layer 25 in the diode region 20. The p-type impurity to be implanted may be, for example, boron (B) or aluminum (Al), etc.

[0079] Next, as shown in FIG. 13(b), a trench 8 is formed that penetrates the p-type base layer 15 and the p-type anode layer 25 from the front surface side of the semiconductor substrate and reaches the n - -type drift layer 1. In the IGBT region 10, the side wall of the trench 8 that penetrates the n + -type source layer 13 includes a part of the n + -type source layer 13. In the IGBT region 10, the side wall of the trench 8 that penetrates the p + -type contact layer 14 includes a part of the p + -type contact layer 14. In the diode region 20, the side wall of the trench 8 that penetrates the p + -type contact layer 24a includes a part of the p + -type contact layer 24a.

[0080] For example, after depositing an oxide film such as SiO2 on a semiconductor substrate, an opening is formed in the oxide film of the portion where the trench 8 is to be formed by mask processing, and the semiconductor substrate is etched using the oxide film with the opening as a mask to form the trench 8. In FIG. 13(b), the pitch of the trench 8 is made the same in the IGBT region 10 and the diode region 20, but the pitch of the trench 8 may be made different between the IGBT region 10 and the diode region 20. The pitch of the trench 8 and the pattern in a plan view can be appropriately changed by the mask pattern of the mask processing.

[0081] Next, as shown in FIG. 14(a), the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner wall of the trench 8 and the front surface of the semiconductor substrate. The oxide film 9 formed in the trench 8 of the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. Also, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the front surface of the semiconductor substrate is removed in a later process except for the portion formed in the trench 8.

[0082] Next, as shown in FIG. 14(b), polysilicon doped with n-type or p-type impurities is deposited on the oxide film 9 in the trench 8 by CVD (chemical vapor deposition) or the like to form the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0083] Next, as shown in FIG. 15(a), an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10. The interlayer insulating film 4 may be, for example, SiO2. By performing mask processing to form contact holes in the insulating film that becomes the deposited interlayer insulating film 4 and to remove the oxide film 9 formed on the front surface of the semiconductor substrate, the interlayer insulating film 4 in FIG. 15(a) and the like are formed. The contact holes in the interlayer insulating film 4 are on the n + -type source layer 13, p +On the type contact layer 14, p + It is formed on the type contact layer 24a, on the dummy trench electrode 12a, and on the diode trench electrode 21a.

[0084] Next, as shown in Fig. 15(b), a barrier metal 5 is formed on the front surface of the semiconductor substrate of the IGBT region 10 and on the interlayer insulating film 4, and a silicon layer 51 containing oxygen is formed on the front surface of the semiconductor substrate of the diode region 20. The barrier metal 5 is formed by depositing titanium nitride by PVD (physical vapor deposition) or CVD. The silicon layer 51 is formed by plasma treatment or WET treatment in an atmosphere containing oxygen. The oxygen density of the silicon layer 51 thus formed is lower than that of a silicon layer formed by thermal diffusion or CVD. The oxygen density of the silicon layer 51 can be adjusted according to the oxygen concentration in the atmosphere during the process and the type of process for forming the silicon layer 51. Note that the thickness of the silicon layer 51 is preferably set to be half or less of the height of the first silicon module 52 to be formed in the next step.

[0085] Next, by performing sputtering of aluminum silicon (for example, an aluminum silicon alloy), as shown in Fig. 16(a), a conductive film 6b containing silicon and aluminum is formed on the barrier metal 5 and the silicon layer 51. By adjusting the growth temperature of this sputtering, while forming the conductive film 6b, a first silicon module 52 containing oxygen is formed between the p-type anode layer 25 and the conductive film 6b. The higher the growth temperature of the sputtering, the easier it is for the first silicon module 52 to be generated at the silicon substrate interface, the easier it is for interdiffusion to occur between the aluminum silicon and the silicon layer 51, and the easier it is for an alloy spike (that is, an aluminum spike) to be formed. Therefore, the growth temperature of the sputtering is appropriately set in consideration of these factors. Note that since interdiffusion also occurs between the first silicon module 52 and aluminum, the first silicon module 52 usually contains aluminum and has p-type conductivity.

[0086] Note that by adjusting the flow rate of the sputtering atmosphere gas (such as argon gas or hydrogen gas), oxygen on the surface of the silicon layer 51 is reduced, and oxygen is incorporated into the aluminum silicon of the first silicon module 52. From the above, by adjusting the processing temperature and processing atmosphere of sputtering, the oxygen concentration contained in the first silicon module 52 can be adjusted.

[0087] In the first embodiment, the first silicon module 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51. However, the silicon layer 51 does not necessarily need to remain and may be removed as necessary, for example, after the formation of the first silicon module 52.

[0088] Next, although specific patterning is not shown in FIG. 16(b), the emitter electrode 6 is formed by patterning the conductive film 6b by etching or the like.

[0089] Next, as shown in FIG. 17(a), the back side of the semiconductor substrate is ground to thin the semiconductor substrate to a designed predetermined thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0090] Next, as shown in FIG. 17(b), an n-type impurity is implanted from the back side of the semiconductor substrate to form an n-type buffer layer 3. Further, a p-type impurity is implanted from the back side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, the termination region 30, etc., or may be formed only in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) ions or protons (H +) may be formed by implanting, or may be formed by implanting both protons and phosphorus. Protons can be implanted from the back surface of the semiconductor substrate to a deep position at a relatively low acceleration energy. Also, by changing the acceleration energy, the depth at which protons are implanted can be changed relatively easily. Therefore, when forming the n-type buffer layer 3 with protons, if implantation is performed multiple times while changing the acceleration energy, an n-type buffer layer 3 thicker in the thickness direction of the semiconductor substrate than when formed with phosphorus can be formed.

[0091] Also, since phosphorus can have a higher activation rate as an n-type impurity compared to protons, if the n-type buffer layer 3 is formed with phosphorus, punch-through of the depletion layer can be suppressed even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus. In this case, the protons are implanted to a deeper position from the back surface than the phosphorus.

[0092] The p-type collector layer 16 may be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the back surface side of the semiconductor substrate, the back surface is irradiated with a laser for laser annealing, whereby the implanted boron is activated and the p-type collector layer 16 is formed. At this time, the phosphorus implanted to a relatively shallow position from the back surface of the semiconductor substrate is also simultaneously activated. On the other hand, since protons are activated at a relatively low annealing temperature such as 350°C to 500°C, it is necessary to pay attention so that the entire semiconductor substrate does not reach a temperature higher than 350°C to 500°C except for the process for activating protons after proton implantation. Since laser annealing can heat only the vicinity of the back surface of the semiconductor substrate to a high temperature, it can be used for activating n-type and p-type impurities even after proton implantation.

[0093] Next, as shown in Fig. 18(a), an n + type cathode layer 26 is formed on the back surface side of the diode region 20. n +The p-type cathode layer 26 may be formed, for example, by implanting arsenic (As), phosphorus (P), or the like. As shown in FIG. 18(a), at a position at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20 side, the boundary between the p-type collector layer 16 and the n + -type cathode layer 26 is located, and n-type impurities are selectively implanted from the back side by a masking process. The n + implantation amount of the n-type impurities for forming the n-type cathode layer 26 is larger than the implantation amount of the p-type impurities for forming the p-type collector layer 16. In FIG. 18(a), the depths of the p-type collector layer 16 and the n + -type cathode layer 26 from the back side are shown to be the same, but the depth of the n + -type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. In the region where the n + -type cathode layer 26 is formed, since it is necessary to implant n-type impurities into the region where p-type impurities have been implanted and finally make it n-type, the concentration of the n-type impurities is higher than the concentration of the p-type impurities implanted throughout the region where the n + -type cathode layer 26 is formed.

[0094] Next, as shown in FIG. 18(b), a collector electrode 7 is formed on the back surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the back surface of the IGBT region 10, the diode region 20, the termination region 30, and the like on the back surface. Also, the collector electrode 7 may be formed over the entire back surface of the n-type wafer which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum-silicon alloy (Al-Si based alloy), titanium (Ti), or the like by PVD such as sputtering or evaporation, or may be formed by laminating a plurality of metals such as an aluminum-silicon alloy, titanium, nickel, or gold. Further, the collector electrode 7 may be formed by further forming a metal film by electroless plating or electroplating on the metal film formed by PVD.

[0095] The semiconductor device 100 is fabricated through the above-described processes. A plurality of semiconductor devices 100 are fabricated in an integrated state in a matrix on a semiconductor substrate such as a single n-type wafer. Therefore, the semiconductor devices 100 are individually separated by laser dicing or blade dicing.

[0096] FIG. 19 is a flowchart showing the main processes for forming the structure on the front side of the semiconductor device among the manufacturing methods of the semiconductor device described above. In step S1, by performing the processes of FIGS. 12 to 14 and FIG. 15(a), an n - type drift layer 1 and a p-type anode layer 25 are included, and a semiconductor substrate provided with an interlayer insulating film 4 having contact holes is prepared. In step S2, by performing the process of FIG. 15(b), a silicon layer 51 containing oxygen is formed. In step S3, by performing the process of FIG. 16(a), that is, sputtering of aluminum silicon, a conductive film 6b containing silicon and aluminum is formed while forming a first silicon module 52 containing oxygen. In step S4, by performing the process of FIG. 16(b), the conductive film 6b is patterned to form an emitter electrode 6. Note that the conductive film 6b, that is, the emitter electrode 6 may be a single-layer film or a multi-layer film. Through the above, the structure on the front side of the semiconductor device is formed.

[0097] <Summary of Embodiment 1> According to the semiconductor device according to the first embodiment as described above, a first silicon module 52 containing oxygen is provided between the p-type anode layer 25 and the emitter electrode 6. According to such a configuration, the first silicon module 52 can suppress the mutual diffusion between the silicon of the p-type anode layer 25 and the aluminum of the emitter electrode 6, so that variations in the diffusion profile of the p-type anode layer 25 can be suppressed. Further, by adjusting the oxygen contained in the first silicon module 52, the resistance value of the first silicon module 52 can be adjusted, and as a result, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted. In addition, the first silicon module 52 can suppress alloy spikes.

[0098] In Embodiment 1 as well, the first silicon module 52 penetrates the silicon layer 51 in the thickness direction of the silicon layer 51. According to such a configuration, the oxygen contained in the first silicon module 52 can be easily adjusted by the silicon layer 51, and the resistance between the emitter electrode 6 and the p-type anode layer 25 can be easily adjusted.

[0099] In Embodiment 1 as well, the first silicon module 52 protrudes toward the emitter electrode 6. According to such a configuration, since the contact area between the first silicon module 52 and the emitter electrode 6 can be increased, the contact resistance can be lowered.

[0100] <Embodiment 2> FIG. 20 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 2.

[0101] In Embodiment 2, the plurality of first silicon modules 52 include first silicon modules 52a and 52b having different particle sizes. As an example, the particle size of the first silicon module 52a located at the grain boundary 6c of the emitter electrode 6 is larger than the particle size of the first silicon module 52b located outside the grain boundary 6c. Further, the oxygen concentration of the first silicon module 52a located at the grain boundary 6c of the emitter electrode 6 is larger than the oxygen concentration of the first silicon module 52b located outside the grain boundary 6c.

[0102] Note that the particle size of the emitter electrode 6 is equal to or less than the thickness of the emitter electrode 6. Further, the emitter electrode 6 may be a single-layer film or a multi-layer film as in Embodiment 1.

[0103] Next, the manufacturing method will be described. By adjusting the temperature of step S3 in FIG. 19 (i.e., sputtering for forming the conductive film 6b or the like), the particle sizes of the plurality of first silicon nodules 52 between the emitter electrode 6 and the p-type anode layer 25 are adjusted to be approximately the same. When heat treatment is performed after the step of step S3 in FIG. 19 and the temperature and time of the heat treatment are adjusted, the movement of the first silicon nodules 52 along the grain boundaries 6c of the emitter electrode 6 is promoted. As a result, the particle size of the first silicon nodule 52a located at the grain boundary 6c of the emitter electrode 6 becomes larger than the particle size of the first silicon nodule 52b located outside the grain boundary 6c. Further, when the treatment atmosphere, temperature, and time of the heat treatment after the step of step S3 in FIG. 19 are adjusted, the movement of the first silicon nodules 52 and oxygen along the grain boundary 6c of the emitter electrode 6 is promoted.

[0104] FIG. 21 is a diagram showing the results of analyzing and evaluating the oxygen concentration of a first silicon nodule or the like by EDS (Energy Dispersive X-ray Spectroscopy) in a typical structure using the above manufacturing method according to the second embodiment. The unit of the numerical value is atm%. As can be seen from this result, according to the above manufacturing method, the oxygen concentration of the first silicon nodule 52a located at the grain boundary 6c of the emitter electrode 6 becomes larger than the oxygen concentration of the first silicon nodule 52b located outside the grain boundary 6c.

[0105] <Summary of Embodiment 2> According to the semiconductor device according to the second embodiment as described above, since the particle sizes of the plurality of first silicon nodules 52 are different, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be accurately adjusted.

[0106] Also, in the second embodiment, the particle size of the first silicon nodule 52a located at the grain boundary 6c of the emitter electrode 6 is larger than the particle size of the first silicon nodule 52b located outside the grain boundary 6c. According to such a configuration, by adjusting the grain boundary 6c of the emitter electrode 6, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted.

[0107] Also, in Embodiment 2, the oxygen concentration of the first silicon module 52a located at the grain boundary 6c of the emitter electrode 6 is higher than the oxygen concentration of the first silicon module 52b located outside the grain boundary 6c. According to such a configuration, by adjusting the grain boundary 6c of the emitter electrode 6, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted.

[0108] <Embodiment 3> FIG. 22 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 3.

[0109] In Embodiment 3, the particle size of the emitter electrode 6 is larger than the thickness of the emitter electrode 6, and the upper portions of some grain boundaries 6c of the emitter electrode 6 are cut off at the upper surface of the emitter electrode 6. Embodiment 3 is the same as Embodiment 2 except for this point. Such a configuration can be realized by adjusting the temperature and time of step S3 in FIG. 19 (that is, sputtering for forming the conductive film 6b, etc.) to adjust the particle size and thickness of the emitter electrode 6.

[0110] According to the semiconductor device according to Embodiment 3, since the particle size of the emitter electrode 6 is larger than the thickness of the emitter electrode 6, the component in the lateral direction among the extending directions of the grain boundaries 6c can be reduced, and the component in the longitudinal direction can be increased. As a result, the movement of the first silicon module 52 along the grain boundary 6c of the emitter electrode 6 can be promoted, so that the particle size of the first silicon module 52a located at the grain boundary 6c of the emitter electrode 6 can be easily increased.

[0111] <Embodiment 4> FIG. 23 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 4.

[0112] In the semiconductor device described so far, the barrier metal 5 was not provided in the diode region 20. In contrast, in the semiconductor device according to the fourth embodiment, instead of the silicon layer 51, a barrier metal 5 that makes ohmic contact with the diode trench electrode 21a and the p + -type contact layer 24a is provided between the p-type anode layer 25 and the emitter electrode 6. And the first silicon module 52 penetrates the barrier metal 5 in the thickness direction of the barrier metal 5.

[0113] Next, the manufacturing method will be described. First, when forming the barrier metal 5 in the IGBT region 10, the barrier metal 5 is also formed in the diode region 20. Next, holes reaching the semiconductor substrate surface are formed in the barrier metal 5 in the diode region 20 by performing an etching process or the like. Then, by performing step S3 in FIG. 19 (that is, sputtering for forming the conductive film 6b, etc.), the first silicon module 52 is formed from the surface of the semiconductor substrate (the p + -type contact layer 24a in the example of FIG. 23) exposed from the hole of the barrier metal 5.

[0114] According to the semiconductor device according to the fourth embodiment, the first silicon module 52 penetrates the barrier metal 5 in the thickness direction of the barrier metal 5. According to such a configuration, even if the barrier metal 5 is provided in the diode region 20, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be adjusted.

[0115] <Embodiment 5> FIG. 24 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to the fifth embodiment.

[0116] In the fifth embodiment, similar to the first embodiment, a diode region 20 including a p-type anode layer 25 and functioning as a diode, and provided with a diode trench gate 21, is defined in the semiconductor substrate. And in the fifth embodiment, in a cross-section along the width direction of the diode trench gate 21, p +A p-type contact layer 24a is partially provided on the p-type anode layer 25. The width direction of the diode trench gate 21 is substantially perpendicular to the extension direction of the diode trench gate 21 (the direction from the front side to the back side of the paper in FIG. 24).

[0117] In the fifth embodiment, p + The ratio of the first silicon nodules 52 per unit area in the p-type anode layer 25 exposed from the p-type contact layer 24a is + The ratio of the first silicon nodules 52 per unit area in the contact layer 24a is larger than that in the contact layer 24b. + It is the ratio of the area or number of the first silicon nodules 52 provided between the p-type anode layer 25 exposed from the p-type contact layer 24a and the emitter electrode 6 to the area of ​​the p-type anode layer 25 in a plan view. + The area or number of the first silicon nodules 52 provided between the contact layer 24a and the emitter electrode 6 in a plan view is + This is a ratio with respect to the area of ​​the mold contact layer 24a in a plan view.

[0118] In addition, the above configuration is p + The mask pattern for forming the contact layer 24a is adjusted to + The p-type contact layer 24a is formed by appropriately selecting the p-type impurity.

[0119] According to the semiconductor device of the fifth embodiment, in a cross section along the width direction of the diode trench gate 21, + The p-type contact layer 24a is partially provided on the p-type anode layer 25. + In this way, the resistance between the emitter electrode 6 and the p-type anode layer 25 in the region where the type contact layer 24a is not provided can be adjusted.

[0120] In the fifth embodiment, p +The ratio per unit area of the first silicon module 52 in the p-type anode layer 25 exposed from the p-type contact layer 24a is p + larger than the ratio per unit area of the first silicon module 52 in the p-type contact layer 24a. According to such a configuration, in a region of the p-type anode layer 25 where the p + type contact layer 24a is not provided, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be reduced.

[0121] <Embodiment 6> FIG. 25 is a cross-sectional view showing the configuration of a boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 6 of the present invention.

[0122] The semiconductor substrate according to Embodiment 6 of the present invention further includes an n + type impurity layer 53 provided partially on the p-type anode layer 25. The n + type impurity layer 53 in the example of FIG. 25 is partially provided on the p-type anode layer 25 in a cross section along the width direction of the diode trench gate 21, similar to the p + type contact layer 24a. Note that the n + type impurity layer 53 may have the same concentration as or a different concentration from the n + type source layer 13.

[0123] In Embodiment 6 of the present invention, the ratio per unit area of the first silicon module 52 in the n + type impurity layer 53 is larger than the ratio per unit area of the first silicon module 52 in the p-type anode layer 25 exposed from the n + type impurity layer 53. Note that the former ratio is the ratio of the area or the number of the first silicon modules 52 provided between the n + type impurity layer 53 and the emitter electrode 6 in a plan view of the n + type impurity layer 53 to the area of the n +It is the ratio of the area or the number in a plan view of the first silicon module 52 provided between the p-type anode layer 25 exposed from the n-type impurity layer 53 and the emitter electrode 6 to the area of the p-type anode layer 25 in a plan view. n + The p-type anode layer 25 exposed from the n-type impurity layer 53 may or may not include the p + type contact layer 24.

[0124] Note that the above configuration is obtained by adjusting the mask pattern when forming the n + type impurity layer 53 and appropriately selecting the n-type impurities of the n + type impurity layer 53.

[0125] According to the semiconductor device according to the sixth embodiment as described above, the semiconductor substrate further includes an n + type impurity layer 53 partially provided on the p-type anode layer. According to such a configuration, according to such a configuration, n + the resistance between the emitter electrode 6 and the p-type anode layer 25 in the region where the n-type impurity layer 53 is provided can be adjusted.

[0126] Also, in the sixth embodiment, n + the ratio per unit area of the first silicon module 52 in the n-type impurity layer 53 is larger than the ratio per unit area of the first silicon module 52 in the p-type anode layer 25 exposed from the n-type impurity layer 53. According to such a configuration, n + in the region where the n-type impurity layer 53 is provided, the resistance between the emitter electrode 6 and the p-type anode layer 25 can be reduced. +

[0127] <Embodiment 7> FIG. 26 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to the seventh embodiment.

[0128] In Embodiment 7, similar to Embodiment 1, a p-type anode layer 25 is included to function as a diode, and a diode region 20 provided with a diode trench gate 21 and an IGBT region 10 that functions as an IGBT and is provided with a trench gate are defined on a semiconductor substrate. Here, the trench gate mentioned here may be an active trench gate 11 or a dummy trench gate 12.

[0129] Here, usually, the first silicon module 52 is not provided on the diode trench gate 21. Considering this, in the semiconductor device according to Embodiment 7, the interval between the diode trench gates 21 is larger than the interval between the trench gates, and the number of the diode trench gates 21 is reduced. According to such a configuration, the number of the first silicon modules 52 provided in the diode region 20 can be increased, so that the resistance between the emitter electrode 6 and the p-type anode layer 25 can be reduced.

[0130] <Embodiment 8> FIG. 27 is a cross-sectional view showing the configuration of a boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 8.

[0131] The semiconductor substrate according to Embodiment 8 further includes an n-type Schottky layer 54 Schottky-connected to the emitter electrode 6. In FIG. 27, the n-type Schottky layer 54 is directly provided on the n - type drift layer 1, but it may be indirectly provided on the n - type drift layer 1. And in Embodiment 8, a second silicon module 55 containing oxygen is provided between the n-type Schottky layer 54 and the emitter electrode 6.

[0132] According to such a semiconductor device according to Embodiment 8, the characteristics of the Schottky junction can be adjusted by the second silicon module 55 containing oxygen.

[0133] <Embodiment 9> FIG. 28 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 9.

[0134] In the previous description, the diode region 20 that includes the p-type anode layer 25 and functions as a diode, and in which the diode trench gate 21 is provided, was defined on the semiconductor substrate. In contrast, in Embodiment 9, the diode region 20 that includes the p-type anode layer 25 and functions as a diode, but in which the diode trench gate 21 is not provided, is defined on the semiconductor substrate. According to such a semiconductor device according to Embodiment 9, since there is no step due to the diode trench gate 21, the first silicon module 52 can be stably formed.

[0135] <Embodiment 10> FIG. 29 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 10.

[0136] In Embodiment 10, the p-type anode layer 25 is provided on the n - -type drift layer of the diode region 20, and the p + -type contact layer 24 is not provided. Embodiment 10 is the same as Embodiment 9 except for this point. According to such a configuration, similarly to Embodiment 1, the mutual diffusion between the silicon of the p-type anode layer 25 and the aluminum of the emitter electrode 6 can be suppressed, and the alloy spike can be suppressed by the first silicon module 52.

[0137] <Embodiment 11> FIG. 30 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of the semiconductor device according to Embodiment 11.

[0138] In Embodiment 11, similar to Embodiment 1, a diode region 20 that includes a p-type anode layer 25 and functions as a diode, and an IGBT region 10 that functions as an IGBT are defined on a semiconductor substrate. And the semiconductor substrate according to Embodiment 11, similar to the semiconductor substrate according to Embodiment 1, includes a p-type base layer 15 that is a base layer, and an n + type source layer 13 and a p + type contact layer 14 that is a second contact layer.

[0139] Also in Embodiment 11, similar to Embodiment 1, an emitter electrode 6 is provided above the p-type anode layer 25 and above at least one of the p-type base layer 15, the n + type source layer 13, and the p + type contact layer 14. And in Embodiment 11, a third silicon module 56 containing oxygen is provided between at least one of the above layers and the emitter electrode 6. Note that the third silicon module 56 may also be provided in the IGBT region 10 in FIGS. 4 and 5.

[0140] According to such a semiconductor device according to Embodiment 11, the resistance between at least one of the above layers and the emitter electrode 6 in the IGBT region 10 can be adjusted by the third silicon module 56 containing oxygen.

[0141] <Modification Example> The semiconductor devices according to Embodiments 1 to 6, 8 to 10 were RC-IGBTs in which an IGBT region 10 and a diode region 20 were defined, but it may also be a single diode having a diode region 20 without having an IGBT region 10. Also, a silicon layer 51 was provided in some of Embodiments 1 to 11, but the silicon layer 51 may not be provided.

[0142] Note that each embodiment and each modification example can be freely combined, or each embodiment and each modification example can be appropriately modified or omitted.

[0143] Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0144] (Appendix 1) A semiconductor substrate including a drift layer of a first conductivity type and an anode layer of a second conductivity type provided on at least a part of the drift layer, An electrode containing aluminum provided above the anode layer, A first silicon module containing oxygen provided between the anode layer and the electrode A semiconductor device comprising the same.

[0145] (Appendix 2) The semiconductor device according to Appendix 1, wherein the semiconductor substrate further includes a first contact layer of the second conductivity type provided on at least a part of the anode layer and having a higher impurity concentration of the second conductivity type than the anode layer.

[0146] (Appendix 3) The semiconductor device according to Appendix 1 or Appendix 2, further comprising a silicon layer containing oxygen provided between the anode layer and the electrode, wherein the first silicon module penetrates the silicon layer in the thickness direction of the silicon layer.

[0147] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein the first silicon module protrudes toward the electrode.

[0148] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, wherein the particle sizes of a plurality of the first silicon modules are different.

[0149] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 5, A semiconductor device in which the particle size of the first silicon module located at the grain boundary of the electrode is larger than the particle size of the first silicon module located outside the grain boundary.

[0150] (Appendix 7) A semiconductor device according to any one of Appendices 1 to 5, A semiconductor device in which the oxygen concentration of the first silicon module located at the grain boundary of the electrode is higher than the oxygen concentration of the first silicon module located outside the grain boundary.

[0151] (Appendix 8) A semiconductor device according to any one of Appendices 1 to 7, A semiconductor device in which the particle size of the electrode is larger than the thickness of the electrode.

[0152] (Appendix 9) A semiconductor device according to Appendix 1 or Appendix 2, Further comprising a barrier metal provided between the anode layer and the electrode, A semiconductor device in which the first silicon module penetrates the barrier metal in the thickness direction of the barrier metal.

[0153] (Appendix 10) A semiconductor device according to any one of Appendices 2 to 9, Functioning as a diode including the anode layer, a diode region provided with a diode trench gate is defined on the semiconductor substrate, A semiconductor device in which the first contact layer is partially provided on the anode layer in a cross section along the width direction of the diode trench gate.

[0154] (Appendix 11) A semiconductor device according to Appendix 10, A semiconductor device in which the ratio per unit area of the first silicon module provided between the anode layer exposed from the first contact layer and the electrode is larger than the ratio per unit area of the first silicon module provided between the first contact layer and the electrode.

[0155] (Appendix 12) A semiconductor device according to any one of Appendices 1 to 11, wherein the semiconductor substrate further includes an impurity layer of the first conductivity type partially provided on the anode layer.

[0156] (Appendix 13) A semiconductor device according to Appendix 12, wherein the ratio per unit area of the first silicon module provided between the impurity layer and the electrode is larger than the ratio per unit area of the first silicon module provided between the anode layer exposed from the impurity layer and the electrode.

[0157] (Appendix 14) A semiconductor device according to any one of Appendices 1 to 13, wherein a diode region that functions as a diode including the anode layer and is provided with diode trench gates, and an IGBT region that functions as an IGBT and is provided with trench gates are defined on the semiconductor substrate, and the distance between the diode trench gates is larger than the distance between the trench gates.

[0158] (Appendix 15) A semiconductor device according to any one of Appendices 1 to 14, wherein the semiconductor substrate further includes a Schottky layer of the first conductivity type selectively provided on the drift layer and Schottky-connected to the electrode, and further includes a second silicon module containing oxygen provided between the Schottky layer and the electrode.

[0159] (Appendix 16) A semiconductor device according to any one of Appendices 1 to 13, wherein a diode region that functions as a diode including the anode layer and in which a diode trench gate is not provided is defined on the semiconductor substrate.

[0160] (Appendix 17) A semiconductor device according to any one of Appendices 1 to 13, wherein a diode region that functions as a diode including the anode layer and an IGBT region that functions as an IGBT are defined on the semiconductor substrate, the semiconductor substrate further includes a base layer of the second conductivity type selectively provided on the drift layer of the IGBT region, an emitter layer of the first conductivity type selectively provided on the base layer, and a second contact layer of the second conductivity type having a higher impurity concentration of the second conductivity type than the base layer, and the electrode is provided above the anode layer and above at least one of the base layer, the emitter layer, and the second contact layer, and further includes a third silicon module containing oxygen provided between the at least one layer and the electrode.

[0161] (Appendix 18) A step of preparing a semiconductor substrate including a drift layer of the first conductivity type and an anode layer of the second conductivity type provided on at least a part of the drift layer, a step of forming a silicon layer containing oxygen on the upper surface of the semiconductor substrate, a step of forming a conductive film containing silicon and aluminum on the silicon layer and forming a first silicon module containing oxygen between the anode layer and the conductive film, a step of forming an electrode by patterning the conductive film, and a method for manufacturing a semiconductor device.

Explanation of Symbols

[0162] 1 n - type drift layer, 5 barrier metal, 6 emitter electrode, 6b conductive film, 6c grain boundary, 10 IGBT region, 11 active trench gate, 12 dummy trench gate, 13 n + type source layer, 14 p + type contact layer, 15 p-type base layer, 20 diode region, 21 diode trench gate, 24a p + type contact layer, 25 p-type anode layer, 51 silicon layer, 52, 52a, 52b first silicon module, 53 n + type impurity layer, 54 Schottky layer, 55 second silicon module, 56 third silicon module.

Claims

1. A semiconductor substrate including a drift layer of a first conductivity type and a second conductivity type anode layer provided on at least a part of the drift layer, An electrode containing aluminum provided above the anode layer, A first silicon module containing oxygen provided between the anode layer and the electrode A semiconductor device comprising.

2. The semiconductor device according to claim 1, The semiconductor substrate is provided on at least a part of the anode layer, and further includes a first contact layer of the second conductivity type in which the impurity concentration of the second conductivity type is higher than that of the anode layer. A semiconductor device.

3. The semiconductor device according to claim 1 or claim 2, A silicon layer containing oxygen is further provided between the anode layer and the electrode, The first silicon module penetrates the silicon layer in the thickness direction of the silicon layer. A semiconductor device.

4. The semiconductor device according to claim 1 or claim 2, The first silicon module protrudes from the electrode. A semiconductor device.

5. The semiconductor device according to claim 1 or claim 2, The particle sizes of the plurality of first silicon modules are different. A semiconductor device.

6. The semiconductor device according to claim 1 or claim 2, The particle size of the first silicon module located at the grain boundary of the electrode is larger than the particle size of the first silicon module located outside the grain boundary. A semiconductor device.

7. The semiconductor device according to claim 1 or claim 2, The oxygen concentration of the first silicon module located at the grain boundary of the electrode is higher than the oxygen concentration of the first silicon module located outside the grain boundary. A semiconductor device.

8. The semiconductor device according to claim 1 or claim 2, The particle size of the electrode is larger than the thickness of the electrode. A semiconductor device.

9. The semiconductor device according to claim 1 or claim 2, A barrier metal provided between the anode layer and the electrode is further provided, The first silicon module penetrates the barrier metal in the thickness direction of the barrier metal. A semiconductor device.

10. The semiconductor device according to claim 2, Functioning as a diode including the anode layer, a diode region provided with a diode trench gate is defined in the semiconductor substrate, A semiconductor device in which, in a cross section along the width direction of the diode trench gate, the first contact layer is partially provided on the anode layer.

11. The semiconductor device according to claim 10, wherein a ratio per unit area of the first silicon module provided between the anode layer exposed from the first contact layer and the electrode is larger than a ratio per unit area of the first silicon module provided between the first contact layer and the electrode.

12. The semiconductor device according to claim 1 or claim 2, wherein the semiconductor substrate further includes an impurity layer of the first conductivity type partially provided on the anode layer.

13. The semiconductor device according to claim 12, wherein a ratio per unit area of the first silicon module provided between the impurity layer and the electrode is larger than a ratio per unit area of the first silicon module provided between the anode layer exposed from the impurity layer and the electrode.

14. The semiconductor device according to claim 1 or claim 2, wherein a diode region that functions as a diode including the anode layer and is provided with a diode trench gate and an IGBT region that functions as an IGBT and is provided with a trench gate are defined on the semiconductor substrate, and a distance between the diode trench gates is larger than a distance between the trench gates.

15. The semiconductor device according to claim 1 or claim 2, wherein the semiconductor substrate further includes a Schottky layer of the first conductivity type selectively provided on the drift layer and Schottky-connected to the electrode, and further includes a second silicon module containing oxygen provided between the Schottky layer and the electrode.

16. The semiconductor device according to claim 1 or claim 2, wherein a diode region that functions as a diode including the anode layer and is not provided with a diode trench gate is defined on the semiconductor substrate.

17. The semiconductor device according to claim 1 or claim 2, wherein a diode region that functions as a diode including the anode layer and an IGBT region that functions as an IGBT are defined on the semiconductor substrate, wherein the semiconductor substrate is the base layer of the second conductivity type selectively provided on the drift layer of the IGBT region; the emitter layer of the first conductivity type selectively provided on the base layer, and the second contact layer of the second conductivity type having a higher impurity concentration of the second conductivity type than the base layer further comprising; the electrode is provided above the anode layer and above at least one of the base layer, the emitter layer, and the second contact layer; a semiconductor device further comprising a third silicon module containing oxygen provided between the at least one layer and the electrode.

18. a step of preparing a semiconductor substrate including a drift layer of the first conductivity type and an anode layer of the second conductivity type provided on at least a part of the drift layer; a step of forming a silicon layer containing oxygen on the upper surface of the semiconductor substrate; a step of forming a conductive film containing silicon and aluminum on the silicon layer, and forming a first silicon module containing oxygen between the anode layer and the conductive film; a step of forming an electrode by patterning the conductive film A method of manufacturing a semiconductor device comprising:

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