Semiconductor device

Abstract

To provide a semiconductor device which has a transistor protection function and is reduced in size.SOLUTION: A semiconductor device according to the present disclosure comprises a first transistor QP and a second transistor QN formed in the same substrate. The first transistor QP is a P-channel type field-effect transistor provided with a P-type first source region and a P-type first drain region, and the second transistor QN is an N-channel type field-effect transistor provided with an N-type second source region and an N-type second drain region. The first drain region of the first transistor QP (first P-type semiconductor region 6) extends to a position adjoining the second source region of the second transistor QN (second N-type semiconductor region 5), and the second drain region of the second transistor QN (first N-type semiconductor region 4) extends to a position adjoining the first source region of the first transistor QP (second P-type semiconductor region 10).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] The present disclosure provides a semiconductor device having a protection function for transistors and being miniaturized.

[0005] The semiconductor device of the present disclosure includes a first transistor and a second transistor formed in the same substrate. The first transistor is a P-channel field effect transistor including a P-type first source region and a P-type first drain region. The second transistor is an N-channel field effect transistor including an N-type second source region and an N-type second drain region. The first drain region of the first transistor extends to a position adjacent to the second source region of the second transistor, and the second drain region of the second transistor extends to a position adjacent to the first source region of the first transistor.

Brief Description of the Drawings

[0006]

Figure 1

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[0007] [Detailed Description] Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will be omitted.

[0008] FIG. 1 is a perspective view of a semiconductor device shown in a partially disassembled state.

[0009] The semiconductor device 100 includes a semiconductor substrate 1. An XYZ three-dimensional orthogonal coordinate system is set. The thickness direction of the semiconductor substrate 1 is the Z-axis direction. The depth direction from the surface of the semiconductor substrate 1 toward the deep part is the positive direction of the Z-axis. The width direction perpendicular to the Z-axis is the X-axis direction. The length direction perpendicular to both the Z-axis and the X-axis is the Y-axis direction. The semiconductor device 100 includes a P-type semiconductor region 6 that passes through the center position in the width direction (X-axis direction) and extends along the length direction (Y-axis direction) in a plan view seen from the Z-axis direction. In the figure, the P-type semiconductor region 6 divides the substrate surface into two regions: a left region (first region) and a right region (second region).

[0010] The semiconductor device 100 includes a first transistor QP and a second transistor QN formed in the same substrate.

[0011] The first transistor QP is a P-channel metal-oxide-semiconductor field-effect transistor (FET). The first transistor QP is a first P-channel transistor QP located in the first region described above. Aand a second P-channel transistor QP located within the second region B is provided. The first P-channel transistor QP A and the second P-channel transistor QP B may be electrically connected in parallel. In the figure, two first P-channel transistors QP A and two second P-channel transistors QP B are shown, but the number of each transistor may be one or two or more. Each P-channel transistor in this example is a P-channel lateral double-diffused metal oxide semiconductor (LDMOS) FET.

[0012] The second transistor QN is an N-channel field effect transistor (FET). The second transistor QN includes a first N-channel transistor QN located within the above-described first region A and a second N-channel transistor QN located within the second region B is provided. The first N-channel transistor QN A and the second N-channel transistor QN B may be electrically connected in parallel. In the figure, two first N-channel transistors QN A and two second N-channel transistors QN B are shown, but the number of each transistor may be one or two or more. Each N-channel transistor in this example is an N-channel LDMOS-FET. The plurality of first transistors QP and the plurality of second transistors QN are alternately arranged along the Y-axis direction.

[0013] Note that the structure of the first region and the structure of the second region have a plane-symmetric structure with respect to the YZ plane passing through the central P-type semiconductor region 6. Therefore, since the structure of the first region is the same as the structure of the second region, the structure of the first region will be described below.

[0014] The first gate electrode 9 of the first transistor QP, the source region (the second P-type semiconductor region 10), and the contact region (the first N-type semiconductor region 4) are short-circuited. The source region (the second P-type semiconductor region 10) and the contact region (the first N-type semiconductor region 4) are electrically connected by a silicide layer provided on their surfaces. An insulating film is provided on the silicide layer. A contact hole is opened in this insulating film, a contact electrode is formed in the contact hole, and the silicide layer can be electrically connected to the first gate electrode 9 through the contact electrode.

[0015] The source region (the second N-type semiconductor region 5) of the second transistor QN and the contact region (the first P-type semiconductor region 6) are short-circuited. The source region (the second N-type semiconductor region 5) and the contact region (the first P-type semiconductor region 6) are electrically connected by a silicide layer provided on their surfaces. An insulating film is provided on the silicide layer. A contact hole is opened in this insulating film, a contact electrode is formed in the contact hole, and the silicide layer can be electrically connected to the drain electrode 6E through the contact electrode.

[0016] When a surge current or a surge voltage is input, the first transistor QP can pass a current through the parasitic diode formed inside it, so it can function as a protection circuit for the second transistor QN.

[0017] FIG. 2 is a cross-sectional view taken along the line A-A of the semiconductor device shown in FIG. 1.

[0018] The figure shows a first transistor QP (P-channel DMOS-FET). The first transistor QP includes an N-type well region 2 and a P-type well region 3 formed on the surface side of a semiconductor substrate 1. The region on the surface side of the semiconductor substrate 1 can be an epitaxial semiconductor layer. The first transistor QP includes a source region (second P-type semiconductor region 10) formed in the N-type well region 2 and a drain region (first P-type semiconductor region 6) formed in the P-type well region 3. On the N-type well region 2, a first gate electrode 9 is disposed via an insulating film 11.

[0019] The insulating film 11 can include a gate insulating film formed only directly under the first gate electrode 9 and an insulating film covering the entire surface of the semiconductor substrate 1. As the material of the gate insulating film and the insulating film covering the semiconductor substrate, an inorganic insulating film such as SiO2 or silicon nitride can be used. On the surface side of the P-type well region 3, an insulating region 8 (8P) is formed. The insulating region 8 is adjacent to the drain region (first P-type semiconductor region 6). The material of the insulating region 8 in this example is SiO2 and can be formed of a field oxide film or the like. The insulating region 8 may include other insulating materials such as silicon nitride and may include a plurality of insulating layers. In plan view, the first gate electrode 9 extends over the insulating region 8 from one end position in the X-axis direction of the source region (second P-type semiconductor region 10) beyond the end positions of the N-type well region 2 and the P-type well region 3.

[0020] The P-type well region 3 is originally the carrier (hole) drift region in a P-channel DMOS-FET. When a negative potential is applied to the first gate electrode 9 in the first transistor QP, a P-type channel is formed on the surface of the N-type well region 2 directly below the first gate electrode 9. In this example, the first gate electrode 9, the source region (the second P-type semiconductor region 10), and the contact region (the first N-type semiconductor region 4) are short-circuited. The contact region (the first N-type semiconductor region 4) is adjacent to and joined with the source region (the second P-type semiconductor region 10). Also, a drain electrode 6E (terminal) is connected to the drain region (the first P-type semiconductor region 6) via a contact electrode.

[0021] Note that the figure is a schematic cross-sectional view, and an upper layer portion (epitaxial semiconductor layer) of the semiconductor substrate 1 is depicted as intervening between the P-type well region 3 and the N-type well region 2, but the P-type well region 3 and the N-type well region 2 may be joined (in contact). The P-type well region 3 (anode) and the N-type well region 2 (cathode) are PN-junctioned, and these constitute the first diode D1 (parasitic diode).

[0022] The P-type well region 3 in the first transistor QP is common with the P-type well region 3 (see FIGS. 4 and 5) in the second transistor QN, and these are continuous. The first P-type semiconductor region 6 (drain region) in the first transistor QP is common with the first P-type semiconductor region 6 (contact region (see FIGS. 4 and 5)) in the second transistor QN, and these are continuous.

[0023] FIG. 3 is a cross-sectional view taken along the A-A arrow of the semiconductor device shown in FIG. 1.

[0024] The semiconductor device 100 shown in the figure shows a detailed structural example of the semiconductor substrate 1 shown in FIG. 2. The semiconductor substrate 1 includes a substrate 1A, a buried semiconductor layer 1B formed on the substrate 1A, and an epitaxial semiconductor layer 1C formed on the buried semiconductor layer 1B. In this example, the substrate 1A is a P-type semiconductor substrate, the buried semiconductor layer 1B is an N-type semiconductor layer, and the epitaxial semiconductor layer 1C is an N-type semiconductor layer.

[0025] The periphery of the first transistor QP (and the second transistor QN) is surrounded by an isolation region for performing element isolation. The isolation region in this example is a P-type semiconductor region and includes a lower semiconductor region 12, an upper semiconductor region 13, and a surface semiconductor region 14. The lower semiconductor region 12 continuously extends upward from the surface of the substrate 1A, and the upper semiconductor region 13 is located thereon. Note that the figure is a schematic cross-sectional view, and a gap is depicted between the lower semiconductor region 12 and the upper semiconductor region 13, but they may be in contact. The impurity concentration of the surface semiconductor region 14 is higher than that of the upper semiconductor region 13, and if necessary, an electrode can be provided in the surface semiconductor region 14 to apply an appropriate potential such as a ground potential. Further, the isolation region may be configured by a structure such as deep trench isolation including a trench, and if necessary, N-type impurities may be added around the trench.

[0026] In this example, an insulating region 81 is disposed outside the first N-type semiconductor region 4. The insulating region 81 is made of the same material as the insulating region 8 that constitutes a field oxide film or the like, and in plan view, these may be continuous.

[0027] The thickness DZ in the depth direction from the surface of the semiconductor substrate of the first insulating region 8P (8) in the first transistor is 0.01 μm or more and 1 μm or less. When the thickness DZ in the depth direction exceeds the upper limit value, carriers are difficult to travel, and when it is less than the lower limit value, electric field relaxation cannot be achieved, resulting in a decrease in the breakdown voltage. It can also be set as 0.1 μm ≤ DZ ≤ 0.8 μm. It can also be set as 0.2 μm ≤ DZ ≤ 0.6 μm.

[0028] FIG. 4 is a cross-sectional view taken along the line B-B of the semiconductor device shown in FIG. 1.

[0029] In this figure, a second transistor QN (N-channel DMOS-FET) is shown. The second transistor QN includes an N-type well region 2 formed on the surface side of the semiconductor substrate 1 and a P-type well region 3. The region on the surface side of the semiconductor substrate 1 can be an epitaxial semiconductor layer. The second transistor QN includes a source region (second N-type semiconductor region 5) formed in the P-type well region 3 and a drain region (first N-type semiconductor region 4) formed in the N-type well region 2. On the P-type well region 3, a second gate electrode 7 is disposed via an insulating film 11. A terminal 7E for the gate electrode is electrically connected to the second gate electrode 7.

[0030] The insulating film 11 can include a gate insulating film formed only directly under the second gate electrode 7 and an insulating film covering the entire surface of the semiconductor substrate 1. An insulating region 8(8N) is formed on the surface side of the N-type well region 2. The insulating region 8 is adjacent to the drain region (first N-type semiconductor region 4). The insulating region 8(8N) in this example is continuous with the insulating region 8(8P) in the first transistor QP and is made of the same material as this. The second gate electrode 7 extends on the insulating region 8 from one end position in the X-axis direction of the source region (second N-type semiconductor region 5) beyond the end positions of the P-type well region 3 and the N-type well region 2 in a plan view.

[0031] The N-type well region 2 is a carrier (electron) drift region in the N-channel DMOS-FET. When a positive potential is applied to the second gate electrode 7, an N-type channel is generated on the surface of the P-type well region 3 directly under the second gate electrode 7. A contact region (first P-type semiconductor region 6) is adjacent to and joined to the source region (second N-type semiconductor region 5). Also, a drain electrode 4E (terminal) is electrically connected to the drain region (first N-type semiconductor region 4) via a contact electrode.

[0032] Note that the figure is a schematic cross-sectional view, and although it is depicted that an upper layer portion (epitaxial semiconductor layer) of the semiconductor substrate 1 is interposed between the P-type well region 3 and the N-type well region 2, the P-type well region 3 and the N-type well region 2 may be joined (in contact). The P-type well region 3 (anode) and the N-type well region 2 (cathode) are PN-junctioned, and these constitute the second diode D2 (parasitic diode).

[0033] In an N-channel type transistor, the potential of the drain side (first N-type semiconductor region 4) is higher than that of the source, and electrons flow from the source (second N-type semiconductor region 5) to the drain (the current flows from the drain to the source). A reverse bias voltage is applied to the second diode D2.

[0034] When a voltage exceeding the maximum rating is applied between the drain / source of the transistor, avalanche breakdown may occur. At the time of this avalanche breakdown, an avalanche current flows in the reverse direction through the parasitic diode in the transistor. The carriers of the second transistor QN are electrons, the second diode D2 breaks down, and the parasitic bipolar transistor connected in parallel to the second diode D2 operates, and the second transistor QN may be destroyed.

[0035] For example, when a positive surge of ESD (Electro Static Discharge) is input to the drain terminal of the second transistor QN and discharged toward the source terminal, the parasitic bipolar transistor may operate and the second transistor QN may be destroyed. If no avalanche current flows through the second diode D2, the destruction of the second transistor QN due to the operation of the parasitic bipolar transistor can be suppressed.

[0036] Since the carrier of the first transistor QP is a hole, avalanche breakdown (impact ionization) is less likely to occur than in the N-channel type second transistor QN, and avalanche breakdown is less likely to occur. The first transistor QP can conduct a larger current than the second transistor QN. The magnitude of the voltage at which the first diode D1 attached to the first transistor QP breaks down is set to be smaller than the magnitude of the voltage at which the second diode D2 breaks down. When a surge voltage is input, instead of the second diode D2, current flows through the first diode D1, and the first transistor QP protects the second transistor QN. By combining the first transistor QP and the second transistor QN, destruction of the second transistor QN is suppressed even against changes in surge current when using a large current. Therefore, the semiconductor device 100 in this example has high resistance to ESD.

[0037] FIG. 5 is a cross-sectional view taken along the line B-B of the semiconductor device shown in FIG. 1.

[0038] The semiconductor device 100 shown in the figure shows a detailed structural example of the semiconductor substrate 1 shown in FIG. 4. The semiconductor substrate 1 includes a substrate 1A, a buried semiconductor layer 1B formed on the substrate 1A, and an epitaxial semiconductor layer 1C formed on the buried semiconductor layer 1B. The substrate 1A, the buried semiconductor layer 1B, and the epitaxial semiconductor layer 1C are the same as the respective elements shown in FIGS. 2 to 4.

[0039] The periphery of the second transistor QN (and the first transistor QP) is surrounded by an isolation region for element isolation. The isolation region in this example is the same as that shown in FIG. 3 and includes a lower semiconductor region 12, an upper semiconductor region 13, and a surface semiconductor region 14. If necessary, an electrode can be provided in the surface semiconductor region 14 to apply an appropriate potential such as a ground potential. Further, the isolation region may be configured by a structure such as deep trench isolation including a trench, and if necessary, N-type impurities may be added around the trench.

[0040] In this example, an insulating region 81 is disposed outside the first N-type semiconductor region 4. The insulating region 81 is made of the same material as the insulating region 8 that constitutes a field oxide film or the like, and these may be continuous in a plan view.

[0041] Next, the materials and impurity concentrations of the semiconductor regions will be described.

[0042] The material of the substrate 1A in this example is made of silicon (Si). The material of the substrate 1A can also be composed of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). The conductivity type of the substrate 1A is P-type (first conductivity type), and the impurity concentration (C 1A ) is, for example, 1×10 14 cm -3 ~5×10 18 cm -3 and can be set accordingly. The thickness of the substrate 1A is, for example, 250 μm to 800 μm. An SOI (silicon on insulator) structure can also be adopted by using an insulating substrate or insulating layer such as Al2O3 as the material of the substrate 1A. Further, as the N-type impurity material in silicon, phosphorus (P) or arsenic (As) etc. can be used, and as the P-type impurity material, boron (B) or aluminum (Al) etc. can be used.

[0043] The material of the buried semiconductor layer 1B can be the same as the semiconductor material of the substrate 1A. The conductivity type of the buried semiconductor layer 1B is N-type (second conductivity type), and the impurity concentration (C 1B ) is, for example, 1×10 17 cm -3 ~1×10 19 cm -3 and can be set accordingly. The thickness of the buried semiconductor layer 1B can be, for example, 1 μm to 5 μm.

[0044] The material of the epitaxial semiconductor layer 1C can be the same as the semiconductor material of the substrate 1A. The conductivity type of the epitaxial semiconductor layer 1C is N-type (second conductivity type), and the impurity concentration (C 1C ) is, for example, 5×10 14 cm -3 ~1×1017 cm -3 can be set. The thickness of the epitaxial semiconductor layer 1C can be, for example, 3 μm to 20 μm. The impurity concentration in this example is C 1C <C 1A <C 1B satisfies the relationship of.

[0045] The material of the N-type well region 2 can be the same as the semiconductor material of the substrate 1A. The conductivity type of the N-type well region 2 is N-type (second conductivity type), and the impurity concentration (C2) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 can be set. The thickness of the N-type well region 2 can be, for example, 0.5 μm to 4 μm.

[0046] The material of the P-type well region 3 can be the same as the semiconductor material of the substrate 1A. The conductivity type of the P-type well region 3 is P-type (first conductivity type), and the impurity concentration (C3) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 can be set. The thickness of the P-type well region 3 can be, for example, 0.5 μm to 4 μm.

[0047] The materials of the first N-type semiconductor region 4 and the second N-type semiconductor region 5 can be the same as the semiconductor material of the substrate 1A. The conductivity types of the first N-type semiconductor region 4 and the second N-type semiconductor region 5 are N-type (second conductivity type), and the respective impurity concentrations (C4, C5) are, for example, 1×10 19 cm -3 ~5×10 21 cm -3 can be set. The thicknesses of the first N-type semiconductor region 4 and the second N-type semiconductor region 5 can be, for example, 0.2 μm to 1 μm.

[0048] The materials of the first P-type semiconductor region 6 and the second P-type semiconductor region 10 can be the same as the semiconductor material of the substrate 1A. The conductivity types of the first P-type semiconductor region 6 and the second P-type semiconductor region 10 are P-type (the first conductivity type), and the impurity concentrations (C6, C 10 ) can be, for example, 1×10 19 cm -3 ~5×10 21 cm -3 . The thicknesses of the first N-type semiconductor region 4 and the second N-type semiconductor region 5 can be, for example, 0.2 μm to 2 μm. The thicknesses (depths) of the first N-type semiconductor region 4, the second N-type semiconductor region 5, the first P-type semiconductor region 6, and the second P-type semiconductor region 10 may be the same.

[0049] The materials of the first gate electrode 9 and the second gate electrode 7 are not particularly limited as long as they are conductors. For example, polysilicon doped with impurities can be used.

[0050] The materials of the lower semiconductor region 12, the upper semiconductor region 13, and the surface semiconductor region 14 that constitute the isolation can be the same as the semiconductor material of the substrate 1A. The conductivity types of these semiconductor regions are P-type (the first conductivity type), and the impurity concentration can be set higher than the impurity concentration (C 1C ) of the epitaxial semiconductor layer 1C.

[0051] The thickness DZ in the depth direction from the surface of the semiconductor substrate of the second insulating region 8N(8) in the second transistor QN is 0.01 μm or more and 1 μm or less. When the thickness DZ in the depth direction exceeds the upper limit value, it becomes difficult for carriers to travel. When it is less than the lower limit value, electric field relaxation cannot be achieved, resulting in a decrease in the breakdown voltage. When the thickness DZ in the depth direction is within the above range, it operates suitably as a DMOS-FET. It can also be 0.1 μm ≦ DZ ≦ 0.8 μm. It can also be 0.2 μm ≦ DZ ≦ 0.6 μm.

[0052] FIG. 6 is a circuit diagram of the semiconductor device.

[0053] The first transistor QP and the second transistor QN are connected in parallel between a first wiring L1 and a second wiring L2.

[0054] The first wiring L1 is located on a first N-type semiconductor region 4 (Figs. 1 to 5), is electrically connected to the first N-type semiconductor region 4, and extends in parallel to the first N-type semiconductor region 4. The connection between the first wiring L1 and the first N-type semiconductor region 4 is made by a plurality of first via electrodes. Specifically, a plurality of first via electrodes VE1 (see Fig. 7(A)) are aligned along the Y-axis direction in a plan view. The source region and the gate electrode of the first transistor QP are electrically connected to the first wiring L1. The drain region of the second transistor QN is electrically connected to the first wiring L1.

[0055] The second wiring L2 is located on a first P-type semiconductor region 6 (Figs. 1 to 5), is electrically connected to the first P-type semiconductor region 6, and extends in parallel to the first P-type semiconductor region 6. The connection between the second wiring L2 and the first P-type semiconductor region 6 is made by a plurality of via electrodes. Specifically, a plurality of second via electrodes VE2 (see Fig. 7(A)) are aligned along the Y-axis direction in a plan view. The drain region of the first transistor QP is electrically connected to the second wiring L2. The source region of the second transistor QN is electrically connected to the second wiring L2.

[0056] The second transistor QN is a DMOS-type NMOS-FET. When a positive potential is applied to the gate electrode, an N-type channel is formed directly under the gate electrode. Since a positive potential is applied to the drain region, electrons in the source region flow through the N-type channel to the drain region. That is, when the second transistor QN is in the ON state, current flows from the drain region to the source. The first transistor QP is a protection circuit for the second transistor QN and can protect the second transistor QN when a surge voltage or the like is input to the circuit.

[0057] FIG. 7 is a plan view of a semiconductor device (FIG. 7(A)) and a diagram showing a horizontal cross-sectional structure of a well region (FIG. 7(B)). In FIG. 7(A), the insulating film on the semiconductor substrate is shown omitted. Further, FIG. 7(B) shows the horizontal cross-sectional structure of the well at a position deeper than the insulating region located on the surface of the semiconductor substrate.

[0058] As shown in FIG. 7(A), a plurality of first via electrodes VE1 (contact electrodes) are provided in the first N-type semiconductor region 4 and are aligned along the Y-axis direction. A plurality of second via electrodes VE2 (contact electrodes) are provided in the first P-type semiconductor region 6 and are aligned along the Y-axis direction. A third via electrode VE3 (contact electrode) is provided in the second P-type semiconductor region 10 and is electrically connected to the first gate electrode 9 together with the first N-type semiconductor region 4 as shown in FIG. 1. In plan view, the insulating region 8 is provided so as to fill the periphery of the first transistor QP and the second transistor QN. Note that, as the material of each via electrode, for example, tungsten (W) can be used, but other conductive materials (aluminum (Al), copper (Cu), etc.) may also be used.

[0059] As shown in FIG. 7(B), in plan view, the deep N-type well region 2 has left and right regions. Focusing on only one of the regions, the deep N-type well region 2 has a first X-axis direction width XN1 corresponding to the first transistor QP and a second X-axis direction width XN2 corresponding to the second transistor QN (XN1 < XN2). In plan view, the deep P-type well region 3 has a third X-axis direction width XP1 corresponding to the first transistor QP and a fourth X-axis direction width XP2 corresponding to the second transistor QN (XP1 < XP2). These widths alternately change along the Y-axis direction, and the boundary line between the deep N-type well region 2 and the P-type well region 3 forms an interdigitated structure in plan view.

[0060] The first source region (the second P-type semiconductor region 10) is formed within the first N-well region 21A. The first drain region (the first P-type semiconductor region 6) is formed within the first P-well region 31A. A first insulating region (8(8P)) is interposed between the first drain region (6) and the first N-well region 21A. The first transistor QP has the same DMOS-FET structure as the second transistor QN, and has the advantage that it is easy to design the characteristics of the first diode as a protection circuit for the second transistor QN.

[0061] The second source region (the second N-type semiconductor region 5) is formed within the second P-well region 32A. The second drain region (the first N-type semiconductor region 4) is formed within the second N-well region 22A. A second insulating region (8(8N)) is interposed between the second drain region (the first N-type semiconductor region 4) and the second P-well region 32A. In the region directly below the second insulating region (8(8N)), N-type carriers drift and travel.

[0062] The first P-well region 31A and the second P-well region 32A are a common P-type well region 3 and are continuous. The first N-well region 21A and the second N-well region 22A are a common N-type well region 2 and are continuous. The first insulating region (8P) and the second insulating region (8N) are a common insulating region 8 and are continuous.

[0063] The first transistor QP includes a first gate electrode 9 that controls a channel between a first source region (second P-type semiconductor region 10) and a first drain region (first P-type semiconductor region 6). The first gate electrode 9 is provided to cover a first N-well region 21A, a first P-well region 31A, and a first insulating region (8P) in a region between the first source region (second P-type semiconductor region 10) and the first drain region (first P-type semiconductor region 6). The second transistor QN includes a second gate electrode 7 that controls a channel between a second source region (second N-type semiconductor region 5) and a second drain region (first N-type semiconductor region 4). The second gate electrode 7 is provided to cover a second P-well region 32A, a second N-well region 22A, and a second insulating region (8N) in a region between the second source region (second N-type semiconductor region 5) and the second drain region (first N-type semiconductor region 4).

[0064] Note that, with respect to the YZ plane passing through the center in the X-axis direction, an N-well region at a position symmetric to the first N-well region 21A is defined as the first N-well region (21B). With respect to this YZ plane, an N-well region at a position symmetric to the second N-well region 22A is defined as the second N-well region (22B). With respect to this YZ plane, a P-well region at a position symmetric to the first P-well region 31A is defined as the first N-well region (31B). With respect to this YZ plane, a P-well region at a position symmetric to the second P-well region 32A is defined as the second N-well region (32B).

[0065] The length of the first transistor QP in the Y-axis direction (the dimension of the first gate electrode 9 in the Y-axis direction) is smaller than the length of the second transistor QN in the Y-axis direction (the dimension of the second gate electrode 7 in the Y-axis direction). The first transistor QP is a protection circuit and does not operate during a period when protection is not required. Therefore, in this example, the dimension is designed to be small. Note that it is not always necessary to make the dimension of the first transistor QP in the Y-axis direction smaller than that of the second transistor QN, and it can be adjusted as needed.

[0066] In the above semiconductor device, since element isolation and power wiring can be reduced, the area (cost) can be reduced and the design ease can be enhanced. Further, since the average power density (heat generation) of the ESD operation can be reduced, the breakdown voltage with respect to the discharge current can be increased, the amount of heat generation when the discharge current is input can be decreased, and high ESD performance can be obtained.

[0067] The first transistor QP is arranged near the second transistor QN with low ESD resistance, and the back gate ratio (the ratio of the area of the P-type region) of the second transistor QN can be reduced and it can be operated. Since the back gate portion does not contribute to the on-current (on-resistance), by reducing the back gate ratio, the area (A) × on-resistance (Ron) can be reduced.

[0068] The first transistor QP as a protection circuit can be arranged limited to the locations that require protection. That is, the first transistor QP can be locally arranged within the region where the second transistor QN is likely to be damaged in terms of circuit configuration, and an efficient design can be achieved. For example, in a power array, regions close to bonding pads, regions with low wiring resistance, and regions at the outermost periphery are likely to have transistors damaged. Within these regions with weak resistance, more of the first transistors QP as protection circuits can be arranged than in other regions.

[0069] The above semiconductor device can be applied to a semiconductor chip equipped with a (DMOS)FET. Further, the above semiconductor device can also be applied to FETs other than (DMOS)FETs. Such semiconductor chips can be mounted on various devices mounted on automobiles, airplanes, ships, etc.

[0070] (Supplementary Note) As described above, in the above semiconductor device, the second transistor QN can be protected by the first transistor QP, but since it has a structure in which the first and second transistors are integrated, it is small. Various embodiments in the present disclosure can be defined as the following supplementary notes.

[0071] [A1] A semiconductor device including a first transistor QP and a second transistor QN formed in the same substrate. The first transistor QP is a P-channel field-effect transistor having a P-type first source region and a P-type first drain region. The second transistor QN is an N-channel field-effect transistor having an N-type second source region and an N-type second drain region. The first drain region (first P-type semiconductor region 6) of the first transistor QP extends to a position adjacent to the second source region (second N-type semiconductor region 5) of the second transistor QN, and the second drain region (first N-type semiconductor region 4) of the second transistor QN extends to a position adjacent to the first source region (second P-type semiconductor region 10) of the first transistor QP. According to this semiconductor device, the first transistor QP includes elements common to the second transistor QN (the first drain region (first P-type semiconductor region 6), the second drain region (first N-type semiconductor region 4)), and while functioning as a protection circuit for the second transistor QN, the semiconductor device can be miniaturized.

[0072] [A2] The first source region (second P-type semiconductor region 10) of the first transistor QP is formed in a first N-well region (2(21A)), the first drain region (first P-type semiconductor region 6) of the first transistor QP is formed in a first P-well region (3(31A)), and a first insulating region (8(8P)) is interposed between the first drain region (6) and the first N-well region (21A). The semiconductor device according to A1.

[0073] [A3] The second source region (second N-type semiconductor region 5) of the second transistor QN is formed in a second P-well region (3(32A)), the second drain region (first N-type semiconductor region 4) of the second transistor QN is formed in a second N-well region (2(22A)), and a second insulating region (8(8N)) is interposed between the second drain region (first N-type semiconductor region 4) and the second P-well region (3(32A)). The semiconductor device according to A2.

[0074] [A4] The first P-well region (31A) and the second P-well region (32A) are a common P-type well region 3 and are continuous. The first N-well region (21A) and the second N-well region (22A) are a common N-type well region 2 and are continuous. The first insulating region (8P) and the second insulating region (8N) are a common insulating region 8 and are continuous. The semiconductor device according to A3.

[0075] [A5] The thickness DZ in the depth direction from the surface of the semiconductor substrate of the first insulating region (8P) and the second insulating region (8N) is 0.01 μm or more and 1 μm or less. The semiconductor device according to A4. When the thickness DZ in the depth direction exceeds the upper limit value, it becomes difficult for carriers to travel. When it is less than the lower limit value, electric field relaxation cannot be achieved and the breakdown voltage decreases.

[0076] [A6] The first transistor (QP) includes a first gate electrode (9) that controls a channel between the first source region (the second P-type semiconductor region 10) and the first drain region (the first P-type semiconductor region 6). The first gate electrode (9) is provided so as to cover the first N-well region (21A), the first P-well region (31A), and the first insulating region (8P) in the region between the first source region (the second P-type semiconductor region 10) and the first drain region (the first P-type semiconductor region 6). The second transistor (QN) includes a second gate electrode (7) that controls a channel between the second source region (the second N-type semiconductor region 5) and the second drain region (the first N-type semiconductor region 4). The second gate electrode (7) is provided so as to cover the second P-well region (32A), the second N-well region (22A), and the second insulating region (8N) in the region between the second source region (the second N-type semiconductor region 5) and the second drain region (the first N-type semiconductor region 4). The semiconductor device according to any one of A3 to A5.

[0077] Although various exemplary embodiments have been described above, various omissions, substitutions, and changes may be made without being limited to the exemplary embodiments described above. Also, it is possible to form other embodiments by combining elements in different embodiments. Further, from the above description, it will be understood that various embodiments of the present disclosure have been described herein for the purpose of illustration, and that various changes can be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

Description of Reference Numerals

[0078] 1... semiconductor substrate, 1A... substrate, 1B... embedded semiconductor layer, 1C... epitaxial semiconductor layer, 2... N-type well region, 3... P-type well region, 4... first N-type semiconductor region, 4E... drain electrode, 5... second N-type semiconductor region, 6... first P-type semiconductor region, 6E... drain electrode, 7... second gate electrode, 7E... terminal for gate electrode, 8, 81... insulating region, 8N... second insulating region, 8P... first insulating region, 9... first gate electrode, 10... second P-type semiconductor region, 11... insulating film, 12... lower semiconductor region, 13... upper semiconductor region, 14... surface semiconductor region, 21A, 21B... first N well region, 22A, 22B... second N well region, 31A, 31B... first P well region, 32A, 32B... second P well region, 100... semiconductor device, D1... first diode, D2... second diode, L1... first wiring, L2... second wiring, QP... first transistor, QP A ... first P-channel transistor, QP B ... second P-channel transistor, QN... second transistor, QN A ... first N-channel transistor, QN B ... second N-channel transistor, VE1... first via electrode, VE2... second via electrode, VE3... third via electrode, XN1... first X-axis direction width, XN2... second X-axis direction width, XP1... third X-axis direction width, XP2... fourth X-axis direction width.

Claims

1. A semiconductor device comprising a first transistor and a second transistor formed in the same substrate, wherein the first transistor is a P-channel field-effect transistor having a P-type first source region and a P-type first drain region, and the second transistor is an N-channel field-effect transistor having an N-type second source region and an N-type second drain region, wherein the first drain region of the first transistor extends to a position adjacent to the second source region of the second transistor, and the second drain region of the second transistor extends to a position adjacent to the first source region of the first transistor. Semiconductor device.

2. The first source region of the first transistor is formed in a first N-well region, the first drain region of the first transistor is formed in a first P-well region, and a first insulating region is interposed between the first drain region and the first N-well region. The semiconductor device according to claim 1.

3. The second source region of the second transistor is formed in a second P-well region, the second drain region of the second transistor is formed in a second N-well region, and a second insulating region is interposed between the second drain region and the second P-well region. The semiconductor device according to claim 2.

4. The first P-well region and the second P-well region are a common P-type well region and are continuous, the first N-well region and the second N-well region are a common N-type well region and are continuous, and the first insulating region and the second insulating region are a common insulating region and are continuous. The semiconductor device according to claim 3.

5. The thickness DZ in the depth direction from the surface of the semiconductor substrate of the first insulating region and the second insulating region is 0.01 μm or more and 1 μm or less. The semiconductor device according to claim 4.

6. The first transistor includes a first gate electrode that controls a channel between the first source region and the first drain region, wherein the first gate electrode is provided to cover the first N-well region, the first P-well region, and the first insulating region in a region between the first source region and the first drain region, and the second transistor includes a second gate electrode that controls a channel between the second source region and the second drain region, wherein the second gate electrode is provided to cover the second N-well region, the second P-well region, and the second insulating region in a region between the second source region and the second drain region.

7. ​ ​ ​ ​ Provided so as to cover the second P-well region, the second N-well region, and the second insulating region in a region between the second source region and the second drain region. The semiconductor device according to any one of claims 3 to 5.

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