High performance high breakdown voltage reverse conduction semiconductor device

Abstract

To eliminate or significantly suppress the snapback phenomenon in a small cell area by using a highly concentrated buffer layer suitable for realizing ultra high breakdown voltage, and to reduce losses by utilizing this small cell size to reduce steady-state ON loss and switching time, in 8 to 25 kV-class ultra high breakdown voltage reverse conduction IGBTs.SOLUTION: A buffer layer structure, which has both semiconductor and insulator regions is provided, furthermore, insulating protrusions in the semiconductor region connected to the insulating region provide high resistance conductive paths in the semiconductor region, and a buffer layer in the form of a double-tooth comb, which is suitable for stripe cell structures, or a triangular buffer layer, which is suitable for polygonal cell structures such as honeycombs, is used to eliminate or significantly suppress the snapback phenomenon of ultra high breakdown voltage reverse conduction IGBTs in a small area.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a high-voltage semiconductor device, and particularly to a high-performance ultra-high-voltage wide-gap reverse-conducting semiconductor device and a method for manufacturing the same.

Background Art

[0002] Conventionally, in high-voltage high-power and medium-power applications, Si-IGBT semiconductor devices made of silicon (Si) as the material have been the mainstream and are widely used in various application fields, and products up to the 6.5 kV class have been supplied. However, for higher ultra-high voltages, it is difficult to achieve compatibility with other characteristics such as losses, and productization has not been achieved. In recent years, wide-gap semiconductor materials such as silicon carbide (SiC) have attracted attention as semiconductor materials suitable for high-voltage applications, and a 1.2 kV class SiC MOSFET has been developed and put into practical use for electric vehicles. As for higher-voltage SiC MOSFETs, 10 kV class ultra-high-voltage elements have also been developed, but due to the large temperature dependence of the characteristic on-resistance, the power consumption loss becomes large at high temperatures, and thus productization has not been achieved yet. On the other hand, SiC-IGBT is attracting attention because it can be expected to have low losses in the high-current region due to the conductivity modulation effect peculiar to bipolar elements and has a small temperature dependence of the on-characteristics, and ultra-high-voltage elements in the 8 - 20 kV class have been developed. However, since the built-in voltage is as large as about 2.7 V, which is about 4 times that of Si, there is a problem that it can hardly be energized up to an on-voltage of about 3 V and cannot be utilized, and there is a demand for reducing the switching loss by reducing the switching time, particularly the turn-off time.

[0003] As a technology capable of reducing the turn-off time of IGBT, reverse-conducting Si IGBTs such as [Non-Patent Document 1] and [Non-Patent Document 2] have been developed. In the reverse-conducting Si IGBT, the n-drift layer is short-circuited to the collector electrode by an n-short-circuit region provided in the p-collector layer, and the turn-off time is shortened by eliminating the carriers remaining in the n-drift layer through this n-short-circuit region during turn-off, and a significant reduction in switching loss can be achieved. The same effect can be expected for reverse-conducting SiC IGBTs.

[0004] In addition, in the case of Si IGBTs, the built-in voltage is as low as about 0.7 V, which has not been a major obstacle to reducing the on-voltage. However, in the case of SiC IGBTs, the built-in voltage is as high as 2.7 V as described above, which becomes a serious obstacle. However, in the case of reverse-conducting IGBTs, since the MOSFET exists in parallel with the IGBT through the short-circuit region, in the case of reverse-conducting SiC IGBTs, even when the voltage is below the built-in voltage, the current flowing through the short-circuit region can be utilized, and a significant mitigation of the obstacle can be expected.

[0005] However, in the output characteristics of the Si reverse-conducting IGBTs of Conventional Example 1 of [Non-Patent Document 1] and Conventional Example 2 of [Non-Patent Document 2] disclosed, that is, in the Ice-Vce characteristics between the collector-emitter voltage (hereinafter referred to as Vce) and the collector-emitter current (hereinafter referred to as Ice), a snap-back phenomenon as shown in FIG. 1 occurs in which the collector-emitter voltage immediately before turning on is larger than the collector-emitter voltage immediately after turning on. The collector-emitter voltage immediately before turning on is

Non-Patent Document 1

Non-Patent Document 2

[0006] To solve this problem, in Conventional Example 2, a reverse-conducting Si IGBT is composed of a reverse-conducting Si-IGBT region and a pilot IGBT region for improvement. That is, in addition to the reverse-conducting IGBT standard cell in the chip, a pilot IGBT region is provided. The width of the collector of the pilot IGBT region is made significantly larger than the width of the collector of the reverse-conducting IGBT cell, and the lateral resistance of the buffer layer on the p collector is made significantly larger. First, with a small Ice, the pilot IGBT region is driven ahead of the reverse-conducting IGBT region, and the entire Si reverse-conducting IGBT chip is turned on by significantly suppressing or eliminating the snap-back phenomenon.

[0007] However, in the case of this Conventional Example 2, the area of the pilot IGBT region in the entire IGBT chip area becomes quite large. For example, in the case of Conventional Example 2, when read from the data, even at a relatively low breakdown voltage of 3.3 kV design, the p collector width of the Si reverse-conducting IGBT standard cell is 240 micrometers, while the p collector width of the pilot IGBT is made 650 micrometers or more, which is about three times or more, so that Vsb is set to about 0.7 V, which is the built-in voltage. Since the snap-back phenomenon becomes more severe as the breakdown voltage of the semiconductor device increases, the p collector width of this pilot IGBT further increases significantly. As a result, the snap-back phenomenon is eliminated, but the area of the reverse-conducting IGBT region in the entire IGBT chip of a predetermined area decreases, so the number of standard reverse-conducting cells to be integrated decreases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. Also, at turn-off, the elimination of the remaining carriers of the pilot IGBT, which occupies a large area, becomes significantly slower than that of the standard reverse-conducting cell, so the turn-off time becomes long and the turn-off loss becomes large. Also, from the viewpoint of economic efficiency such as yield, in the current situation of wide-gap semiconductors where the chip size of the element is usually set to about 15 mm x 15 mm or less, the fact that the pilot IGBT occupies a large area becomes a more serious problem as the breakdown voltage increases.

[0008] Therefore, as shown in [Patent Document 1], the inventor of the present invention significantly thinned the drift layer using a wide-gap semiconductor such as SiC to reduce the loss and size of the high-voltage reverse-conducting IGBT, while providing an element structure that eliminates the obstacle that even if it is significantly thinned, it is easily broken in the manufacturing process and the economic efficiency is impaired. That is, unevenness is provided on the collector side of the element, the IGBT part is provided in the concave part, the MOSFET part is provided in the convex part, and the part thicker than the IGBT part is utilized as a high-concentration drain layer of the MOSFET and a support layer for strength enhancement, maintaining the low-loss property of the high-voltage reverse-conducting IGBT while increasing the strength to maintain high economic efficiency.

[0009] In addition, as shown in [Patent Document 2] and [Non-Patent Document 3], the inventor of the present invention used a wide-gap semiconductor such as SiC, and by performing a detailed analysis of the buffer layer structure of the SiC pilot IGBT to make the impurity concentration and thickness of the buffer layer appropriate or to form a multi-buffer layer structure, the width of the collector layer (i.e., the width of the buffer layer) was dramatically reduced even at ultra-high voltages, and a standard cell with a pilot IGBT function that was miniaturized to the same level as a standard cell was provided. The active region of the SiC reverse-conducting IGBT was configured only with this standard cell with a pilot IGBT function to eliminate or significantly suppress the snap-back phenomenon.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0011]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0012] However, in order to realize an ultra-high breakdown voltage reverse-conducting semiconductor device with a breakdown voltage of 8 kV or higher for power utilities and industrial use, when using the above prior art, for example, using a wide-gap semiconductor such as the above SiC and using the technology of [Patent Document 1] and [Patent Document 2] with a standard cell having a pilot IGBT function, when the impurity concentration of the buffer layer is low, it is necessary to increase the thickness of the drift layer to achieve ultra-high breakdown voltage, which may cause an obstacle in reducing the on-resistance of the reverse-conducting semiconductor device. On the other hand, if the impurity concentration of the buffer layer is increased to a punch-through type to reduce the on-resistance, the lateral resistance of the buffer layer becomes small. Therefore, in order to make the voltage drop in the buffer layer higher than the built-in voltage and inject holes from the collector to turn on the IGBT, a relatively large Isb current is required, and the snap-back phenomenon increases significantly, and Vsb may reach a value of 1000 V or more, causing a major obstacle. In this case, in order to eliminate the snap-back phenomenon or significantly suppress Vsb to a practically acceptable range, for example, 10 V or less, it is necessary to make the lateral length of the buffer layer (corresponding to the p-collector width of the reverse-conducting IGBT cell) 7 mm or more, which increases the cell size and causes a problem that the area of the chip composed of a plurality of cells must be made considerably large. Furthermore, the discharge of residual carriers during device turn-off becomes slow, resulting in a long turn-off time and an increase in turn-off loss, which may also cause the aim of making it reverse-conducting to be impaired.

[0013] The present invention aims to solve the problems of the above prior art, and in particular, to provide a high-performance reverse-conducting semiconductor device that can achieve the elimination or significant suppression of the snap-back phenomenon even in a high-concentration buffer layer suitable for reverse-conducting semiconductor devices such as ultra-high breakdown voltage reverse-conducting IGBTs. Another object is to provide a highly economical high-performance reverse-conducting semiconductor device suitable for an ultra-high breakdown voltage reverse-conducting semiconductor device, which has a small p-collector width and can reduce the cell size and thus the chip size. Still another object is to provide a high-performance reverse-conducting semiconductor device capable of reducing the steady-state loss and turn-off loss.

Means for Solving the Problems

[0014] Hereinafter, in order to avoid complexity and facilitate understanding, an n-channel type wide-gap semiconductor, particularly a SiC reverse-conducting IGBT, will be described as a reverse-conducting semiconductor device. Naturally, the solution means described below has particularly remarkable application effects in wide-gap reverse-conducting semiconductor devices such as SiC in terms of physical property values. However, even in the case of Si semiconductors, which can reduce the cost and increase the diameter of wafers compared to wide-gap semiconductors and have fewer restrictions in terms of large chip size, the effects are significant because a substantial improvement in economic efficiency can be achieved.

[0015] In order to solve the above-described problems and achieve the object of the present invention, the reverse-conducting semiconductor device according to the present invention is mainly a reverse-conducting IGBT semiconductor device. The IGBT reverse-conducting semiconductor device has a reverse-conducting IGBT chip. The reverse-conducting IGBT chip has an active region having one or more reverse-conducting IGBT standard cells and a breakdown voltage structure surrounding the active region. The IGBT chip has an active region including a plurality of reverse-conducting IGBT standard cells and a breakdown voltage structure surrounding the active region. In the reverse-conducting IGBT standard cell of the IGBT chip, a MOS surface portion region is provided so as to be exposed on one main surface of the active region between one main surface and the surface of a drift layer of a first conductivity type. An emitter main electrode is provided on the exposed surface of the MOS surface portion region. Further, a buffer layer is provided in contact with the back surface of the drift layer of the first conductivity type. On the back surface of the buffer layer, a collector region of a second conductivity type and a short-circuit region of a first conductivity type (also serving as the drain region of the MOSFET portion) are provided such that a part of each side surface is in contact with the other region. In the reverse-conducting IGBT standard cell having a cross-sectional configuration with a collector main electrode provided on the back surface of the collector region of the second conductivity type and the short-circuit region (also serving as the drain region) of the first conductivity type. A current density increasing layer CEL of a first conductivity type may be provided between the MOS surface portion region and the drift layer of the first conductivity type. Moreover, the buffer layer on the collector region is characterized in that the reverse-conducting IGBT standard cell has a semiconductor region of a first conductivity type serving as a conduction path and an insulating region or a semi-insulating region. Note that the MOS surface region is defined as follows. That is, each reverse-conducting IGBT cell is composed of an IGBT part and a MOSFET part connected in parallel. However, each MOS surface part on the main surface side from the drift layer is shared by both the MOSFET part and the IGBT part, and is connected to the emitter main electrode of the topmost reverse-conducting IGBT. The region where these shared MOS surface parts are gathered, including the emitter main electrode, is collectively defined as the MOS surface region and is called so. Also, the insulating region referred to in this patent is a region composed of either one or both of an insulator or a semi-insulator. An insulator is a substance with a resistivity exceeding 1x10 11 Ωcm, and a semi-insulator is a substance with a resistivity in the range of 1x10 5 Ωcm to 1x10 11 Ωcm. In this patent, to avoid complexity in the description, it is simply called the insulating region without much distinction unless there is a strong necessity hereinafter. Note that it is effective to provide an n-current density enhancement layer CEL (Current density Enhancement Layer) between the MOS surface region and the n-drift layer to accumulate carriers in the n-drift layer and increase the current density, and it is often provided especially in the case of an ultra-high voltage IGBT with a breakdown voltage of 8 kV or more.

[0016] To solve the above problems and achieve the object of the present invention, the reverse-conducting semiconductor device according to this invention is The reverse-conducting IGBT standard cell in the active region has a stripe structure or a stripe structure equally divided in the longitudinal direction. The buffer layer has a stripe-shaped double comb-tooth planar shape as shown in FIG. 4, and a plurality of comb teeth are connected to the comb axis. The comb axis, the comb teeth, and the comb tooth gathering part are composed of the semiconductor region, and the space between the comb teeth is composed of the insulating region or the semi-insulating region. The comb teeth, the comb tooth gathering part, and the insulating region or the semi-insulating region therebetween are in contact with the collector region, and the comb axis is in contact with the short-circuit region, which is characterized.

[0017] In order to solve the above-described problems and achieve the object of the present invention, the reverse-conducting semiconductor device according to the present invention is The reverse-conducting IGBT standard cell has a polygonal planar shape surrounded by three or more line segments, and a triangular portion connecting an intersection of the line segments and a center point of the polygon is formed of the semiconductor region or the insulator region, and the triangular portion of the semiconductor region and the triangular portion of the insulator region are alternately arranged to form the buffer layer.

[0018] In order to solve the above-described problems and achieve the object of the present invention, the reverse-conducting semiconductor device according to the present invention is An insulating protrusion made of the same insulator as the insulator region is provided in the semiconductor region of the reverse-conducting IGBT standard cell, the insulating protrusion is in contact with either the upper or lower insulator region adjacent to the semiconductor region, and the resistance of the conductive path of the buffer layer can be set by setting the shape and number of the insulating protrusions, and Isb and thus Vsb can be set.

[0019] In order to solve the above-described problems and achieve the object of the present invention, the reverse-conducting semiconductor device according to the present invention is In the reverse-conducting semiconductor device having the reverse-conducting IGBT standard cell, In addition to the reverse-conducting IGBT standard cell, the reverse-conducting semiconductor device is configured to include, instead, a reverse-conducting IGBT cell having a smaller cell width than the reverse-conducting IGBT standard cell around the reverse-conducting IGBT standard cell.

[0020] In order to solve the above-described problems and achieve the object of the present invention, the reverse-conducting semiconductor device according to the present invention is In the reverse-conducting IGBT semiconductor device, the insulator region of the buffer layer is formed of an epitaxial film doped with vanadium, the conductive path is formed of a first-conductivity-type ion implantation layer reaching the first-conductivity-type drift layer, and the impurity concentration of the ion implantation layer is higher than the impurity concentration of the drift layer.

[0021] In order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a reverse-conducting semiconductor device according to the present invention is as follows. In the method for manufacturing the reverse-conducting IGBT semiconductor device, the manufacturing process of the insulating region includes a process of selectively implanting insulating ions, or includes a trench formation process for a trench MOS gate or the like and a subsequent process of forming an oxide film of a semiconductor exposed along the trench surface, and the manufacturing process of the insulating region is carried out after the manufacturing process of the collector region.

[0022] In order to solve the above-described problems and achieve the object of the present invention, an operating method of a reverse-conducting semiconductor device according to the present invention is as follows. In the reverse-conducting semiconductor device, after the temperature of the built-in pn junction diode and the IGBT portion is raised to a temperature equal to or higher than the on-voltage degradation suppression temperature by energizing the majority carrier current of the MOSFET portion, predetermined electrical operations are performed.

[0023] In order to solve the above-described problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, In a reverse-conducting IGBT cell having a stripe structure, unlike a mere stripe structure buffer layer on a conventional p collector region, the stripe structure buffer layer on the p collector region has a planar configuration composed of a conductive path made of a semiconductor having a double comb-shaped planar shape with teeth on both the left and right sides of the axis of the comb and an insulator or semi-insulator filling the space between the teeth as shown in FIG. 4. The buffer layer having this configuration is defined as a double comb-shaped buffer layer and will be described by this name hereinafter.

[0024] As a result, each comb tooth portion will function as a key structural factor for suppressing the snap-back phenomenon. However, since the space between the comb teeth is an insulator or a semi-insulator, almost no current flows through this portion between the comb teeth. The current branches off from each comb tooth from the conductive path portion facing the JFET on the main surface side, i.e., the comb tooth assembly, and flows into the short-circuit region. Therefore, for example, it is preferable because it is relatively easy to design the resistance value Ri of each comb tooth to a desired value when the following conditions are satisfied. (1) There are N comb teeth of the same shape. Let the width, length, and thickness of the comb teeth be Wa, La, and t, the width, length, and thickness between the comb teeth be Wb, Lb, and t, and the length of the insulators on the left and right at both upper and lower ends of the comb tooth group be Lb / 2. (2) Let the width of the conventional simple stripe-type buffer layer be W, the length be L, and the thickness be t. (3) Make Nx(La + Lb)=L and Wa = Wb = W. In this case, since the resistances Ri of the N comb teeth are connected in parallel, the total resistance RbufferT of the buffer layer for half of the cell is given by the following equation. ρ is the resistivity of the conductive path. Ri = ρx(Wa / (Laxt)) [1] RbufferT = 1 / (1 / R1 + 1 / R2 + ··· + 1 / Ri + ··· + 1 / RN) [2]

[0025] As a result, when the surface area {Nx(La + Lb)xW} of the two-comb-tooth-type buffer layer of the present invention is the same as that of the conventional simple stripe-type buffer layer, the cross-sectional area of the conductive path is smaller by the cross-sectional area of the insulator between the comb teeth. Therefore, the total resistance Rbuffer of the two-comb-tooth-type buffer layer can be increased accordingly. Thus, carriers from the p collector can be injected and started with a smaller current Isb, and the IGBT can be turned on. Since Isb is smaller, the voltage drop in the drift layer is also smaller, and the Vsb of the snap-back phenomenon immediately before the IGBT is turned on can be reduced. Also, by further reducing only the length La of the comb teeth, the total resistance RbufferT of the buffer layer can be further increased. In this way, according to the present invention, since Rbuffer can be increased or decreased by the comb tooth length La and the comb tooth width Wa, it is easy and flexible to eliminate the snap-back phenomenon or suppress it within an allowable range. In addition, in FIG. 4, the lengths of both comb teeth are made approximately the same as the length of the cell and are lengthened. By equally dividing and providing a plurality of them in the length direction and connecting them in parallel, the degree of freedom in manufacturing and design can be expanded and it can be made easily and flexibly. Further, by equally dividing the cell itself in the length direction and providing a plurality of them and connecting them freely, the degree of freedom in manufacturing and design can be further expanded and it can be made easily and flexibly.

[0026] In addition, in order to solve the above-described problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, In the comb tooth region, as shown in FIG. 6, by alternately providing an insulating projection (hereinafter referred to as an insulating projection) connected to the upper adjacent insulating region portion and an insulating projection connected to the lower adjacent insulating region portion, a conductive path made of a semiconductor is formed between the comb tooth assembly portion and the short-circuit region. This buffer layer is defined as a double comb tooth type buffer layer with insulating projections and will be described by this name hereinafter. This double comb tooth type buffer layer with insulating projections is zigzagged in the width direction of the cell within the comb teeth. Compared with the comb tooth-shaped buffer layer of the double comb tooth type buffer layer in FIG. 4, the length can be increased and the width can be narrowed. Therefore, when the thickness of the buffer layer is the same, the resistance Ri of the comb teeth of the buffer layer can be increased, and the total RbufferT of the parallel resistance of N comb teeth can also be increased. As a result, carrier injection from the p collector can be started with a smaller current Isb, and the IGBT can be turned on. Since Isb is even smaller, the voltage drop in the drift layer is even smaller, and Vsb of the snap-back phenomenon immediately before IGBT turn-on can be made even smaller. In this double comb tooth type buffer layer with insulating projections, by making the surface area of the comb teeth the same, increasing the number of projections, and further reducing the width of the projections, the total resistance RbufferT can be further increased. Thus, by setting the number and shape of the projections, it can be set easily and flexibly for the purpose of eliminating or suppressing the snap-back phenomenon within an allowable range.

[0027] In addition, in order to solve the above-described problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, The reverse-conducting IGBT cell can be applied and developed to various structures other than the stripe structure, such as polygonal structures like the honeycomb structure in FIG. 8. These polygonal structure cells are relatively easy to apply the trench gate structure. As a result, the cell can be significantly miniaturized, and the economic effect due to low loss and reduction of chip area can be greatly increased. Also, similar to the above-described double comb-shaped buffer layer, by providing insulating protrusions in the triangular semiconductor region, the conduction path resistance can be increased, and by setting the number and shape of the protrusions, it can be easily and flexibly set for the purpose of eliminating the snap-back phenomenon or suppressing it within an allowable range. Furthermore, in each of the triangular insulating regions, for example, it is divided into three triangles with the center as the vertex, and the left and right two in contact with the semiconductor region are made into semiconductor regions, and only the middle one remains as the insulating region, etc., to substantially reduce the area of the insulating region. Thereby, the collector area within the cell can be increased, the on-resistance can be reduced, and the turn-off time can also be reduced.

[0028] Also, in order to solve the above-described problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, In addition to the reverse-conducting IGBT standard cell, it is configured to alternatively include a reverse-conducting IGBT standard cell with a smaller cell width or a reverse-conducting IGBT cell with a different small cell width other than the standard cell around it. Thereby, while eliminating or significantly suppressing the snap-back phenomenon in the reverse-conducting IGBT standard cell, more reverse-conducting IGBT cells can be integrated within the active region of the same dimension, the on-resistance can be reduced, and more reverse-conducting IGBT cells with smaller cells and shorter turn-off times can be integrated, and further loss reduction can be expected.

[0029] Also, in order to solve the above-described problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, Despite the fact that the vanadium-doped semiconductor epitaxial film has semi-insulating properties, homoepitaxial growth without crystal mismatch on the drift layer is easy, and it has good compatibility with the manufacturing processes of the front and back reverse-conducting IGBT semiconductor devices. Ion implantation for forming a conduction path can be performed directly before forming the collector layer, and the ion implantation depth can be reduced by the thickness of the collector. As a result, the implantation energy can be reduced, eliminating the need for expensive ultra-high energy ion implantation equipment. Additionally, implantation damage can be reduced, mask formation for selective ion implantation can be simplified, and the yield can be improved, thus promising high economic efficiency. Moreover, the vanadium doping layer has a function of suppressing the growth of stacking defects, and an effect of suppressing the on-voltage degradation of reverse-conducting IGBTs and built-in pn diodes for flywheeling is expected.

[0030] Also, in order to solve the above-mentioned problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, In the manufacturing method of the reverse-conducting IGBT semiconductor device, after the n-buffer layer formation step, the p-collector formation step is carried out, and then a trench-type insulator region formation step similar to the trench gate formation steps of known MOSFETs and IGBTs is selectively performed. However, the insulating oxide film formed after trench formation is made sufficiently thicker than in the case of trench gates, and the concave oxide film is filled with the subsequent p-epitaxial layer 57 for ohmic contact and polished and smoothed. Thereby, a p-collector layer with the same shape can be simultaneously formed directly under the conduction path of the n-buffer layer, reducing the number of process steps. Moreover, it can be effectively utilized to form a voltage drop that promotes the injection from the p-collector for the on-current of the MOSFET part, and it is also effective for Isb reduction.

[0031] Also, in order to solve the above-mentioned problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, In the method for manufacturing the reverse-conducting IGBT semiconductor device, after the semiconductor buffer layer formation step, a p collector formation step is carried out, and then selective ion implantation is carried out for selectively forming insulating protrusions or insulating material regions within the semiconductor region of the buffer layer. That is, a photomask for selective implantation is provided, and oxygen, vanadium ions, etc., which are insulating or semi-insulating dopants with ultra-high resistance, are selectively implanted from the p collector side to the drain layer except for the conductive path portion of the buffer layer. Then, annealing for recovering damage caused by the ion implantation is carried out. Thereby, a p collector layer having the same shape can be simultaneously formed directly under the n buffer layer serving as the conductive path, the number of process steps can be reduced, and the on-current of the MOSFET portion can be effectively utilized for forming a voltage drop that promotes injection from the p collector of the IGBT, and Isb reduction can also be achieved. Also, in order to solve the above-described problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, In the method for manufacturing the reverse-conducting IGBT semiconductor device, after forming the drain layer, a vanadium-doped epitaxial growth step is carried out, and then a step of forming a conductive path having the same first conductivity type as the drain layer by selective ion implantation of nitrogen into this vanadium-doped epitaxial layer is performed. Thus, portions where nitrogen is not implanted automatically become insulating regions or semi-insulating regions. Thereafter, a collector layer of the second conductivity type is formed by epitaxial growth, and a collector layer with high-quality crystallinity and no crystal structure mismatch with the vanadium-doped epitaxial layer can be formed. Also, since it is not necessary to penetrate the collector layer, the implantation energy is small, an ordinary ion implantation device can be used, the implantation damage is small, annealing for recovery is thus easy, and the mask for selective implantation is also simple, resulting in high economic efficiency.

[0032] Also, in order to solve the above-described problems and achieve the object of the present invention, according to the reverse-conducting IGBT semiconductor device of the present invention, In the method of operating a reverse-conducting semiconductor device, after the temperature of the built-in pn junction diode is raised to a temperature equal to or higher than the on-voltage degradation suppression temperature by the heat generated by the conduction of the majority carrier current in the MOSFET section, predetermined electrical operations are performed. As a result, it is possible to suppress characteristic degradation due to element damage caused by on-voltage degradation of the built-in pn junction diode or IGBT peculiar to the SiC bipolar device caused by stacking defects and higher-order snap-back phenomena.

Advantages of the Invention

[0033] As described above, according to the present invention, a reverse-conducting IGBT, which is a typical reverse-conducting semiconductor device, uses a buffer layer with a high impurity concentration that is advantageous for achieving ultra-high breakdown voltage with low loss, and can eliminate or suppress the snap-back phenomenon to an allowable range with a significantly smaller cell area. When the active regions have the same dimensions, more cells can be integrated by the reduction in cell area, resulting in lower losses. Further, due to the miniaturization of the cells by reducing the cell area, the residual carriers during turn-off can be effectively discharged, reducing the turn-off time and switching losses. In addition, the built-in pn diode of the cell can be utilized as a flywheel diode, eliminating the need to separately provide it inside and outside the chip, significantly reducing the chip area, and by the TEDREC operation method that utilizes the heat generated by the conduction of the majority carrier current in the MOSFET section, it is possible to eliminate or significantly suppress the on-voltage degradation and characteristic degradation due to higher-order snap-back of the SiC-specific reverse-conducting IGBT and the built-in pn diode.

Brief Description of the Drawings

[0034]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8a

Figure 8b

Figure 9

Mode for Carrying Out the Invention

[0035] Hereinafter, with reference to the drawings, the high-voltage wide-gap reverse-conducting semiconductor device of the present invention will be described in more detail using examples. In this specification and the accompanying drawings, in the layers and regions preceded by n or p, it means that electrons or holes are the majority carriers, respectively. In the case of the same layer or region, the numbers and arrows indicating the layers and regions in the drawings are, in principle, each represented by only one, and the others are mostly omitted. Each drawing is a schematic diagram for better explaining the invention, and there is no correlation such as proportionality in the dimensions within each drawing and between the drawings.

Examples

[0036] The first embodiment of the present invention is a 15 kV-class SiC double comb buffer layer type ultra-high voltage reverse-conducting IGBT made of 4H-SiC. FIGS. 2 to 4 are schematic diagrams for explaining this embodiment. FIG. 2 is a plan view of the chip surface of Example 1, FIG. 3 is a cross-sectional view of the cell, and FIG. 4 is a plan view of the buffer layer of the cell. Note that FIG. 3 shows a cross-sectional view of the portion corresponding to the dotted line A - B in the plan view of the buffer layer of FIG. 4.

[0037] First, the main planar configuration of the surface of Example 1 will be described with reference to FIG. 2. Hereinafter, for the sake of avoiding complexity and facilitating understanding, the description will be made with respect to an n-channel type reverse-conducting IGBT. In the center of the chip in FIG. 2, an active region 2 composed of stripe structure IGBT cells is provided like a thick line, and a breakdown voltage structure for realizing the breakdown voltage is provided so as to surround this active region 2. In the case of this Example 1, this breakdown voltage structure is composed of, for example, a JTE (Junction Termination Extension) 3 for electric field relaxation, a field region 4, and then an n-channel stopper 5 in order from the closest to the active region. The chip size of the reverse-conducting IGBT is 8 mm x 8 mm, and the size of the active region 2 is about 6 mm x 6 mm. The width of the breakdown voltage structure includes the difference between the sum of an integer number of standard cell widths and 6 mm and also includes a dicing region, and is made wider than the originally necessary width and is about 1 mm. One or a plurality of cells of the two-comb buffer layer type reverse-conducting IGBT according to the present invention are provided in the active region 2. FIG. 3 shows a case where there are 4 cells for the purpose of principle explanation.

[0038] FIG. 3 is a cross-sectional view of the reverse-conducting IGBT standard cell of FIG. 2, and is a cross-sectional view of a portion corresponding to the portion between the dotted lines A - B in the plan view of the buffer layer of FIG. 4 as described above. The schematic configuration will be briefly described below. Each reverse-conducting IGBT cell is configured by connecting an IGBT part and a MOSFET part in parallel. On one main surface side of FIG. 3, a MOS surface part region 114 where MOS surface parts shared by both the MOSFET part and the IGBT part constituting each reverse-conducting IGBT cell are gathered is provided, and an emitter main electrode 113 of the reverse-conducting IGBT is provided on the uppermost surface. A current density increasing layer CEL106 is provided between the MOS surface part region 114 and the n-drift layer 100. In the p - body region 107, there are about two regions that function as an n - emitter region 108 for the IGBT part and as an n - source region for the MOSFET part, which are provided separately. On the right end of the p - body region 107 and above the right end of the right - hand n - emitter region 108, a gate electrode 112 is provided via a gate oxide film 111. When a predetermined gate voltage is applied to the gate electrode 112 during operation, a channel 109 is formed. The same applies to the left - hand side of the p - body region 107. The exposed surface of the p - body region 107 between the two n - emitter regions 108 (or between the n - source regions) functions as an ohmic contact 110 and is directly connected to the emitter main electrode 113 of the reverse - conducting IGBT. The n - emitter region 108 (or the n - source region) is also directly connected to the emitter main electrode 113 of the reverse - conducting IGBT. However, each gate electrode 112 is insulated from the emitter main electrode 113 via an insulating film 115. A number of MOS surface parts with such a structure gather to form a MOS surface part region 114. Each n - emitter region 108 (or n - source region) is electrically connected via the emitter main electrode 113, and each gate electrode 112 is also electrically connected to a gate main electrode (not shown).

[0039] Also, in contact with the back surface of the n - drift layer 100 from one main - surface side toward the other main - surface (back surface), a buffer layer 104 composed of nSiC conductive paths 116, 116Y, 118 and an insulator region 117 is provided. Further, in contact with the back surface of the n - buffer layer 104, a p - collector layer 102 of the IGBT part, an ion - implanted collector region 117Z, and an n - short - circuit region (also serving as the drain region of the MOSFET part) 103 are provided. The n - short - circuit region 103 is provided in substantially the same shape, facing and contacting only the conductive path 116Y corresponding to the comb - tooth gathering part at both ends of the cell. These are provided in contact with the collector main electrode 101 of the reverse - conducting IGBT. Also, the p - collector layer 102 is provided facing the conductive path 116 of the buffer layer, and the ion - implanted collector region 117Z is provided facing the insulator region 117 of the buffer layer in substantially the same shape. All the gate electrodes are connected and aggregated and connected to the gate main electrode (not shown) of the reverse - conducting IGBT.

[0040] Next, the operation leading to turn-on during forward biasing of the reverse-conducting IGBT standard cell with the above configuration will be briefly described below. In FIG. 6, the main current paths a and b of the on-current of the MOSFET section during forward biasing are schematically shown by dotted lines. That is, the current of the MOSFET section with a stripe structure flows through the route of emitter main electrode 113 → source region 108 → channel region 109 → drift layer 100 → conduction path 116 to 116Y in the buffer layer → n short-circuit region 103 → collector main electrode 101. Focusing on the IGBT section, the conduction path from 116 of the n comb-shaped buffer region 104 to 116Y via the comb teeth 118 is connected to the p collector 102 to form a pn junction. When the voltage drop in the conduction path due to the current flowing through the above route exceeds the built-in voltage Vbi (about 2.7 V) of SiC, the injection of holes starts from the p collector 102 and eventually leads to the turn-on of the IGBT section.

[0041] Regarding the main structural factors of the standard cell in this Example 1, for example, the following values are selected. The impurity concentration and thickness of the n emitter region 108 are 5e19 cm -3 and 0.3 μm, the impurity concentration and thickness of the p body region are 1e18 cm -3 and 0.6 μm, the impurity concentration and thickness of the nCSL are 5e16 cm -3 and 0.3 μm, the impurity concentration and thickness of the n drift layer are 2 to 5e14 cm -3 and 150 μm, the impurity concentration and thickness of the n buffer layer are 1e17 cm -3 and 2 μm, the impurity concentration and thickness of the p collector layer are 4e18 cm -3 and 1 to 3 μm.

[0042] Next, the snapback phenomenon of this embodiment will be described. The generation mechanism of the snapback phenomenon during forward bias is almost the same as the mechanism disclosed in Patent No. 7385932 of the prior art documents and Non-Patent Document 3 by the present inventor. Therefore, the general explanation will be omitted by referring to the above publication, and the description will be focused on the main part that expresses the features of the present invention, and first, the analytical expressions of Vsb, Isb, and Rbuffer necessary for quantitative description in each embodiment will be

[0043] summarized and shown in

[0044] and an analysis example of Vsb and Rbuffer in Example 1 using these analytical expressions will be shown in

[0043] <Analytical Expressions of Vsb, Isb, and Rbuffer> FIG. 5 schematically shows the main current paths a and b of the on-current of the MOSFET section during forward bias. That is, the current of the stripe-structured MOSFET flows through the route of emitter main electrode → source region → channel region → drift layer → comb-axis part of the conductive path of the double comb-shaped conductive path in the buffer layer → conductive path of the comb teeth → conductive path of the comb tooth collection part → n short-circuit region → collector main electrode. Focusing on the IGBT section, the n-comb-shaped buffer region 104 is connected to the p collector 102 to form a pn junction. When the voltage drop of the current flowing through the conductive path of the comb-shaped buffer region exceeds the built-in voltage Vbi 2.7V of SiC in the above route, the injection of holes starts from the p collector 102 and finally leads to the on-state of the IGBT section. The Vsb just before the turn-on of the SiC reverse-conducting IGBT flowing through such a route can be approximated by Equation [3]. Vsb = Isb×Rch + Isb×Rdrift + Vbi [3] Here, Rch is the channel resistance of the MOS gate, Rdrift is the resistance of the drift layer, and Vbi is the built-in voltage of the collector junction. In a high-voltage reverse-conducting IGBT, Rch is significantly smaller than Rdrift and can be ignored. Focusing on the current path a, when the voltage drop caused by Isb flowing through the buffer layer reaches Vbi of the collector junction of SiC, the injection of holes from the collector junction of the SiC reverse-conducting IGBT into the drift layer starts and the IGBT part begins to turn on. Therefore, Isb can be approximated by Equation [4] assuming the lateral resistance in the n-buffer layer conduction path in the current path a is Rbuffer. Isb = Vbi / Rbuffer [4] Here, Rbuffer is the resistance of the n-buffer layer conduction path on the p-collector surface from the center of the p-collector (Wp / 2) to the collector electrode. However, the + resistance of the short-circuit region is ignored because its impurity concentration is high and its thickness is thin. Since Isb flows through the non-depleted part of the buffer layer due to the Vbi of the junction formed between the p-collector layer and the n-buffer layer conduction path, Rbuffer can be approximated by Equation [5]. Rbuffer = ρbuffer x (Wp / 2) / {(Tbuffer - Tdep-buffer) x Lcell} [5] Here, ρbuffer is the resistivity of the n-buffer layer conduction path, Tbuffer is its thickness, and Lcell is its length in the direction perpendicular to the paper surface (6 mm). Tdep-buffer is the depletion layer thickness in the n-buffer layer when a Vbi of 2.7 V is applied and can be approximated by Equation [6]. Tdep-buffer = {(2ε / q) x (Na / Nd) + (Vbi / (Nd + Na))} 0.5 [6] Na and Nd are the impurity concentrations of the p-collector layer and the n-buffer layer conduction path, respectively. Using Rbuffer obtained from Equation [5], Isb can be obtained from Equation [4], and Vsb can be calculated from Equation [3].

[0044] FIG. 4 shows a plan view for explaining the structure of the double comb-shaped buffer layer 104 of the SiC reverse-conducting IGBT cell. Focusing on the structure of the buffer layer for one cell, it is in the shape of double combs. That is, there is a conduction path 116 corresponding to the axis of the double combs made of nSiC in the center (hereinafter referred to as the comb axis), and conduction paths corresponding to the comb teeth made of nSiC semiconductor are provided by connecting five each on the left and right. The space between the comb teeth is composed of an insulator region 117. In this specification, the buffer layer of this shape is defined as a double comb-shaped buffer layer, and will be described by this name hereinafter. When the length of the SiC semiconductor region constituting the comb teeth 116 is La, the length of the insulator region 117 constituting the space between the comb teeth is Lb, the length of the cell is L, and the widths of the insulator regions 117-2 at the upper and lower ends of the cell are each 0.5Lb, L = N(La + Lb) [7] and in the case of FIG. 4 for principle explanation, N is 5. Since the length of the cell Lcell is 6 mm, therefore (La + Lb) is 1200 μm. When La = Lb is set, each becomes 600 μm. Since the 6 mm active region in FIG. 2 is composed of 4 cells, the cell width is 1500 μm. When the width of the p collector is Wp, the width of the double combs, that is, Wp / 2, is 730 μm considering the width of 20 μm of the comb axis and the comb tooth assembly. Since the length of the comb teeth La is 600 μm, Rbuffer can be calculated from Equation [5] and becomes 1795 Ω. Since five comb teeth are connected in parallel, the total resistance RbufferT is 359 Ω. Therefore, Isb is calculated to be 7.5 mA from Equation [4], and Vsb is calculated to be 17.8 V from Equation [3]. When the cell width (=Wp + Wn) is 3040 μm, Vsb can be suppressed to 10.0 V. In the conventional example where the buffer layer has a simple stripe structure, in order to suppress Vsb to 10.0 V, when the impurity concentration of the conduction path of the buffer layer is the same 1x19 17 cm -3 it is necessary to set the cell width to 6110 μm which slightly exceeds the active region width. Therefore, the effect of using the double comb buffer layer type reverse-conducting IGBT standard cell of this embodiment is obvious, and the cell can be miniaturized to approximately half. For example, if (La+Lb) is kept constant at 1200 μm, the resistance of the comb teeth can be increased as La is made smaller than Lb, allowing the cell to be further miniaturized while still maintaining the same Vsb of 10.0 V.

[0045] Next, the main process flow (5a) to (5f) for fabricating the double-tooth comb buffer layer type reverse conducting IGBT of this embodiment will be briefly described below with reference to FIG. (5a): First, a 200 μm thick n-type drain layer 51 is epitaxially grown on a 4-layer hexagonal n-type SiC off-angle single crystal wafer 50 having a diameter of 4 inches. Next, an n-buffer layer 52 and a p-collector layer 53 are epitaxially grown. Considering the possibility of forming these layers by ion implantation, the thickness of these layers is preferably about 1 to 2 μm.

[0046] (5b): Then, the inter-tooth insulator region is formed. For this, one of the following various methods such as <Method a>, <Method b>, and <Method c> is selected in consideration of the device structure and the economics of the process, but in most embodiments, including this embodiment, both <Method a> and <Method b> are tried for comparison. In any case, it is important to form the inter-tooth insulator region 54 so that it runs from the p collector side through the p collector 53, over the n buffer layer 52, and completely reaches the drain layer 51, and to form the conductive path 55 from the desired shape of the comb tooth, i.e., the comb axis 116 to the short-circuit region 116Y. In addition, <Method c> requires many considerations regarding maintaining the semi-insulating properties of the vanadium epitaxial layer at high temperatures, and in this patent, it is only applied to Example 8. <Method a> This is a method of repurposing the gate formation process of high-voltage SiC trench gate type or U-trench gate type MOSFET to form the inter-comb insulator region. This embodiment may require modification and improvement in that the trench width is wide and the trench depth is somewhat deep. For example, in order to cope with a wide insulating region, a technique such as forming a plurality of trenches or U-grooves close to each other and arranging them adjacent to each other in parallel may be adopted. In addition to the conventional electric field relaxation technique at the trench corner, an electric field relaxation technique for coping with a high electric field may be additionally applied. In the case of <Method a>, for example, after removing the p-collector or n-buffer layer in the portion where the insulating region is formed by dry etching or the like, an insulating oxide film is formed on the exposed trench etching wall for coating, and further, the recesses in the oxide film are filled and planarized by polishing with polycrystalline Si or a p-epitaxial layer 57 for ohmic contact. Since it is a reverse-conducting IGBT, the voltage applied between the p-collector and the n-buffer is low, and the risk of deterioration of characteristics due to these fillings is relatively small. <Method b> This is a method of improving SIMOX technology or the like for high breakdown voltage and applying it to the formation of the insulating region between the comb teeth. In this embodiment, it is necessary to perform selective ion implantation about 3 to 5 μm deep so that insulating or semi-insulating ions such as oxygen ions and vanadium ions completely reach the drain layer through the p-collector layer and beyond the n-buffer layer. For this reason, it is important to implant ions at a high voltage, and it is necessary to use a 60 MeV-class high-voltage ion implantation device equipped with a 15 MeV-class tandem accelerator or the like that has an implantation record of a depth of 10 μm or more. Furthermore, it is important to use a mask for selective ion implantation that can withstand such high-voltage selective ion implantation, and it is important to apply an annealing technique to eliminate implantation damage such as defects generated during implantation. In the case of the above <Method b>, the p-collector facing the insulating region may have a large implantation damage of oxygen ions and require an advanced annealing technique. However, unlike the collector portion under the conduction path, this portion of the collector does not need to function as a complete collector, and it only needs to function as a substance with low conductivity. Moreover, since it is reverse-conducting, the applied voltage is also small, so it is less likely to cause an obstacle to the reverse-conducting IGBT characteristics. <Method c> In addition, after epitaxially growing an n-type drain layer 51 on the above-described n-type SiC off-angle single-crystal wafer 50, an epitaxial growth of a vanadium-doped semi-insulating layer 71 is performed, and then a conductive path 55 such as a comb tooth or a comb axis having a desired shape is formed by selective ion implantation of nitrogen. Naturally, since the insulating region between the comb teeth is covered with a mask, it remains as a semi-insulating region after the selective ion implantation. This method requires less man-hours and can be performed with a high-voltage ion implantation apparatus having a relatively low implantation energy, and has advantages such as less implantation damage. Further, the subsequently grown p-collector epitaxial layer and the vanadium-doped epitaxial layer have almost no crystal mismatch and can form a high-quality collector, achieving good device characteristics. On the other hand, there are unstable matters in maintaining semi-insulating properties at high temperatures and improvements are required.

[0047] (5c): Next, a mask for selective ion implantation for forming the n-short circuit region 56 is formed, and high-concentration nitrogen ion implantation is performed. (5d): Thereafter, a high-concentration p-epitaxial layer 57 for ohmic contact having a thickness of about 60 μm is formed. This thickness is selected so as to have a strength that does not cause breakage during the manufacturing process of the wafer. Then, this epitaxial wafer is turned upside down, and the n-type drain layer portion is cut along the dotted line portion in FIG. (5c) parallel to the epitaxial growth surface to separate the n single-crystal substrate, and then the cut surface of the n-type drain layer is polished. For example, an n-drain layer 51 having a thickness of about 150 μm corresponding to the withstand voltage in use, an n-buffer layer having a thickness of 1 to 2 μm, a p-collector layer having a thickness of about 2 μm, and further a p-epitaxial layer 57 for ohmic contact are formed. The SiC wafer is finished. (5e): Next, an n-type current density increasing layer CEL58 is formed on the n-type drain layer of this SiC wafer. (5f): Next, a MOS surface region 59 excluding the emitter main electrode is formed on the n-type current density increasing layer CEL58 by utilizing manufacturing methods for high-voltage SiC MOSFETs, high-voltage Si power ICs, etc. Thereafter, an emitter main electrode 60 and a gate main electrode are formed, and further a collector main electrode 61 is formed and diced to complete a double-comb buffer layer type reverse-conducting IGBT element.

[0048] Next, the operation and typical characteristics of this embodiment will be described. The above-described double-comb buffer layer type reverse-conducting IGBT element is die-bonded to a TO-type package, and a plurality of Al (aluminum) wires with a diameter of 100 μm for connection are wire-bonded onto the emitter main electrode 113, and further wire-bonded to the gate main electrode with Al wire. Then, the chip and the Al wire are coated with nanotech resin, which is a high heat-resistant resin for protection, to finish the reverse-conducting IGBT semiconductor device, and then an operation test is carried out.

[0049] The breakdown voltage between the collector main electrode and the emitter main electrode measured with the emitter main electrode and the gate main electrode short-circuited is about 16.6 kV, which is good. It shows good forward blocking characteristics, and the leakage current at 12 kV applied at room temperature is typically 5.5x10 -5 A / cm 2 or so.

[0050] When a gate voltage equal to or higher than the threshold voltage is applied to the gate main electrode, and then a voltage is applied between the collector main electrode 101 and the emitter main electrode 113 so that the potential of the collector main electrode is higher than the potential of the emitter main electrode, that is, in a so-called forward direction state, an on-current starts to flow from near zero volts. As this applied voltage is increased, the on-current increases almost linearly. This is because the MOSFET part turns on. When the applied voltage is further increased, the on-resistance per unit area at around 5 V is about 220 mΩ·cm 2 and an output current of about 8 A can be obtained. This is a sufficient current for suppressing the on-voltage degradation specific to SiC by the TEDREC method described later.

[0051] The on-voltage at 80 A / cm 2 when the reverse-conducting IGBT is on is 5.4 V, and the on-characteristics are good. Also, the turn-on time is approximately 280 ns and the turn-off time is approximately 550 ns, which are good, and high-speed operation can be realized. The effects of miniaturizing the cells by changing the buffer layer described in

[0041] to a double-comb buffer layer contribute to these. In Fig. 4, the lengths of both combs are made approximately the same as the length of the cell and are lengthened. By equally dividing them into a plurality of cells in the length direction and connecting them, the degrees of freedom in manufacturing and design can be expanded, making it easy and flexible.

[0052] Also, due to stacking defects in the element, so-called on-voltage degradation occurs in which the internal resistance of the SiC-IGBT particularly increases during energization, resulting in an increase ΔVon in the on-voltage and a significant reduction in reliability. There was also concern that the above on-voltage degradation would be accelerated by higher-order snapback with a large Isb associated with the snapback phenomenon. Furthermore, ΔVon due to on-voltage degradation is superimposed on Vsb associated with the snapback phenomenon, and there were concerns about malfunctions due to an increase in the generated noise voltage during operation, and operational failures and element damage due to imbalance in the switching operation balance of IGBT modules with a plurality of elements connected in parallel. However, the reduction of Vsb and the application of the TEDREC method operation according to this embodiment are effective, and the variation in the on-voltage remains below 0.2V even in stress tests such as a 1000-hour energization test, and no significant adverse effects on reliability have been found. This TEDREC operation method is disclosed in Japanese Patent No. 5835679 by the present inventor.

[0053] As described above, according to the double-comb buffer layer type reverse-conducting IGBT semiconductor device composed of the stripe structure SiC reverse-conducting IGBT cells of the first embodiment, different from the conventional simple stripe-shaped buffer layer type, even at a high buffer layer impurity concentration suitable for ultra-high breakdown voltage, Vsb can be reduced to 10V, which is the practical allowable level, and in that case, the cell area can be halved compared to the conventional simple stripe-shaped buffer type. By making the length La of the comb teeth smaller than the comb tooth interval Lb, the SB suppression effect can be achieved with a smaller cell area, but since the on-resistance and turn-off time tend to increase, it is necessary to balance them.

Embodiment

[0054] The second embodiment of the present invention is a double-tooth comb buffer layer type reverse-conducting IGBT with a 15 kV class insulating protrusion made of 4H-SiC. Compared with the first embodiment, in order to suppress the snap-back phenomenon at a smaller cell area, the chip structure, device configuration factors, etc. are almost the same except that insulating protrusions are provided by connecting them to the inter-tooth insulator regions within the teeth of the buffer layer. Also, <Method b> described in

[0046] is used for forming the inter-tooth insulator regions and the insulating protrusions.

[0055] FIG. 6 is a schematic diagram for explaining the configuration of the buffer layer 104 of the second embodiment, and FIG. 7 is a cross-sectional view taken along the line C-D corresponding to the dotted line portion passing through the insulating protrusion 119 in FIG. 6. In the comb tooth portion 118 made of the SiC semiconductor in FIG. 6, insulating protrusions 119 made of an insulator on a rectangle are provided. Two insulating protrusions are provided for each comb tooth, and since there are 10 comb teeth per half cell, a total of 20 insulating protrusions 119 exist in one cell. The width of the insulating protrusion 119 is 10 μm, and each insulating protrusion 119 is provided 10 μm away from the inter-tooth insulator regions 117-1 and 117-2 facing the inter-tooth insulator region to which the connected comb teeth are opposed, and the interval between each insulating protrusion 119 is set to 10 μm. As a result, a conductive path with a width of 10 μm is formed in the comb tooth 118. Compared with the resistance of one comb tooth in the first embodiment, since the length of this conductive path is long and the width is narrow, the conductive path resistance becomes significantly large. In this specification, this buffer layer is defined as a double-tooth comb buffer layer with insulating protrusions and will be described by this name hereinafter. In this double-tooth comb buffer layer with insulating protrusions, the resistance of the comb-shaped buffer layer can be arbitrarily set by setting the number and shape of the protrusions, and it is characterized in that Isb and thus Vsb can be arbitrarily set, and the snap-back phenomenon can be eliminated or arbitrarily suppressed to a predetermined allowable level.

[0056] In the actual second embodiment, unlike the plan view for explaining the configuration of FIG. 6, in order to further increase the snap-back phenomenon suppression effect, eight insulating protrusions 119 are provided per comb tooth, so 80 insulating protrusions 119 are provided in one cell. Also, since there are eight insulating protrusions per comb tooth, the total width of one comb tooth is 170 μm, so the cell width is 380 μm. On the other hand, the conductive path length per comb tooth is 4290 μm, and the conductive path resistance is about 631 kΩtp. Since five comb teeth are connected in parallel per half cell, the total conductive path resistance RbufferT of the buffer layer for half cell is about 125 kΩ. As a result of the analysis in

[0044] , the voltage drop due to the current flowing through the conductive path of the comb-tooth-shaped buffer region with insulating protrusions exceeds 2.7 V of the built-in voltage Vbi of SiC, and the current Isb at the start of hole injection from the p collector 102 is about 21 μA, which is significantly small. Therefore, the voltage drop in the drift region is as small as 0.04 V, and Vsb immediately before the IGBT part turns on can be made as small as about 2.74 V.

[0057] For example, based on the analysis method of

[0043] disclosed in the prior patent document 2, for a 15 kV-class reverse-conducting IGBT with a buffer layer of a conventional stripe structure cell of 1x10 17 cm ―3 In the case of, to suppress the snap-back phenomenon to Vsb of 10 V, which is an acceptable level in practical use, it was necessary to set the width Wp of the p collector to 6110 μm. However, in the case of the second embodiment, even when Wp is 380 μm, Vsb can be suppressed to 2.74 V. After snap-back, an on-current of the IGBT flows, so the on-voltage is 3.7 V in the case of a 15 kV-class ultra-high voltage withstand IGBT as shown in FIG. 1 for example. However, since Vsb of this embodiment is smaller at about 2.74 V, the snap-back phenomenon is eliminated. In the case of the first embodiment, it is difficult to eliminate Vsb, and it was necessary to set Wp to 3040 μm even to make Vsb within the allowable range of 10 V. However, in the second embodiment, there is a great effect that the snap-back phenomenon can be eliminated with a significantly smaller cell width of 380 μm.

[0058] Next, the operation and typical characteristics of the reverse-conducting IGBT of the second embodiment will be described below. The reverse-conducting IGBT element was mounted in a TO-type package in the same manner as in Example 1 and after being finished into a reverse-conducting IGBT semiconductor device, an operation test was carried out. The breakdown voltage between the collector main electrode 101 and the emitter main electrode 113 measured with the emitter main electrode and the gate main electrode short-circuited was about 16.2 kV, which was good. When a forward voltage is applied between the collector main electrode 101 and the emitter main electrode 113 without applying a gate voltage, a leakage current flows, but it shows good forward blocking characteristics. The leakage current is typically 4x10 -5 A / cm 2 or so, which is good.

[0059] When a gate voltage equal to or higher than the threshold voltage is applied to the gate main electrode and then a voltage is applied so as to be in a so-called forward state, an on-current starts to flow from near zero volts and the on-current increases almost linearly. This is because the MOSFET part is turned on. When the applied voltage is further increased, the current starts to increase rapidly from around 2.7 V which is the built-in voltage. This is because the IGBT part also turns on and its on-current starts to flow superimposed. The on-resistance per unit area below the built-in voltage is about 185 mΩ·cm 2 and a considerable output current can be taken out even at a forward voltage below the built-in voltage, and it can be utilized for countermeasures against on-voltage degradation described later, etc., and high performance can be achieved.

[0060] On the other hand, the differential on-resistance per unit area above the built-in voltage of the IGBT is about 32 mΩ·cm 2 and the on-voltage at 80 A / cm 2 is 5.5 V and the on-characteristics are good. Also, the turn-on time is approximately 310 ns and the turn-off time is approximately 570 ns, and high-speed operation can be realized. In addition, by applying the above-mentioned TEDREC operation method, even in a long-term energization test, the on-voltage degradation and the rapid on-voltage degradation due to the higher-order snap-back phenomenon are limited to 0.2 V or less, and no significant adverse effect on reliability is found, which is good.

[0061] As described above, although the second embodiment has an ultra-high breakdown voltage of 15 kV, the double comb buffer layer type SiC reverse conduction IGBT structure with insulating protrusions is effective, the snap-back phenomenon can be eliminated with a significantly small cell area, and high noise resistance performance and high cost-effectiveness can be achieved. In addition, since the cell area can be made significantly smaller, the residual carriers can be quickly discharged during turn-off, the turn-off time can be shortened, high-speed operation becomes possible, and the turn-off loss can be significantly reduced.

Embodiment

[0062] The third embodiment of the present invention is a 15 kV class double comb buffer layer type reverse conduction IGBT made of 4H-SiC. While maintaining the snap-back phenomenon suppression effect compared to the first and second embodiments, the on characteristics and switching characteristics are improved. Except for reducing the comb tooth length La and the length Lb of the insulating region between the comb teeth, the element configuration factors, dimensions, and impurity concentrations are the same as those in the second embodiment described in

[0038] . Compared with the conventional reverse conduction IGBT with a stripe structure in the first and second embodiments, the on-voltage at the same conduction current is relatively large, and the switching time is also relatively large. As a result of investigating the cause, it was considered that this was due to the fact that the comb tooth buffer layer, which is a feature of the present invention provided to eliminate or significantly suppress the snap-back phenomenon, is configured to include an insulating region in addition to the wide-gap semiconductor region serving as the conduction path. That is, when the comb tooth buffer layer type reverse conduction IGBT of the present invention is turned on, the conduction path in the comb tooth is energized to inject holes from the p collector under the conduction path to first turn on and energize the IGBT portion facing the p collector. Then, the on-current region is expanded to the drain region on the insulating region close to the on-current conduction region, and subsequently, the on-region is further expanded to the drain region on the insulating region slightly farther away. This operation is sequentially repeated to turn on the entire cell. Therefore, in the drain region on the insulating region, the current density gradually decreases as the distance from the p collector region increases, so the on-voltage increases when compared at the same current level.

[0063] Also, at turn-off, carriers are sequentially discharged from the portion close to the short-circuit region and the portion close to the short-circuit region of the conductive path connected to the short-circuit region. Finally, almost all of the residual carriers in the insulator region away from the short-circuit region and the conductive path are discharged to complete the turn-off operation. Therefore, due to the presence of the insulator region compared with the conventional reverse-conducting IGBT, it is considered that the elimination of carriers in the insulator region farther from the short-circuit region and the conductive path becomes slower and the turn-off time becomes longer. In the case of Example 2, although there are insulating protrusions, the width is as small as about 10 μm, so it is considered that the influence on the above operation mechanism is small. Therefore, in this Example 3, a measure was taken by reducing the length Lb of the insulator region so that the distance in the insulator region farthest from the short-circuit region and the conductive path connected thereto becomes shorter. At the same time, the width La of the comb teeth was also reduced to the same length as the insulator region.

[0064] Specifically, in Example 1 and Example 2, the length Lb of the insulator region was reduced from 600 μm to 1 / 6, which is 100 μm, and La was also reduced to the same 100 μm. However, the structures of other chips and device configuration factors are almost the same. As a result, the maximum distance from the conductive paths on both sides adjacent to the insulator region is as large as 300 μm in the cases of Example 1 and 2, but in this example, it is 1 / 6, which is 50 μm. Although it varies depending on the carrier lifetime, in the ultra-high voltage IGBT of this example, where known lifetime reduction suppression and lifetime increase are also achieved, if it is up to about 50 μm, the spread of current during turn-on and the discharge of carriers from the insulator region during turn-off are relatively rapid, and it can be expected that the on-voltage and turn-off time can be reduced.

[0065] On the other hand, regarding the snap-back phenomenon, in the actual Example 3, different from the plan view for configuration explanation in FIG. 6, in order to further increase the snap-back phenomenon suppression effect, 8 insulating protrusions 119 are provided per comb tooth as in Example 2. Therefore, the total width of the comb teeth is 170 μm, and the cell width Wp is 380 μm. Accordingly, the conductive path length per comb tooth is 790 μm and the resistance is about 540 kΩ. Since 30 comb teeth are connected in parallel per half cell, the conductive path resistance of the entire buffer layer for half cell is about 8.5 kΩ.

[0066] Based on the analysis method of

[0049] , the current Isb, that is, the voltage drop due to the current flowing through the conductive path of the comb-shaped buffer region, exceeds 2.7 V of the built-in voltage Vbi of SiC, and the current Isb when the injection of holes from the p collector starts is about 320 μA. As a result, the voltage drop in the drift region is as small as 0.6 V, and Vsb immediately before the IGBT part turns on can be as small as about 3.3 V. Therefore, at the time of switching on, it only switches from Vsb of 3.3 V immediately before turning on to the on-voltage in the vicinity of 3.7 V of the on-voltage immediately after turning on shown in FIG. 1, and the problematic snap-back phenomenon is eliminated and does not occur. For example, based on the analysis method of

[0040] disclosed in the prior patent document 2, in a 15 kV-class reverse-conducting IGBT with a conventional stripe structure cell, when the buffer layer is 1×10 17 cm ―3 and its thickness is 1 μm, even when suppressing the snap-back phenomenon to Vsb of 10 V, which is an acceptable level in practical use, it was necessary to set the width Wp of the p collector to 6110 μm. However, in Example 3, there is a great effect that the snap-back phenomenon can be eliminated even when the width Wp of the p collector is reduced to 380 μm and the cell area is significantly reduced.

[0067] Next, the operation and typical characteristics of the reverse-conducting IGBT of Example 3 will be described below. The reverse-conducting IGBT element was mounted in a TO-type package similar to that of Example 1 and then subjected to an operation test after being finished as a reverse-conducting IGBT semiconductor device. The breakdown voltage between the collector main electrode and the emitter main electrode measured with the emitter main electrode and the gate main electrode short-circuited is about 16.4 kV, which is good. When a forward voltage is applied between the collector main electrode 101 and the emitter main electrode 113 without applying a gate voltage, a leakage current flows, but it shows good forward blocking characteristics. The leakage current is typically 1.5x10 -5 A / cm 2 or so at room temperature.

[0068] Also, the on-voltage at 80 A / cm 2 is 4.9 V, and the on-characteristics are good. Furthermore, the turn-on time is approximately 240 ns, and the turn-off time is approximately 480 ns, which are good, and high-speed operation can be achieved. In addition, even in the long-term energization test applying the above TEDREC operation method, there is no occurrence of on-voltage degradation due to stacking defects or rapid on-voltage degradation due to higher-order snap-back phenomena, and the on-voltage change remains below 0.2 V, and no significant adverse effect on reliability is found, which is good.

[0069] As described above, in this Example 3, the insulated protrusion double comb buffer layer type SiC reverse-conducting IGBT structure is effective, the snap-back phenomenon can be eliminated with a small cell area, and the on-voltage and the turn-off time can be reduced by reducing the comb tooth length La and the length Lb of the insulating region between the comb teeth, and further reduction of loss can be achieved.

Example

[0070] The fourth embodiment of the present invention is a 25 kV-class insulated protrusion double comb buffer layer type reverse-conducting IGBT made of 4H-SiC, which aims to suppress the snap-back phenomenon of a reverse-conducting IGBT with a further significantly increased breakdown voltage in consideration of power utilities etc. compared to the first to third embodiments. The element configuration is the same as that of Example 2 except that the dimensions, impurity concentrations, etc. of each element configuration factor are set so as to be able to handle 25 kV. Examples of the main element configuration factors are shown below. The impurity concentration and thickness of the n-emitter region 108 are 5e19 cm -3 and 0.3 μm, the impurity concentration and thickness of the p-body region are 1e18 cm -3 and 0.6 μm, the impurity concentration and thickness of the nCEL are 4e16 cm -3 and 0.4 μm, the impurity concentration and thickness of the n-drift layer are 2e14 cm -3 and 250 μm, the impurity concentration and thickness of the n-buffer layer are 1e17 cm -3 and 2 μm, the impurity concentration and thickness of the p-collector layer are 4e18 cm -3 and 2 μm.

[0071] Also, both the length La of the comb teeth and the length Lb of the insulator region are 600 μm, and the cell width is 1020 μm. The number of insulating protrusions provided in one comb tooth to form the conduction path is 20, the length of the conduction path is 11600 μm, and its width is 10 μm. When the analysis described in

[0043] is performed, the total resistance RbufferT of the conduction paths of the 5 parallel n-buffer layers is 342 kΩ, Isb is 7.9 μA, and Vsb is about 2.76 V. As a result, the voltage immediately before turning on the 25 kV-class reverse-conducting IGBT is 2.7 V, which is smaller than the on-voltage immediately after turning on of about 3.7 V shown in FIG. 1, so the snap-back phenomenon can be substantially eliminated. The reason why Vsb could be made so small is that by providing 20 insulating protrusions in the comb teeth, the conduction path length could be increased dramatically and Isb could be reduced, resulting in a significant reduction in the voltage drop in the drift layer for a breakdown voltage of 25 kV.

[0072] The typical characteristics of the reverse-conducting IGBT of this Example 4 are a breakdown voltage at room temperature of 26.2 kV and an on-voltage at 50 A / cm 2 during energization of about 5.2 V. As described above, according to this Example, by adopting the double-comb-tooth buffer layer type SiC reverse-conducting IGBT structure with insulating protrusions, the snap-back phenomenon can be substantially eliminated despite the ultra-high breakdown voltage of 25 kV class.

Example

[0073] The fifth embodiment of the present invention is an 8 kV-class reverse-conducting IGBT with a double comb-shaped buffer layer having protrusions made of Si. Compared with the first to fourth embodiments of the SiC reverse-conducting IGBT, it aims at a reverse-conducting Si-IGBT having a breakdown voltage of 8 kV with a proven track record in power utility Si-GTOs, etc., suppressing the snap-back phenomenon with a small cell area and achieving high speed and low loss, and significantly improving the economic efficiency because the wafer can be made cheaper and larger in diameter compared to SiC. The chip configuration is almost the same as that in FIG. 2 except for the chip size, and the buffer layer is a double comb-shaped buffer layer with insulating protrusions similar to that in Embodiment 2. Also, the <Method b> described in

[0046] is used for the formation process of the insulator region and the insulating protrusions. As the main structural factors, for example, the following values are selected. The impurity concentration and thickness of the n-emitter region 808 are 5e19 cm -3 and 10 μm, the impurity concentration and thickness of the p-body region 807 are 1e18 cm -3 and 12 μm, the impurity concentration and thickness of the n-drift layer 800 are 7e12 cm -3 and 650 μm, the impurity concentration and thickness of the semiconductor region of the n-buffer layer 804 are 1e17 cm -3 and 1 μm, the impurity concentration and thickness of the p-collector layer 802 are 3e18 cm -3 and 2 μm.

[0074] FIG. 6 is a schematic plan view for explaining the configuration of the buffer layer 104 of the fifth embodiment, and FIG. 7 is a cross-sectional view taken along the dotted line corresponding to the insulating protrusion 119 in FIG. 6 between points C and D. Two insulating protrusions 119 made of an insulator on a rectangle are provided in each comb tooth portion 118 in FIG. 6. In the actual Example 5, different from the plan view for configuration explanation in FIG. 6, 16 insulating protrusions 119 are provided per comb tooth in order to further increase the snap-back phenomenon suppression effect (not shown as it would be complicated). Therefore, the total width of the comb teeth is 330 μm, the cell width Wp is 700 μm, the conduction path length per comb tooth is 10380 μm, and the resistance is approximately 1.22 MΩ. Since 5 comb teeth are connected in parallel per half cell, the total conduction path resistance RbufferT of the buffer layer for half cell is approximately 245 kΩ. Therefore, when the analysis described in

[0043] is carried out with changes for the Si reverse-conducting IGBT, the voltage drop due to the current Isb, that is, the current flowing through the conduction path of the comb-shaped buffer region, exceeds 0.7 V of the built-in voltage Vbi of Si, and the current Isb when the hole injection starts from the p collector 102 becomes significantly smaller, about 2.9 μA. As a result, the voltage drop in the drift region is as small as 0.5 V, and Vsb when the Si-IGBT turns on can be reduced to about 1.20 V. After snap-back, since the on-current of the Si-IGBT flows, the on-voltage is larger than 0.7 V in the case of an 8 kV Si-IGBT. Therefore, the amount by which Vsb exceeds the on-voltage is 0.5 V or less, and the snap-back phenomenon is substantially eliminated.

[0075] Next, the operation and typical characteristics of the reverse-conducting Si-IGBT of Example 5 will be described below. After mounting the reverse-conducting IGBT element in the same TO-type package as in Example 1 and finishing it into a reverse-conducting IGBT semiconductor device, an operation test was carried out. The breakdown voltage between the collector main electrode and the emitter main electrode measured with the emitter main electrode and the gate main electrode short-circuited is about 8.9 kV, which is good. When a forward voltage is applied between the collector main electrode 101 and the emitter main electrode 113 without applying a gate voltage, a leakage current flows, showing good forward blocking characteristics. The leakage current is typically 1x10 -4 A / cm 2 or so at room temperature, which is good.

[0076] 50 A / cm of the IGBT 2The on-voltage during energization is 6.1 V. Also, the turn-on time is approximately 560 ns and the turn-off time is approximately 950 ns, enabling high-speed operation. In the case of Si-IGBT, since on-voltage degradation due to stacking defects does not occur, the above TEDREC operation method can be omitted. On the other hand, since the primary snap-back phenomenon is substantially eliminated, rapid on-voltage degradation due to the higher-order snap-back phenomenon also does not occur, and no adverse effect on reliability is found, which is good.

[0077] As described above, in the fifth embodiment, an 8 kV-class reverse-conducting Si-IGBT different from the first to third SiC-reverse-conducting IGBTs was implemented. Despite the withstand voltage of 8 kV, the snap-back phenomenon can be almost eliminated with a small cell area with a cell width Wp of 700 μm, and high noise performance and high economy can be achieved. In addition to the reduction in loss due to the speeding up of switching by the effect of reverse-conducting IGBT, the cost of wafers can be reduced and the wafer diameter can be increased compared to SiC, resulting in a significant improvement in economy.

Example

[0078] The sixth embodiment of the present invention is an 8 kV-class insulated protrusion honeycomb buffer layer type reverse-conducting IGBT made of 4H-SiC, and the fact that the cells in the active region have a honeycomb structure and a trench gate structure is a significant difference from the first to fifth embodiments. The cells can be significantly miniaturized, and the loss reduction effect and the economic effect due to the reduction of the chip area can be greatly increased.

[0079] Figures 8a and 8b are a cross-sectional view for explaining the sixth embodiment and a plan view of the buffer layer 804, respectively. Figure 8a is a cross-sectional view taken along the dotted line passing through both the semiconductor region 818-1 including the insulating protrusion 819 in Figure 8b and the insulating region 817-3, corresponding to the cross-section between E and F. In the semiconductor regions 818-1 to 818-3 made of SiC semiconductors in Fig. 8b, rectangular insulating protrusions 819 made of an insulator are provided. Five insulating protrusions 819 are provided for each triangular semiconductor region 818. Since there are three triangular semiconductor regions 818 per cell, a total of 15 insulating protrusions 819 exist in one cell. The width of each insulating protrusion 819 is 10 μm. Focusing on the triangular semiconductor region 818-1, each insulating protrusion 819 is provided at an average distance of 10 μm from the adjacent insulator regions 817-1 and 817-2, and the interval between the five insulating protrusions 819 is set to 10 μm. As a result, a conductive path with a width of 10 μm is formed between the insulating protrusions 819, the adjacent insulator regions 817-1 and 817-2, through the buffer layer portion 816 facing the trench gate 820 to the buffer layer portion 816Y on the short-circuit region 803. Therefore, the on-current of the MOSFET portion is shunted from the conductive path 816 at the center of the cell facing the trench gate portion on the main surface side to the triangular semiconductor regions 818-1 to 818-3 and flows to the short-circuit region 816Y.

[0080] By the way, compared with the resistance in the case of a simple triangle without the insulating protrusion 819, the conductive path in this embodiment has a long length and a narrow width, so the conductive path resistance can be significantly increased. In this specification, this buffer layer is defined as a honeycomb buffer layer with insulating protrusions and will be described by this name hereinafter. In the case of this honeycomb buffer layer with insulating protrusions, the resistance of the conductive path can be arbitrarily set by setting the number and shape of the insulating protrusions 819. It is characterized in that Isb and thus Vsb can be arbitrarily set, and the snap-back phenomenon can be eliminated or suppressed to an allowable range. However, from the point of view of electric field relaxation at the trench corner portion of the trench gate structure, it is preferably applied to elements with a relatively low breakdown voltage among ultra-high voltage reverse conduction elements.

[0081] In the actual Example 6, unlike FIG. 8b, 10 insulating protrusions are provided in one triangular semiconductor region to increase the snap-back phenomenon suppression effect. As a result, the width of the cell is 440 μm. Note that the width of the buffer layer portion 816 facing the trench gate 820 is 20 μm, and the width of the buffer layer portion 816Y on the short-circuit region 803 is also 20 μm. Approximately 180 cells are provided in the 6 mm square active region. As the main structural factors, for example, the following values are selected. The impurity concentration and thickness of the n-emitter region 808 are 5e19 cm -3 and 0.3 μm, the impurity concentration and thickness of the p-body region 807 are 1e18 cm -3 and 0.6 μm, the impurity concentration and thickness of the nCEL806 are 5e16 cm -3 and 0.3 μm, the impurity concentration and thickness of the n-drift layer 800 are 7e14 cm -3 and 80 μm, the impurity concentration and thickness of the semiconductor region 818 of the n-buffer layer 804 are 1e17 cm -3 and 1 μm, the impurity concentration and thickness of the p-collector layer 802 are 3e18 cm -3 and 2 μm. When the same analysis as described in

[0043] is performed, Vsb becomes 2.8 V, which is smaller than the on-voltage Von immediately after turning on the reverse-conducting IGBT, which is about 3.7 V. Therefore, the snap-back phenomenon has been eliminated.

[0082] Next, the operation and typical characteristics of the honeycomb buffer layer type SiC reverse-conducting IGBT with insulating protrusions of Example 6 will be described below. After mounting the reverse-conducting IGBT element in the same TO-type package as in Example 1 and finishing it into a reverse-conducting IGBT semiconductor device, an operation test is performed. The breakdown voltage between the collector main electrode 801 and the emitter main electrode 807 measured with the emitter main electrode 807 and the gate main electrode (not shown) short-circuited is about 8.5 kV, which is good. The leakage current is typically 3x10 -5 A / cm 2 at room temperature of 7 kV, which is good. Current density 80 A / cm 2The on-voltage at this point is 4.5 V and the on-characteristics are good. Also, the turn-on time is approximately 220 ns and the turn-off time is approximately 450 ns, enabling high-speed operation. In each triangular insulating region, for example, divide it into three equal triangles with the center as the vertex, make the left and right two adjacent to the semiconductor region into semiconductor regions, and only leave the middle one as an insulating region to substantially reduce the area of the insulating region. As a result, the on-voltage at a current density of 80 A / cm 2 can be reduced to approximately 4.3 V, the turn-on time can be approximately 205 ns, and the turn-off time can be approximately 410 ns. In addition, in the long-term operation test by the TEDREC operation method, no on-voltage degradation due to stacking defects is found, and the same is true for the rapid on-voltage degradation due to the higher-order snap-back phenomenon. No adverse effect on reliability is found even in the long-time drive test, and it is good.

[0083] As described above, according to the sixth embodiment, with the honeycomb buffer layer type reverse-conducting IGBT with insulating protrusions, the conduction path resistance of a very large buffer layer can be increased in a small-area cell, the snap-back phenomenon can be eliminated, and its suppression within the allowable range can be achieved. In addition, the cell can be significantly miniaturized, and significant low-loss effects and economic effects due to chip area reduction can be expected.

Example

[0084] In the above [Example 1] to [Example 6], each IGBT chip is configured based on the concept of forming a cell in the active region with the reverse-conducting IGBT standard cell unique to each embodiment of the present invention. The reverse-conducting IGBT standard cell here is a cell equipped with snap-back suppression measures such as the cell with a pilot function disclosed in Patent Document 2, Japanese Patent No. 7385932 by the present inventor. Therefore, it is a cell in which the snap-back phenomenon is substantially eliminated or significantly suppressed within the allowable range (up to about 10 V of Vsb, which is not a problem in practical use). As a result, for example, in Example 2, Vsb could be set to approximately 2,74V and the snap-back phenomenon could be eliminated, but only 15 reverse-conducting IGBT standard cells could be integrated within a given 6mm square active region. Therefore, in this Example 7, the number of integrated cells is significantly increased to further reduce the on-resistance. For this purpose, as shown in FIG. 1, in the active region where cells are integrated in parallel, only the three central cells are used as the standard cells with the stripe structure in Example 2, and the rest are narrow-width stripe structure standard cells with a narrow width to increase the number of cells. That is, for the three central cells, standard cells with a cell width of 380μm having eight insulating protrusions similar to those in Example 2 are used, and the rest are standard cells with a narrow-width stripe structure having a cell width of 140μm and two insulating protrusions. As a result, in the case of an active region of the same size, a composite element having a total of 34 narrow-width stripe structure cells, 17 on each side of the three central standard cells, can be configured. When the active region is composed only of these narrow-width stripe structure cells, Vsb is 3.0V. Therefore, for this composite element, Vsb is at most 3V or less in the worst case. Accordingly, it is approximately 0.6V smaller than the on-voltage immediately after turning on in FIG. 1, and the snap-back phenomenon can be substantially eliminated. On the other hand, the number of integrated cells per chip can be increased more than twice from 15 to 37. Therefore, loss reduction due to a significant reduction in on-resistance can be achieved.

[0085] For the composite element of this example, the breakdown voltage is 16.3kV, and the on-voltage at 80A / cm 2 can be reduced to 5.2V. On the other hand, regarding the turn-off loss, when the composite element turns off, since the discharge of the residual carriers in the narrow-width stripe structure cells with a significantly smaller cell area is faster than the discharge in the three central standard cells, ultimately the total turn-off time of the composite element can be shortened, and the reduction in turn-off loss due to a significant increase in the number of cells of the composite element can be achieved. Note that since the Vth of the composite element of this example is still approximately 0.6V smaller than the on-voltage immediately after turning on as described above, by separately configuring a composite element using various narrow-width stripe structure cells with an even smaller cell width according to the concept of Example 7, the number of cells can be further significantly increased while eliminating the snap-back phenomenon, and further loss reduction can be achieved.

Example

[0086] This Example 8 is the same as Example 3, except that <Method C> described in

[0042] is used as the manufacturing method, and the impurity concentration in the semiconductor region of the n-buffer layer is 1e17 cm -3 and the thickness is reduced to 1 μm.

[0087] First, the main manufacturing process flow will be briefly described below. Figure 9 shows (9a) to (9c) of the first half of the manufacturing process flow. First, in (9a), an n-type drain layer 51 is epitaxially grown on an n-type SiC off-angle single crystal wafer 50. Next, a semi-insulating layer 71 with an impurity concentration of 1e17 cm -3 and a thickness of 1 μm, doped with vanadium, is epitaxially grown. Semi-insulating means that the resistivity is about 1x10 5 ~1x10 10 Ωcm, but the resistivity in this example is about 5x10 6 Ωcm. Next, in (9b), selective ion implantation of nitrogen is performed to form conductive paths 55 such as comb teeth and comb shafts with a desired shape as shown in Figure 6. It is important to set the implantation depth so that it becomes a conductive path that surely reaches the above-mentioned n-type drain layer 51 through the 1-μm-thick semi-insulating layer. Then, a predetermined annealing is performed to eliminate implantation damage. Next, in (9c), a p-collector layer 53 is epitaxially grown, and a short-circuit region 56 is formed by selective ion implantation of nitrogen. Thereafter, although not shown because it is the same, the same steps as those in (5d) to (5f) of Figure 5 are performed to complete the SiC reverse-conducting IGBT wafer.

[0088] Unlike the process of FIG. 9 described above, the process of FIG. 5 does not need to penetrate the p - collector layer 53 during ion implantation. Therefore, the implantation depth only needs to slightly exceed 1 μm to reach the drift layer 51, without the need for an expensive ultra - high - energy ion implantation device of 20 MeV or more, with less implantation damage, enabling cost reduction of the device and simplification of the annealing process, and having extremely high economic efficiency.

[0089] In the eighth embodiment, similar to the third embodiment, eight insulating protrusions 119 are provided per comb tooth. Therefore, the total width of the comb teeth is 170 μm, and the cell width Wp is 380 μm. Also, the conductive path length per comb tooth is 790 μm, and the resistance is about 1080 kΩ. Since 30 comb teeth are connected in parallel per half - cell, the conductive path resistance of the entire buffer layer for half - cell is about 18.5 kΩ. Based on the analysis method in

[0049] , the current Isb, that is, the voltage drop due to the current flowing through the conductive path in the comb - shaped buffer region, exceeds 2.7 V of the built - in voltage Vbi of SiC, and the current Isb when the injection of holes from the p - collector starts is about 145 μA. As a result, the voltage drop in the drift region is as small as 0.3 V, and Vsb immediately before the IGBT part turns on can be as small as about 3.0 V. Therefore, at the time of switch - on, it only switches from the Vsb of 3.0 V immediately before turning on to the on - voltage in the vicinity of 3.7 V of the on - voltage immediately after turning on shown in FIG. 1, and the problematic snap - back phenomenon is eliminated and does not occur. Also, the breakdown voltage at room temperature is about 8.7 kV, which is good. The leakage current is typically about 2x10 -4 A / cm 2 at room temperature of 6 kV. The on - voltage at a current density of 80 A / cm 2 is 5.1 V, and the on - characteristics are good. In the long-term operation test using the TEDREC operation method, no on-voltage degradation due to stacking defects was found, and the same was true for the rapid on-voltage degradation due to the higher-order snapback phenomenon. No adverse effect on reliability was found even in the long-time drive test, and the result was good. The vanadium-doped buffer layer has a function of suppressing the growth of stacking defects and is expected to be effective in suppressing on-voltage degradation, and it can be expected to contribute to the above good long-term test results. Note that the influence related to the instability of maintaining semi-insulation at high temperatures has not been grasped in this example.

[0090] As described above, according to this embodiment, when forming the insulating region of the buffer layer, since an epitaxial growth film doped with semi-insulating vanadium is used, it is not necessary to perform ultra-high energy ion implantation for forming the conductive path, and the implantation damage can be small. Therefore, the process and the apparatus can be greatly simplified, and together with high economic efficiency, an effect of suppressing on-voltage degradation due to stacking defects can also be expected.

[0091] The present invention has been described based on Examples 1 to 8 above. However, the present invention is not limited to these, and it is obvious to those skilled in the art that various modifications and applications can be easily made. For example, it is natural that the numerical values of the structural specifications can be changed and the invention can be extended to reverse-conducting IGBTs with a withstand voltage of 7 kV or less other than the withstand voltage of the examples, or even higher withstand voltages such as approximately 30 kV or more. Also, although the case where the electric field relaxation structure is JTE has been described, the same applies to cases of other electric field relaxation structures such as FLR and RESURF, or to JTEs composed of a plurality of regions with different concentrations. It is also natural that various cell structures can be adopted for the cell shape, such as stripe structures, equally divided stripe structures, and polygonal structures other than the honeycomb structure. It is of course possible to change and optimize the planar shape and area ratio of the unipolar transistor and bipolar transistor according to the specifications of the reverse-conducting IGBT. Also, although the formation processes of the conductive paths and insulating regions in the buffer layer have been mentioned with respect to <Method a><Method b><Method c>, it is obvious to those skilled in the art that various other modifications and applications can be made. Furthermore, although planar gate type IGBTs and trench gate type IGBTs have been mentioned, the invention can be similarly applied to IGBTs with other gate structures such as V-gate. Furthermore, although SiC and Si have been mentioned, the invention can be applied and extended to reverse-conducting IGBTs using other wide-gap semiconductors such as GaN and diamond, and can also be modified and applied to other reverse-conducting semiconductor devices such as reverse-conducting GTO thyristors and JMGBTs other than IGBTs. Naturally, it can also be applied and extended to the case of wide-gap semiconductor materials using a p-type drift layer.

Industrial Applicability

[0092] The present invention can be used in various high-voltage converters and power stabilization devices directly connected to the power distribution system, enabling significant reduction in size and weight and energy savings of the system. There is great potential for use in the grid connection of renewable energy power generation devices such as wind power generation, where size reduction, weight reduction, and energy savings can be achieved. It can also be used in control devices for industrial equipment such as large fans, pumps, and rolling mills.

Explanation of Reference Numerals

[0093] 1: SiC trench drain reverse-conducting IGBT chip 2: Active region 3: JTE for electric field relaxation 4: Surface exposed part of the field region 5: n-channel stopper layer 50: SiC off-angle single crystal wafer 51, 100: n-drift layer 52, 104, 804: n-buffer layer 53, 102, 802: p-collector region 56, 103, 803: n-short circuit region 57: p-layer for ohmic contact 58, 106, 806: Current density increasing layer CEL 59, 114: MOS surface region 60, 113, 813: Emitter main electrode 61, 101, 801: Collector main electrode 71: Vanadium-doped epitaxial semi-insulating layer 107, 807: p-body region 108, 808: Emitter region 109: Channel 110: Ohmic contact 111, 811: Gate oxide film 112, 812: Gate metal electrode 115: Insulating film 116: Comb axis and conductive path corresponding to the comb axis 116Y, 816Y: Conductive path on the short circuit region 117, 817: Insulating region 117Z, 118Z: Ion-implanted p-collector region 118, 818: Semiconductor region or semiconductor conductive path 119, 819: Insulating protrusion 816: Trench gate opposing conductive path 820: Gate electrode

Claims

1. An inverse-conducting IGBT semiconductor device, wherein the IGBT chip has an active region including a plurality of inverse-conducting IGBT standard cells and a breakdown voltage structure surrounding the active region, in the inverse-conducting IGBT standard cell of the IGBT chip, a MOS surface region is provided on one main surface of the active region and exposed between one main surface and the surface of a drift layer of a first conductivity type, an emitter main electrode is provided on the exposed surface of the MOS surface region, and further a buffer layer is provided in contact with the back surface of the drift layer of the first conductivity type, on the back surface of the buffer layer, a collector region of a second conductivity type and a short-circuit region of a first conductivity type (also serving as a drain region) are provided with a part of each side surface in contact with each other's regions, and a collector main electrode is provided on the back surfaces of the collector region of the second conductivity type and the short-circuit region of the first conductivity type (also serving as a drain region), in an inverse-conducting IGBT standard cell having a minimum cross-sectional configuration, a current density increasing layer CEL of a first conductivity type may be provided between the MOS surface region and the drift layer of the first conductivity type, and the buffer layer on the collector region has a semiconductor region of a first conductivity type serving as a conduction path and an insulating region or a semi-insulating region, and the inverse-conducting semiconductor device is characterized by the inverse-conducting IGBT standard cell.

2. According to

1. , the inverse-conducting IGBT standard cells in the active region have a stripe structure or a stripe structure equally divided in the longitudinal direction, the buffer layer has a stripe-shaped double comb-tooth type planar shape, a plurality of comb teeth are connected to a comb axis, the comb axis, the comb teeth and the comb tooth assembly are composed of the semiconductor region, and the spaces between the comb teeth are composed of the insulating region or the semi-insulating region, the comb teeth, the comb tooth assembly and the insulating region or the semi-insulating region therebetween are in contact with the collector region, and the comb axis is in contact with the short-circuit region, and the inverse-conducting semiconductor device is characterized by this.

3. In claim 1, the reverse-conducting IGBT standard cell has a polygonal planar shape surrounded by three or more line segments, and a triangular portion connecting the intersection of the line segments and the center of the polygon is composed of the semiconductor region, the insulator region, or the semi-insulating region, and the triangular portion of the semiconductor region and the triangular portion of the insulator region or the semi-insulating region are alternately arranged to form the buffer layer. A reverse-conducting semiconductor device characterized by this.

4. In claim 2 or claim 3, an insulating protrusion made of the same insulator as the insulator region or the semi-insulating region is provided in the semiconductor region of the reverse-conducting IGBT standard cell, and the insulating protrusion is in contact with either the upper and lower insulator regions or the semi-insulating regions adjacent to the semiconductor region. A reverse-conducting semiconductor device characterized in that the resistance of the conductive path of the buffer layer can be set by setting the shape and number of the insulating protrusions, and Isb and thus Vsb can be set.

5. In a reverse-conducting semiconductor device having the reverse-conducting IGBT standard cell described in any one of claims 2 to 4, In addition to the reverse-conducting IGBT standard cell, a reverse-conducting semiconductor device characterized by including, instead, narrow-width reverse-conducting IGBT cells having a smaller cell width than the reverse-conducting IGBT standard cell around the reverse-conducting IGBT standard cell.

6. In the reverse-conducting IGBT semiconductor device described in any one of claims 1 to 4, The insulator region or the semi-insulating region of the buffer layer is composed of an epitaxial film doped with oxygen or vanadium, the conductive path is composed of a first-conductivity-type ion implantation layer reaching the drift layer of the first conductivity type, and the impurity concentration of the ion implantation layer is higher than the impurity concentration of the drift layer. A reverse-conducting semiconductor device characterized by this.

7. In the manufacturing method of the reverse-conducting IGBT semiconductor device of claim 1, The manufacturing process of the insulator region or the semi-insulating region includes a selective implantation process of insulating ions such as oxygen or vanadium, or includes a trench formation process for a trench MOS gate or the like and a subsequent oxide film formation process of the semiconductor exposed along the trench surface, and the manufacturing process of the conductive path is carried out after the manufacturing process of the collector region. A manufacturing method of a reverse-conducting semiconductor device characterized by this.

8. In the method for manufacturing a reverse-conducting IGBT semiconductor device according to claim 1, the manufacturing process of the insulating region and the semi-insulating region includes a vanadium-doped epitaxial growth process, and selective ion implantation for forming a conductive path is performed on the vanadium-doped epitaxial layer after the epitaxial growth process. A method for manufacturing a reverse-conducting semiconductor device, characterized by this.

9. In the reverse-conducting semiconductor device according to any one of claims 2 and 4, After the temperature of the built-in pn junction diode and the IGBT part is raised to a temperature equal to or higher than the on-voltage degradation suppression temperature by passing a majority carrier current through the MOSFET part, a predetermined electrical operation is performed. A method for operating a reverse-conducting semiconductor device, characterized by this.

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