Gas introduction pipe and method for manufacturing gas introduction pipe

Abstract

To suppress localized formation of depot membranes in a gas introduction pipe.SOLUTION: A gas introduction pipe 6 is used to introduce gas into a semiconductor processing apparatus 1. The gas introduction pipe 6 has a Si-SiC substrate 61 and CVD-SiC films 62,63. The Si-SiC substrate 61 is a tubular Si-SiC substrate with a plurality of voids 61a. The CVD-SiC films 62,63 are CVD-SiC films formed on the face of the Si-SiC substrate 61.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a gas introduction pipe for introducing gas into a semiconductor processing apparatus.

Background Art

[0002] Conventionally, heat treatment processes such as LP-CVD (low-pressure CVD) and annealing of semiconductors have been performed using a vertical semiconductor heat treatment furnace. In this vertical semiconductor heat treatment furnace, a gas introduction pipe for introducing a processing gas is provided in a processing space of a vertically arranged furnace core tube. A conventional gas introduction pipe is, for example, made of a quartz glass tube body because of its excellent purity and workability, and has a substantially L shape, and has a vertical portion extending into the furnace core tube, a bent portion, and a horizontal portion disposed near the bottom of the furnace core tube.

[0003] When a deposition film is formed in the gas introduction pipe and the thickness of the deposition film becomes large with respect to the inner diameter of the gas introduction pipe, the gas supply ability by the gas introduction pipe decreases, and finally clogging occurs. Since it is difficult to suppress the generation of the deposition film itself, it is necessary to perform cleaning for removing the deposition film before clogging occurs. Patent Document 1 and Patent Document 2 describe forming a CVD-SiC film on the inner and outer surfaces of the introduction pipe in order to avoid shortening the life of the introduction pipe due to this cleaning.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] The longer the gas introduction pipe is, the greater the variation in the deposition film formation rate in the axial direction of the gas introduction pipe due to the influence of external temperature variations. The deposition film is locally generated inside the gas introduction pipe, and the gas introduction pipe is likely to become clogged. When the gas introduction pipe becomes clogged, it becomes difficult to completely remove the deposition film even by cleaning. Also, even if it is not completely clogged, the gas supply capacity of the gas introduction pipe decreases, posing a risk of causing film thickness abnormalities in the wafer.

[0006] The present invention has been made to solve the above problems, and an object thereof is to suppress the local generation of a deposition film in a gas introduction pipe.

Means for Solving the Problems

[0007] The disclosed gas introduction pipe is a gas introduction pipe for introducing gas into a semiconductor processing apparatus, having a tubular Si—SiC substrate with a plurality of voids, is one.

[0008] The disclosed method for manufacturing a gas introduction pipe is a method for manufacturing a gas introduction pipe for introducing gas into a semiconductor processing apparatus, including a step of forming a tubular Si—SiC substrate having a plurality of voids, is one.

Advantages of the Invention

[0009] According to the present invention, local generation of a deposition film in a gas introduction pipe can be suppressed.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0011] Hereinafter, an example of a gas introduction pipe for a semiconductor device according to the present embodiment will be described with reference to the drawings.

[0012] <Configuration of Semiconductor Processing Apparatus> FIG. 1 is a cross-sectional view showing a semiconductor processing apparatus 1 which is an example of a semiconductor processing apparatus to which the gas introduction pipe according to the present embodiment can be applied. FIG. 2 is a cross-sectional view showing a gas introduction pipe 6 which is an example of the gas introduction pipe according to the present embodiment, cut in a plane passing through the axis of the gas introduction pipe 6. FIG. 3 is a cross-sectional view showing the gas introduction pipe 6 cut in a plane orthogonal to the axis of the gas introduction pipe 6. The axis of the gas introduction pipe 6 is the center line of the tubular gas introduction pipe 6. Therefore, the axis of the L-shaped gas introduction pipe 6 (for example, the gas introduction pipe 6 in FIGS. 1 and 2) is L-shaped, and the axis of the linear gas introduction pipe 6 (for example, the gas introduction pipe 6 in FIG. 4) is linear.

[0013] The vertical semiconductor processing apparatus 1 shown in FIG. 1 includes a furnace tube 2 having an overall cylindrical shape. This furnace tube 2 has an opening 3 at the lower part, and a large number of semiconductor wafers W mounted on a wafer boat 4 are taken in and out through this opening 3.

[0014] The furnace tube 2 is formed of quartz glass, and a processing space 5 is formed inside thereof. In the processing space 5, for example, two gas introduction pipes 6 having different lengths are provided so that a predetermined gas (for example, silane gas) can be introduced into the processing space 5.

[0015] The gas introduction pipe 6 is a pipe having a gas inlet 6a and a gas outlet 6b, and is formed in an L shape in the example shown in FIGS. 1 and 2. That is, the gas introduction pipe 6 is composed of a horizontal portion 6h disposed horizontally in the core pipe 2, a bent portion 6c bent at about 90 degrees, and a vertical portion 6v disposed vertically in the core pipe 2.

[0016] In the semiconductor processing apparatus 1, a lifting device 10 for opening and closing the opening 3 is provided near the bottom of the core pipe 2, and a boat table 11 for supporting the wafer boat 4 is placed thereon. A heater 12 for heating the core pipe 2 is provided around the core pipe 2. An exhaust port 13 for the processing gas is provided at the top of the core pipe 2.

[0017] <Configuration of the gas introduction pipe 6> The axis A1 shown in FIGS. 2 and 3 is the axis of the gas introduction pipe 6. In the examples of FIGS. 1 to 3, since the gas introduction pipe 6 is L-shaped, the axis A1 is also L-shaped.

[0018] Also, as shown in FIG. 3, the gas introduction pipe 6 is composed of a tubular Si-SiC base material 61 and CVD-SiC films 62 and 63. The Si-SiC base material 61 is a base material made of Si-SiC (silicon silicon carbide) and having a large number of voids. Si-SiC is a composite material of Si (silicon) and SiC (silicon carbide), and is formed by bonding Si and SiC at a specific ratio.

[0019] The CVD-SiC films 62 and 63 are SiC films formed by CVD (Chemical Vapor Deposition) treatment. The CVD-SiC film 62 is formed on the outer surface (outside) of the Si-SiC base material 61. The CVD-SiC film 63 is formed on the inner surface (inside) of the Si-SiC base material 61.

[0020] For example, the inner diameter of the Si-SiC base material 61 is 5 to 6 mm, and the outer diameter of the Si-SiC base material 61 is 8 to 10 mm. Also, for example, the length of the Si-SiC base material 61 in the horizontal portion 6h is 8 to 10 cm, and the length of the Si-SiC base material 61 in the vertical portion 6v is 40 to 120 cm.

[0021] The CVD-SiC film 62 formed on the outer surface of the Si-SiC substrate 61 has a film thickness of, for example, 30 to 60 μm and is formed with a uniform thickness in the horizontal portion 6h and the vertical portion 6v.

[0022] The CVD-SiC film 63 formed on the inner surface of the Si-SiC substrate 61 has a surface roughness in the range of 20 μm ≤ Rzjis (ten-point mean roughness) ≤ 70 μm and 5 μm ≤ Ra (arithmetic mean roughness) ≤ 15 μm. By setting the roughness in this way, it is possible to improve the adhesion of the deposited film due to the anchor effect while suppressing the influence on the gas flow.

[0023] To manufacture the gas introduction pipe 6 as described above, first, an L-shaped tubular Si-SiC substrate 61 is formed. Specifically, it is formed into a tubular shape using Si-SiC powder and sintered at 1500°C. Thereby, a Si-SiC sintered body having a large number of voids is formed. Next, CVD-SiC films 62 and 63 are formed on the outer surface and the inner surface of this Si-SiC substrate 61 by CVD treatment.

[0024] After forming the CVD-SiC films 62 and 63 on the outer surface and the inner surface of the Si-SiC substrate 61, the inner surface side CVD-SiC film 63 is processed to have a predetermined surface roughness, specifically, in the range of 20 μm ≤ Rzjis (ten-point mean roughness) ≤ 70 μm and 5 μm ≤ Ra (arithmetic mean roughness) ≤ 15 μm. This process can be performed by carrying out a blasting process on the inner surface of the pipe using SiC particles of a predetermined size for a specified time and then applying a CVD film thickness of a predetermined thickness. In this way, the gas introduction pipe 6 can be manufactured.

[0025] <Heat treatment of wafers in the semiconductor processing apparatus 1> In the semiconductor processing apparatus 1 configured as described above, first, a wafer boat 4 on which a large number of semiconductor wafers W are placed is placed on a boat table 11 placed on an elevating device 10 and housed in a furnace core tube 2 heated by a heater 12.

[0026] Then, further raise the temperature inside the core tube 2. For example, introduce a processed gas doped with heated boron from the gas introduction tube 6 into the core tube 2. The introduced processed gas deposits a silicon film on the semiconductor wafer W, and then the processed gas is exhausted from the exhaust port 13.

[0027] In this processing step, a silicon film (depo film) generated from the processed gas is deposited on the inner and outer surfaces of the gas introduction tube 6. However, CVD-SiC films 62 and 63 are formed on the inner and outer surfaces of the gas introduction tube 6, and the difference in the thermal expansion coefficients between SiC and the deposited silicon film is not large. Therefore, when the gas flow rate is not high (for example, less than 50 sccm), breakage and partial peeling of the deposited film (depo film) due to the difference in thermal expansion coefficients can be suppressed.

[0028] <Suppression of Local Generation of Depo Film> As the base material of the peripheral members (for example, the core tube 2, the wafer boat 4, and the gas introduction tube 6) in the processing section of the Si wafer in the semiconductor processing apparatus 1, for example, Si-SiC having a thermal expansion rate closer to Si than SiC is used. In this case, by using Si-SiC as the base material also in the gas introduction tube 6, the thermal expansion rates of the peripheral members can be approximated, and the risk of damage due to the expansion difference can be reduced. However, since a general Si-SiC base material is a dense body, when Si-SiC is used as the base material of the gas introduction tube 6, if the temperature variation of the outside of the gas introduction tube 6 is large, the temperature variation inside the gas introduction tube 6 in the axial direction (the direction along the axis A1) of the gas introduction tube 6 becomes large, and local generation of the depo film in the gas introduction tube 6 occurs.

[0029] Therefore, a configuration is adopted in which an Si-SiC base material 61 having a large number of voids 61a is used as the base material of the gas introduction tube 6. Thereby, the heat insulation property of the gas introduction tube 6 is enhanced, and even if the temperature variation of the outside of the gas introduction tube 6 is large, the temperature variation inside the gas introduction tube 6 in the axial direction of the gas introduction tube 6 can be made small. Thereby, local generation of the depo film in the gas introduction tube 6 can be suppressed. For this reason, the risk of abnormal film thickness of the wafer is reduced, and the cleaning frequency can also be decreased.

[0030] <Modification example of the gas introduction pipe 6> FIG. 4 is a cross-sectional view showing a modification example of the gas introduction pipe 6. Similar to FIG. 2, FIG. 4 shows the gas introduction pipe 6 cut along a plane passing through the axis of the gas introduction pipe 6. As shown in FIG. 4, the gas introduction pipe 6 according to the embodiment is not limited to the L-shape shown in FIG. 2, and may be linear. Further, the gas introduction pipe 6 is not limited to the L-shape or the linear shape, and may have a shape bent at a plurality of locations, for example. Which shape of the gas introduction pipe 6 is used is determined according to the structure of the semiconductor processing apparatus (for example, the semiconductor processing apparatus 1) to which the gas introduction pipe 6 is applied.

[0031] <Size of the void 61a in the Si-SiC substrate 61> The size of the void 61a in the Si-SiC substrate 61 is preferably 1 μm or more and 150 μm or less. This is because if the size of the void 61a is smaller than 1 μm, the heat insulation performance of the Si-SiC substrate 61 becomes weak, and if the size of the void 61a is larger than 150 μm, the risk of rupture of the Si-SiC substrate 61 starting from the void 61a during use increases due to expansion during heat treatment. Note that the size of the void 61a is, for example, the equivalent diameter (volume equivalent diameter or surface area equivalent diameter) of the void 61a in the Si-SiC substrate 61.

[0032] <Porosity of the Si-SiC substrate 61> As shown in FIG. 3, when the gas introduction pipe 6 is viewed from the direction of the axis A1, the Si-SiC substrate 61 is considered to be divided into an outer tubular region Ro and an inner tubular region Ri. The outer tubular region Ro is a region outside the inner tubular region Ri including the outer surface of the Si-SiC substrate 61. The inner tubular region Ri is a region outside the outer tubular region Ro including the inner surface of the Si-SiC substrate 61.

[0033] For example, as shown in FIG. 3, let the radius of the inner surface of the Si-SiC substrate 61 be r1, and the thickness of the Si-SiC substrate 61 be T. Then, assume a cylindrical boundary surface 61b (dashed line in FIG. 3) whose distance from the axis A1 is equal to r1 + T / 2. In this case, the region inside the boundary surface 61b (on the side of the axis A1) of the Si-SiC substrate 61 is defined as the inner tubular region Ri, and the region outside the boundary surface 61b of the Si-SiC substrate 61 is defined as the outer tubular region Ro. That is, each of the outer tubular region Ro and the inner tubular region Ri is a tubular region having a thickness of T / 2, which is half of the thickness T of the Si-SiC substrate 61.

[0034] It is preferable that the porosity of the outer tubular region Ro is 3% or more and 10% or less, and the porosity of the inner tubular region Ri in the Si-SiC substrate 61 is 0% or more and 2% or less. This is because if the porosity of one of the regions of the outer tubular region Ro and the inner tubular region Ri is less than 3%, the heat insulation performance will be weakened, and if the porosity of the other region of the outer tubular region Ro and the inner tubular region Ri is more than 2%, the strength required for the semiconductor processing member of the gas introduction pipe 6 cannot be ensured.

[0035] In addition, the outer tubular region Ro is likely to reach a high temperature because it receives heat from the outer surface during processing, and the amount of expansion is likely to be larger than that of the inner tubular region Ri. On the other hand, by setting the porosity of the outer tubular region Ro to be larger than the porosity of the inner tubular region Ri, the outside of the gas introduction pipe 6 becomes more likely to deform, and the stress due to the deformation can be reduced.

[0036] Table 1 shows the evaluation results of the presence or absence of clogging and strength in the gas introduction pipe 6 for each combination of the porosity of the outer tubular region Ro and the porosity of the inner tubular region Ri. In this example, an experiment was conducted using a linear gas introduction pipe 6 with a length of 1500 mm (for example, the gas introduction pipe 6 shown in FIG. 4).

[0037]

Table 1

[0038] The presence or absence of clogging in Table 1 was determined as follows: When the gas introduction pipe 6 was used a predetermined number of times, if clogging occurred in the gas introduction pipe 6, it was considered "present", and if no clogging occurred in the gas introduction pipe 6, it was considered "absent". The predetermined number of times was the same as the number of times the gas introduction pipe 6 became clogged when the porosity of the outer tubular region Ro and the inner tubular region Ri was 0%.

[0039] Regarding the strength in Table 1, if a strength of 250 MPa or more, which is acceptable as a semiconductor processing member, was obtained, it was marked as "〇", and if a strength of 250 MPa or more was not obtained, it was marked as "×".

[0040] As shown in Table 1, by setting the porosity of the outer tubular region Ro to 3% or more, clogging of the gas introduction pipe 6 can be suppressed. Also, if the porosity of the inner tubular region Ri is made too high, micro-damage is likely to occur in the inner tubular region Ri, which is the part in contact with the gas, and there is a risk that micro-fragments from the inner tubular region Ri will be dispersed into the furnace. On the other hand, by setting the porosity of the inner tubular region Ri to not be high (for example, 2% or less) and the porosity of the outer tubular region Ro to 3% or more, while suppressing the above risk, clogging of the gas introduction pipe 6 can be suppressed.

[0041] Also, as shown in Table 1, by setting the porosity of the outer tubular region Ro to 3% or more and 10% or less and the porosity of the inner tubular region Ri to 0% or more and 2% or less, while suppressing clogging of the gas introduction pipe 6, the strength (250 MPa) required as a semiconductor processing member can be ensured.

[0042] As described above, according to the gas introduction pipe according to the embodiment, by using a Si-SiC substrate having a large number of voids as the substrate, even when there is a large variation in the external temperature, the high heat insulation property due to the large number of voids in the Si-SiC substrate can reduce the temperature variation inside the gas introduction pipe in the axial direction of the gas introduction pipe. Thereby, local generation of the deposition film in the gas introduction pipe can be suppressed. For this reason, the risk of film thickness abnormality of the wafer can be reduced, and the frequency of cleaning can also be decreased.

[0043] Also, by setting the size of the voids in the Si-SiC substrate to be 1 μm or more and 150 μm or less, it is possible to suppress a decrease in the heat insulation performance of the Si-SiC substrate and suppress cracking of the Si-SiC substrate during use of the gas introduction tube.

[0044] Also, by setting the porosity of the outer tubular region of the Si-SiC substrate to be 3% or more and 10% or less, and the porosity of the inner tubular region of the Si-SiC substrate to be 0% or more and 2% or less, it is possible to suppress a decrease in heat insulation performance and ensure the strength required for a semiconductor processing member. Further, by making the porosity of the outer tubular region higher than that of the inner tubular region, the outer side of the Si-SiC substrate becomes more easily deformable, and the stress due to deformation can be reduced.

[0045] <Modification Example of Method for Forming Roughness of CVD-SiC Film 63> In the above embodiment, as a method for forming the roughness of the CVD-SiC film 63 on the inner surface of the gas introduction tube 6, blasting treatment was performed for a specified time using SiC particles of a predetermined size on the inner surface of the tube, and a CVD film thickness of a predetermined film thickness was given. However, the method for forming the roughness of the CVD-SiC film 63 is not limited to this. For example, roughness may be formed by adhering powder of the same material as the substrate to the CVD-SiC film 63 on the inner surface of the gas introduction tube 6.

[0046] At least the following matters are described in this specification.

[0047] (1) A gas introduction tube for introducing gas into a semiconductor processing apparatus, having a tubular Si-SiC substrate having a plurality of voids, gas introduction tube.

[0048] (2) The gas introduction tube according to (1), wherein the size of the voids is 1 μm or more and 150 μm or less, gas introduction tube.

[0049] (3) (1) or (2), a gas introduction pipe, Among the Si-SiC substrates, a region including the outer surface of the Si-SiC substrate is defined as an outer tubular region, When, among the Si-SiC substrates, a region different from the outer tubular region and including the inner surface of the Si-SiC substrate is defined as an inner tubular region, The porosity of the outer tubular region is 3% or more, Gas introduction pipe.

[0050] (4) (3), a gas introduction pipe, The porosity of the outer tubular region is 3% or more and 10% or less, The porosity of the inner tubular region is 0% or more and 2% or less, Gas introduction pipe.

[0051] (5) (3) or (4), a gas introduction pipe, Each of the outer tubular region and the inner tubular region is a tubular region having a thickness of half the thickness of the Si-SiC substrate, Gas introduction pipe.

[0052] (6) A method for manufacturing a gas introduction pipe for introducing gas into a semiconductor processing apparatus, Including a step of forming a tubular Si-SiC substrate having a plurality of voids, Method for manufacturing a gas introduction pipe.

Explanation of reference numerals

[0053] 1 Semiconductor processing apparatus 2 Core tube 3 Opening 4 Wafer boat 5 Processing space 6 Gas introduction pipe 6b Gas outlet 6c Bending portion 6h Horizontal portion 6v Vertical portion 10 Lifting device 11 Boat table 12 heaters 13 exhaust ports 61 Si-SiC substrate 61a voids 61b interfaces 62, 63 CVD-SiC films A1 axis

Claims

1. A gas introduction pipe for introducing gas into a semiconductor processing apparatus, having a tubular Si—SiC substrate with a plurality of voids, the gas introduction pipe.

2. The gas introduction pipe according to Claim 1, wherein the size of the voids is 1 μm or more and 150 μm or less, the gas introduction pipe.

3. The gas introduction pipe according to Claim 1, wherein, when a region including the outer surface of the Si—SiC substrate among the Si—SiC substrates is defined as an outer tubular region, and a region different from the outer tubular region among the Si—SiC substrates and including the inner surface of the Si—SiC substrate is defined as an inner tubular region, the porosity of the outer tubular region is 3% or more, the gas introduction pipe.

4. The gas introduction pipe according to Claim 3, wherein the porosity of the outer tubular region is 3% or more and 10% or less, and the porosity of the inner tubular region is 0% or more and 2% or less, the gas introduction pipe.

5. The gas introduction pipe according to Claim 3 or 4, wherein each of the outer tubular region and the inner tubular region is a tubular region having a thickness that is half the thickness of the Si—SiC substrate, the gas introduction pipe.

6. A method for manufacturing a gas introduction pipe for introducing gas into a semiconductor processing apparatus, including a step of forming a tubular Si—SiC substrate having a plurality of voids, the method for manufacturing a gas introduction pipe. ​

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