Printed circuit board

Abstract

To provide a printed circuit board on which electron components, semiconductor chips, and the like can be mounted, and which can realize a metal post having a fine pitch, and can improve reliability against warpage.SOLUTION: In an electron device 1000, a printed circuit board includes: an interconnection portion 100 including one or more insulating layers 110, one or more interconnection layers 120, and one or more via layers 130, and having a cavity penetrating through at least a portion of the one or more insulating layers; an electronic component 200 disposed in the cavity; a first insulating material 310 disposed in at least a portion of the cavity and burying at least a portion of the electronic component; a second insulating material 320 disposed on the first insulating material; and a micro-via 330 penetrating through at least a portion of the second insulating material and connected to the electronic component. The micro-via has a width smaller than at least one via among the one or more via layers.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board.

Background Art

[0002] Recently, due to the development of technologies such as artificial intelligence (AI), multi-chip packages including memory chips such as high bandwidth memory (HBM) for geometrically increasing data processing, and processor chips such as central processing unit (CPU), graphics processing unit (GPU), application specific integrated circuit (ASIC), and field programmable gate array (FPGA) have been used. In particular, the number of CPU and GPU cores in server products has increased rapidly, and it is necessary to cope with a finer chip metal post pitch. In particular, research has been continuously conducted to form pads on the substrate more finely for connecting the chip and the substrate, and to increase the yield while improving the reliability of the connection between the chip and the substrate.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present disclosure is to provide a printed circuit board capable of realizing metal posts having a fine pitch in a printed circuit board for mounting electronic components, semiconductor chips, etc.

[0004] One of the various objects of the present disclosure is to provide a printed circuit board capable of improving the reliability against warpage.

Means for Solving the Problems

[0005] One of the various objectives of the present disclosure is to provide a printed circuit board capable of realizing metal posts having a fine pitch in a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0006] Another one of the various objectives of the present disclosure is to provide a printed circuit board capable of improving the reliability against warpage.

Advantages of the Invention

[0007] Among the various effects of the present disclosure, as one effect, one of the various objectives is to be able to provide a printed circuit board capable of realizing metal posts having a fine pitch in a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0008] Among the various effects of the present disclosure, as another effect, it is possible to provide a printed circuit board capable of improving the reliability against warpage.

Brief Description of the Drawings

[0009]

Figure 1

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape, size, etc. of the elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer explanation.

[0011] [Electronic Device] FIG. 1 is a block diagram schematically showing an example of an electronic device system.

[0012] Referring to the drawings, the electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040, etc. are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described later to form various signal lines 1090.

[0013] Examples of the chip-related components 1020 include memory chips such as volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), and flash memories, application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). However, the components are not limited to these, and other forms of chip-related electronic components can also be included. Furthermore, these chip-related components 1020 can be combined with each other. The chip-related components 1020 can also be in a package form including the above-described chips and electronic components.

[0014] Examples of the network-related components 1030 include Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated for future use. However, the components are not limited to these, and any of a number of other wireless or wired standards and protocols can also be included. Also, the network-related components 1030 can be combined with the chip-related components 1020 with each other.

[0015] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condensers), etc. However, it is not limited to these, and passive elements in the form of chip components used for various other purposes may also be included. In addition, the other components 1040 can be combined with the chip-related components 1020 and / or the network-related components 1030 with each other.

[0016] Depending on the type of the electronic device 1000, the electronic device 1000 can include other electronic components that are physically and / or electrically connected or not connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited to these, and audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. can also be mentioned. In addition, other electronic components used for various purposes according to the type of the electronic device 1000 can also be included.

[0017] The electronic device 1000 can be, for example, a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, it is not limited to these, and it can also be any other electronic device that processes data.

[0018] FIG. 2 is a perspective view schematically showing an example of the electronic device.

[0019] Referring to the drawings, the electronic device can be, for example, a smart phone 1100. Inside the smart phone 1100, a motherboard 1110 is accommodated, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Further, other components that are physically and / or electrically connected or not connected to the motherboard 1110, such as a camera module 1130 and / or a speaker 1140, are accommodated inside. A part of the components 1120 can be the above-described chip-related components, for example, a component package 1121, but is not limited thereto. The component package 1121 can be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Or, the component package 1121 can also be in the form of a printed circuit board with built-in active components and / or passive components. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and can also be other electronic devices as described above.

[0020] [Printed Circuit Board] FIG. 3 is a cross-sectional view schematically showing a printed circuit board according to an example.

[0021] Referring to FIG. 3, a printed circuit board according to an example includes a wiring portion 100, a first insulating material 310, and a second insulating material 320, and may further include an electronic component 200, a micro via 330, a solder resist layer 411, and a metal post 420.

[0022] The wiring portion 100 can include one or more insulating layers 110, one or more wiring layers 120 respectively disposed on or within the one or more insulating layers, and one or more via layers 130 penetrating the one or more insulating layers to connect the one or more wiring layers, and can have a cavity penetrating at least a part of the one or more insulating layers.

[0023] The electronic component 200 can be disposed within the cavity. A connection pad 201 can be disposed on the upper surface of the electronic component 200.

[0024] The first insulating material 310 can fill at least a part of the cavity and embed at least a part of the electronic component 200. The first insulating material 310 includes an insulating substance, but a material that does not include a fiber reinforcing material such as glass cloth, for example, ABF (Ajinomoto Build-up Film) and the like can be used. ABF can be provided in the form of RCC (Resin Coated Copper), but is not limited thereto. If necessary, a photosensitive insulating material such as PID (Photo Image-able Dielectric) can also be used.

[0025] The second insulating material 320 is disposed on the first insulating material 310 and can include a reinforcing material. Specifically, the second insulating material 320 can include a fiber reinforcing material such as glass cloth, and can be, for example, a prepreg. The second insulating material 320 including a fiber reinforcing material such as glass cloth can further reinforce the rigidity of the printed circuit board 1000 and improve the reliability against warpage of the printed circuit board.

[0026] In the printed circuit board 1000 according to the present embodiment, the first insulating material and the second insulating materials 310 and 320 are disposed on the upper surface of the electronic component 200. The second insulating material 320 can be a prepreg including a fiber reinforcing material such as glass cloth, and fine via holes can be formed by punching using a mold before laminating the second insulating material 320. However, the size of the fine via holes may decrease due to resin flow during the thermocompression bonding process of the prepreg. Therefore, before laminating the second insulating material 320, the electronic component 200 can be embedded with the first insulating material 310, thereby minimizing the volume that must be filled with the second insulating material 320.

[0027] The wiring layer disposed on the uppermost side among the one or more wiring layers 120 can include the first pad 141. The first pad 141 can be disposed on the uppermost insulating layer 112 among the one or more insulating layers 110. The upper surface of the first pad 141 can be located within the second insulating material 320. The side surface of the first pad 141 can be in contact with the first insulating material 310 and the second insulating material 320. The interface between the first insulating material 310 and the second insulating material 320 can be located between the upper surface and the lower surface of the first pad 141. This is because, as will be described later, after the formation of the first insulating material 310, a part of the first insulating material 310 can be etched through an etching process.

[0028] The connection pad 201 of the electronic component 200 can have its upper surface located within the second insulating material 320. The side surface of the connection pad 201 can contact the first insulating material 310 and the second insulating material 320. Similarly, the boundary surface between the first insulating material 310 and the second insulating material 320 can be located between the upper surface and the lower surface of the connection pad 201.

[0029] When observing the cross-section using measuring equipment such as a SEM (Scanning Electron Microscope), the boundary surface between the first insulating material 310 and the second insulating material 320 can be distinguished and confirmed for the presence or absence of the reinforcing material.

[0030] The micro via 330 can penetrate at least a part of the second insulating material 320. The micro via 330 can have a diameter smaller than at least one of the vias in the above-mentioned one or more via layers 130. Specifically, the micro via 330 has a diameter d of the first via 131 described later 131 and / or the diameter d of the second via 132 132 and can be smaller. Also, the micro via 330 can have a diameter smaller than the diameter d of the first pad 141 141 and can be smaller.

[0031] Figure 4 is an enlarged view of part A in Figure 3. As shown in Figure 4, when the side surface of the via has a taper, the diameter of one end of the via can be larger than the diameter of the other end. In such a case, the diameter can be measured as the relatively larger diameter at one end as shown in Figure 4. However, it is not necessarily limited to this, and depending on convenience, the diameter of the other end can also be measured. The diameter of the above-mentioned via can be measured multiple times, and the arithmetic mean of the values measured multiple times can be used as the diameter.

[0032] The micro via 330 can be separated from the above-mentioned one or more insulating layers 110. The micro via 330 can be separated from the first insulating material 310. This is because, as described above, after the formation of the first insulating material 310, a part of the first insulating material 310 can be etched through an etching process.

[0033] The solder resist layer 411 can be disposed on the upper surface of the second insulating material 320.

[0034] The metal post 420 is disposed on the micro via 330 and can penetrate at least a part of the solder resist layer 411.

[0035] The insulating layer 110 of one or more layers can include a first insulating layer 111 as a core layer and a second insulating layer 112 as a build-up insulating layer. The insulating layer 110 can include an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, and / or Glass Fabric) together with such a resin. The insulating material can be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the insulating layer 110 can be an insulating material of ABF (Ajinomoto Build-up Film), but is not limited thereto, and can also include PPG (Prepreg), RCC (Resin Coated Copper), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc. However, it is not limited thereto, and if necessary, other materials excellent in rigidity such as glass materials can also be used.

[0036] The cavity can penetrate at least a part of the second insulating layer 112. The cavity can not penetrate the first insulating layer 111 which is a core layer. That is, the cavity according to the present embodiment can be a blind cavity.

[0037] The wiring layer 120 with one or more layers can include a first wiring layer 121 disposed on the first insulating layer 111 and a second wiring layer 122 as a build-up wiring layer disposed on or within the second insulating layer 112. Specifically, among the second insulating layers 112, the wiring layer disposed on or within the uppermost insulating layer can be referred to as the first pad 141.

[0038] The wiring layer 120 can contain a metallic substance. As the metallic substance, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or their alloys, etc. can be used. The metallic substance can preferably contain copper (Cu), but is not limited thereto, and the first wiring layer 121 and the second wiring layer 122 can also contain different metallic substances from each other. The wiring layer 120 can perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc., but is not limited thereto, and can also function as a pad for mounting electronic components and chips, etc., or can function as a stopper for forming a cavity. These patterns can each have various forms such as lines, planes, pads, etc. The wiring layer 120 can have different pitches from each other according to its function. When the wiring layer 120 requires a high-density fine pitch for connection with a connection structure or a semiconductor chip, etc., the interval between the wiring layers 120 can be narrowed, and when performing other signal connections, etc., the interval between the wiring layers 120 can also be widened.

[0039] The wiring layer 120 can be formed by any one of the SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or Subtractive processes, but is not limited thereto. The wiring layer 120 can include an electroless plating layer (or electroless copper) as a seed layer and an electroplating layer (or electroformed copper) as a plating layer, respectively, but is not limited thereto. A sputtering layer can be formed instead of the electroless plating layer as the electroless copper. Optionally, a copper foil can be further included.

[0040] One or more via layers 130 can penetrate the one or more insulating layers 110 to connect the one or more wiring layers 120. The one or more via layers 130 can include a first via layer 131 as a via penetrating the first insulating layer 111 and a second via layer 132 as a build-up via layer penetrating at least a part of the second insulating layer 112.

[0041] The first via layer 131 can include a metal layer formed on the wall surface of a through-hole penetrating the first insulating layer 111 and a plug filling the metal layer. The metal layer can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, etc., and preferably can include copper (Cu), but is not limited thereto. The plug can include an insulating ink. The metal layer can include an electroless plating layer (or electroless copper) and an electroplating layer (or electroformed copper), but is not limited thereto. A sputtering layer can be formed instead of the electroless plating layer, or both can be included. The first via layer 131 can perform various functions according to the design. For example, it can include a ground via, a power via, a signal via, etc.

[0042] The second via layer 132 can include microvias. The microvias can be filed vias that fill via holes or conformal vias disposed along the wall surfaces of the via holes. The microvias can be arranged in a stacked type and / or a staggered type. Each of the second via layers 132 can include a metal, which can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, etc., and preferably can include copper (Cu), but is not limited thereto. Each of the second via layers 132 can include an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper), but is not limited thereto. A sputtering layer can also be formed instead of the electroless plating layer, or both can be included. The second via layer 132 can perform various functions according to the design of the corresponding layer. For example, it can include ground vias, power vias, signal vias, etc.

[0043] Among one or more wiring layers 120 of a printed circuit board according to an example, the wiring layer disposed on the uppermost side can include a first pad 141. The first pad 141 can be disposed on or within the insulating layer disposed on the uppermost side among the second insulating layers 112. As described above, among the second insulating layers 112, the wiring layer disposed on the uppermost insulating layer can be referred to as the first pad 141. In FIG. 3, the first pad 141 is shown as being disposed on the second insulating layer 112 and protruding above the second insulating layer 112, but is not necessarily limited thereto, and the first pad 141 can also have a structure embedded within the second insulating layer 112. The first pad 141 can be connected to at least a part of the second wiring layer 122 through one via layer 130 among the second via layers 132.

[0044] The first pad 141 can contain a metallic substance, and the metallic substance can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys, etc., and preferably can contain copper (Cu), but is not limited thereto. The first pad 141 can be disposed on the uppermost side of the printed circuit board, can be an area for mounting electronic components and chips, etc., and can also be connected to a circuit pattern for signal connection with other pads. However, without being limited thereto, the micro via 330 can also be formed above the first pad 141. The first pad 141 can perform various functions according to the respective design. For example, it can include a ground pad, a power pad, a signal pad, etc. Here, the signal pad can include pads for electrical connection of various signals excluding ground, power, etc., such as data signals. When the first pad 141 requires a high-density fine pitch for mounting a semiconductor chip or the like, the interval between the first pads 141 can be narrowed, and when it is for mounting an electronic component, the interval between the first pads 141 can also be widened.

[0045] The printed circuit board according to an example can include a second pad 142 below the wiring portion 100. The first pad 142 can be disposed on or within the insulating layer disposed at the lowermost side of the second insulating layer 112. In FIG. 3, the second pad 142 is shown as being disposed on the second insulating layer 112 and protruding from the lower side of the second insulating layer 112, but is not necessarily limited thereto, and the second pad 142 can also have a so-called coreless structure in which it is embedded in the lower side of the second insulating layer 112. The second pad 142 can be connected to at least a part of the second wiring layer 122 via one of the via layers of the second via layer 132.

[0046] The second pad 142 can contain a metallic substance, and the metallic substance can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys, etc., and preferably can contain copper (Cu), but is not limited thereto. The second pad 142 is disposed on the lowermost side of the printed circuit board and can function as a connection pad so that the lower surface of the printed circuit board can be connected to other components such as the main board. However, it is not limited thereto, and the second pad 142 can also function as a means for connecting to a configuration having a fine pitch such as a semiconductor chip, and the pitch can be designed in various ways according to the function. The second pad 142 can execute various functions according to the respective design. For example, it can include a ground pad, a power pad, a signal pad, etc. Here, the signal pad can include pads for electrical connection of various signals excluding ground, power, etc., such as data signals.

[0047] The first pad 141 and the second pad 142 can each be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive (Subtractive) processes, but are not limited thereto, and can be formed using methods available to those with ordinary knowledge in the relevant technical field.

[0048] The micro via 330 can penetrate at least a part of the second insulating material 320 and be connected to the electronic component 200. The micro via 330 can be arranged on the uppermost side of the printed circuit board, can be an area for mounting electronic components, chips, etc., and can also be connected to the circuit pattern to make a signal connection with other pads. The micro vias 330 can each perform various functions according to the design. For example, they can include ground pads, power pads, signal pads, etc. Here, the signal pads can include pads for electrical connection of various signals excluding ground, power, etc., such as data signals. When the micro vias 330 require a high-density fine pitch for mounting a semiconductor chip or the like, the interval between the micro vias 330 can be narrowed, and when it is for mounting electronic components, the interval between the micro vias 330 can also be widened.

[0049] As described above, the micro via 330 can have a diameter smaller than that of at least one via among the above one or more via layers 130. The micro via 330 can be formed by punching the second insulating material 320 using a mold to form a micro via hole before the lamination of the second insulating material 320, and can be formed by a process such as SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or Subtractive. However, it is not limited thereto, and it can be formed using a method available to those with ordinary knowledge in the relevant technical field.

[0050] A printed circuit board according to an example can include a first solder resist layer 411 and a second solder resist layer 412 arranged on the upper side and the lower side of the wiring part 100, respectively. The first solder resist layer 411 is arranged on the insulating layer arranged on the uppermost side among the second insulating layers 112, and the second solder resist layer 412 can be arranged on the insulating layer arranged on the lowermost side among the second insulating layers 112.

[0051] The first solder resist layer 411 and the second solder resist layer 412 are respectively disposed on the outermost side of the printed circuit board, and can protect the printed circuit board from the outside. The first solder resist layer 411 and the second solder resist layer 412 can use a known solder resist. Each of the first solder resist layer 411 and the second solder resist layer 412 contains a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, but may not contain glass fibers. The insulating resin can be a photosensitive insulating resin, and the filler can be an inorganic filler and / or an organic filler, but is not limited thereto. If necessary, other polymer materials can also be used. When a photosensitive insulating resin is used as the solder resist layer, it can be advantageous for forming fine openings, but is not limited thereto. It can include a non-photosensitive insulating resin, and fine openings can also be formed by forming fine openings with a UV laser.

[0052] The first solder resist layer 411 can cover at least a part of the micro via 330. Also, the metal post 420 can penetrate a part of the first solder resist layer 411 and can have a structure protruding from the first solder resist layer 411. The fact that the metal post 420 protrudes more than the first solder resist layer 411 can mean that the upper surface of the metal post 420 can be located higher than the upper surface of the first solder resist layer 411.

[0053] The first solder resist layer 411 can expose at least a part of the micro via 330 through the first opening, and the first opening can be filled by the metal post 420. At this time, the width of the lower end portion of the metal post 420 in the region where the metal post 420 is in contact with the micro via 330 can be formed smaller than the width of the micro via 330. On the other hand, since the width of the first opening formed in the first solder resist layer 411 can also have various widths like the width of the second opening described later, the width of the metal post 420 can also be formed wider than the width of the micro via 330.

[0054] The second solder resist layer 412 can have a second opening, and at least a part of the second pad 142 can be exposed by the second opening. The fact that a part of the second pad 142 can be exposed by the second opening can mean that the second solder resist layer 412 covers the second pad 142, but in the region where the second opening is formed, the second solder resist layer 412 does not cover the second pad 142. That is, it can mean that not only is the second pad 142 exposed to the outside of the printed circuit board, but also a part of the second pad 142 is not covered by the second solder resist layer 412 and a part of the second pad 142 can be connected to other components.

[0055] On the other hand, in FIG. 3, the second opening of the second solder resist layer 412 is shown as exposing a part of the upper surface of the second pad 142. However, the second solder resist layer 412, the second opening, and the second pad are not limited to being aligned in the form of SMD (Solder Mask Defined), and can also be aligned in the form of NSMD (Non-Solder Mask Defined). The relationship between the second pad 142 and the second solder resist layer 412 is not limited to that shown in the drawing. When aligned in the form of NSMD, the width of the second opening of the second solder resist layer 412 can be formed wider than the width of the second pad 142. Not only can the upper surface of the second pad 142 be exposed by the second solder resist layer 412, but also the side surface of the second pad 142 can be exposed by the second solder resist layer 412.

[0056] A printed circuit board according to one example can further include a metal post 420 disposed on at least a part of the micro via 330. The metal post 420 can be disposed on the micro via 330 and penetrate at least a part of the first solder resist layer 411. The metal post 420 can include a metallic substance. As the metallic substance, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof can be used. The metallic substance can preferably include copper (Cu), but is not limited thereto. The metal post 420 can be an area for mounting electronic components and chips, etc., and can be configured to protrude so as to smooth the connection when electronic components and chips are mounted on the micro via 330. The metal post 420 can perform various functions according to the design of the micro via 330. The metal post 420 can transmit and receive electrical signals with the wiring layer 120.

[0057] When the micro via 330 requires a high-density fine pitch for mounting a semiconductor chip or the like, not only the interval between the micro vias 330 but also the interval between the metal posts 420 can be narrowed. By disposing the metal posts 420 on the micro vias 330, even when a semiconductor chip with a fine pitch is mounted, the possibility of a short circuit of the connecting member disposed between the semiconductor chip and the metal post 420 can be reduced, and the defect of the semiconductor chip coming off can also be reduced. Further, by disposing the metal posts 420 on the micro vias 330, the adhesion can be ensured via the metal posts 420 rather than in a structure where the connecting member is directly disposed on the micro vias 330, and the reliability of the printed circuit board can be improved through this.

[0058] The metal post 420 can be formed by any one of the SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or Subtractive processes, but is not limited thereto, and can be formed using available methods by those having ordinary knowledge in the relevant technical field.

[0059] A printed circuit board according to an example can further include a surface treatment layer disposed on at least a part of the metal post 420. The surface treatment layer can include any one of the metals nickel (Ni), palladium (Pd), and gold (Au), and can also be realized by including a plurality of these metal layers. For example, the surface treatment layer can be at least a part of an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) structure, or can be at least a part of an ENIG (Electroless Nickel Immersion Gold) structure. The surface treatment layer is not limited thereto, and can also include an OSP (Organic Solder Passivation) structure containing an organic substance. The surface treatment layer can improve the adhesion force and signal transmission force between the metal post 420 and the connecting member. In FIG. 3, the surface treatment layer is shown as being composed of one layer, but is not limited thereto, and the surface treatment layer can also be realized by a plurality of metal layers as described above.

[0060] The surface treatment layer can cover at least a part of the metal post 420. In FIG. 3, the surface treatment layer is shown as covering the upper surface of the metal post 420, but is not necessarily limited thereto, and can also be arranged to further cover the exposed side surface of the metal post 420.

[0061] A printed circuit board according to an example can further include an electronic component 200 and an adhesive layer 210. The electronic component 200 can be an IC in which hundreds to millions or more of elements are integrated in one chip. For example, the electronic component 200 can be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, specifically, an application processor (AP), but is not limited thereto. In addition, it can also be other volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), memories such as flash memory, analog-digital converters, or logic such as ASIC (application-specific IC). The electronic component 200 can be a chip-shaped passive component, such as a chip inductor or a chip capacitor. Or it can be a combination of an IC and a chip-shaped passive component. In this case, a plurality of cavities can also be formed.

[0062] The electronic component 200 can be disposed in a cavity penetrating at least a part of the second insulating layer 112 and embedded by the first insulating material 310. In order for the electronic component 200 to be mounted in the cavity, an adhesive layer 210 can be further included. Regarding the structure and mounting of the electronic component 200, it can be formed using structures and methods available to those with ordinary knowledge in the relevant technical field.

[0063] Connection pads 201 can be disposed on the upper surface of the electronic component 200. The electronic component 200 can be connected to the wiring portion 100 via the connection pads 201, and the upper surface on which the connection pads 201 are disposed can be the active surface. However, it is not limited thereto. The electronic component 200 can also be capable of two-sided connection and, in some cases, can have a three-dimensional structure.

[0064] The printed circuit board according to one example is not limited to the configuration shown in FIG. 3, and other configurations can be further included, and in some cases, some configurations can be omitted. That is, it can further include configurations that can be utilized by those having ordinary knowledge in the relevant technical field.

[0065] [Method for manufacturing a printed circuit board] FIGS. 5 to 12 are cross-sectional views schematically showing a method for manufacturing a printed circuit board according to one example.

[0066] The method for manufacturing a printed circuit board according to one example can include the steps of preparing a wiring portion 100 and electronic components 200, embedding the electronic components 200 with a first insulating material 310, etching a part of the first insulating material 310, forming a second insulating material 320 with micro via holes processed thereon on the first insulating material 310, forming micro vias 330 on the second insulating material, forming solder resist layers 411 and 412 on the upper and lower sides of the wiring portion 100, and forming metal posts 420.

[0067] Referring to FIG. 5, it can include the step of preparing a wiring portion 100 and electronic components 200. The wiring portion 100 can include one or more insulating layers 110, one or more wiring layers 120 respectively disposed on or within one or more insulating layers 110, and one or more via layers 130 that penetrate one or more insulating layers to connect one or more wiring layers. The step of preparing the wiring portion 100 can include the step of forming a first wiring layer 121 on a first insulating layer 111, forming a second insulating layer 112 on the first insulating layer 111, forming a second wiring layer 122, and forming one or more via layers 130 that connect the above wiring layers. Further, it can include the step of forming a first pad 141 and a second pad 142 respectively on the outermost second insulating layer 112. At this time, the steps of forming the insulating layer 110 and the wiring layer 120 can be performed by a known build-up process.

[0068] On the one hand, the manufacturing method of a printed circuit board according to an example can include a step of forming a cavity that penetrates at least a part of the second insulating layer 112 and attaching and mounting an electronic component 200 with an adhesive layer 210.

[0069] Referring to FIG. 6, it can include a step of embedding the electronic component 200 with the first insulating material 310. The first insulating material 310 can fill at least a part of the cavity and can embed the electronic component 200. The first insulating material 310 includes an insulating substance, but a material that does not include a fiber reinforcing material such as glass cloth, for example, ABF (Ajinomoto Build-up Film) and the like can be used. ABF can be provided in the form of RCC (Resin Coated Copper), but is not limited thereto. If necessary, a photosensitive insulating material such as PID (Photo Image-able Dielectric) can also be used.

[0070] Referring to FIG. 7, it can include a step of etching a part of the first insulating material 310. A part of the first insulating material 310 can be etched through an etching process. Thereby, the interface between the first insulating material 310 and the second insulating material 320 can be located between the upper surface and the lower surface of the first pad 141. Similarly, the interface between the first insulating material 310 and the second insulating material 320 can be located between the upper surface and the lower surface of the connection pad 201. As will be described later, in the thermocompression bonding process of the second insulating material 320 (prepreg), the fine via hole size can be reduced due to the resin flow. To prevent this, after embedding the electronic component 200 with the first insulating material 310 before laminating the second insulating material 320, it is etched, thereby minimizing the volume that must be filled with the second insulating material 320.

[0071] Referring to FIGS. 8 and 9, it can include the step of forming a second insulating material 320 with fine via holes processed thereon on the first insulating material 310. Referring to FIG. 8, before laminating the second insulating material 320, punching can be performed using a mold to form fine via holes. The second insulating material 320 can be a prepreg containing a fiber reinforcing material such as glass cloth. Thereafter, the second insulating material 320 with fine via holes processed thereon as shown in FIG. 9 is laminated on the first insulating material 310.

[0072] Referring to FIG. 10, it can include the step of forming fine vias 330 on the second insulating material. The fine vias 330 can penetrate at least a part of the second insulating material 320. The diameter of the fine vias 330 can be smaller than the diameter of at least one via among the above-mentioned one or more via layers 130.

[0073] Referring to FIG. 11, it can include the step of forming solder resist layers 411 and 412 on the upper and lower sides of the wiring part 100. Each solder resist layer can be formed simultaneously, but it is not necessarily limited thereto. The method of forming the first solder resist layer 411 and the second solder resist layer 412 can be used without limitation as long as it is a known method of forming a solder resist.

[0074] Referring to FIG. 12, it can include the step of forming metal posts 420 on the fine vias 330. In order to form the metal posts 420, an opening can be formed in the first solder resist layer 411 to expose at least a part of the fine vias 330. The method of forming the opening can be used without limitation as long as it is a known method of forming an opening such as UV laser processing. After forming the metal posts 420, a surface treatment layer can be formed on the upper surface of the metal posts 420.

[0075] On the other hand, the manufacturing method of the printed circuit board according to an example is not necessarily limited to the content shown in FIGS. 5 to 12, and can be appropriately corrected and changed as needed.

[0076] In the present disclosure, the meaning of "cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed in a side view. Further, the meaning of "plane" can be the shape when the object is cut horizontally, or the planar shape when the object is viewed in a top view or a bottom view.

[0077] In the present disclosure, terms such as "upper side", "upper part", "upper surface", etc. are used to mean the direction toward the surface on which electronic components can be mounted, based on the cross-section of the drawing for convenience, and terms such as "lower side", "lower part", "lower surface", etc. are used as the opposite direction. However, this is a definition of the direction for convenience of explanation, and the scope of rights in the claims is not particularly limited by the description of such a direction.

[0078] In the present disclosure, the meaning of "connected" is a concept that includes not only the case of direct connection but also the case of indirect connection via an adhesive layer or the like. Further, the meaning of "electrically connected" is a concept that includes all cases of physical connection and cases of non-connection. Furthermore, expressions such as "first", "second", etc. are used to distinguish one component from another component, and do not limit the order and / or importance of the component. In some cases, without departing from the scope of the rights, the first component can also be named the second component, and similarly the second component can also be named the first component.

[0079] In the present disclosure, it can be judged including process errors, position deviations, errors during measurement, etc. that occur in the manufacturing process substantially. For example, the meaning of "substantially vertical" can include not only the case of being completely vertical but also the case of being roughly vertical. Further, the meaning of "substantially coplanar" can include not only the case of existing on exactly the same plane but also the case of existing on a roughly the same plane.

[0080] In the present disclosure, the same material can mean not only when it is exactly the same material, but also when it includes the same type of material. Therefore, the composition of the materials may be substantially the same, but these specific composition ratios may vary slightly.

[0081] The expression "an example used in the present disclosure" does not mean the same embodiment as each other, but is provided to emphasize and explain their respective unique features. However, the above-mentioned example does not exclude being realized in combination with the features of another example. For example, even if a matter described in a specific example is not described in another example, it can be understood as an explanation related to another example as long as there is no explanation contrary to or conflicting with that matter in another example.

[0082] The terms used in the present disclosure are merely used to explain an example and are not intended to limit the present disclosure. At this time, the singular expression includes the plural expression unless it clearly means something different in the context.

Explanation of Reference Numerals

[0083] 100 Wiring portion 110 Insulating layer 111 First insulating layer 112 Second insulating layer 120 Wiring layer 121 First wiring layer 122 Second wiring layer 130 Via layer 131 First via layer 132 Second via layer 141 First pad 142 Second pad 200 Electronic component 201 Connection pad 210 Adhesive layer 310 First insulating material 320 Second insulating material 330 Micro via 411 First solder resist layer 412 Second solder resist layer 420 Metal Post 1000 Electronic Device 1010 Main Board 1020 Chip-Related Parts 1030 Network-Related Parts 1040 Other Parts 1050 Camera Module 1060 Antenna Module 1070 Display 1080 Battery 1090 Signal Line 1100 Smartphone 1110 Smartphone Internal Main Board 1120 Smartphone Internal Electronic Components 1121 Smartphone Internal Antenna Module 1130 Smartphone Internal Camera Module 1140 Smartphone Internal Speaker

Claims

1. A wiring portion including one or more insulating layers, one or more wiring layers, and one or more via layers, having a cavity penetrating at least a part of the one or more insulating layers; An electronic component disposed in the cavity; A first insulating material filling at least a part of the cavity and embedding at least a part of the electronic component; A second insulating material disposed on the first insulating material; A fine via penetrating at least a part of the second insulating material and connected to the electronic component, and including: The fine via has a smaller diameter than at least one via of the one or more via layers, a printed circuit board.

2. The one or more insulating layers include a first insulating layer and a second insulating layer built up on the first insulating layer, The one or more via layers include a first via penetrating the first insulating layer and a second via penetrating at least a part of the second insulating layer, the printed circuit board according to Claim 1.

3. The cavity penetrates at least a part of the second insulating layer, the printed circuit board according to Claim 2.

4. The diameter of the fine via is smaller than the diameter of the first via, the printed circuit board according to Claim 2.

5. The diameter of the fine via is smaller than the diameter of the second via, the printed circuit board according to Claim 2.

6. The fine via is separated from the one or more insulating layers, the printed circuit board according to Claim 1.

7. The fine via is separated from the first insulating material, the printed circuit board according to Claim 1.

8. A solder resist layer disposed on the upper surface of the second insulating material; A metal post disposed on the fine via and penetrating at least a part of the solder resist layer, further including the printed circuit board according to Claim 1.

9. The second insulating material includes a reinforcing material, the printed circuit board according to Claim 1.

10. The first insulating material does not include a fiber reinforcing material, the printed circuit board according to Claim 1.

11. A wiring portion including one or more insulating layers and one or more wiring layers, having a cavity penetrating at least a part of the one or more insulating layers; A first insulating material filling at least a part of the cavity; A second insulating material disposed on the first insulating material and including a reinforcing material, and including: The wiring layer disposed on the uppermost side of the one or more wiring layers includes a first pad. A printed circuit board in which the upper surface of the first pad is located within the second insulating material.

12. The printed circuit board according to claim 11, wherein the interface between the first insulating material and the second insulating material is located between the upper surface and the lower surface of the first pad.

13. Further comprising an electronic component disposed within the cavity and having connection pads disposed on an upper surface thereof, The printed circuit board according to claim 11, wherein the upper surface of the connection pad is located within the second insulating material.

14. The printed circuit board according to claim 13, wherein the interface between the first insulating material and the second insulating material is located between the upper surface and the lower surface of the connection pad.

15. The one or more insulating layers include a first insulating layer and a second insulating layer built up on the first insulating layer, The printed circuit board according to claim 11, wherein the one or more wiring layers include a first wiring layer disposed on the first insulating layer and a second wiring layer disposed within the second insulating layer.

16. The printed circuit board according to claim 15, wherein the cavity penetrates at least a portion of the second insulating layer.

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