Semiconductor device

Abstract

To solve a problem which becomes obvious with the increased memory capacity and with progression of scaling of a transistor that a DRAM in the past requires refresh at intervals of a few tens of seconds for retaining data to cause increase in power consumption, and that a state of a transistor is switched between an ON-state and an OFF-state frequently to cause deterioration of the transistor.SOLUTION: In a semiconductor device, by using a transistor having a wide-gap semiconductor, a trench transistor having a trench for a gate electrode and a trench for element isolation is provided. Even when a distance between a source electrode and a drain electrode is decreased, by setting a depth of the trench for the gate electrode appropriately, onset of a short channel effect can be inhibited.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the miniaturization technology of semiconductor integrated circuits. Among the inventions disclosed in this specification, elements composed of compound semiconductors in addition to silicon semiconductors are included as elements constituting semiconductor integrated circuits, and an example thereof applying a wide-gap semiconductor is disclosed.

Background Art

[0002] Dynamic random access memory (DRAM) is a well-known product as a semiconductor memory device and is still used in various electronic devices today. The memory cell that constitutes the core of DRAM is composed of a transistor for writing and reading and a capacitor.

[0003] Similar to other semiconductor integrated circuits, DRAM has been miniaturized according to the scaling rule, but it was considered difficult to make the design rule less than 100 nm at one time. One of the reasons is that when the channel length of the transistor becomes less than 100 nm, punch-through current easily flows due to the short-channel effect, and it has been regarded as a problem that the transistor no longer functions as a switching element. However, to prevent punch-through current, the silicon substrate can be doped with a high concentration of impurities, but this will easily cause a junction leakage current to flow between the source and the substrate or between the drain and the substrate, ultimately resulting in a decrease in the retention characteristics of the memory, which is not an appropriate solution to this problem.

[0004] In response to such problems, the transistor constituting the memory cell is formed three-dimensionally, and one ​​​​​​​​​​​​While reducing the area occupied by the memory cell, a method has been considered to maintain the effective channel length of the transistor so that the short-channel effect does not occur. For example, a U-shaped vertical groove is formed in the region where the channel portion of the transistor is formed, a gate insulating film is formed along the wall surface of the groove, and further, a gate electrode is embedded in the groove (see Non-Patent Document 1).

[0005] In a transistor having such a structure in the channel portion, the current flowing between the source region and the drain region flows in a form that wraps around the groove portion, so the effective channel length is long. For this reason, while reducing the occupied area of the transistor in the memory cell, the merit of being able to suppress the short-channel effect has been obtained.

Prior Art Documents

Non-Patent Documents

[0006]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, conventional DRAMs have to be refreshed at intervals of several tens of milliseconds to hold data, leading to an increase in power consumption. Also, since the on state and off state of the transistor frequently switch, the deterioration of the transistor has been a problem. This problem is As the memory capacity increases and the miniaturization of transistors progresses, it has become remarkable.

[0008] Therefore, one object of the present invention is to provide a technology capable of improving data retention characteristics in a semiconductor memory device. Another object is to provide a technology capable of reducing power consumption while improving data retention characteristics in a semiconductor memory device.

Means for Solving the Problems

[0009] To solve the above problems, a transistor having a wide-gap semiconductor, particularly an insulated-gate transistor having a wide-gap semiconductor, is used to form a circuit, specifically a semiconductor memory device. By using a transistor having a wide-gap semiconductor, refreshing can be performed at intervals longer than those of conventional DRAMs, and power consumption can be reduced. Also, since the number of switching times between the on-state and off-state of the transistor per unit time is reduced, the lifespan of the transistor can be made longer than that of conventional DRAMs.

[0010] Moreover, in a transistor using a wide-gap semiconductor layer, as the miniaturization of the transistor progresses, the short-channel effect may occur. Therefore, a novel transistor structure using a wide-gap semiconductor layer is proposed.

[0011]

[0012] One aspect of the embodiments disclosed in this specification includes a first trench and a second trench in an insulating layer, a wide-gap semiconductor layer in contact with the bottom surface and inner wall surface of the first trench, a gate insulating layer on the wide-gap semiconductor layer, a gate electrode on the gate insulating layer, and filling the second trench. ​ It has an insulating layer to be formed, and the gate insulating layer is on the bottom surface and the inner wall surface of the second trench, and the g ate electrode fills the first trench. The semiconductor device is characterized by this. The first tr ench is a trench for the gate electrode, and the second trench is a trench for element isolation. Note that the upper surface shape of the first trench is a stripe shape or a rod shape, and the upper surface shape of the second tr ench is a lattice shape or a stripe shape or a rod shape.

[0013] In the above configuration, it further has a source electrode or a drain electrode in contact with the wide-gap semiconductor layer. It is characterized by this.

[0014] As the wide-gap semiconductor, at least an oxide semiconductor having a bandgap wider than 1.1 eV of silicon (for example, In-Ga-Zn-O-based oxide semiconductor is 3.15 eV, indium tin zinc oxide semiconductor is 2.6 eV to 2.8 eV or more, indium oxide is about 3.0 eV, indium tin oxide is about 3.0 eV, indium gallium oxide is about 3.3 eV, indium zinc oxide is about 2.7 eV, tin oxide is about 3.3 eV, zinc oxide is about 3.37 e V, etc.) and GaN (about 3.4 eV) can be mentioned.

[0015] Also, the cross-sectional shape of the wide-gap semiconductor layer in the channel length direction is a shape curved along the cross-sectional shape of the first trench, that is, a U-shaped shape. The deeper the first trench is, the longer the channel length of the transistor becomes. It is a structure.

[0016] Also, for the transistor with the trench structure disclosed in this specification, even if the distance between the source electrode and the drain electrode is narrowed, by appropriately setting the depth of the first trench, the short-channel effect can be manifested. ​​ can be suppressed.

Advantages of the Invention

[0017] Improvement in data retention characteristics in a semiconductor memory device can be achieved. Also, while attempting to improve the data retention characteristics in a semiconductor memory device, reduction in power consumption can be realized.

Brief Description of the Drawings

[0018]

Figure 1

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Figure 13

Figure 14

Figure 15

Modes for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below.

[0020] (Embodiment 1) In this embodiment, the structure and manufacturing method of a transistor, which are one aspect of the present invention, will be described with reference to FIG. 1. FIG. 1(A) shows an example of a cross-sectional view of the transistor 162 in the channel length direction. Further, FIG. 1(B) shows an example of a cross-sectional view of the element isolation region 165 between the transistor 162 and the transistor 163. Also, FIG. 1(C) shows an example of a top view of the transistor 162 and the transistor 163. Note that FIG. 1(B) is a part of the cross-sectional view of the transistor 162 in the channel width direction and corresponds to the cross-section cut along the dashed line D1 - D2 in FIG. 1(C). Also, FIG. 1(A) corresponds to the cross-section cut along the dashed line A1 - A2 in FIG. 1(C).

[0021] First, an insulating layer 130 made of an oxide film is formed on a semiconductor substrate. Then, a plurality of trenches (also called grooves) are formed in the insulating layer 130. And a wide-gap semiconductor layer 144 is formed so as to cover the trenches. The method of forming the trenches may use a known technique. In this embodiment, trenches having a depth of about 0.4 μm are formed. Also, in this embodiment, the trenches for gate electrodes are formed by single etching or multiple etchings.

[0022] ​​​​As the semiconductor substrate, an SOI substrate, a semiconductor substrate on which a drive circuit including transistors having a MOSFET structure is formed, a semiconductor substrate on which a capacitor is formed, etc. are used.

[0023] The insulating layer 130 can be formed using a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film.

[0024] The film thickness of the wide-gap semiconductor layer 144 is set to be 1 nm or more and 100 nm or less, and sputtering method, MBE (Molecular Beam Epitaxy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition) method, coating method, printing method, etc. can be appropriately used. Further, the wide-gap semiconductor layer 144 may be formed using a sputtering apparatus in which a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface, that is, a so-called CP sputtering apparatus (Columnar Plasma Sputtering system).

[0025] As the material of the wide-gap semiconductor layer 144, an oxide semiconductor having a band gap width larger than at least silicon, gallium nitride, gallium oxynitride, and zinc gallium oxynitride are used. As the oxide semiconductor having a band gap width larger than silicon, it is preferable to contain at least indium (In) or zinc (Zn). Particularly, it is preferable to contain In and Zn. Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them as a stabilizer. ​​​​​​​​​​​​​​It is preferable to have tin (Sn) as a stabilizer. Also, the stabilizer preferably has hafnium (Hf). Also, it is preferable to have aluminum (Al) as a stabilizer.

[0026] Also, as other stabilizers, lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), any one or more of these may be included.

[0027] For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, ternary metal oxides such as In-Ga-Zn oxide (also denoted as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0028] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0029] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. It indicates one or more metal elements. In addition, as an oxide semiconductor, In3SnO5 (ZnO) n A material expressed as (n>0, and n is an integer) may be used.

[0030] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that.

[0031] In addition, the In-Sn-Zn-based oxide can be called ITZO (registered trademark), and the composition ratio of the target used is an oxide target in which In:Sn:Zn is an atomic ratio of 1:2:2, 2:1:3, 1:1 :1, or 20:45:35, etc. is used.

[0032] However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). In addition, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, etc. appropriate. For example, in the In-Sn-Zn-based oxide, relatively high mobility can be obtained easily. However, in the In-Ga-Zn-based oxide as well, the mobility can be increased by reducing the defect density in the bulk.

[0033]

[0034]

[0035] 2 +(b - B) 2 + (c - C) 2 ≦r 2 is satisfied, and r may be, for example, 0.05. The same applies to other oxides.

[0035] The oxide semiconductor may be single crystal or polycrystal. In the latter case, it may be amorphous or polycrystalline. Also, a structure including a crystalline portion in the amorphous may be non-amorphous.

[0036] ​​​ Since an amorphous oxide semiconductor can relatively easily obtain a flat surface, when a transistor is fabricated using this, interface scattering can be reduced, and relatively easily, a relatively high mobility can be obtained.

[0037] In the present embodiment, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) that is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers along the c-axis, and the directions of the a-axis or b-axis are different (rotated around the c-axis as the center) in the ab-plane will be described. The oxide containing CAAC, in a broad sense, is a non-single crystal, and when viewed from a direction perpendicular to its ab-plane, it has a triangular, hexagonal, equilateral triangular, or regular hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis direction, it refers to an oxide containing a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers.

[0038] Although CAAC is not a single crystal, it is not formed only from amorphous material. Also, CAAC contains crystallized portions (crystal portions), but in some cases, the boundaries between one crystal portion and another crystal portion cannot be clearly distinguished.

[0039] When oxygen is contained in CAAC, part of the oxygen may be substituted with nitrogen. Also, the c-axes of the individual crystal portions constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface supporting CAAC, the surface of CAAC, etc.). Or, the normal lines of the ab-planes of the individual crystal portions constituting CAAC may be in a certain direction (for example, the substrate surface supporting CAAC, CAAC

[0040] 's surface, etc.). It may be oriented in a direction perpendicular to the surface or the like.

[0041] Depending on its composition and the like, the CAAC may be a conductor, a semiconductor, or an insulator. Also, depending on its composition and the like, it may be transparent or opaque to visible light.

[0042] As an example of such a CAAC, a crystal formed in a film shape, having a triangular or hexagonal atomic arrangement when observed from a direction perpendicular to the film surface or the substrate surface supporting it, and having a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) when observing its film cross-section can be cited. When observed from a direction perpendicular to the film surface or the substrate surface supporting it, a triangular or hexagonal atomic arrangement is recognized, and when observing its film cross-section, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized.

[0043] An example of the crystal structure included in the CAAC will be described in detail with reference to FIGS. 13 to 15. Unless otherwise specified, in FIGS. 13 to 15, the upward direction is the c-axis direction, and the plane perpendicular to the c-axis direction is the ab-plane. When simply referring to the upper half and the lower half, it means the upper half and the lower half with the ab-plane as the boundary. Also, in FIG. 13, the O enclosed by a circle indicates a 4-coordinate O, and the O enclosed by a double circle indicates a 3-coordinate O.

[0044] FIG. 13(A) shows a structure having one 6-coordinate In and six 4-coordinate oxygen atoms (hereinafter 4-coordinate O) adjacent to the In. Here, the structure showing only the adjacent oxygen atoms with respect to one metal atom is called a small group. The structure of FIG. 13(A) has an octahedral structure, but is shown in a planar structure for simplicity. Note that there are three 4-coordinate O each in the upper half and the lower half of FIG. 13(A). The small group shown in FIG. 13(A) has a charge of 0.

[0045] ​​​​​​​​​​Figure 13(B) shows a structure having one five - coordinated Ga, three three - coordinated oxygen atoms (hereinafter referred to as three - coordinated O) close to Ga, and two four - coordinated O close to Ga. The three - coordinated O are all present on the ab plane. There is one four - coordinated O each in the upper half and the lower half of Figure 13(B). Also, since In also takes a five - coordinated form, it can take the structure shown in Figure 13(B). The small group shown in Figure 13(B) has a charge of 0. Figure 13(B) shows a structure having one five - coordinated Ga, three three - coordinated oxygen atoms (hereinafter referred to as three - coordinated O) close to Ga, and two four - coordinated O close to Ga. The three - coordinated O are all present on the ab plane. There is one four - coordinated O each in the upper half and the lower half of Figure 13(B). Also, since In also takes a five - coordinated form, it can take the structure shown in Figure 13(B). The small group shown in Figure 13(B) has a charge of 0. Figure 13(B) shows a structure having one five - coordinated Ga, three three - coordinated oxygen atoms (hereinafter referred to as three - coordinated O) close to Ga, and two four - coordinated O close to Ga. The three - coordinated O are all present on the ab plane. There is one four - coordinated O each in the upper half and the lower half of Figure 13(B). Also, since In also takes a five - coordinated form, it can take the structure shown in Figure 13(B). The small group shown in Figure 13(B) has a charge of 0. Figure 13(B) shows a structure having one five - coordinated Ga, three three - coordinated oxygen atoms (hereinafter referred to as three - coordinated O) close to Ga, and two four - coordinated O close to Ga. The three - coordinated O are all present on the ab plane. There is one four - coordinated O each in the upper half and the lower half of Figure 13(B). Also, since In also takes a five - coordinated form, it can take the structure shown in Figure 13(B). The small group shown in Figure 13(B) has a charge of 0. Figure 13(B) shows a structure having one five - coordinated Ga, three three - coordinated oxygen atoms (hereinafter referred to as three - coordinated O) close to Ga, and two four - coordinated O close to Ga. The three - coordinated O are all present on the ab plane. There is one four - coordinated O each in the upper half and the lower half of Figure 13(B). Also, since In also takes a five - coordinated form, it can take the structure shown in Figure 13(B). The small group shown in Figure 13(B) has a charge of 0.

[0046] Figure 13(C) shows a structure having one four - coordinated Zn and four four - coordinated O close to Zn. There is one four - coordinated O in the upper half of Figure 13(C) and three four - coordinated O in the lower half. Or, there may be three four - coordinated O in the upper half of Figure 13(C) and one four - coordinated O in the lower half. The small group shown in Figure 13(C) has a charge of 0. Figure 13(C) shows a structure having one four - coordinated Zn and four four - coordinated O close to Zn. There is one four - coordinated O in the upper half of Figure 13(C) and three four - coordinated O in the lower half. Or, there may be three four - coordinated O in the upper half of Figure 13(C) and one four - coordinated O in the lower half. The small group shown in Figure 13(C) has a charge of 0. Figure 13(C) shows a structure having one four - coordinated Zn and four four - coordinated O close to Zn. There is one four - coordinated O in the upper half of Figure 13(C) and three four - coordinated O in the lower half. Or, there may be three four - coordinated O in the upper half of Figure 13(C) and one four - coordinated O in the lower half. The small group shown in Figure 13(C) has a charge of 0. Figure 13(C) shows a structure having one four - coordinated Zn and four four - coordinated O close to Zn. There is one four - coordinated O in the upper half of Figure 13(C) and three four - coordinated O in the lower half. Or, there may be three four - coordinated O in the upper half of Figure 13(C) and one four - coordinated O in the lower half. The small group shown in Figure 13(C) has a charge of 0.

[0047] Figure 13(D) shows a structure having one six - coordinated Sn and six four - coordinated O close to Sn. There are three four - coordinated O in the upper half of Figure 13(D) and three four - coordinated O in the lower half. The small group shown in Figure 13(D) has a charge of +1. Figure 13(D) shows a structure having one six - coordinated Sn and six four - coordinated O close to Sn. There are three four - coordinated O in the upper half of Figure 13(D) and three four - coordinated O in the lower half. The small group shown in Figure 13(D) has a charge of +1. Figure 13(D) shows a structure having one six - coordinated Sn and six four - coordinated O close to Sn. There are three four - coordinated O in the upper half of Figure 13(D) and three four - coordinated O in the lower half. The small group shown in Figure 13(D) has a charge of +1.

[0048] Figure 13(E) shows a small group containing two Zn. There is one four - coordinated O in the upper half of Figure 13(E) and one four - coordinated O in the lower half. The small group shown in Figure 13(E) has a charge of - 1. Figure 13(E) shows a small group containing two Zn. There is one four - coordinated O in the upper half of Figure 13(E) and one four - coordinated O in the lower half. The small group shown in Figure 13(E) has a charge of - 1. Figure 13(E) shows a small group containing two Zn. There is one four - coordinated O in the upper half of Figure 13(E) and one four - coordinated O in the lower half. The small group shown in Figure 13(E) has a charge of - 1.

[0049] Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell). Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell).

[0050] Here, the rule for the combination of these small groups will be described. As shown in Figure 13(A), The three O atoms in the upper half of the 6 - coordinated In each have three adjacent In atoms downward, and the three O atoms in the lower half each have three adjacent In atoms upward. The one O atom in the upper half of the 5 - coordinated Ga shown in Fig. 13(B) has one adjacent Ga atom downward, and the one O atom in the lower half has one adjacent Ga atom upward. The one O atom in the upper half of the 4 - coordinated Zn shown in Fig. 13(C) has one adjacent Zn atom downward, and the three O atoms in the lower half each have three adjacent Zn atoms upward. In this way, the number of 4 - coordinated O atoms above the metal atom and the number of adjacent metal atoms below that O are equal, and similarly, the number of 4 - coordinated O atoms below the metal atom and the number of adjacent metal atoms above that O are equal. Since O is 4 - coordinated, the sum of the number of adjacent metal atoms below and the number of adjacent metal atoms above is 4. Therefore, when the sum of the number of 4 - coordinated O atoms above one metal atom and the number of 4 - coordinated O atoms below another metal atom is 4, two types of small groups with metal atoms can bond to each other. The reason is shown below. For example, when a 6 - coordinated metal atom (In or Sn) bonds through the 4 - coordinated O atoms in the lower half, since there are 3 4 - coordinated O atoms, it will bond to either a 5 - coordinated metal atom (Ga or In) or a 4 - coordinated metal atom (Zn). Metal atoms with these coordination numbers bond through 4 - coordinated O atoms in the c - axis direction. In addition, multiple small groups combine to form a medium - sized group so that the total charge of the layer structure is 0. Fig. 14(A) shows a model diagram of the medium - sized group that constitutes the layer structure of the In - Sn - Zn - O system. Fig. 14(B) shows a large group composed of three medium - sized groups. Note that Fig. 14(

[0051]

[0052] ​​​​​​ (C) shows the atomic arrangement when observing the layer structure of Fig. 14(B) from the c-axis direction.

[0053] In Fig. 14(A), for simplicity, the 3-coordinated O is omitted, and only the number of 4-coordinated O is shown , for example, there are three 4-coordinated O atoms each in the upper and lower halves of Sn, which are indicated by the solid circle 3. Similarly, in Fig. 14(A), there is one 4-coordinated O atom each in the upper and lower halves of In, which is indicated by the solid circle 1. Also, similarly, in Fig. 14 (A), there is one 4-coordinated O atom in the lower half and three 4-coordinated O atoms in the upper half of Zn, and there is one 4-coordinated O atom in the upper half and three 4-coordinated O atoms in the lower half of Zn are shown.

[0054] In Fig. 14(A), the middle group that constitutes the layer structure of the In-Sn-Zn-O system is, from top downward, Sn with three 4-coordinated O atoms each in the upper and lower halves, which binds to In with one 4-coordinated O atom each in the upper and lower halves. Then, that In binds to Zn with three 4-coordinated O atoms in the upper half. Through the one 4-coordinated O atom in the lower half of that Zn, it binds to In with three 4-coordinated O atoms each in the upper and lower halves. Then, that In binds to a small group consisting of two Zn atoms with one 4-coordinated O atom in the upper half. Through the one 4-coordinated O atom in the lower half of this small group, it binds to Sn with three 4-coordinated O atoms each in the upper and lower halves. This middle loop binds multiple times to form a large group.

[0055] Here, for 3-coordinated O and 4-coordinated O, the charge per bond can be considered to be -0.6 67 and -0.5, respectively. For example, In (6-coordinated or 5-coordinated), Zn (4 The charges of In (3 - coordination), Sn (5 - coordination or 6 - coordination) are +3, +2, +4 respectively. Therefore, the small group containing Sn has a charge of +1. Thus, in order to form a layer structure containing Sn, a charge of -1 that cancels out the charge of +1 is required. As a structure with a charge of -1, as shown in Fig. 1 3(E), a small group containing 2 Zn atoms can be cited. For example, if there is one small group containing Sn and one small group containing 2 Zn atoms, the charges are cancelled out, so that the total charge of the layer structure can be made 0. Specifically, by repeating the large group shown in Fig. 14(B), a crystal of In - Sn - Zn

[0056] -O system (In2SnZn3O8) can be obtained. Note that the obtained In - Sn -Zn - O system layer structure can be represented by the composition formula of In2SnZn2O7(ZnO) (m is 0 or a natural number.) m (m is 0 or a natural number.) and can be expressed by the composition formula.

[0057] In addition, there are also In - Sn - Ga - Zn - based oxides which are quaternary metal oxides, and In - Ga - Zn - based oxides (also denoted as IGZO) which are ternary metal oxides, In - Al - Zn - based oxides, Sn - Ga - Zn - based oxides, Al - Ga - Zn - based oxides, Sn - A l - Zn - based oxides, In - Hf - Zn - based oxides, In - La - Zn - based oxides, In - C e - Zn - based oxides, In - Pr - Zn - based oxides, In - Nd - Zn - based oxides, In - Sm -Zn - based oxides, In - Eu - Zn - based oxides, In - Gd - Zn - based oxides, In - Tb - Zn - based oxides, In - Dy - Zn - based oxides, In - Ho - Zn - based oxides, In - Er - Z n - based oxides, In - Tm - Zn - based oxides, In - Yb - Zn - based oxides, In - Lu - Zn - based oxides, In - Yb - Zn - based oxides, In - Lu - Zn Oxides, In-Zn oxides which are binary metal oxides, Sn-Zn oxides, Al -Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and I n-Ga oxides, etc. are the same when used.

[0058] For example, FIG. 15(A) shows a model diagram of the middle group constituting the layer structure of the In-Ga-Zn-O system. diagram.

[0059] In FIG. 15(A), the middle group constituting the layer structure of the In-Ga-Zn-O system has, from top downward, three 4-coordinate O atoms each in the upper and lower halves and In atoms, and one 4-coordinate O atom in the upper half binds to Zn, and through the three 4-coordinate O atoms in the lower half of the Zn, one 4-coordinate O atom each in the upper and lower halves binds to Ga, and through the one 4-coordinate O atom in the lower half of the Ga, it binds to In with three 4-coordinate O atoms each in the upper and lower halves. A plurality of these middle groups combine to form a large group.

[0060] FIG. 15(B) shows a large group composed of three middle groups. Note that FIG. 15(C) shows the atomic arrangement when observing the layer structure of FIG. 15(B) from the c-axis direction.

[0061] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3 respectively. Therefore, a small group containing any of In, Zn, and Ga has a charge of 0. Therefore, for any combination of these small groups, the total charge of the middle group is always 0.

[0062] Also, the middle group constituting the layer structure of the In-Ga-Zn-O system is as shown in FIG. 15(A). ​​It is not limited to the middle group, and a large group combining middle groups with different arrangements of In, Ga, and Zn can also be used. It is also possible.

[0063] Next, electrodes 142a and 142b that function as a source electrode or a drain electrode are formed in contact with the wide-gap semiconductor layer 144. Electrodes 142a and 142b can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or an alloy material having these as a main component. When GaN is used as the wide-gap semiconductor layer 144, the materials of electrodes 142a and 142b that function as a source electrode or a drain electrode use titanium or the like, and aluminum gallium nitride (AlGaN) is used as a buffer layer for forming a two-dimensional electron gas between electrodes 142a, 142b and the wide-gap semiconductor layer 144. Next, insulating layers 143a and 143b are formed to protect electrodes 142a and 142b. Then, a planarization process is performed using CMP (chemical mechanical polishing) or the like. During this planarization process, insulating layers 143a and 143b function as a buffer layer for not eroding electrodes 142a and 142b.

[0064] Next, trenches for element isolation in the channel length direction and trenches for element isolation in the channel width direction are formed. These trenches for element isolation may have a connected upper surface pattern shape or an independent upper surface pattern shape. In this embodiment, since the wide-gap semiconductor layer is separated by forming trenches, in FIG. 1(C), these trenches

[0065]

[0066]

[0066] The pattern of the channel is a continuous upper surface pattern shape (lattice shape). When forming the trench for element isolation, the electrodes 142a and 142b can also be separated. Note that the timing of forming the trench for element isolation is not particularly limited. Also, the depth of the trench for element isolation is not limited to the depth at the same horizontal position as the bottom surface of the trench for the gate electrode as long as element isolation can be sufficiently performed. By making the horizontal position of the bottom surface of the trench for element isolation deeper than that of the trench for the gate electrode, element isolation can be surely performed. When forming the trench for element isolation, the electrodes 142a and 142b can also be separated. Note that the timing of forming the trench for element isolation is not particularly limited. Also, the depth of the trench for element isolation is not limited to the depth at the same horizontal position as the bottom surface of the trench for the gate electrode as long as element isolation can be sufficiently performed. By making the horizontal position of the bottom surface of the trench for element isolation deeper than that of the trench for the gate electrode, element isolation can be surely performed.

[0067] Next, a gate insulating layer 146 is formed to cover a part of the wide-gap semiconductor layer 144, the electrodes 142a and 142b that function as source electrodes or drain electrodes, and the insulating layers 143a and 143b. Also, the gate insulating layer 146 is formed on the inner walls and bottom surfaces of the trenches for element isolation in the channel length direction and on the inner walls and bottom surfaces of the trenches in the channel width direction.

[0068] The film thickness of the gate insulating layer 146 is set to be 1 nm or more and 100 nm or less, and sputtering method, MBE method, CVD method, pulsed laser deposition method, ALD method, coating method, printing method, etc. can be appropriately used. Also, the gate insulating layer 146 can be formed using a sputtering apparatus, a so-called CP sputtering apparatus, in which a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target.

[0069] As the material of the gate insulating layer 146, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. Further, the gate insulating layer 146 is formed when manufacturing the It is preferable to form it in consideration of the size of the transistor and the step coverage of the gate insulating layer 146. In this embodiment, as the gate insulating layer 146, SiO 2+α (where α > 0) A certain silicon oxide film is used. By using this silicon oxide film as the gate insulating layer 146, oxygen can be supplied to the In-Ga-Zn-O-based oxide semiconductor, and the characteristics can be improved.

[0070] In addition, as the material of the gate insulating layer 146, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y x > 0, y > 0)), hafnium silicate with nitrogen added (HfSi x O y N z (x > 0, y > 0, z > 0)), hafnium aluminate (Hf Al x O y (x > 0, y > 0)), etc. By using high-k materials such as these, gate leakage current can be reduced. Furthermore, the gate insulating layer 146 may have a single-layer structure or a laminated structure.

[0071] Then, the gate electrode 148a is formed on the gate insulating layer 146 so as to be filled in the trench for the gate electrode. The material of the gate electrode 148a can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material having these as the main components. The gate electrode 148a may have a single-layer structure or a laminated structure.

[0072] As a layer of the gate electrode 148a in contact with the gate insulating layer 146, a metal oxide containing nitrogen, Specifically, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (such as InN or SnN) is used. These films have a work function of 5 electron volts, preferably 5.5 electron volts or more. When used as a gate electrode, the threshold voltage of the transistor can be made positive, and a so-called normally-off switching element can be realized. An In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (such as InN or SnN) is used. These films have a work function of 5 electron volts, preferably 5.5 electron volts or more. When used as a gate electrode, the threshold voltage of the transistor can be made positive, and a so-called normally-off switching element can be realized. An In-O film containing nitrogen, or a metal nitride film (such as InN or SnN) is used. These films have a work function of 5 electron volts, preferably 5.5 electron volts or more. When used as a gate electrode, the threshold voltage of the transistor can be made positive, and a so-called normally-off switching element can be realized. These films have a work function of 5 electron volts, preferably 5.5 electron volts or more. When used as a gate electrode, the threshold voltage of the transistor can be made positive, and a so-called normally-off switching element can be realized. When used as a gate electrode, the threshold voltage of the transistor can be made positive, and a so-called normally-off switching element can be realized. When used as a gate electrode, the threshold voltage of the transistor can be made positive, and a so-called normally-off switching element can be realized.

[0073] When the gate electrode 148a is formed in the trench for the gate electrode, the trench-structured transistor 162 is formed. When the gate electrode 148a is formed in the trench for the gate electrode, the trench-structured transistor 162 is formed.

[0074] Next, an insulating layer 149 covering the gate electrodes 148a and 148b is formed. It is preferable to use an insulating film with good step coverage for the insulating layer 149. As the material of the insulating layer 149, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. Next, an insulating layer 149 covering the gate electrodes 148a and 148b is formed. It is preferable to use an insulating film with good step coverage for the insulating layer 149. As the material of the insulating layer 149, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. Next, an insulating layer 149 covering the gate electrodes 148a and 148b is formed. It is preferable to use an insulating film with good step coverage for the insulating layer 149. As the material of the insulating layer 149, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. Next, an insulating layer 149 covering the gate electrodes 148a and 148b is formed. It is preferable to use an insulating film with good step coverage for the insulating layer 149. As the material of the insulating layer 149, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. In this embodiment, an aluminum oxide film is used as the material of the insulating layer 149. In FIGS. 1(A) and 1(B), a gate insulating layer 146 is formed in contact with the side surface of the wide-gap semiconductor layer 144, and further, an insulating layer 149 is formed. Therefore, in this embodiment, the side surface of the wide-gap semiconductor layer 144 is covered with a silicon oxide film of SiOx (where α > 0), and the oxygen in the silicon oxide film is diffused and blocked so that oxygen does not pass through the insulating layer 149 by the aluminum oxide film covering the silicon oxide film. In FIGS. 1(A) and 1(B), a gate insulating layer 146 is formed in contact with the side surface of the wide-gap semiconductor layer 144, and further, an insulating layer 149 is formed. Therefore, in this embodiment, the side surface of the wide-gap semiconductor layer 144 is covered with a silicon oxide film of SiOx (where α > 0), and the oxygen in the silicon oxide film is diffused and blocked so that oxygen does not pass through the insulating layer 149 by the aluminum oxide film covering the silicon oxide film. In FIGS. 1(A) and 1(B), a gate insulating layer 146 is formed in contact with the side surface of the wide-gap semiconductor layer 144, and further, an insulating layer 149 is formed. Therefore, in this embodiment, the side surface of the wide-gap semiconductor layer 144 is covered with a silicon oxide film of SiOx (where α > 0), and the oxygen in the silicon oxide film is diffused and blocked so that oxygen does not pass through the insulating layer 149 by the aluminum oxide film covering the silicon oxide film. O 2+α In FIGS. 1(A) and 1(B), a gate insulating layer 146 is formed in contact with the side surface of the wide-gap semiconductor layer 144, and further, an insulating layer 149 is formed. Therefore, in this embodiment, the side surface of the wide-gap semiconductor layer 144 is covered with a silicon oxide film of SiOx (where α > 0), and the oxygen in the silicon oxide film is diffused and blocked so that oxygen does not pass through the insulating layer 149 by the aluminum oxide film covering the silicon oxide film. In FIGS. 1(A) and 1(B), a gate insulating layer 146 is formed in contact with the side surface of the wide-gap semiconductor layer 144, and further, an insulating layer 149 is formed. Therefore, in this embodiment, the side surface of the wide-gap semiconductor layer 144 is covered with a silicon oxide film of SiOx (where α > 0), and the oxygen in the silicon oxide film is diffused and blocked so that oxygen does not pass through the insulating layer 149 by the aluminum oxide film covering the silicon oxide film. In FIGS. 1(A) and 1(B), a gate insulating layer 146 is formed in contact with the side surface of the wide-gap semiconductor layer 144, and further, an insulating layer 149 is formed. Therefore, in this embodiment, the side surface of the wide-gap semiconductor layer 144 is covered with a silicon oxide film of SiOx (where α > 0), and the oxygen in the silicon oxide film is diffused and blocked so that oxygen does not pass through the insulating layer 149 by the aluminum oxide film covering the silicon oxide film.

[0075] After forming the insulating layer 149, an insulating layer 150 for filling the trench for device isolation is formed by the CV method or the like. By filling the trench for device isolation with the insulating layer 150 device isolation regions 161 and 165 are formed. Note that before forming the insulating layer 150, by laminating the gate insulating layer 146 and the insulating layer 149 in the trench for device isolation, the region to be filled with the insulating layer 150 can be made smaller, and the filling of the insulating layer 150 can be performed smoothly. Then, a planarization process is performed using CMP or the like to obtain the structures shown in FIGS. 1(A) and 1(B). This can be achieved.

[0076] Also, as shown in FIG. 1(B), the insulating layer 150 is filled between the gate electrode 148a of the transistor 162 and the adjacent gate electrode 148b of the transistor 163 to prevent short - circuiting between the gate electrodes. Further, as shown in FIG. 1(A), between the electrode that functions as the source electrode or drain electrode of the transistor 162 and the electrode that functions as the source electrode or drain electrode of the adjacent transistor in the channel length direction, the insulating layer 150 is filled to prevent short - circuiting of the source electrode or drain electrode. This is also achieved.

[0077] In this embodiment, since the wide - gap semiconductor layer 144 is formed in contact with the inner wall of the 0.4 - μm trench, the channel length is about 0.8 μm or more. When an In - Ga - Zn - O - based oxide semiconductor is used as the wide - gap semiconductor layer 144, by setting the channel length to 0.8 μm or more, a normally - off transistor can be formed, and the short - channel effect can be prevented from occurring. Also, by adopting the trench structure, the planar area of the transistor can be reduced, enabling high integration.

[0078] (Embodiment 2) Using the transistor 162 shown in FIG. 1, an example of a semiconductor device capable of retaining stored content even in a situation where no power is supplied and having no limitation on the number of write operations is shown in FIG. 2. Since the transistor 162 has a small off-current, it is possible to retain the stored content over a long period of time by using it. That is, since the frequency of the refresh operation can be made extremely low, the power consumption can be sufficiently reduced.

[0079] Since the transistor 162 has a small off-current, it is possible to retain the stored content over a long period of time by using it. That is, since the frequency of the refresh operation can be made extremely low, the power consumption can be sufficiently reduced. Since the transistor 162 has a small off-current, it is possible to retain the stored content over a long period of time by using it. That is, since the frequency of the refresh operation can be made extremely low, the power consumption can be sufficiently reduced. Since the transistor 162 has a small off-current, it is possible to retain the stored content over a long period of time by using it. That is, since the frequency of the refresh operation can be made extremely low, the power consumption can be sufficiently reduced.

[0080] FIG. 2(A) shows an example of a cross-section of a semiconductor device.

[0081] The semiconductor device shown in FIG. 2(A) has a transistor 160 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. Since the transistor 162 is the same as that in Embodiment 1, the same parts as those in FIG. 1(A) in FIGS. 2(A) and (B) will be described using the same reference numerals. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics.

[0082] Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics.

[0083] Note that all of the above transistors are described as n-channel type transistors. However, it goes without saying that a p-channel type transistor can also be used. Also, the technical essence of the disclosed invention lies in using a wide-gap semiconductor for the transistor 162 to hold information. Therefore, it is not necessary to limit the specific configuration of the semiconductor device here, such as the materials used in the

[0084] semiconductor device and the structure of the semiconductor device. The transistor 160 in Fig. 2(A) has a channel formation region 116 provided on a substrate 100 containing a semiconductor material (e.g., silicon, etc.), impurity regions 120 provided so as to sandwich the channel formation region 116, a metal compound region 124 in contact with the impurity region 120, a gate insulating layer 108 provided

[0085] on the channel formation region 116, and a gate electrode 110 provided on the gate insulating layer 108. Here, an electrode 126 is connected to a part of the metal compound region 124 of the transistor 160. Here, the electrode 126 functions as a source electrode or a drain electrode of the transistor 160. Also, an element isolation insulating layer is provided on the substrate 100 so as to surround the transistor 160, and an insulating layer 130 is provided so as to cover the transistor 160. In order to achieve high integration,

[0086] it is desirable that the transistor 160 has a configuration without a sidewall insulating layer as shown in Fig. 2(A). On the other hand, when emphasizing the characteristics

[0087] Here, the wide-gap semiconductor layer 144 is desirably highly purified. By using a highly purified wide-gap semiconductor, transistors 162 with extremely excellent electrical characteristics can be obtained.

[0088] In the transistor 162 of FIG. 2(A), an element isolation region 161 is provided to suppress the leakage that occurs between elements due to miniaturization. Further, a wide-gap semiconductor layer 144 processed into an island shape smaller than the region surrounded by the element isolation region 161 is used. However, as shown in Embodiment 1, a configuration that is not processed into an island shape until a trench for element isolation is formed may be adopted. When the wide-gap semiconductor layer is not processed into an island shape, contamination of the wide-gap semiconductor layer 144 due to etching during processing can be prevented. Of course, when the wide-gap semiconductor layer is not processed into an island shape, the number of processes can also be reduced. Also, when a wide-gap semiconductor layer processed into an island shape smaller than the region surrounded by the element isolation region 161 is used, since it is not necessary to divide the wide-gap semiconductor layer by forming a trench for element isolation, the horizontal position of the bottom surface of the trench for element isolation can be shallower than that of the trench for the gate electrode, or the total area of forming the trench for element isolation can be reduced.

[0089] An insulating layer 151 is provided on the transistor 162, and an electrode 153 electrically connected to the gate electrode 148a is provided on the insulating layer 151. Then, an insulating layer 152 is provided on the electrode 153. And the gate insulating layer 146, the insulating layer 150, the insulating layer ​​​​​​​​​​​​​​An electrode 154 is provided in an opening formed in an insulating layer 151, 152, etc., and a wiring 156 connected to the electrode 154 is formed on the insulating layer 152. In FIG. 2(A), the metal compound region 124, the electrode 142b, and the wiring 156 are connected using the electrodes 126 and 154, but the disclosed invention is not limited to this. For example, the electrode 142b may be directly brought into contact with the metal compound region 124. Alternatively, the wiring 156 may be directly brought into contact with the electrode 142b. Next, an example of a circuit configuration corresponding to FIG. 2(A) is shown in FIG. 2(B). In FIG. 2(B), the first wiring (1st Line) is electrically connected to the source electrode of the transistor 160, and the second wiring (2nd Line) is electrically connected to the drain electrode of the transistor 160. Also, the third wiring (3rd Line) is electrically connected to one of the source electrode or the drain electrode of the transistor 162, and the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 162. And, the gate electrode of the transistor 160 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected to one of the electrodes of the capacitor 164, and the fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 164. The capacitor 164 can be formed of a pair of electrodes and an insulating layer serving as a dielectric sandwiched therebetween in the same process as the manufacturing process of the transistor 160 and the transistor 162. Note that it is formed in the same process as the manufacturing process of the transistor 160 and the transistor 162.

[0090]

[0091]

[0092] ​​​​​​​​​​​​​​​ It is not limited, and the layer of the capacitor 164 may be separately provided above the transistor 162. For example, a trench-type capacitor or a stack-type capacitor may be separately formed above the transistor 16 2 or below the transistor 160, and high integration may be achieved by three-dimensionally stacking them. Integration may be attempted.

[0093] In the semiconductor device shown in FIG. 2(B), by taking advantage of the feature that the potential of the gate electrode of the transistor 160 can be held, information can be written, held, and read as follows. Regarding the writing and holding of information, first, the potential of the fourth wiring is set to a potential at which the transistor 16

[0094] 2 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode of the transistor 160 ( writing). Here, it is assumed that either one of two different charge levels (hereinafter referred to as Low-level charge and High-level charge) is applied. Then, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off. By doing so, the charge applied to the gate electrode of the transistor 160 is held ( holding).

[0095]

[0096] Also, a back gate electrode may be provided, and it is preferable to apply a voltage to the back gate electrode to ensure that the transistor 162 is normally off.

[0096] This embodiment can be freely combined with Embodiment 1.

[0097] (Embodiment 3) In this embodiment, a semiconductor device that can retain stored content even when power is not supplied and has no limit on the number of write operations will be described with reference to FIG. 3, using the transistor 162 shown in FIG. 1 and having a configuration different from that shown in Embodiment 2.

[0098] The semiconductor device shown in FIG. 3 has a transistor 350 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. Also, a plurality of transistors are formed in the upper and lower semiconductor materials, and typically, the transistor 350 and the transistor 162 will be described. Note that FIG. 3 cut along the line B1 - B2 corresponds to a cross-sectional view perpendicular to the channel length direction of the transistor.

[0099] Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can retain charges for a long time due to its characteristics.

[0100] Also, since the transistor 162 using the second semiconductor material at the upper part is the same as the transistor 162 described in the previous Embodiment 1 and Embodiment 2, the same reference numerals are used for the same parts as in FIG. 1(A) in FIG. 3, and detailed description is omitted.

[0101] ​​​​​​​​​​​​Here, the transistor 350 using the lower first semiconductor material will be described below. as follows.

[0102] The transistor 350 is composed of a semiconductor substrate 310, a gate insulating layer 314, a semiconductor layer 316, a conductive layer 318, a protective insulating layer 320, a sidewall insulating layer 322, an impurity region 324, and an insulating layer 326. Note that the semiconductor layer 316 and the conductive layer 318 function as gate electrodes, and the impurity region 324 functions as a source region or a drain region. Also, the transistor 350 has an adjacent STI (Shallow Trench Isolation) region 312.

[0103] olation) region 312.

[0104] As the STI region 312, first, a protective insulating film is formed on a desired region on the semiconductor substrate 310, and a trench (also called a groove) is formed by etching. After forming the trench, the STI region 312 can be formed by embedding an insulating dielectric film in the trench. As the insulating dielectric film, a silicon oxide film, a silicon nitride film, etc. can be used. Next, a detailed description of the transistor 350 will be given. As the gate insulating layer 314 of the transistor 350, after forming an insulating film on the semiconductor substrate 310 where the STI region 312 is formed, patterning and etching are performed at a desired position to form a trench having a depth different from that of the STI region 312 in the semiconductor substrate 310. Then, by performing a heat treatment in an oxygen atmosphere, the semiconductor substrate 310 in the trench is oxidized, and the gate insulating layer 314 can be formed.

[0105]

[0106] ​​​​​​​​​​After forming the gate insulating layer 314, a silicon film is formed using the LPCVD method or the like. Note that , the silicon film is doped with n + , p + , or heat treatment or the like is performed to form a semiconductor layer with high conductivity as a so-called polysilicon. Then, a metal film is formed on the semiconductor layer by a sputtering method or the like. As the metal film, tungsten, titanium, cobalt, nickel, or an alloy film containing tungsten, titanium, cobalt, nickel, a metal nitride film, a silicide film, etc. can be appropriately used. Patterning is performed on a desired region on the metal film and etched to form the conductive layer 318. Also, the semiconductor layer 316 can be formed by etching the semiconductor layer using the conductive layer 318 as a mask. Note that the conductive layer 318 and the semiconductor layer 316 function as the gate electrode of the transistor 350. .

[0107] Next, a protective insulating layer 320 is formed on the conductive layer 318. As the protective insulating layer 320, using the plasma CVD method or the like, a silicon oxide film, a silicon nitride film, etc. are formed, and patterning and etching processes are performed on a desired region to form it.

[0108] Next, a silicon nitride film is formed by the plasma CVD method or the like so as to cover the semiconductor substrate 310 and the protective insulating layer 320, and etch-back is performed to form the sidewall insulating layer 32 2.

[0109] Next, an impurity region 324 is formed by performing a doping process using the protective insulating layer 320 and the sidewall insulating layer 322 as masks. Note that as the dopant, boron or Phosphorus or the like may be used, and an n + region, p + region, etc. can be appropriately formed. Note that the impurity region 324 functions as the source region or the drain region of the transistor 350 .

[0110] Next, an insulating layer 326 is formed so as to cover the impurity region 324, the protective insulating layer 320, and the sidewall insulating layer 322. As the insulating layer 326, a silicon oxide film or the like can be formed by a plasma CVD method or the like.

[0111] Next, openings are provided in a desired region of the insulating layer 326, and connection electrodes 325 and connection electrodes 331 that are electrically connected to the impurity region 324 are formed. Note that after the connection electrodes 325 and the connection electrodes 331 are formed, a CMP process or the like for planarizing the surfaces of the insulating layer 326, the connection electrodes 325, and the connection electrodes 331 may be performed.

[0112] Next, a conductive film is formed on the insulating layer 326, the connection electrodes 325, and the connection electrodes 331 by a sputtering method or the like, patterned in a desired region, and etched to form electrodes 328 and electrodes 332. As materials that can be used for the electrodes 328 and the electrodes 332, tungsten, copper, titanium, etc. can be appropriately used.

[0113] Next, an insulating layer 329 is formed on the insulating layer 326, the electrodes 328, and the electrodes 332. As the insulating layer 329, it can be formed by the same materials and methods as the insulating layer 326.

[0114] Through the above steps, a semiconductor substrate on which a transistor 350 using a first semiconductor material is formed ​​​​​​​​​The plate 310 can be formed.

[0115] Here, the connection relationship between the transistor 350 using the lower first semiconductor material and the transistor 162 using the upper second semiconductor material will be described below. The connection relationship between the transistor 350 using the lower first semiconductor material and the transistor 162 using the upper second semiconductor material will be described below.

[0116] The transistor 350 is electrically connected to the transistor 162 by an impurity region 324, a connection electrode 325, an electrode 328, and a connection electrode 330. On the other hand, the impurity region 324, a connection electrode 331, an electrode 332, a connection electrode 334, an electrode 336, and a connection electrode 338 are electrically connected to the wiring 156. The transistor 350 is electrically connected to the transistor 162 by an impurity region 324, a connection electrode 325, an electrode 328, and a connection electrode 330. On the other hand, the impurity region 324, a connection electrode 331, an electrode 332, a connection electrode 334, an electrode 336, and a connection electrode 338 are electrically connected to the wiring 156. The transistor 350 is electrically connected to the transistor 162 by an impurity region 324, a connection electrode 325, an electrode 328, and a connection electrode 330. On the other hand, the impurity region 324, a connection electrode 331, an electrode 332, a connection electrode 334, an electrode 336, and a connection electrode 338 are electrically connected to the wiring 156. The transistor 350 is electrically connected to the transistor 162 by an impurity region 324, a connection electrode 325, an electrode 328, and a connection electrode 330. On the other hand, the impurity region 324, a connection electrode 331, an electrode 332, a connection electrode 334, an electrode 336, and a connection electrode 338 are electrically connected to the wiring 156.

[0117] Also, the gate electrode of the transistor 350 (that is, the semiconductor layer 316 and the conductive layer 318) is electrically connected to the source electrode of the transistor 162. However, in FIG. 3, the connection between the gate electrode of the transistor 350 and the source electrode of the transistor 162 is not shown, and the connection is made in the three-dimensional direction. Also, the gate electrode of the transistor 350 (that is, the semiconductor layer 316 and the conductive layer 318) is electrically connected to the source electrode of the transistor 162. However, in FIG. 3, the connection between the gate electrode of the transistor 350 and the source electrode of the transistor 162 is not shown, and the connection is made in the three-dimensional direction. Also, the gate electrode of the transistor 350 (that is, the semiconductor layer 316 and the conductive layer 318) is electrically connected to the source electrode of the transistor 162. However, in FIG. 3, the connection between the gate electrode of the transistor 350 and the source electrode of the transistor 162 is not shown, and the connection is made in the three-dimensional direction. Also, the gate electrode of the transistor 350 (that is, the semiconductor layer 316 and the conductive layer 318) is electrically connected to the source electrode of the transistor 162. However, in FIG. 3, the connection between the gate electrode of the transistor 350 and the source electrode of the transistor 162 is not shown, and the connection is made in the three-dimensional direction.

[0118] As described above, the plurality of memory cells formed on the upper part are formed by transistors using an oxide semiconductor which is one of wide-gap semiconductors. Since the off-current of the transistor using the oxide semiconductor is small, the memory content can be maintained for a long time by using this. That is, the frequency of the refresh operation can be extremely low, so that the power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. Examples of the semiconductor material other than the oxide semiconductor include silicon, germanium, silicon germanium, silicon carbide, or gallium. As described above, the plurality of memory cells formed on the upper part are formed by transistors using an oxide semiconductor which is one of wide-gap semiconductors. Since the off-current of the transistor using the oxide semiconductor is small, the memory content can be maintained for a long time by using this. That is, the frequency of the refresh operation can be extremely low, so that the power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. Examples of the semiconductor material other than the oxide semiconductor include silicon, germanium, silicon germanium, silicon carbide, or gallium. As described above, the plurality of memory cells formed on the upper part are formed by transistors using an oxide semiconductor which is one of wide-gap semiconductors. Since the off-current of the transistor using the oxide semiconductor is small, the memory content can be maintained for a long time by using this. That is, the frequency of the refresh operation can be extremely low, so that the power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. Examples of the semiconductor material other than the oxide semiconductor include silicon, germanium, silicon germanium, silicon carbide, or gallium. As described above, the plurality of memory cells formed on the upper part are formed by transistors using an oxide semiconductor which is one of wide-gap semiconductors. Since the off-current of the transistor using the oxide semiconductor is small, the memory content can be maintained for a long time by using this. That is, the frequency of the refresh operation can be extremely low, so that the power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. Examples of the semiconductor material other than the oxide semiconductor include silicon, germanium, silicon germanium, silicon carbide, or gallium. As described above, the plurality of memory cells formed on the upper part are formed by transistors using an oxide semiconductor which is one of wide-gap semiconductors. Since the off-current of the transistor using the oxide semiconductor is small, the memory content can be maintained for a long time by using this. That is, the frequency of the refresh operation can be extremely low, so that the power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. Examples of the semiconductor material other than the oxide semiconductor include silicon, germanium, silicon germanium, silicon carbide, or gallium. As described above, the plurality of memory cells formed on the upper part are formed by transistors using an oxide semiconductor which is one of wide-gap semiconductors. Since the off-current of the transistor using the oxide semiconductor is small, the memory content can be maintained for a long time by using this. That is, the frequency of the refresh operation can be extremely low, so that the power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. Examples of the semiconductor material other than the oxide semiconductor include silicon, germanium, silicon germanium, silicon carbide, or gallium. As described above, the plurality of memory cells formed on the upper part are formed by transistors using an oxide semiconductor which is one of wide-gap semiconductors. Since the off-current of the transistor using the oxide semiconductor is small, the memory content can be maintained for a long time by using this. That is, the frequency of the refresh operation can be extremely low, so that the power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. Examples of the semiconductor material other than the oxide semiconductor include silicon, germanium, silicon germanium, silicon carbide, or gallium. Muhi element or the like can be used, and it is preferable to use a single crystal semiconductor. Such a semiconductor transistor using this material can operate at a sufficiently high speed. Therefore, various circuits (logic circuits, driving circuits, etc.) that require high-speed operation can be preferably realized by transistors using materials other than oxide semiconductors.

[0119] Thus, by integrating a peripheral circuit using a transistor made of a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a memory circuit using a transistor made of an oxide semiconductor (more broadly, a transistor with a sufficiently small off-current), a semiconductor device with unprecedented characteristics can be realized. Also, by forming the peripheral circuit and the memory circuit in a stacked structure, the integration of the semiconductor device can be achieved. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0120]

[0121] (Embodiment 4) In this embodiment, regarding a semiconductor device that can retain stored content even when power is not supplied and has no limit on the number of write operations, using the transistor 162 shown in FIG. 1, a configuration different from the configurations shown in Embodiment 2 and Embodiment 3 will be described with reference to FIGS. 4 and 5.

[0122] FIG. 4(A) shows an example of the circuit configuration of a semiconductor device, and FIG. 4(B) is a conceptual diagram showing an example of the semiconductor device. First, the semiconductor device shown in FIG. 4(A) will be described, and then the semiconductor device shown in FIG. 4(B) will be described below.

[0123] ​​​​​​​​​​​ In the semiconductor device shown in FIG. 4(A), the bit line BL is electrically connected to the source electrode of the transistor 162 or the drain electrode, the word line WL is electrically connected to the gate electrode of the transistor 162 and the source electrode or the drain electrode of the transistor 162 is electrically connected to the first terminal of the capacitor 254.

[0124] The transistor 162 using an oxide semiconductor as the wide-gap semiconductor layer has the characteristic that the off-current is extremely small. Therefore, by turning off the transistor 162, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitor 254) can be held for an extremely long time. Also, in the transistor 162 using an oxide semiconductor as the wide-gap semiconductor layer, there is also the advantage that the short-channel effect hardly appears.

[0125] Next, the case of writing and holding information in the semiconductor device (memory cell 250) shown in FIG. 4 will be described.

[0126] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the bit line BL is applied to the first terminal of the capacitor 254 (writing). Then, the potential of the word line WL is set to a potential at which the transistor 162 is turned off, and by turning off the transistor 162, the potential of the first terminal of the capacitor 254 is held (holding).

[0127] Since the off-current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 254 Bits (or the charges stored in the capacitor) can be held for a long time.

[0128] Next, the reading of information will be described. When the transistor 162 is turned on, the floating bit line BL in the floating state and the capacitor 254 are electrically connected, and the charges are redistributed between the bit line BL and the capacitor 25 4. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL depends on the potential of the first terminal of the capacitor 254 (or the charges stored in the capacitor 254) and takes different values.

[0129] For example, if the potential of the first terminal of the capacitor 254 is V, the capacitance of the capacitor 254 is C, the capacitance component (hereinafter also referred to as the bit line capacitance) of the bit line BL is CB, and the potential of the bit line BL before the charge redistribution is VB0, then the potential of the bit line BL after the charge redistribution is (CB * VB0 + C * V) / (CB + C). Therefore, as the state of the memory cell 250 where the potential of the first terminal of the capacitor 254 takes two states of V1 and V0 (V1 > V0), it can be seen that the potential of the bit line BL when holding the potential V1 (= (CB * VB0 + C * V1) / (CB + C)) is higher than the potential of the bit line BL when holding the potential V0 (= CB * VB0 + C * V0) / (CB + C)). Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read

[0130] out.

[0131] As described above, due to the extremely small off-current of the transistor 162, the charges stored in the capacitor 254 can be held for a long time, which is a characteristic of the semiconductor device shown in FIG. 4(A). ​It becomes possible. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to retain the stored content over a long period of time.

[0132] Next, the semiconductor device shown in FIG. 4(B) will be described.

[0133] The semiconductor device shown in FIG. 4(B) has, at the upper part, a memory cell array 251 having a plurality of memory cells 250 shown in FIG. 4(A) as memory elements, and a memory cell array 252 having a plurality of memory cells 250 shown in FIG. 4(A). At the lower part, it has a peripheral circuit 253 necessary for operating the memory cell array 251 and the memory cell array 252. In the present embodiment, although the memory cell array 252 is located inside the memory cell array 251 and the peripheral circuit 253, since it is located above the peripheral circuit 253, the memory cell array 251 and the memory cell array 252 are considered to be located at the upper part.

[0134] By adopting the configuration shown in FIG. 4(B), the peripheral circuit 253 can be provided directly below the memory cell array 251 and the memory cell array 252. Also, since the memory cell array 251 and the memory cell array 252 also have a stacked structure, the semiconductor device can be miniaturized.

[0135] Next, the specific configuration of the semiconductor device shown in FIG. 4(B) will be described with reference to FIG. 5.

[0136] The semiconductor device shown in FIG. 5 has, at the upper part, a plurality of memory cells (memory cells 452) formed in multiple layers. ​​​​​​​​​​​a, and a memory cell 452b), and has a peripheral circuit 400 at the lower part. The lower peripheral circuit 400 has a transistor 450 using a first semiconductor material, and a plurality of memory cells (memory cell 452a and memory cell 452b) formed in multiple layers at the upper part have a transistor 162 using a second semiconductor material. Note that FIG. 5 cut along line C1 - C2 corresponds to a cross-sectional view perpendicular to the channel length direction of the transistor. Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon),

[0137] and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can hold charges for a long time due to its characteristics.

[0138]

[0139]

[0139] A gate insulating layer 411 provided over a forming region 404, and a gate electrode layer 412 provided in contact with the gate insulating layer 411, and a source electrode or a drain electrode 418a that is electrically connected to an impurity region, and a source electrode or a drain electrode 418b. Here, a sidewall insulating layer 414 is provided on a side surface of the gate electrode layer 412. In addition, an element isolation insulating layer 403 is provided on the substrate 402 so as to surround the transistor 450, and an interlayer insulating layer 420 and an interlayer insulating layer 422 are provided so as to cover the transistor 450. The source electrode or drain electrode 418a, and the source electrode or drain electrode 418b are electrically connected to the metal compound region 410 through openings formed in the interlayer insulating layer 420 and the interlayer insulating layer 422. That is, the source electrode or drain electrode 418a, and the source electrode or drain electrode 418b are electrically connected to the high-concentration impurity region 408 and the impurity region 406 through the metal compound region 410. Note that the sidewall insulating layer 414 may not be formed for the integration of the transistor 450 or the like. Also, on the interlayer insulating layer 422, there are an electrode 424a, an electrode 424b, and an electrode 424c that are electrically connected to the source electrode or drain electrode 418a of the transistor 450, and the source electrode or drain electrode 418b, and are planarized by an insulating layer 425 that covers the interlayer insulating layer 422, the electrode 424a, the electrode 424b, and the electrode 424c.

[0140] Here, a sidewall insulating layer 414 is provided on a side surface of the gate electrode layer 412. In addition, an element isolation insulating layer 403 is provided on the substrate 402 so as to surround the transistor 450, and an interlayer insulating layer 420 and an interlayer insulating layer 422 are provided so as to cover the transistor 450. The source electrode or drain electrode 418a, and the source electrode or drain electrode 418b are electrically connected to the metal compound region 410 through openings formed in the interlayer insulating layer 420 and the interlayer insulating layer 422. That is, the source electrode or drain electrode 418a, and the source electrode or drain electrode 418b are electrically connected to the high-concentration impurity region 408 and the impurity region 406 through the metal compound region 410. Note that the sidewall insulating layer 414 may not be formed for the integration of the transistor 450 or the like. Also, on the interlayer insulating layer 422, there are an electrode 424a, an electrode 424b, and an electrode 424c that are electrically connected to the source electrode or drain electrode 418a of the transistor 450, and the source electrode or drain electrode 418b, and are planarized by an insulating layer 425 that covers the interlayer insulating layer 422, the electrode 424a, the electrode 424b, and the electrode 424c. The electrode 424c is electrically connected to the electrode 428 by a connection electrode 426. Note that For the integration of the transistor 450 or the like, the sidewall insulating layer 414 may not be formed. Also, on the interlayer insulating layer 422, there are an electrode 424a, an electrode 424b, and an electrode 424c that are electrically connected to the source electrode or drain electrode 418a of the transistor 450, and the source electrode or drain electrode 418b, and are planarized by an insulating layer 425 that covers the interlayer insulating layer 422, the electrode 424a, the electrode 424b, and the electrode 424c. The electrode 424c is electrically connected to the electrode 428 by a connection electrode 426. Note that The electrode 424c is electrically connected to the electrode 428 by a connection electrode 426. Note that

[0141] The electrode 424c is electrically connected to the electrode 428 by a connection electrode 426. Note that , the electrode 428 is formed in the same layer as the source electrode layer and the drain electrode layer of the transistor 162. It is formed.

[0142] Also, the wiring 432 is electrically connected to the electrode 428 by the connection electrode 430, and is electrically connected to the electrode 436 formed in the same layer as the source electrode layer and the drain electrode layer of the transistor 162 by the connection electrode 434. Also, the electrode 436 is electrically connected to the wiring 440 by the connection electrode 4 38. It is electrically connected.

[0143] The electrode 424c, the wiring 432, and the wiring 440 can be used to make electrical connections between memory cells and between the peripheral circuit 400 and the memory cells. It can perform electrical connections such as those between the peripheral circuit 400 and the memory cells.

[0144] In the semiconductor device shown in FIG. 5, a configuration in which two memory cells (memory cell 452a and memory cell 452b) are stacked is illustrated, but the number of stacked memory cells is not limited to this. A configuration in which three or more memory cells are stacked may also be used. It is not limited to this. It may be a configuration in which three or more memory cells are stacked.

[0145] Also, in the semiconductor device shown in FIG. 5, for the connection between the memory cell 452a, the memory cell 452b, and the peripheral circuit 400, a connection configuration using the electrode 424c, the electrode 428, the wiring 432, the electrode 436, and the wiring 440 is illustrated, but it is not limited to this. Between the memory cell 452a, the memory cell 452b, and the peripheral circuit 400, a configuration in which two or more wiring layers and electrodes are provided may also be used. It may be a configuration in which two or more wiring layers and electrodes are provided. It may be a configuration in which two or more wiring layers and electrodes are provided.

[0146] As described above, the plurality of memory cells formed in multiple layers on the upper part are formed by transistors using an oxide semiconductor as a wide-gap semiconductor layer. The wide-gap semiconductor layer is used. Since a transistor using an oxide semiconductor has a small off-current, using this makes it possible to retain the stored content for a long time. That is, since the refresh operation frequency can be made extremely low, power consumption can be sufficiently reduced. On the other hand, in the peripheral circuit, a semiconductor material other than the oxide semiconductor is used. As the semiconductor material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide can be used, and it is preferable to use a single-crystalline semiconductor. Alternatively, an organic semiconductor material or the like may be used. A transistor using such a semiconductor

[0147] material can operate at a sufficiently high speed. Therefore, various circuits requiring high-speed operation (such as logic circuits and drive circuits ) can be suitably realized by transistors using materials other than the oxide semiconductor.

[0148] By integrating a peripheral circuit using a transistor made of a material other than the oxide semiconductor (in other words, a transistor capable of

[0149] sufficiently high-speed operation) and a memory circuit using a transistor (Embodiment 5) using the oxide semiconductor (more broadly, a transistor having a sufficiently An example of application to a portable device such as an e - book will be described with reference to FIGS. 9 to 12.

[0150] In portable devices such as mobile phones, smartphones, and e - books, SRAM or DRAM is used for temporary storage of image data. The reason for using SRAM or DRAM is that flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

[0151] A normal SRAM, as shown in FIG. 9(A), has one memory cell composed of six transistors, transistors 801 to 806. It is driven by an X - decoder 807 and a Y - decoder 808. Transistors 803 and 805, transistors 804 and 806 form inverters, enabling high - speed driving. However, since one memory cell is composed of six transistors, it has the drawback of a large cell area. When the minimum dimension of the design rule is F, the memory cell area of SRAM is usually 100 - 150F. For this reason, SRAM has the highest unit price per bit among various memories. 2

[0152] In contrast, a DRAM has a memory cell composed of a transistor 811 and a storage capacitor 812 as shown in FIG. 9(B), and is driven by an X - decoder 813 and a Y - decoder 814. One cell has a configuration of one transistor and one capacitor, and the area is small. The memory cell area of DRAM is usually 10F or less. However, DRAM always needs to be refreshed. 2 ​​​​​​​​​​​​​Y is necessary and consumes power even when no rewriting is performed.

[0153] However, the memory cell area of the semiconductor device described in the previous embodiment is about 10F 2 plus or minus and frequent refreshing is not required. Therefore, the memory cell area can be reduced and power consumption can be reduced.

[0154] Next, FIG. 10 is a block diagram of a portable device. The portable device shown in FIG. 10 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904 , a power supply circuit 905, an application processor 906, a flash memory 910, a dis play controller 911, a memory circuit 912, a display 913, a touch sensor 9 19, an audio circuit 917, a keyboard 918, etc. The display 913 is composed of a display unit 914, a source driver 915, and a gate driver 916 . The application processor 906 has a CPU 907, a DSP 908, and an interface 909 (IF909). Generally, the memory circuit 912 is composed of SRAM or DRAM . By adopting the semiconductor device described in the previous embodiment for this part, information can be written and read at high speed, long-term memory retention is possible, and power consumption can be sufficiently reduced.

[0155] Next, FIG. 11 shows an example in which the semiconductor device described in the previous embodiment is used for the memory circuit 950 of the display. The memory circuit 950 shown in FIG. 11 is composed of a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. 。Also, the memory circuit 950 reads the image data (input image data) input from the signal line, the data (stored image data) stored in the memory 952 and the memory 953, and is connected to a display controller 956 that performs control, and a display 957 that is displayed by a signal from the display controller 956. First, a certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. Then, the image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and is displayed. When there is no change in the input image data A, the stored image data A is normally read from the memory 952 via the switch 955 by the display controller 956 at a cycle of about 30 to 60 Hz.

[0156] Next, for example, when the user performs an operation to rewrite the screen (that is, when there is a change in the input image data A), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is also periodically read from the memory 952 via the switch 955. When the new image data (stored image data B) is stored in the memory 953, from the next frame of the display 957, the stored image data B is read, and via the switch 955 and the display controller 956, the stored image data is sent to the display 957.

[0157]

[0158] 5, and via the display controller 956, the stored image data is sent to the display 957.​​​​​​​​​​​​​ Tab B is sent and the display is performed. This reading continues until new image data is stored in the memory 952 next.

[0159] In this way, the memories 952 and 953 perform the display on the display 957 by alternately writing and reading the image data. Note that the memories 952 and 953 are not limited to separate memories, and one memory may be divided and used. By adopting the semiconductor device described in the previous embodiment for the memories 952 and 953, writing and reading of information can be performed at high speed, long-term storage can be maintained, and power consumption can be sufficiently reduced. 952 and 953 are not limited to separate memories, and one memory may be divided and used. By adopting the semiconductor device described in the previous embodiment for the memories 952 and 953, writing and reading of information can be performed at high speed, long-term storage can be maintained, and power consumption can be sufficiently reduced.

[0160] Next, FIG. 12 is a block diagram of an electronic book. FIG. 12 is composed of a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

[0161] Here, the semiconductor device described in the previous embodiment can be used for the memory circuit 1007 in FIG. 12. The role of the memory circuit 1007 has a function of temporarily holding the contents of the book. Examples of the function include when the user uses the highlighting function. When the user is reading an electronic book, there may be a case where the user wants to mark a specific location. This marking function is called a highlighting function, and it indicates the difference from the surroundings by changing the display color, underlining, thickening the characters, changing the font of the characters, etc. As an example of the function, there is a case where the user uses the highlighting function. When the user is reading an electronic book, there may be a case where the user wants to mark a specific location. This marking function is called a highlighting function, and it indicates the difference from the surroundings by changing the display color, underlining, thickening the characters, changing the font of the characters, etc. ​​​​​​It is a function to memorize and hold information of a specified location. When storing this information in the long term, it may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the previous embodiment, writing and reading of information can be performed at high speed, long-term memory retention is possible, and power consumption can be sufficiently reduced.

[0162] As described above, the semiconductor device according to the previous embodiment is mounted on the portable device shown in this embodiment. Therefore, a portable device with high-speed reading, long-term memory retention, and reduced power consumption is realized.

[0163] The configuration, method, etc. shown in this embodiment can be appropriately combined and used with the configuration, method, etc. shown in other embodiments.

Example

[0164] In this example, calculations were performed to confirm whether the short-channel effect appears in the transistor with the trench structure shown in Embodiment 1.

[0165] For the calculations, the device simulation software Sentaurus Device manufactured by Synopsys was used.

[0166] Fig. 6(A) shows the structure and individual sizes used for the calculations. The thickness of the gate insulating layer is 5 nm, the thickness of the wide-gap semiconductor layer is 5 nm, and the depth of the trench for the gate electrode is set to 0.4 μm. Fig. 6(A) shows a transistor with a trench structure where the length at the bottom of the trench (the length in the channel length direction) is 90 nm, and the distance between the source electrode and the drain electrode (the length in the channel length direction) is 110 nm. The material of the wide-gap semiconductor layer is In-Ga-Zn​​​​ -O-based oxide semiconductor (band gap 3.15 eV, electron affinity 4.6 eV, electron mobility 10 cm 2 / Vs) is used, and the work function of the electrodes (source electrode and drain electrode) in contact with the wide-gap semiconductor layer is 4.6 eV, and the work function of the gate electrode is 5.5 eV. The calculated result of the Vg-Id characteristics (Vds = 1 V, temperature 27 °C) of this trench structure transistor is shown in Fig. 6(B). Fig. 6(B).

[0167] Fig. 7(A) shows a trench structure transistor in which the length of the bottom of the trench (length in the channel length direction) is 60 nm and the distance between the source electrode and the drain electrode (length in the channel length direction) is 80 nm. The result of calculation under the same conditions as in Fig. 6(B) except for the length of the bottom of the trench and the distance between the source electrode and the drain electrode is shown in Fig. 7(B). Fig. 7(A) shows a trench structure transistor in which the length of the bottom of the trench (length in the channel length direction) is 60 nm and the distance between the source electrode and the drain electrode (length in the channel length direction) is 80 nm. The result of calculation under the same conditions as in Fig. 6(B) except for the length of the bottom of the trench and the distance between the source electrode and the drain electrode is shown in Fig. 7(B).

[0168] Fig. 8(A) shows a trench structure transistor in which the length of the bottom of the trench (length in the channel length direction) is 30 nm and the distance between the source electrode and the drain electrode (length in the channel length direction) is 50 nm. The result of calculation under the same conditions as in Fig. 6(B) except for the length of the bottom of the trench and the distance between the source electrode and the drain electrode is shown in Fig. 8(B). Fig. 8(A) shows a trench structure transistor in which the length of the bottom of the trench (length in the channel length direction) is 30 nm and the distance between the source electrode and the drain electrode (length in the channel length direction) is 50 nm. The result of calculation under the same conditions as in Fig. 6(B) except for the length of the bottom of the trench and the distance between the source electrode and the drain electrode is shown in Fig. 8(B).

[0169] As a result of the calculation, the transistor characteristics of all the structures in Fig. 6(A), Fig. 7(A), and Fig. 8(A) were substantially equivalent. The threshold value (Vth) of each transistor was 0.8 V, and the S value was 60 mV / dec, showing good values.

[0170] From these calculation results, even if the distance between the source electrode and the drain electrode (length in the channel length direction) is narrowed to 5 0 nm, short-channel effects such as a negative shift in the threshold value and an increase in the S value do not occur. It does not appear and shows good transistor characteristics.

[0171] For comparison, the same calculation was performed using the structure of a planar-type transistor instead of a trench structure. As a result, when the distance between the source electrode and the drain electrode (the length in the channel length direction) was narrowed, the channel length also became narrow, and short-channel effects such as a negative shift in the threshold value and an increase in the S value occurred. Furthermore, an increase in the leakage current (off-current) when a negative bias was applied to the gate was also confirmed.

[0172] Compared with the calculation results for this comparison, the calculation results in FIGS. 6(B), 7(B), and 8(B) are good. By adopting the transistor structure shown in Embodiment 1, even if the distance between the source electrode and the drain electrode (the length in the channel length direction) is narrowed, the change in the effective channel length is small. Therefore, the short-channel effect does not occur, and the off-current can be suppressed low. As a result, it becomes possible to fabricate a memory cell having good holding characteristics.

Explanation of Signs

[0173] 100 Substrate 108 Gate insulating layer 110 Gate electrode 116 Channel formation region 120 Impurity region 124 Metal compound region 126 Electrode 130 Insulating layer 142a, 142b Electrodes 143a, 143b Insulating layers 144 Wide-gap semiconductor layer 146 Gate insulating layer 148a, 148b Gate electrodes 149 Insulating layer 150 Insulating layer 151 Insulating layer 152 Insulating layer 153 Electrode 154 Electrode 156 Wiring 160 Transistor 161 Element isolation region 162 Transistor 163 Transistor 164 Capacitor 165 Element isolation region 250 Memory cell 251 Memory cell array 253 Peripheral circuit 254 Capacitor 310 Semiconductor substrate 312 STI region 314 Gate insulating layer 316 Semiconductor layer 318 Conductive layer 320 Protection insulating layer 322 Sidewall insulating layer 324 Impurity region 325 Connection electrode 326 Insulating layer 328 Electrode 329 Insulating layer 330 Connection electrode 331 Connection electrode 332 Electrode 334 Connection electrode 336 Electrode 338 Connection electrode 350 Transistor 400 Peripheral circuit 402 Substrate 403 Element isolation insulating layer 404 Channel formation region 406 Impurity region 408 High-concentration impurity region 410 Metal compound region 411 Gate insulating layer 412 Gate electrode 414 Sidewall insulating layer 418a Source electrode or drain electrode 418b Source electrode or drain electrode 420 Interlayer Insulation Layer 422 Interlayer Insulation Layer 424a Electrode 424b Electrode 424c Electrode 425 Insulation Layer 426 Connection Electrode 428 Electrode 430 Connection Electrode 432 Wiring 434 Connection Electrode 436 Electrode 438 Connection Electrode 440 Wiring 450 Transistor 452a Memory Cell 452b Memory Cell 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X - Decoder 808 Y - Decoder 811 Transistor 812 Holding Capacitance 813 X - Decoder 814 Y - Decoder 901 RF Circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power Supply Circuit 906 Application Processor 907 CPU 908 DSP 909 Interface 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display Unit 915 Source Driver 916 Gate Driver 917 Audio Circuit 918 Keyboard 919 Touch Sensor 950 Memory Circuit 951 Memory Controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display Controller 957 Display 1001 Battery 1002 Power Circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 Keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller

Claims

【Claim 1】 a first trench and a second trench in an insulating layer; a wide-gap semiconductor layer in contact with a bottom surface and an inner wall surface of the first trench; a gate insulating layer on the wide-gap semiconductor layer; a gate electrode on the gate insulating layer; the gate insulating layer on a bottom surface and an inner wall surface of the second trench; an insulating layer filling the second trench; and the gate electrode fills the first trench, a semiconductor device characterized by this.

Images