SiC SEMICONDUCTOR SWITCHING DEVICE

Abstract

To provide an SiC semiconductor device with which an external force can be relaxed.SOLUTION: An SiC semiconductor device includes: an SiC chip having a first main surface at one side and a second main surface at another side; a first main surface electrode including a first Al layer and formed on the first main surface; a pad electrode formed on the first main surface electrode and to be connected to a lead wire; and a second main surface electrode including a second Al layer and formed on the second main surface.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a SiC semiconductor device.

Background Art

[0002] Patent Document 1 discloses a SiC semiconductor device including a SiC substrate (SiC chip), a pad electrode containing Al and formed on the surface of the SiC substrate, and an ohmic electrode formed on the back surface of the SiC substrate. A bonding wire (conductive wire) is bonded to the pad electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the post-process (assembly process), various external forces are applied to the SiC semiconductor device. For example, when mounting the SiC semiconductor device, a mounter equipped with a suction nozzle is used. The SiC semiconductor device is transported to the connection object while being adsorbed and held by the suction nozzle, and then press-mounted to the connection target part. At this time, an external force from the suction nozzle toward the connection object and an external force from the connection object toward the suction nozzle are applied to the SiC semiconductor device.

[0005] Also, after mounting the SiC semiconductor device, the conductive wire is press-bonded to the pad electrode by a capillary. At this time, an external force from the capillary toward the connection object and an external force from the connection object toward the capillary are applied to the SiC semiconductor device. When an external force exceeding the strength of the SiC chip is applied to the SiC semiconductor device, cracks occur in the SiC chip.

[0006] One embodiment of the present invention provides a SiC semiconductor device capable of relaxing external forces.

Means for Solving the Problem

[0007] One embodiment of the present invention provides a SiC semiconductor device including a SiC chip having a first main surface on one side and a second main surface on the other side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and connected to a conducting wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

[0008] According to this SiC semiconductor device, the first Al layer is formed as a first buffer layer that relaxes external forces on the first main surface side, and the second Al layer is formed as a second buffer layer that relaxes external forces on the second main surface side. Thereby, external forces in the direction from the first main surface toward the second main surface and external forces in the direction from the second main surface toward the first main surface can be relaxed.

[0009] The above-mentioned or further other objects, features, and effects in the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0010]

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MODE FOR CARRYING OUT THE INVENTION

[0011] FIG. 1 is a plan view showing the SiC semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1, showing a form in which the second main surface electrode 31 according to the first exemplary form is incorporated. FIG. 3 is a cross-sectional view schematically showing the second main surface electrode 31 shown in FIG. 2.

[0012] Referring to FIGS. 1 and 2, the SiC semiconductor device 1 includes an SiC chip 2. The SiC chip 2 includes a hexagonal SiC single crystal. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. according to the period of the atomic arrangement. In this embodiment, the SiC chip 2 is made of a 4H-SiC single crystal, but does not exclude other polytypes.

[0013] The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") when viewed from their normal direction Z.

[0014] The thickness of the SiC chip 2 may be 40 μm or more and 300 μm or less. The thickness of the SiC chip 2 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less. The thickness of the SiC chip 2 is preferably 60 μm or more and 150 μm or less.

[0015] The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the silicon plane ((0001) plane) of the SiC single crystal. The first main surface 3 is a non-mounting surface. The second main surface 4 faces the carbon plane ((000-1) plane) of the SiC single crystal. The second main surface 4 is a mounting surface. The second main surface 4 may be a rough surface having either or both of grinding marks and annealing marks. The annealing mark is a laser irradiation mark. The second main surface 4 may be an ohmic surface having an annealing mark.

[0016] The first major surface 3 and the second major surface 4 have an off-angle that is inclined at an angle of 0° or more and 10° or less with respect to the a-axis direction ([11-20] direction) with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off-angle with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0017] The off-angle may be 0° or more and 6° or less. The off-angle may be 0° or more and 2° or less, 2° or more and 4° or less, or 4° or more and 6° or less. The off-angle is preferably more than 0° and 4.5° or less. The off-angle may be 3° or more and 4.5° or less. In this case, the off-angle is preferably 3° or more and 3.5° or less, or 3.5° or more and 4° or less. The off-angle may be 1.5° or more and 3° or less. In this case, the off-angle is preferably 1.5° or more and 2° or less, or 2° or more and 2.5° or less.

[0018] The side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend along the first direction X and face each other in the second direction Y that intersects the first direction X. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.

[0019] The first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal. The first side surface 5A and the second side surface 5B may form an inclined surface that is inclined toward the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z when the normal direction Z is used as a reference. When the normal direction Z is set to 0°, the first side surface 5A and the second side surface 5B may be inclined at an angle corresponding to the off-angle with respect to the normal direction Z. The angle corresponding to the off-angle may be equal to the off-angle or may be an angle greater than 0° and less than the off-angle.

[0020] The third side surface 5C and the fourth side surface 5D may be formed by an m-plane of a SiC single crystal. The third side surface 5C and the fourth side surface 5D extend planarly along the normal direction Z. More specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0021] The side surfaces 5A to 5D may be cleaved or ground surfaces. The length of the side surfaces 5A to 5D may be 0.1 mm or more and 10 mm or less. The length of the side surfaces 5A to 5D is preferably 0.5 mm or more and 2.5 mm or less.

[0022] In this embodiment, the SiC chip 2 is + The SiC chip 2 has a layered structure including an n-type SiC semiconductor substrate 6 and an n-type SiC epitaxial layer 7. The second main surface 4 of the SiC chip 2 is formed by the SiC semiconductor substrate 6. The first main surface 3 of the SiC chip 2 is formed by the SiC epitaxial layer 7. The SiC semiconductor substrate 6 and the SiC epitaxial layer 7 form side surfaces 5A to 5D of the SiC chip 2.

[0023] The n-type impurity concentration of the SiC epitaxial layer 7 is less than the n-type impurity concentration of the SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0024] The thickness of the SiC semiconductor substrate 6 may be 40 μm or more and 250 μm or less. The thickness of the SiC semiconductor substrate 6 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, or 200 μm or more and 250 μm or less. The thickness of the SiC semiconductor substrate 6 is preferably 40 μm or more and 150 μm or less. By thinning the SiC semiconductor substrate 6, the resistance value of the SiC semiconductor substrate 6 can be reduced.

[0025] The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 7 is preferably 5 μm or more and 15 μm or less.

[0026] The SiC chip 2 includes an active region 8 and an outer region 9. The active region 8 is a region including an SBD (Schottky Barrier Diode) as an example of a functional device (diode). The active region 8 is formed at the central portion of the SiC chip 2 at an interval inward from the side surfaces 5A to 5D in a plan view. The active region 8 is formed in a square shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0027] The outer region 9 is a region outside the active region 8. The outer region 9 is formed in the region between the side surfaces 5A to 5D and the active region 8. The outer region 9 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 8 in a plan view.

[0028] The SiC semiconductor device 1 includes an n-type diode region 10 formed in the surface layer portion of the first main surface 3 in the active region 8. The diode region 10 is formed at the central portion of the first main surface 3. The planar shape of the diode region 10 is arbitrary. The diode region 10 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in plan view.

[0029] In this embodiment, the diode region 10 is formed by using a part of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 may exceed the n-type impurity concentration of the SiC epitaxial layer 7. In this case, the diode region 10 is formed by introducing n-type impurities into the surface layer portion of the SiC epitaxial layer 7.

[0030] In the outer region 9, a guard region 11 containing p-type impurities is formed in the surface layer portion of the first main surface 3. The p-type impurities in the guard region 11 may not be activated or may be activated.

[0031] The guard region 11 is formed in a strip shape extending along the diode region 10 in plan view. More specifically, the guard region 11 is formed in an annular shape (more specifically, endless shape) surrounding the diode region 10 in plan view. Thereby, the guard region 11 is formed as a guard ring region.

[0032] The active region 8 (diode region 10) is defined by the guard region 11. The planar shape of the active region 8 (diode region 10) is adjusted by the planar shape of the guard region 11. The guard region 11 may be formed in a polygonal annular shape or a circular annular shape in plan view.

[0033] The SiC semiconductor device 1 includes a main surface insulating layer 12 formed on the first main surface 3. The main surface insulating layer 12 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The main surface insulating layer 12 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the main surface insulating layer 12 has a single-layer structure composed of a silicon oxide layer.

[0034] The main surface insulating layer 12 includes a contact opening 13 that exposes the diode region 10. The contact opening 13 also exposes the inner peripheral edge of the guard region 11. The planar shape of the contact opening 13 is arbitrary. The contact opening 13 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0035] The peripheral edge of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D. In this form, the peripheral edge of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D. The peripheral edge of the main surface insulating layer 12 may be formed at an interval inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 exposes a portion located in the outer region 9 on the first main surface 3.

[0036] The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness of the main surface insulating layer 12 is 0.5 μm or more and 5 μm or less.

[0037] The SiC semiconductor device 1 includes a first main surface electrode 14 formed on the first main surface 3. The first main surface electrode 14 is connected to the diode region 10 and the guard region 11 within the contact opening 13. The first main surface electrode 14 is drawn out from the contact opening 13 onto the main surface insulating layer 12. The peripheral edge of the first main surface electrode 14 is formed on the main surface insulating layer 12 at an interval inward from the side surfaces 5A to 5D.

[0038] More specifically, the first main surface electrode 14 has a laminated structure including a Schottky barrier layer 15 (barrier layer) and a first Al layer 16 laminated in this order from the side of the first main surface 3. The first Al layer 16 is formed as a first buffer layer that relaxes the external force applied to the SiC chip 2 from the side of the first main surface 3 by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus).

[0039] The Schottky barrier layer 15 is formed in a film shape along the first main surface 3 and the main surface insulating layer 12. The Schottky barrier layer 15 forms a Schottky junction with the diode region 10. Thereby, an SBD is formed with the first main surface electrode 14 as the anode and the diode region 10 as the cathode. That is, the first main surface electrode 14 is the anode electrode of the SBD.

[0040] The Schottky barrier layer 15 may contain at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the Schottky barrier layer 15 may be 0.01 μm or more and 5 μm or less. The thickness of the Schottky barrier layer 15 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less.

[0041] The first Al layer 16 is formed on the Schottky barrier layer 15. The first Al layer 16 is formed in a film shape along the Schottky barrier layer 15. The first Al layer 16 covers the entire main surface of the Schottky barrier layer 15. The periphery of the first main surface electrode 14 is formed by the Schottky barrier layer 15 and the first Al layer 16.

[0042] The first Al layer 16 contains at least one of a pure Al layer (referring to an Al layer made of Al with a purity of 99% or more. The same applies hereinafter), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The first Al layer 16 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in an arbitrary order.

[0043] The first Al layer 16 may have a single-layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. It is preferable that the first Al layer 16 has a single-layer structure composed of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0044] The thickness of the first Al layer 16 exceeds the thickness of the Schottky barrier layer 15. The thickness of the first Al layer 16 may be 0.05 μm or more and 10 μm or less. The thickness of the first Al layer 16 may be 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness of the first Al layer 16 is 1 μm or more and 8 μm or less.

[0045] The SiC semiconductor device 1 includes an insulating layer 17 that covers the first main surface electrode 14 on the first main surface 3. In FIG. 1, the insulating layer 17 is shown by hatching. More specifically, the insulating layer 17 is formed on the main surface insulating layer 12. The periphery of the insulating layer 17 is formed at an interval inward from the side surfaces 5A to 5D. Thereby, the insulating layer 17 exposes a portion that covers the outer region 9 in the main surface insulating layer 12.

[0046] The periphery of the insulating layer 17 demarcates a dicing street DS between the side surfaces 5A to 5D. According to the dicing street DS, when cutting out the SiC semiconductor device 1 from the SiC wafer, it is not necessary to physically cut the insulating layer 17. Thereby, the SiC semiconductor device 1 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the insulating layer 17 can be suppressed. As a result, the insulating layer 17 can appropriately protect the objects to be protected such as the SiC chip 2 and the first main surface electrode 14.

[0047] The width of the dicing street DS may be 1 μm or more and 25 μm or less. The width of the dicing street DS is the width in the direction orthogonal to the direction in which the dicing street DS extends. The width of the dicing street DS may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0048] The insulating layer 17 has a pad opening 18 that exposes the first main surface electrode 14. In this form, the pad opening 18 exposes the first main surface electrode 14 within the region surrounded by the contact opening 13 in a plan view. The pad opening 18 may surround the contact opening 13 in a region outside the contact opening 13 in a plan view. The planar shape of the pad opening 18 is arbitrary. The pad opening 18 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0049] In this form, the insulating layer 17 has a laminated structure including a passivation layer 19 and a resin layer 20 laminated in this order from the SiC chip 2 side.

[0050] The passivation layer 19 may include at least one of a silicon oxide layer and a silicon nitride layer. The passivation layer 19 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The passivation layer 19 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. The passivation layer 19 preferably contains an insulating material different from the main surface insulating layer 12. In this form, the passivation layer 19 has a single-layer structure composed of a silicon nitride layer.

[0051] The passivation layer 19 is formed in a film shape along the main surface insulating layer 12 and the first main surface electrode 14. The passivation layer 19 has a first opening 21 that exposes a part of the first main surface electrode 14. The planar shape of the first opening 21 is arbitrary. The first opening 21 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0052] The thickness of the passivation layer 19 may be 0.1 μm or more and 20 μm or less. The thickness of the passivation layer 19 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0053] The resin layer 20 is formed in a film shape along the main surface of the passivation layer 19. The resin layer 20 may contain a photosensitive resin. The photosensitive resin may be of a negative type or a positive type. The resin layer 20 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the resin layer 20 contains polybenzoxazole.

[0054] In this form, the periphery of the resin layer 20 exposes the periphery of the passivation layer 19. The periphery of the insulating layer 17 is formed by the periphery of the resin layer 20 and the periphery of the passivation layer 19. The resin layer 20 may cover the periphery of the passivation layer 19.

[0055] The resin layer 20 has a second opening 22 that exposes a part of the first main surface electrode 14. The planar shape of the second opening 22 is arbitrary. The second opening 22 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in plan view. The second opening 22 communicates with the first opening 21 of the passivation layer 19 and forms one pad opening 18 with the first opening 21.

[0056] The inner wall of the second opening 22 may be flush with the inner wall of the first opening 21. The inner wall of the second opening 22 may be located on the side surfaces 5A to 5D side with respect to the inner wall of the first opening 21. The inner wall of the second opening 22 may be located inside the SiC chip 2 with respect to the inner wall of the first opening 21. That is, the resin layer 20 may cover the inner wall of the first opening 21.

[0057] The thickness of the resin layer 20 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 20 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0058] The SiC semiconductor device 1 includes a pad electrode 23 formed on the first main surface electrode 14. The pad electrode 23 is electrically connected to the first main surface electrode 14. The pad electrode 23 is formed on the first main surface electrode 14 within the pad opening 18. The pad electrode 23 has a terminal surface 24 that is externally connected to a conducting wire.

[0059] The terminal surface 24 is located on the first main surface electrode 14 side with respect to the main surface of the insulating layer 17 (resin layer 20). The terminal surface 24 may protrude above the main surface of the insulating layer 17 (resin layer 20). The terminal surface 24 may have an overlap portion that covers the main surface of the insulating layer 17 (resin layer 20).

[0060] The pad electrode 23 includes a metal material different from that of the first main surface electrode 14. In this form, the pad electrode 23 has a laminated structure including a Ni layer 25, a Pd layer 26, and an Au layer 27 laminated in this order from the first main surface electrode 14 side. Ni, Pd, and Au each have a Young's modulus (rigidity modulus) that exceeds the Young's modulus (rigidity modulus) of Al. The Ni layer 25, the Pd layer 26, and the Au layer 27 may be plating layers formed by a plating method.

[0061] The pad electrode 23 only needs to include at least one of the Ni layer 25, the Pd layer 26, and the Au layer 27. The pad electrode 23 may have a laminated structure in which at least two of the Ni layer 25, the Pd layer 26, and the Au layer 27 are laminated in an arbitrary order. The pad electrode 23 may have a single-layer structure composed of the Ni layer 25, the Pd layer 26, or the Au layer 27.

[0062] The pad electrode 23 preferably has a terminal surface 24 formed by the Au layer 27. The pad electrode 23 preferably has a laminated structure including an Ni layer 25 and an Au layer 27 laminated in this order at least from the first main surface electrode 14 side.

[0063] The thickness of the Ni layer 25 may be 0.1 μm or more and 10 μm or less. The thickness of the Ni layer 25 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0064] The thickness of the Pd layer 26 may be 0.1 μm or more and 10 μm or less. The thickness of the Pd layer 26 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0065] The thickness of the Au layer 27 may be 0.01 μm or more and 3 μm or less. The thickness of the Au layer 27 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less. The thickness of the Au layer 27 is preferably less than the thickness of the Ni layer 25. The thickness of the Au layer 27 is preferably less than the thickness of the Pd layer 26.

[0066] Referring to FIGS. 2 and 3, the SiC semiconductor device 1 includes a second main surface electrode 31 formed on the second main surface 4. The second main surface electrode 31 is formed as a cathode electrode of the SBD. In this form, the second main surface electrode 31 covers the entire area of the second main surface 4.

[0067] The second main surface electrode 31 is formed at an interval inward from the side surfaces 5A to 5D, and the peripheral portion of the second main surface 4 may be exposed. In this case, when cutting out the SiC semiconductor device 1 from the SiC wafer, it is not necessary to physically cut the second main surface electrode 31. As a result, the SiC semiconductor device 1 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the second main surface electrode 31 can be suppressed. As a result, the second main surface electrode 31 can be appropriately connected to the second main surface 4.

[0068] Such a second main surface electrode 31 can be obtained, for example, by removing unnecessary portions of the second main surface electrode 31 by an etching method through a resist mask during the manufacturing process. Further, as another example, the second main surface electrode 31 can be obtained by forming the second main surface electrode 31 that partially covers the second main surface 4 by a lift-off method using a resist mask during the manufacturing process.

[0069] The second main surface electrode 31 includes a second Al layer 32 that covers the second main surface 4. The second Al layer 32 faces the first Al layer 16 of the first main surface electrode 14 with the SiC chip 2 interposed therebetween. The second Al layer 32 is formed as a second buffer layer that relaxes the external force applied to the SiC chip 2 from the second main surface 4 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus).

[0070] The second Al layer 32 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The second Al layer 32 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in an arbitrary order. The second Al layer 32 may be formed by a sputtering method and / or a vapor deposition method.

[0071] The second Al layer 32 may have a single-layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. The Al-based metal material of the second Al layer 32 may be different from that of the first Al layer 16. The second Al layer 32 preferably has a single-layer structure composed of a pure Al layer.

[0072] The second Al layer 32 may have a thickness less than that of the first Al layer 16. The thickness of the second Al layer 32 may be 0.01 μm or more and 5 μm or less. The thickness of the second Al layer 32 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less.

[0073] In addition to the second Al layer 32, the second main surface electrode 31 further includes one or more electrode layers made of a metal material different from that of the second Al layer 32. In this form, the second main surface electrode 31 includes a Ti layer 33, a Ni layer 34, a Pd layer 35, an Au layer 36, and an Ag layer 37 laminated in this order from the side of the second main surface 4 as an example of a plurality of electrode layers.

[0074] The Ti layer 33 is an ohmic electrode that forms an ohmic contact with the second main surface 4. The second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37 interposed therebetween.

[0075] Ti, Ni, Pd, Au, and Ag each have a Young's modulus (rigidity modulus) exceeding that of Al. The Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37 may be formed by a sputtering method, a vapor deposition method, and / or a plating method.

[0076] The second main surface electrode 31 may include at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37 as one or more electrode layers. The second Al layer 32 preferably covers the second main surface 4 with at least the Ti layer 33 interposed therebetween.

[0077] When the second main surface electrode 31 includes at least one of the Ni layer 34, the Pd layer 35, and the Au layer 36, at least one of the Ni layer 34, the Pd layer 35, and the Au layer 36 may be an electroplated layer formed simultaneously with the Ni layer 25, the Pd layer 26, and the Au layer 27 of the pad electrode 23.

[0078] The thickness of the Ti layer 33 may be 0.01 μm or more and 3 μm or less. The thickness of the Ti layer 33 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less.

[0079] The thickness of the Ni layer 34 may be 0.1 μm or more and 10 μm or less. The thickness of the Ni layer 34 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the Ni layer 34 preferably exceeds the thickness of the Ti layer 33.

[0080] The thickness of the Pd layer 35 may be 0.1 μm or more and 10 μm or less. The thickness of the Pd layer 35 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the Pd layer 35 preferably exceeds the thickness of the Ti layer 33.

[0081] The thickness of the Au layer 36 may be 0.01 μm or more and 3 μm or less. The thickness of the Au layer 36 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less. The thickness of the Au layer 36 is preferably less than the thickness of the Ni layer 34. The thickness of the Au layer 36 is preferably less than the thickness of the Pd layer 35.

[0082] The thickness of the Ag layer 37 may be 0.01 μm or more and 3 μm or less. The thickness of the Ag layer 37 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less. The thickness of the Ag layer 37 is preferably less than the thickness of the Ni layer 34. The thickness of the Ag layer 37 is preferably less than the thickness of the Pd layer 35.

[0083] The second main surface electrode 31 may have the structure shown in FIGS. 4A to 4I.

[0084] FIG. 4A is a cross-sectional view schematically showing the second main surface electrode 31 according to the second exemplary form. Hereinafter, for the structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals will be given and the description will be omitted.

[0085] Referring to FIG. 4A, in this form, the second main surface electrode 31 has a laminated structure including a second Al layer 32, a Ti layer 33, a Ni layer 34, a Pd layer 35, and an Au layer 36. The Ti layer 33, the Ni layer 34, the Pd layer 35, and the Au layer 36 are laminated in this order from the second main surface 4 side. The second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, the Pd layer 35, and the Au layer 36 interposed therebetween.

[0086] FIG. 4B is a cross-sectional view schematically showing the second main surface electrode 31 according to the third exemplary form. Hereinafter, for the structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals will be given and the description will be omitted.

[0087] Referring to FIG. 4B, in this form, the second main surface electrode 31 has a laminated structure including a second Al layer 32, a Ti layer 33, a Ni layer 34, an Au layer 36, and an Ag layer 37. The Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 are laminated in this order from the second main surface 4 side. The second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 interposed therebetween.

[0088] FIG. 4C is a cross-sectional view schematically showing the second main surface electrode 31 according to the fourth exemplary form. Hereinafter, for structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals are given and the description thereof is omitted.

[0089] Referring to FIG. 4C, in this form, the second main surface electrode 31 has a laminated structure including a second Al layer 32, a Ti layer 33, a Ni layer 34, and an Au layer 36. The Ti layer 33, the Ni layer 34, and the Au layer 36 are laminated in this order from the side of the second main surface 4. The second Al layer 32 covers the second main surface 4 with the Ti layer 33, the Ni layer 34, and the Au layer 36 interposed therebetween.

[0090] FIG. 4D is a cross-sectional view schematically showing the second main surface electrode 31 according to the fifth exemplary form. Hereinafter, for structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals are given and the description thereof is omitted.

[0091] Referring to FIG. 4D, in this form, the second main surface electrode 31 has a laminated structure including a second Al layer 32 and a Ti layer 33. The Ti layer 33 is connected to the second main surface 4. The second Al layer 32 covers the second main surface 4 with the Ti layer 33 interposed therebetween.

[0092] FIG. 4E is a cross-sectional view schematically showing the second main surface electrode 31 according to the sixth exemplary form. Hereinafter, for structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals are given and the description thereof is omitted.

[0093] Referring to FIG. 4E, in this form, the second main surface electrode 31 includes a second Al layer 32, a Ti layer 33, a Ni layer 34, and an Au layer 36. The Ti layer 33, the Ni layer 34, and the Au layer 36 are laminated in this order from the side of the second main surface 4. The second Al layer 32 is interposed between the Ti layer 33 and the Ni layer 34 and covers the second main surface 4 with the Ti layer 33 interposed therebetween.

[0094] In this case, the pad electrode 23 preferably has a two-layer structure composed of a Ni layer 25 and an Au layer 27 laminated in this order from the first main surface electrode 14 side. The Ni layer 34 and the Au layer 36 of the second main surface electrode 31 can be formed simultaneously with the Ni layer 25 and the Au layer 27 of the pad electrode 23 by electroplating.

[0095] FIG. 4F is a cross-sectional view schematically showing the second main surface electrode 31 according to the seventh exemplary form. Hereinafter, for structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals are given and the description thereof is omitted.

[0096] Referring to FIG. 4F, in this form, the second main surface electrode 31 includes a second Al layer 32, a Ti layer 33, a Ni layer 34, an Au layer 36, and an Ag layer 37. The Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 are laminated in this order from the second main surface 4 side. The second Al layer 32 is interposed between the Ti layer 33 and the Ni layer 34 and covers the second main surface 4 with the Ti layer 33 interposed therebetween.

[0097] In this case, the pad electrode 23 preferably has a two-layer structure composed of a Ni layer 25 and an Au layer 27 laminated in this order from the first main surface electrode 14 side. The Ni layer 34 and the Au layer 36 of the second main surface electrode 31 can be formed simultaneously with the Ni layer 25 and the Au layer 27 of the pad electrode 23 by electroplating.

[0098] FIG. 4G is a cross-sectional view schematically showing the second main surface electrode 31 according to the eighth exemplary form. Hereinafter, for structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals are given and the description thereof is omitted.

[0099] Referring to FIG. 4G, in this form, the second main surface electrode 31 includes a second Al layer 32, a Ti layer 33, a Ni layer 34, a Pd layer 35, an Au layer 36, and an Ag layer 37. The Ti layer 33, the Ni layer 34, the Au layer 36, and the Ag layer 37 are laminated in this order from the second main surface 4 side. The second Al layer 32 is interposed between the Ti layer 33 and the Ni layer 34 and covers the second main surface 4 with the Ti layer 33 interposed therebetween.

[0100] In this case, the pad electrode 23 preferably has a three-layer structure composed of a Ni layer 25, a Pd layer 26, and an Au layer 27 laminated in this order from the side of the first main surface electrode 14. The Ni layer 34, Pd layer 35, and Au layer 36 of the second main surface electrode 31 can be formed simultaneously with the Ni layer 25, Pd layer 26, and Au layer 27 of the pad electrode 23 by electroplating.

[0101] FIG. 4H is a cross-sectional view schematically showing the second main surface electrode 31 according to the ninth exemplary form. Hereinafter, for the structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals are given and the description is omitted.

[0102] Referring to FIG. 4H, in this form, the second main surface electrode 31 includes a second Al layer 32, a Ti layer 33, a Ni layer 34, a Pd layer 35, and an Au layer 36. The Ti layer 33, Ni layer 34, Pd layer 35, and Au layer 36 are laminated in this order from the side of the second main surface 4. The second Al layer 32 is interposed between the Ti layer 33 and the Ni layer 34 and covers the second main surface 4 with the Ti layer 33 interposed therebetween.

[0103] In this case, the pad electrode 23 preferably has a three-layer structure composed of a Ni layer 25, a Pd layer 26, and an Au layer 27 laminated in this order from the side of the first main surface electrode 14. The Ni layer 34, Pd layer 35, and Au layer 36 of the second main surface electrode 31 can be formed simultaneously with the Ni layer 25, Pd layer 26, and Au layer 27 of the pad electrode 23 by electroplating.

[0104] FIG. 4I is a cross-sectional view schematically showing the second main surface electrode 31 according to the tenth exemplary form. Hereinafter, for the structures corresponding to the structures described in FIGS. 1 to 3, the same reference numerals are given and the description is omitted.

[0105] Referring to FIG. 4I, in this embodiment, the second main surface electrode 31 includes a second Al layer 32 and a silicide layer 38. The silicide layer 38 is formed on the second main surface 4. The silicide layer 38 is a layer in which SiC exposed from the second main surface 4 is silicided by a metal material. The silicide layer 38 may include at least one of an FeSi2 layer, a NiSi layer, a NiSi2 layer, a CoSi2 layer, a CrSi2 layer, a WSi2 layer, a MoSi2 layer, a MnSi2 layer, a NbSi2 layer, a TiSi2 layer, and a VSi2 layer.

[0106] The second Al layer 32 covers the second main surface 4 with the silicide layer 38 interposed therebetween. The second main surface electrode 31 may include at least one of a Ti layer 33, a Ni layer 34, a Pd layer 35, an Au layer 36, and an Ag layer 37 in addition to the second Al layer 32 and the silicide layer 38. The stacking order of the second Al layer 32, the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37 is arbitrary. As a structure for covering the silicide layer 38, any one of the first to tenth form examples of the stacked structure may be adopted.

[0107] FIG. 5 is a diagram showing a semiconductor package 41 in which the SiC semiconductor device 1 shown in FIG. 1 is incorporated. In FIG. 5, the internal structure of the semiconductor package 41 is shown through the package body 42.

[0108] Referring to FIG. 5, in this embodiment, the semiconductor package 41 is a two-terminal type TO-220. The semiconductor package 41 includes a package body 42, a metal plate 43, a first terminal 44, a second terminal 45, the SiC semiconductor device 1, a conductive bonding material 46, and a lead wire 47.

[0109] The package body 42 is made of a mold resin. The package body 42 may include an epoxy resin as an example of the mold resin. The package body 42 is formed in a rectangular parallelepiped shape. The package body 42 includes a first surface 48 on one side and a second surface 49 on the other side, and four side surfaces 50A, 50B, 50C, 50D connecting the first surface 48 and the second surface 49.

[0110] The four side surfaces 50A to 50D more specifically include a first side surface 50A, a second side surface 50B, a third side surface 50C, and a fourth side surface 50D. The first side surface 50A and the second side surface 50B face each other. The third side surface 50C and the fourth side surface 50D face each other.

[0111] The metal plate 43 may contain at least one of Fe, Au, Ag, Cu, and Al. The metal plate 43 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed. The planar shape of the metal plate 43 is arbitrary. In this form, the metal plate 43 is formed in a rectangular shape (a rectangular shape) in a plan view.

[0112] The metal plate 43 integrally includes a pad portion 51 located inside the package body 42 and a heat sink portion 52 located outside the package body 42. The heat sink portion 52 is drawn out of the package body 42 across the second side surface 50B from the pad portion 51. The heat sink portion 52 includes a through hole 52a. The through hole 52a is formed in a circular shape.

[0113] In this form, the metal plate 43 is disposed inside the package body 42 so as to be exposed from the second surface 49. The metal plate 43 may be disposed inside the package body 42 so as not to be exposed from the second surface 49.

[0114] The first terminal 44 may contain at least one of Fe, Au, Ag, Cu, and Al. The first terminal 44 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed. The first terminal 44 is drawn out of the package body 42 across the first side surface 50A from inside the package body 42. The first terminal 44 is disposed in a region on the fourth side surface 50D side in a plan view. The first terminal 44 is disposed in a region on the first surface 48 side with respect to the plate surface of the metal plate 43.

[0115] The first terminal 44 includes a first inner end portion 53, a first outer end portion 54, and a first strip portion 55. The first inner end portion 53 is connected to the metal plate 43 within the package body 42. The first outer end portion 54 is disposed outside the package body 42. The first strip portion 55 extends between the first inner end portion 53 and the first outer end portion 54 in a direction orthogonal to the first side surface 50A.

[0116] The second terminal 45 may include at least one of Fe, Au, Ag, Cu, and Al. The second terminal 45 may include at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film. The second terminal 45 is drawn out from within the package body 42 across the first side surface 50A to the outside of the package body 42.

[0117] The second terminal 45 is disposed in a region on the third side surface 50C side at an interval from the first terminal 44 in a plan view. The second terminal 45 is disposed in a region on the first surface 48 side with respect to the plate surface of the metal plate 43.

[0118] The second terminal 45 includes a second inner end portion 56, a second outer end portion 57, and a second strip portion 58. The second inner end portion 56 is disposed within the package body 42 at an interval from the metal plate 43. The second outer end portion 57 is disposed outside the package body 42. The second strip portion 58 extends between the second inner end portion 56 and the second outer end portion 57 in a direction orthogonal to the first side surface 50A.

[0119] The SiC semiconductor device 1 is disposed on the pad portion 51 of the metal plate 43 within the package body 42. The conductive bonding material 46 is interposed between the SiC semiconductor device 1 and the pad portion 51, and joins the second main surface electrode 31 of the SiC semiconductor device 1 to the pad portion 51. Thereby, the SiC semiconductor device 1 is electrically connected to the first terminal 44 via the metal plate 43.

[0120] The conductive bonding material 46 may be a metal paste or solder. The metal paste may contain at least one of Au, Ag, and Cu. The conductive bonding material 46 preferably consists of solder. The solder may be lead-free solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi.

[0121] The conductive wire 47 consists of a metal wire (bonding wire) or a metal clip. The metal wire may be an Al wire, an Au wire, a Cu wire, or a solder wire. The solder wire may be a lead-free solder wire. The solder wire may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi. The metal clip may be an Al clip, an Au clip, or a Cu clip. In this form, the conductive wire 47 consists of a solder wire.

[0122] The conductive wire 47 is connected to the second inner end portion 56 of the second terminal 45 and the pad electrode 23 within the package body 42. Thereby, the SiC semiconductor device 1 is electrically connected to the second terminal 45.

[0123] In FIG. 5, an example in which one conductive wire 47 is connected to the second inner end portion 56 and the pad electrode 23 is shown, but the number of conductive wires 47 is arbitrary. Two or more conductive wires 47 may be connected to the second inner end portion 56 and the pad electrode 23.

[0124] The semiconductor package 41 can also take forms other than TO-220. The semiconductor package 41 may have forms such as SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package), or various forms similar thereto.

[0125] As described above, according to the SiC semiconductor device 1, the first Al layer 16 is formed as a first buffer layer that relaxes external forces on the first main surface 3 side, and the second Al layer 32 is formed as a second buffer layer that relaxes external forces on the second main surface 4 side. Thereby, external forces in the direction from the first main surface 3 toward the second main surface 4 and external forces in the direction from the second main surface 4 toward the first main surface 3 can be relaxed.

[0126] As an example, when mounting the SiC semiconductor device 1 on the pad portion 51 of the metal plate 43, the external forces applied to the SiC chip 2 can be relaxed by the first Al layer 16 and the second Al layer 32. Also, when bonding the wire 47 to the pad electrode 23 of the SiC semiconductor device 1, the external forces applied to the SiC chip 2 can be relaxed by the first Al layer 16 and the second Al layer 32. As a result, cracks in the SiC chip 2 can be suppressed.

[0127] The SiC semiconductor device 1 also includes a pad electrode 23 that is externally bonded to the wire 47. The pad electrode 23 includes at least one of the Ni layer 25, the Pd layer 26, and the Au layer 27. Thereby, the wire 47 can be appropriately connected to the pad electrode 23.

[0128] On the other hand, Ni, Pd, and Au each have a Young's modulus (rigidity modulus) that exceeds the Young's modulus (rigidity modulus) of Al. Therefore, in a structure provided with the pad electrode 23, external forces applied during bonding of the wire 47 cannot be appropriately relaxed.

[0129] Therefore, in the SiC semiconductor device 1, a first Al layer 16 containing Al is interposed between the SiC chip 2 and the pad electrode 23. According to the first Al layer 16, the external force applied to the SiC chip 2 can be relaxed from the side of the first main surface 3 by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus). Thus, the conductive wire 47 can be properly joined to the pad electrode 23, and at the same time, cracks in the SiC chip 2 can be suppressed.

[0130] In addition, the SiC semiconductor device 1 includes a second main surface electrode 31 having one or more electrode layers made of a metal material different from the second Al layer 32 in addition to the second Al layer 32. The one or more electrode layers include at least one of a Ti layer 33, a Ni layer 34, a Pd layer 35, an Au layer 36, and an Ag layer 37. Thereby, the adhesive force of the conductive joining material 46 to the second main surface electrode 31 can be appropriately increased. As a result, the SiC semiconductor device 1 can be properly mounted on the pad portion 51 of the metal plate 43.

[0131] On the other hand, Ti, Ni, Pd, Au, and Ag each have a Young's modulus (rigidity modulus) exceeding that of Al. Therefore, in a structure in which the second main surface electrode 31 includes at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37, the external force applied during the mounting of the SiC semiconductor device 1 or the joining of the conductive wire 47 cannot be appropriately relaxed.

[0132] Therefore, in the SiC semiconductor device 1, a second main surface electrode 31 including the second Al layer 32 is formed in addition to at least one of the Ti layer 33, the Ni layer 34, the Pd layer 35, the Au layer 36, and the Ag layer 37. According to the second Al layer 32, the external force applied to the SiC chip 2 can be relaxed from the side of the second main surface 4 by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus). Thus, the SiC semiconductor device 1 can be properly mounted on the pad portion 51, and at the same time, cracks in the SiC chip 2 can be suppressed.

[0133] FIG. 6 is a perspective view of an SiC semiconductor device 61 according to a second embodiment of the present invention, showing a form in which a second main surface electrode 200 according to a first form example is incorporated. FIG. 7 is a plan view of the SiC semiconductor device 61 shown in FIG. 6. FIG. 8 is a plan view in which the structure on the first main surface electrode 150 is removed.

[0134] FIG. 9 is an enlarged plan view showing the internal structure of the region IX shown in FIG. 8. FIG. 10 is a cross-sectional view taken along the line X-X shown in FIG. 9. FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG. 9. FIG. 12 is an enlarged view of the region XII shown in FIG. 10.

[0135] FIG. 13 is a cross-sectional view taken along the line XIII-XIII shown in FIG. 7. FIG. 14 is a cross-sectional view showing the gate pad electrode 191. FIG. 15 is a cross-sectional view showing the source pad electrode 192. FIG. 16 is a cross-sectional view schematically showing the second main surface electrode 200. FIGS. 14 and 15 are cross-sectional views showing the schematic structures of the gate pad electrode 191 and the source pad electrode 192, and do not show the cross-section of a specific portion.

[0136] Referring to FIGS. 6 to 13, the SiC semiconductor device 61 includes an SiC chip 62. The SiC chip 62 includes a hexagonal SiC single crystal. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. according to the period of the atomic arrangement. In this form, the SiC chip 62 is made of a 4H-SiC single crystal, but does not exclude other polytypes.

[0137] The SiC chip 62 has a first main surface 63 on one side, a second main surface 64 on the other side, and side surfaces 65A, 65B, 65C, 65D connecting the first main surface 63 and the second main surface 64. The first main surface 63 and the second main surface 64 are formed in a rectangular shape (rectangular shape in this form) in a plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction Z thereof.

[0138] The thickness of the SiC chip 62 may be 40 μm or more and 300 μm or less. The thickness of the SiC chip 62 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less. The thickness of the SiC chip 62 is preferably 60 μm or more and 150 μm or less.

[0139] In this form, the first main surface 63 and the second main surface 64 face the c-plane of the SiC single crystal. The first main surface 63 faces the silicon plane ((0001) plane) of the SiC single crystal. The first main surface 63 is a non-mounting surface. The second main surface 64 faces the carbon plane ((000-1) plane) of the SiC single crystal. The second main surface 64 is a mounting surface. The second main surface 64 may be a rough surface having either or both of grinding marks and annealing marks. The annealing mark is a laser irradiation mark. The second main surface 64 may be an ohmic surface having an annealing mark.

[0140] The first main surface 63 and the second main surface 64 have an off-angle inclined at an angle of 0° or more and 10° or less in the a-axis direction ([11-20] direction) with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off-angle with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0141] The off-angle may be 0° or more and 6° or less. The off-angle may be 0° or more and 2° or less, 2° or more and 4° or less, or 4° or more and 6° or less. The off-angle is preferably more than 0° and 4.5° or less. The off-angle may be 3° or more and 4.5° or less. In this case, the off-angle is preferably 3° or more and 3.5° or less, or 3.5° or more and 4° or less. The off-angle may be 1.5° or more and 3° or less. In this case, the off-angle is preferably 1.5° or more and 2° or less, or 2° or more and 2.5° or less.

[0142] The side surfaces 65A to 65D include a first side surface 65A, a second side surface 65B, a third side surface 65C, and a fourth side surface 65D. The first side surface 65A and the second side surface 65B extend along a first direction X and face each other in a second direction Y that intersects the first direction X. The first side surface 65A and the second side surface 65B form the short sides of the SiC chip 62 in a plan view. The third side surface 65C and the fourth side surface 65D extend along the second direction Y and face each other in the first direction X. The third side surface 65C and the fourth side surface 65D form the long sides of the SiC chip 62 in a plan view. The second direction Y is, more specifically, orthogonal to the first direction X.

[0143] In this form, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. That is, the first side surface 65A and the second side surface 65B are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction of the SiC single crystal. Also, the third side surface 65C and the fourth side surface 65D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction of the SiC single crystal.

[0144] The first side surface 65A and the second side surface 65B may form inclined surfaces that are inclined toward the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z when the normal direction Z is used as a reference. The first side surface 65A and the second side surface 65B may be inclined at an angle corresponding to the off-angle with respect to the normal direction Z when the normal direction Z is set to 0°. The angle corresponding to the off-angle may be equal to the off-angle or may be an angle greater than 0° and less than the off-angle.

[0145] The third side surface 65C and the fourth side surface 65D extend planar along the normal direction Z. The third side surface 65C and the fourth side surface 65D are, more specifically, formed substantially perpendicular to the first main surface 63 and the second main surface 64.

[0146] The side surfaces 65A to 65D may be cleavage surfaces or ground surfaces. The length of the side surfaces 65A to 65D may be 0.1 mm or more and 10 mm or less. The length of the side surfaces 65A to 65D is preferably 0.5 mm or more and 2.5 mm or less.

[0147] In this form, the SiC chip 62 has a laminated structure including an n + -type SiC semiconductor substrate 66 and an n-type SiC epitaxial layer 67. The SiC semiconductor substrate 66 is formed as a drain region 68. The SiC epitaxial layer 67 is formed as a drift region 69.

[0148] The second main surface 64 of the SiC chip 62 is formed by the SiC semiconductor substrate 66. The first main surface 63 of the SiC chip 62 is formed by the SiC epitaxial layer 67. The side surfaces 65A to 65D of the SiC chip 62 are formed by the SiC semiconductor substrate 66 and the SiC epitaxial layer 67.

[0149] The thickness of the SiC semiconductor substrate 66 may be 40 μm or more and 250 μm or less. The thickness of the SiC semiconductor substrate 66 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, or 200 μm or more and 250 μm or less. The thickness of the SiC semiconductor substrate 66 is preferably 40 μm or more and 150 μm or less. By thinning the SiC semiconductor substrate 66, the resistance value of the SiC semiconductor substrate 66 can be reduced.

[0150] The thickness of the SiC epitaxial layer 67 may be 1 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 67 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 67 is preferably 5 μm or more and 15 μm or less.

[0151] The n-type impurity concentration of the SiC epitaxial layer 67 is less than the n-type impurity concentration of the SiC semiconductor substrate 66. The n-type impurity concentration of the SiC semiconductor substrate 66 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the SiC epitaxial layer 67 may be 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0152] In this form, the SiC epitaxial layer 67 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 67 includes a high-concentration region 70 having a relatively high n-type impurity concentration and a low-concentration region 71 having a lower n-type impurity concentration than the high-concentration region 70.

[0153] The high-concentration region 70 is formed in the region on the first main surface 63 side. The low-concentration region 71 is formed in the region on the second main surface 64 side with respect to the high-concentration region 70. The thickness of the high-concentration region 70 is less than the thickness of the low-concentration region 71. The thickness of the high-concentration region 70 is less than half of the total thickness of the SiC epitaxial layer 67.

[0154] The peak value of the n-type impurity concentration in the high-concentration region 70 may be 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less. The peak value of the n-type impurity concentration in the low-concentration region 71 may be 1.0×10 15 cm -3 or more and 1.0×10 16 cm -3 or less.

[0155] The SiC chip 62 includes an active region 72 and an outer region 73. The active region 72 is a region where a MISFET (Metal Insulator Semiconductor Field Effect Transistor), which is an example of a functional device (transistor), is formed.

[0156] The active region 72 is formed at the central part of the SiC chip 62 at a distance inward from the side surfaces 65A to 65D in a plan view. The active region 72 is formed in a rectangular shape (a rectangular shape in this form) having four sides parallel to the side surfaces 65A to 65D in a plan view.

[0157] The outer region 73 is a region outside the active region 72. The outer region 73 is formed in a region between the side surfaces 65A to 65D and the periphery of the active region 72. The outer region 73 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.

[0158] The SiC semiconductor device 61 includes a p-type body region 74 formed in the surface layer portion of the first main surface 63 in the active region 72. The body region 74 defines the active region 72. The peak value of the p-type impurity concentration in the body region 74 is 1.0×10 17 cm -3 or more and may be 1.0×10 19 cm -3 or less. The peak value of the p-type impurity concentration in the body region 74 is preferably 1.0×10 18 cm -3 or more.

[0159] Referring to FIGS. 9 to 12, the SiC semiconductor device 61 includes a plurality of trench gate structures 75 formed on the first main surface 63 in the active region 72. The plurality of trench gate structures 75 are each formed in a strip shape extending along the first direction X and are formed at intervals along the second direction Y. The plurality of trench gate structures 75 are formed in a stripe shape as a whole in a plan view.

[0160] In this form, the plurality of trench gate structures 75 extend in a strip shape from the peripheral edge on one side (the third side surface 65C side) to the peripheral edge on the other side (the fourth side surface 65D side) in the active region 72. The plurality of trench gate structures 75 cross the middle part between the peripheral edge on one side and the peripheral edge on the other side in the active region 72.

[0161] The length of each trench gate structure 75 may be 1 mm or more and 10 mm or less. The length of each trench gate structure 75 may be 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or more and 6 mm or less, 6 mm or more and 8 mm or less, or 8 mm or more and 10 mm or less. The length of each trench gate structure 75 is preferably 2 mm or more and 6 mm or less. The total extension per unit area of one trench gate structure 75 is 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less.

[0162] Each trench gate structure 75 includes an active portion 76 and a contact portion 77. The active portion 76 is the portion along the channel of the MISFET. The contact portion 77 is the portion outside the channel of the MISFET. The contact portion 77 is the end of the trench gate structure 75 and mainly aims at external connection.

[0163] Each trench gate structure 75 includes a gate trench 78, a gate insulating layer 79, and a gate electrode 80. In FIG. 9, the gate insulating layer 79 and the gate electrode 80 are shown by hatching.

[0164] The gate trench 78 is formed in the SiC epitaxial layer 67 so as to penetrate the body region 74. The gate trench 78 includes side walls and a bottom wall. The side walls forming the long sides of the gate trench 78 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of the gate trench 78 are formed by the m-plane of the SiC single crystal.

[0165] The sidewall of the gate trench 78 may extend along the normal direction Z. The angle formed by the sidewall of the gate trench 78 with respect to the first main surface 63 within the SiC chip 62 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). The sidewall of the gate trench 78 may be formed substantially perpendicular to the first main surface 63. The gate trench 78 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0166] The bottom wall of the gate trench 78 is located in the high-concentration region 70. The bottom wall of the gate trench 78 faces the c-plane of the SiC single crystal. The bottom wall of the gate trench 78 has an off-angle inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The bottom wall of the gate trench 78 may be formed parallel to the first main surface 63. The bottom wall of the gate trench 78 may be formed in a curved shape toward the second main surface 64.

[0167] Regarding the normal direction Z, the depth of the gate trench 78 may be 0.5 μm or more and 3.0 μm or less. The depth of the gate trench 78 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, or 2.5 μm or more and 3.0 μm or less.

[0168] The width of the gate trench 78 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of the gate trench 78 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0169] The opening edge portion of the gate trench 78 includes an inclined portion that slopes downward from the first main surface 63 toward the inside of the gate trench 78. The opening edge portion of the gate trench 78 is a portion that connects the first main surface 63 and the sidewall of the gate trench 78.

[0170] The inclined portion of the gate trench 78 is formed in a curved shape that faces inward of the SiC chip 62. The inclined portion of the gate trench 78 may be formed in a curved shape that faces inward of the gate trench 78. The inclined portion of the gate trench 78 alleviates the electric field concentration with respect to the opening edge portion of the gate trench 78.

[0171] The gate insulating layer 79 contains at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The gate insulating layer 79 may have a laminated structure including a silicon nitride layer and a silicon oxide layer. The gate insulating layer 79 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the gate insulating layer 79 has a single-layer structure composed of a silicon oxide layer.

[0172] The gate insulating layer 79 is formed in a film shape along the inner wall of the gate trench 78 and partitions a recess space within the gate trench 78. The gate insulating layer 79 includes a first region 81, a second region 82, and a third region 83.

[0173] The first region 81 is formed along the side wall of the gate trench 78. The second region 82 is formed along the bottom wall of the gate trench 78. The third region 83 is formed along the first main surface 63.

[0174] The thickness of the first region 81 is less than the thickness of the second region 82 and the thickness of the third region 83. The thickness of the first region 81 may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 82 may be 0.05 μm or more and 0.5 μm or less. The thickness of the third region 83 may be 0.05 μm or more and 0.5 μm or less.

[0175] The gate insulating layer 79 includes a bulging portion 84 that bulges toward the inside of the gate trench 78 at the opening edge portion. The bulging portion 84 is formed at a corner connecting the first region 81 and the third region 83 of the gate insulating layer 79. The bulging portion 84 is formed in a curved shape facing inward of the gate trench 78. The bulging portion 84 narrows the opening of the gate trench 78 at the opening edge portion. A gate insulating layer 79 without the bulging portion 84 may be formed. A gate insulating layer 79 having a uniform thickness may be formed.

[0176] The gate electrode 80 is embedded in the gate trench 78 with the gate insulating layer 79 interposed therebetween. More specifically, the gate electrode 80 is embedded in a recessed space partitioned by the gate insulating layer 79 within the gate trench 78.

[0177] The gate electrode 80 has an upper end portion located on the opening side of the gate trench 78. The upper end portion of the gate electrode 80 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 78. The upper end portion of the gate electrode 80 has a constricted portion constricted along the bulging portion 84 of the gate insulating layer 79.

[0178] The gate electrode 80 includes p-type polysilicon doped with p-type impurities. The p-type impurities of the gate electrode 80 may include at least one of boron, aluminum, indium, and gallium.

[0179] The p-type impurity concentration of the gate electrode 80 exceeds the p-type impurity concentration of the body region 74. The p-type impurity concentration of the gate electrode 80 may be 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less. The sheet resistance of the gate electrode 80 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form). The thickness of the gate electrode 80 may be 0.5 μm or more and 3 μm or less.

[0180] Referring to FIGS. 9 and 11, the SiC semiconductor device 61 includes a gate wiring 85 formed on the first main surface 63 in the active region 72. In FIG. 9, the gate wiring 85 is indicated by hatching. More specifically, the gate wiring 85 is formed on the third region 83 of the gate insulating layer 79. The gate wiring 85 is formed along the first side surface 65A, the third side surface 65C, and the fourth side surface 65D in the active region 72, and partitions the region where the plurality of trench gate structures 75 are formed from three directions.

[0181] The gate wiring 85 is connected to a gate electrode 80 exposed from the contact portion 77 of the trench gate structure 75. In this form, the gate wiring 85 is formed by the lead-out portion of the gate electrode 80 drawn out from the gate trench 78 onto the first main surface 63. The upper end portion of the gate wiring 85 is connected to the upper end portion of the gate electrode 80.

[0182] The SiC semiconductor device 61 includes a low-resistance layer 86 that covers the gate electrode 80. The low-resistance layer 86 covers the upper end portion of the gate electrode 80 in the gate trench 78. The low-resistance layer 86 forms a part of the trench gate structure 75.

[0183] The low-resistance layer 86 includes a conductive material having a sheet resistance less than that of the gate electrode 80. The sheet resistance of the low-resistance layer 86 may be 0.01 Ω / sq or more and 10 Ω / sq or less.

[0184] More specifically, the low-resistance layer 86 includes a polyside layer. The polyside layer is formed by siliciding a portion of the surface layer of the gate electrode 80 with a metal material. More specifically, the polyside layer is composed of a p-type polyside layer containing p-type impurities added to the gate electrode 80 (p-type polysilicon). The polyside layer preferably has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0185] The sheet resistance in the gate trench 78 in which the gate electrode 80 and the low-resistance layer 86 are embedded is equal to or less than the sheet resistance of the gate electrode 80 alone. The sheet resistance in the gate trench 78 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0186] The sheet resistance in the gate trench 78 approximates the sheet resistance of the low-resistance layer 86. That is, the sheet resistance in the gate trench 78 may be 0.01 Ω / sq or more and 10 Ω / sq or less. The sheet resistance in the gate trench 78 is preferably less than 10 Ω / sq.

[0187] The low-resistance layer 86 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Among these types in particular, NiSi, CoSi2, and TiSi2 are suitable as the polyside layer for forming the low-resistance layer 86 because their resistivity values and temperature dependencies are relatively small. The low-resistance layer 86 most preferably consists of CoSi2, which has the property of less diffusion into other regions.

[0188] The low-resistance layer 86 includes a contact portion in contact with the gate insulating layer 79. More specifically, the contact portion of the low-resistance layer 86 is in contact with the third region 83 (bulge portion 84) of the gate insulating layer 79. The contact portion of the low-resistance layer 86 is formed in a region on the first main surface 63 side with respect to the bottom of the body region 74. More specifically, the contact portion of the low-resistance layer 86 is formed in a region on the first main surface 63 side with respect to the bottom of the source region 97 described later. The low-resistance layer 86 does not face the body region 74 with the gate insulating layer 79 interposed therebetween.

[0189] Thereby, formation of a current path between the low-resistance layer 86 and the body region 74 can be suppressed. In particular, a design in which the contact portion of the low-resistance layer 86 is connected to a relatively thick corner portion in the gate insulating layer 79 is effective in reducing the risk of a current path.

[0190] Regarding the normal direction Z, the thickness of the low-resistance layer 86 is preferably less than the thickness of the gate electrode 80. The thickness of the low-resistance layer 86 may be 0.01 μm or more and 3 μm or less.

[0191] The low-resistance layer 86 also covers the upper end portion of the gate wiring 85. The portion of the low-resistance layer 86 that covers the upper end portion of the gate wiring 85 is integrally formed with the portion of the low-resistance layer 86 that covers the upper end portion of the gate electrode 80. Thereby, the low-resistance layer 86 covers the entire area of the gate electrode 80 and the entire area of the gate wiring 85.

[0192] By embedding p-type polysilicon having a work function different from that of n-type polysilicon in the gate trench 78, the gate threshold voltage Vth can be increased by about 1 V. However, p-type polysilicon has a sheet resistance that is several tens of times (about 20 times) higher than the sheet resistance of n-type polysilicon. Therefore, when p-type polysilicon is adopted as the material of the gate electrode 80, the energy loss increases as the parasitic resistance (hereinafter simply referred to as "gate resistance") in the gate trench 78 increases.

[0193] Therefore, in the SiC semiconductor device 61, a low-resistance layer 86 (p-type polyside) is formed on the gate electrode 80 (p-type polysilicon). According to the low-resistance layer 86, the sheet resistance in the gate trench 78 can be reduced while allowing an increase in the gate threshold voltage Vth (for example, an increase of about 1 V).

[0194] For example, according to the structure having the low-resistance layer 86, the sheet resistance can be reduced to 1 / 100 or less compared to the case where the low-resistance layer 86 is not provided. Also, according to the structure having the low-resistance layer 86, the sheet resistance can be reduced to 1 / 5 or less compared to the gate electrode 80 including n-type polysilicon.

[0195] As a result, the gate resistance can be reduced, and current can be efficiently diffused along the trench gate structure 75. That is, the low-resistance layer 86 is formed as a current diffusion layer that diffuses current within the gate trench 78. In particular, in the case of the gate trench 78 having a length on the order of millimeters (a length of 1 mm or more), it takes time for current to be transmitted, but according to the low-resistance layer 86, the switching delay can be appropriately suppressed.

[0196] Also, according to the structure having the low-resistance layer 86, it is not necessary to increase the p-type impurity concentration in the body region 74 in order to increase the gate threshold voltage Vth. Therefore, the gate threshold voltage Vth can be appropriately increased while suppressing an increase in channel resistance.

[0197] The SiC semiconductor device 61 includes a plurality of trench source structures 91 respectively formed in regions between a plurality of trench gate structures 75 adjacent to each other. The plurality of trench source structures 91 are formed at intervals in the second direction Y (the a-axis direction of the SiC single crystal) in a manner sandwiching one trench gate structure 75.

[0198] The plurality of trench source structures 91 are each formed in a strip shape extending along the first direction X (the m-axis direction of the SiC single crystal). The plurality of trench source structures 91 are formed in a stripe shape as a whole in plan view. Regarding the second direction Y, the pitch between the central portions of adjacent trench source structures 91 may be 1.5 μm or more and 3 μm or less.

[0199] Each trench source structure 91 includes a source trench 92, a source insulating layer 93, and a source electrode 94. In FIG. 9, the source insulating layer 93 and the source electrode 94 are indicated by hatching.

[0200] The source trench 92 is formed in the SiC epitaxial layer 67 so as to penetrate the body region 74. The source trench 92 includes side walls and a bottom wall. The side walls forming the long sides of the source trench 92 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of the source trench 92 are formed by the m-plane of the SiC single crystal.

[0201] The side walls of the source trench 92 may extend along the normal direction Z. The angle formed by the side walls of the source trench 92 with respect to the first main surface 63 within the SiC chip 62 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). The side walls of the source trench 92 may be formed substantially perpendicular to the first main surface 63. The source trench 92 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0202] The bottom wall of the source trench 92 is located in the high-concentration region 70. The bottom wall of the source trench 92 is located in a region on the second main surface 64 side with respect to the bottom wall of the gate trench 78. The bottom wall of the source trench 92 is located in a region between the bottom wall of the gate trench 78 and the low-concentration region 71 with respect to the normal direction Z.

[0203] The bottom wall of the source trench 92 faces the c-plane of the SiC single crystal. The bottom wall of the source trench 92 has an off-angle inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal. The bottom wall of the source trench 92 may be formed parallel to the first main surface 63. The bottom wall of the source trench 92 may be formed in a curved shape toward the second main surface 64.

[0204] The depth of the source trench 92 exceeds the depth of the gate trench 78. The ratio of the depth of the source trench 92 to the depth of the gate trench 78 may be 1.5 or more under the condition that the source trench 92 is located within the high-concentration region 70. The ratio of the depth of the source trench 92 to the depth of the gate trench 78 is preferably 2 or more. The depth of the source trench 92 may be equal to the depth of the gate trench 78. In the normal direction Z, the depth of the source trench 92 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm).

[0205] The width of the source trench 92 along the second direction Y may exceed the width of the gate trench 78 along the second direction Y, or may be less than the width of the gate trench 78 along the second direction Y. The width of the source trench 92 along the second direction Y is preferably equal to the width of the gate trench 78 along the second direction Y. The width of the source trench 92 along the second direction Y may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

[0206] The source insulating layer 93 contains at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or tantalum oxide. The source insulating layer 93 may have a laminated structure including a silicon nitride layer and a silicon oxide layer. The source insulating layer 93 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the source insulating layer 93 has a single-layer structure composed of a silicon oxide layer.

[0207] The source insulating layer 93 is formed in a film shape along the inner wall of the source trench 92 and partitions a recess space within the source trench 92. The source insulating layer 93 includes a first region 95 and a second region 96.

[0208] The first region 95 is formed along the sidewall of the source trench 92. The second region 96 is formed along the bottom wall of the source trench 92. The thickness of the first region 95 is smaller than the thickness of the second region 96. The thickness of the first region 95 may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 96 may be 0.05 μm or more and 0.5 μm or less.

[0209] The thickness of the first region 95 may be substantially equal to the thickness of the first region 95 of the gate insulating layer 79. The thickness of the second region 96 may be substantially equal to the thickness of the second region 96 of the gate insulating layer 79. A source insulating layer 93 having a uniform thickness may be formed.

[0210] The source electrode 94 is embedded in the source trench 92 with the source insulating layer 93 interposed therebetween. More specifically, the source electrode 94 is embedded in the recessed space partitioned by the source insulating layer 93 in the source trench 92.

[0211] The source electrode 94 has an upper end portion located on the opening side of the source trench 92. The upper end portion of the source electrode 94 is formed on the bottom wall side of the source trench 92 with respect to the first main surface 63. The upper end portion of the source electrode 94 may be located above the first main surface 63.

[0212] The upper end portion of the source electrode 94 is formed in a curved shape that is recessed toward the bottom wall of the source trench 92. The upper end portion of the source electrode 94 may be formed parallel to the first main surface 63. With respect to the normal direction Z, the thickness of the source electrode 94 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0213] The source electrode 94 preferably contains polysilicon having properties similar to SiC in terms of material. Thereby, the stress generated in the SiC chip 62 can be reduced. In this form, the source electrode 94 contains p-type polysilicon doped with p-type impurities. In this case, the source electrode 94 can be formed simultaneously with the gate electrode 80.

[0214] The p-type impurity concentration of the source electrode 94 exceeds that of the body region 74. The p-type impurity concentration of the source electrode 94 may be equal to the p-type impurity concentration of the gate electrode 80. The p-type impurity concentration of the source electrode 94 is 1.0×10 18 cm -3 or more and may be 1.0×10 22 cm -3 or less.

[0215] The p-type impurity of the source electrode 94 may contain at least one of boron, aluminum, indium, and gallium. The sheet resistance of the source electrode 94 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form). The sheet resistance of the source electrode 94 may be equal to the sheet resistance of the gate electrode 80.

[0216] Instead of or in addition to p-type polysilicon, the source electrode 94 may contain at least one of n-type polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy.

[0217] The SiC semiconductor device 61 includes an n + -type source region 97 formed in a region along the side wall of the gate trench 78 in the surface layer portion of the body region 74. The peak value of the n-type impurity concentration of the source region 97 is 1.0×10 18 cm -3 or more and may be 1.0×10 21 cm -3 or less. The peak value of the n-type impurity concentration of the source region 97 is preferably 1.0×10 20 cm -3 or more.

[0218] A plurality of source regions 97 are formed along one side wall and the other side wall of the gate trench 78. The plurality of source regions 97 are each formed in a strip shape extending along the first direction X. The plurality of source regions 97 are formed in a stripe shape as a whole in a plan view. Each source region 97 is exposed from the side wall of the gate trench 78 and the side wall of each source trench 92.

[0219] In the source region 97, the portion along the side wall of the gate trench 78 defines the channel of the MISFET with the high-concentration region 70. The ON / OFF of the channel is controlled by the gate electrode 80.

[0220] The SiC semiconductor device 61 includes a p-type contact region 98 formed in a region along each source trench 92 in the surface layer portion of the first main surface 63. + The peak value of the p-type impurity concentration in each contact region 98 exceeds the peak value of the p-type impurity concentration in the body region 74. The peak value of the p-type impurity concentration in each contact region 98 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0221] In this form, a plurality of contact regions 98 are formed for each source trench 92. The plurality of contact regions 98 are formed at intervals along the corresponding source trench 92. The plurality of contact regions 98 are formed at intervals from the gate trench 78.

[0222] Each contact region 98 covers the side wall and the bottom wall of the corresponding source trench 92. The bottom of each contact region 98 may be formed parallel to the bottom wall of the corresponding source trench 92.

[0223] The portion of each contact region 98 that covers the side wall of the source trench 92 is formed in a region on the first main surface 63 side with respect to the bottom of the body region 74. The portion of each contact region 98 that covers the side wall of the source trench 92 is drawn toward the adjacent gate trench 78. The portion of each contact region 98 that covers the side wall of the source trench 92 may extend to an intermediate region between the gate trench 78 and the source trench 92. Each contact region 98 is electrically connected to the body region 74 and the source region 97.

[0224] The SiC semiconductor device 61 includes a deep well region 99 formed in the surface layer portion of the first main surface 63 in the active region 72. A plurality of deep well regions 99 are formed in a one-to-one correspondence with a plurality of source trenches 92. Each deep well region 99 is formed in a strip shape extending along the corresponding source trench 92 in a plan view.

[0225] Each deep well region 99 is formed in the high concentration region 70. Each deep well region 99 covers each source trench 92 with each contact region 98 interposed therebetween. Each deep well region 99 covers the side wall and the bottom wall of the source trench 92 with the corresponding contact region 98 interposed therebetween. Each deep well region 99 is continuous with the body region 74 in the surface layer portion of the first main surface 3.

[0226] Each deep well region 99 has a bottom portion located on the second main surface 64 side with respect to the bottom wall of the gate trench 78. The bottom portion of each deep well region 99 may be formed parallel to the bottom wall of each source trench 92. The plurality of deep well regions 99 are preferably formed at a constant depth.

[0227] The peak value of the p-type impurity concentration of each deep well region 99 may be less than the peak value of the p-type impurity concentration of the contact region 98. The peak value of the p-type impurity concentration of each deep well region 99 may be equal to the peak value of the p-type impurity concentration of the body region 74. The peak value of the p-type impurity concentration of each deep well region 99 may exceed the peak value of the p-type impurity concentration of the body region 74, or may be less than the peak value of the p-type impurity concentration of the body region 74.

[0228] The peak value of the p-type impurity concentration of each deep well region 99 is 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The peak value of the p-type impurity concentration of each deep well region 99 is 1.0×10 18cm -3 It is preferably as described above.

[0229] Each deep well region 99 forms a pn junction with the high concentration region 70. From this pn junction, a depletion layer spreads toward the gate trench 78. The depletion layer may overlap the bottom wall of the gate trench 78.

[0230] The SiC semiconductor device 61 includes a p-type peripheral well region 100 formed in the surface layer portion of the first main surface 63 at the peripheral portion of the active region 72. The peripheral well region 100 covers the contact portion 77 of the trench gate structure 75 and exposes the active portion 76.

[0231] The peripheral well region 100 covers the side wall and the bottom wall of the gate trench 78 at the corresponding contact portion 77. The bottom of the peripheral well region 100 is located on the first main surface 63 side with respect to the bottom wall of the deep well region 99. Each peripheral well region 100 is electrically connected to the body region 74 and the deep well region 99 in the surface layer portion of the first main surface 63.

[0232] The p-type impurity concentration of the peripheral well region 100 may be substantially equal to the p-type impurity concentration of the deep well region 99. The peak value of the p-type impurity concentration of the peripheral well region 100 is 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The peak value of the p-type impurity concentration of the peripheral well region 100 is preferably 1.0×10 18 cm -3 or more.

[0233] In a SiC semiconductor device including only a pn junction diode, due to the structure without a trench, the problem of electric field concentration in the SiC chip 62 is small. Each deep well region 99 makes the trench gate type MISFET approach the structure of the pn junction diode.

[0234] As a result, in the trench gate type MISFET, the electric field within the SiC chip 62 can be relaxed. Therefore, narrowing the pitch between a plurality of adjacent deep well regions 99 is effective in alleviating electric field concentration.

[0235] Also, according to the deep well region 99 having a bottom portion on the second main surface 64 side with respect to the bottom wall of the gate trench 78, the depletion layer can appropriately relax the electric field concentration with respect to the gate trench 78. The plurality of deep well regions 99 are preferably formed at a constant depth. Thereby, it is possible to suppress the breakdown voltage (e.g., breakdown withstand voltage) of the SiC chip 62 from being limited by each deep well region 99, and thus it is possible to appropriately improve the breakdown voltage. The peripheral well region 100 also has the same effect as the deep well region 99.

[0236] By using the source trench 92, the deep well region 99 can be appropriately formed in a relatively deep region of the SiC chip 62. Further, since the deep well region 99 can be formed along the source trench 92, it is possible to appropriately suppress variations in the depth of the plurality of deep well regions 99.

[0237] Also, a part of the high concentration region 70 is interposed in the region between a plurality of adjacent deep well regions 99. Thereby, the JFET (Junction Field Effect Transistor) resistance can be reduced in the region between a plurality of adjacent deep well regions 99.

[0238] Also, in this form, the bottom of each deep well region 99 is located in the high concentration region 70. Thereby, a current path can be formed in the lateral direction parallel to the first main surface 63 in the region directly below each deep well region 99 in the high concentration region 70. As a result, the current spreading resistance can be reduced. The low concentration region 71 increases the breakdown voltage of the SiC chip 62 in such a structure.

[0239] The SiC semiconductor device 61 includes a plurality of source sub-trenches 101 formed on the first main surface 63 so as to surround the upper end portions of the source electrodes 94 in the active region 72. The plurality of source sub-trenches 101 are formed in a one-to-one correspondence with the plurality of source electrodes 94. The source sub-trench 101 communicates with the corresponding source trench 92 and forms a part of the side wall of the corresponding source trench 92.

[0240] In this form, the source sub-trench 101 is formed in an annular (more specifically, endless) shape that surrounds the upper end portion of the source electrode 94 in a plan view. The source sub-trench 101 is formed by digging down a part of the source insulating layer 93. More specifically, the source sub-trench 101 is formed by digging down from the first main surface 63 to the upper end portion of the source insulating layer 93 and the upper end portion of the source electrode 94.

[0241] The source sub-trench 101 is formed in a tapered shape in which the bottom area is smaller than the opening area in a cross-sectional view. The bottom wall of the source sub-trench 101 may be formed in a curved shape toward the second main surface 64. The source sub-trench 101 exposes the source region 97, the contact region 98, the source insulating layer 93, the source electrode 94, and the contact region 98.

[0242] The upper end portion of the source electrode 94 has a shape that is constricted inward with respect to the lower end portion of the source electrode 94. The lower end portion of the source electrode 94 is the portion of the source electrode 94 that is located on the bottom wall side of each source trench 92. The width of the upper end portion of the source electrode 94 along the second direction Y may be less than the width of the lower end portion of the source electrode 94 along the second direction Y.

[0243] The opening edge portion of each source trench 92 includes an inclined portion that slopes downward from the first main surface 63 toward the inside of each source trench 92. The opening edge portion of each source trench 92 is the portion that connects the first main surface 63 and the side wall of each source trench 92. The inclined portion of each source trench 92 is formed by the source sub-trench 101.

[0244] In this form, the inclined portion of each source trench 92 is formed in a curved shape that is recessed inwardly toward the SiC chip 62. The inclined portion of each source trench 92 may be formed in a curved shape toward the source sub-trench 101. The inclined portion of each source trench 92 alleviates the electric field concentration with respect to the opening edge portion of each source trench 92.

[0245] Referring to FIG. 13, the active region 72 has an active main surface 111 that forms a part of the first main surface 63. The outer region 73 has an outer main surface 112 that forms a part of the first main surface 63. The outer main surface 112 is connected to the side surfaces 65A to 65D.

[0246] The active main surface 111 and the outer main surface 112 face the c-plane of the SiC single crystal, respectively. The active main surface 111 and the outer main surface 112 each have an off-angle inclined in the [11-20] direction with respect to the (0001) plane of the SiC single crystal.

[0247] The outer region 73 is formed by digging down the first main surface 63 toward the second main surface 64 side. Therefore, the outer main surface 112 is formed in a region that is recessed toward the second main surface 64 side with respect to the active main surface 111. The outer main surface 112 is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78.

[0248] In this form, the outer main surface 112 is formed at a depth position substantially equal to the bottom wall of each source trench 92. The outer main surface 112 is located on substantially the same plane as the bottom wall of each source trench 92. The outer main surface 112 may be located on the second main surface 64 side in the range of 0 μm or more and 1 μm or less with respect to the bottom wall of each source trench 92. The outer main surface 112 exposes the high-concentration region 70.

[0249] In this form, the active region 72 is partitioned into a mesa shape by the outer region 73. The active region 72 is formed as a mesa-shaped active mesa 113 that protrudes upward from the outer main surface 112.

[0250] The active mesa 113 includes an active sidewall 114 that connects the active main surface 111 and the outer main surface 112. The active sidewall 114 demarcates a boundary region between the active region 72 and the outer region 73. The first main surface 63 is formed by the active main surface 111, the outer main surface 112, and the active sidewall 114.

[0251] In this form, the active sidewall 114 extends along the normal direction Z of the active main surface 111 (outer main surface 112). The active sidewall 114 is formed by the m-plane and a-plane of the SiC single crystal. The active sidewall 114 may have an inclined surface that slopes downward from the active main surface 111 toward the outer main surface 112. The active sidewall 114 exposes the high-concentration region 70. The active sidewall 114 may expose the body region 74.

[0252] The SiC semiconductor device 61 includes a p + -type diode region 121 formed in the surface layer portion of the outer main surface 112. The diode region 121 is formed in the high-concentration region 70. The diode region 121 is formed in the region between the active sidewall 114 and the side surfaces 65A to 65D in the outer region 73.

[0253] The diode region 121 is formed at a distance from the active sidewall 114 and the side surfaces 65A to 65D. The diode region 121 extends in a strip shape along the active region 72 in plan view. In this form, the diode region 121 is formed in an annular shape (more specifically, endless) surrounding the active region 72 in plan view.

[0254] The diode region 121 is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78. The bottom of the diode region 121 is located on the second main surface 64 side with respect to the bottom wall of each source trench 92. The bottom of the diode region 121 may be formed at a depth position substantially equal to the bottom of the contact region 98.

[0255] The bottom of the diode region 121 may be located substantially on the same plane as the bottom of the contact region 98. The bottom of the diode region 121 may be located on the second main surface 64 side with respect to the bottom of the contact region 98. The bottom of the diode region 121 may be located on the second main surface 64 side within a range of 0 μm or more and 1 μm or less with respect to the bottom of the contact region 98.

[0256] The diode region 121 forms a pn junction with the high-concentration region 70. Thereby, a pn junction diode is formed with the diode region 121 as the anode and the high-concentration region 70 as the cathode. The peak value of the p-type impurity concentration in the diode region 121 is 1.0×10 17 cm -3 or more and 1.0×10 21 cm -3 or less.

[0257] The SiC semiconductor device 61 includes a p-type outer well region 122 formed in the surface layer portion of the outer main surface 112. The peak value of the p-type impurity concentration in the outer well region 122 is 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The peak value of the p-type impurity concentration in the outer well region 122 may be less than the peak value of the p-type impurity concentration in the diode region 121. The peak value of the p-type impurity concentration in the outer well region 122 may be approximately equal to the peak value of the p-type impurity concentration in the deep well region 99.

[0258] The outer well region 122 is formed in the region between the active sidewall 114 and the diode region 121 in a plan view. The outer well region 122 extends in a strip shape along the active region 72 in a plan view. In this form, the outer well region 122 is formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view.

[0259] The outer well region 122 is formed in the high-concentration region 70. The outer well region 122 is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78. The bottom of the outer well region 122 is located on the second main surface 64 side with respect to the bottom wall of each source trench 92. The bottom of the outer well region 122 is located on the second main surface 64 side with respect to the bottom of the diode region 121. The bottom of the outer well region 122 may be formed at a depth position substantially equal to the bottom of the deep well region 99.

[0260] The inner peripheral edge of the outer well region 122 covers the corner connecting the active sidewall 114 and the outer main surface 112. The inner peripheral edge of the outer well region 122 further extends along the active sidewall 114 and is connected to the body region 74. The inner peripheral edge of the outer well region 122 may be formed at a distance from the active sidewall 114 toward the diode region 121 side.

[0261] The outer peripheral edge of the outer well region 122 covers the diode region 121 from the second main surface 64 side. The outer well region 122 is electrically connected to the diode region 121. The outer well region 122 may form a part of a pn junction diode. The outer peripheral edge of the outer well region 122 may be formed at a distance from the diode region 121 toward the active sidewall 114 side.

[0262] The SiC semiconductor device 61 includes an FL structure 123 (field limit structure) formed in the surface layer portion of the outer main surface 112. The FL structure 123 is formed in the region between the diode region 121 and the side surfaces 65A to 65D in a plan view. In this form, the FL structure 123 is formed at a distance from the side surfaces 65A to 65D toward the diode region 121 side. The FL structure 123 is formed in the high-concentration region 70.

[0263] The FL structure 123 includes one or more (for example, two or more and twenty or less) FL regions 124 (field limit regions). In this form, the FL structure 123 includes a group of FL regions having five FL regions 124A, 124B, 124C, 124D, and 124E. The FL regions 124A to 124E are formed in this order at intervals along the direction away from the diode region 121.

[0264] The FL regions 124A to 124E each extend in a strip shape along the periphery of the active region 72 in a plan view. More specifically, the FL regions 124A to 124E are each formed in an annular shape (more specifically, an endless shape) surrounding the active region 72 in a plan view. The FL regions 124A to 124E are each also referred to as an FLR region (field limiting ring region).

[0265] The bottoms of the FL regions 124A to 124E are located on the second main surface 64 side with respect to the bottom of the diode region 121. The innermost FL region 124A among the FL regions 124A to 124E covers the diode region 121 from the second main surface 64 side. Thereby, the FL region 124A is electrically connected to the diode region 121. The FL region 124A may form a part of a pn junction diode.

[0266] The entirety of the FL regions 124A to 124E is located on the second main surface 64 side with respect to the bottom wall of the gate trench 78. The bottoms of the FL regions 124A to 124E are located on the second main surface 64 side with respect to the bottom wall of the source trench 92.

[0267] The FL structure 123 alleviates electric field concentration in the outer region 73. The number, width, depth, p-type impurity concentration, etc. of the FL regions 124 can take various values according to the electric field to be alleviated. The FL structure 123 may include one or more FL regions 124 formed in the region between the active sidewall 114 and the diode region 121 in a plan view.

[0268] The SiC semiconductor device 61 includes an outer insulating layer 131 that covers the outer main surface 112. The outer insulating layer 131 is formed in a film shape along the active sidewall 114 and the outer main surface 112. The outer insulating layer 131 is continuous with the gate insulating layer 79 (third region 83) on the active main surface 111. The outer insulating layer 131 covers the diode region 121, the outer well region 122, and the FL structure 123 in the outer region 73.

[0269] The outer insulating layer 131 may contain silicon oxide. The outer insulating layer 131 may contain other insulating films such as silicon nitride. In this form, the outer insulating layer 131 is formed of the same type of insulating material as the gate insulating layer 79.

[0270] The periphery of the outer insulating layer 131 is exposed from the side surfaces 65A to 65D. In this form, the periphery of the outer insulating layer 131 is continuous with the side surfaces 65A to 65D. The periphery of the outer insulating layer 131 may be formed at an inward interval from the side surfaces 65A to 65D. In this case, the outer insulating layer 131 exposes the outer main surface 112.

[0271] The SiC semiconductor device 61 further includes a sidewall structure 132 that covers the active sidewall 114. The sidewall structure 132 protects and reinforces the active mesa 113 from the outer region 73 side. Also, the sidewall structure 132 forms a step relaxation structure that relaxes the step formed between the active main surface 111 and the outer main surface 112.

[0272] When an upper layer structure (coating layer) that covers the boundary region between the active region 72 and the outer region 73 is formed, the upper layer structure covers the sidewall structure 132. The sidewall structure 132 enhances the flatness of the upper layer structure. The sidewall structure 132 may have an inclined surface that slopes downward from the active main surface 111 toward the outer main surface 112. The step can be appropriately relaxed by the inclined surface of the sidewall structure 132.

[0273] The inclined surface of the sidewall structure 132 may be formed in a curved shape that is recessed toward the SiC chip 62 side. The inclined surface of the sidewall structure 132 may be formed in a curved shape that faces away from the SiC chip 62 side. The inclined surface of the sidewall structure 132 may extend planar from the active main surface 111 side toward the outer main surface 112 side.

[0274] The sidewall structure 132 is formed along the active sidewall 114. In this form, the sidewall structure 132 is formed in an annular (more specifically endless) shape that surrounds the active region 72 in plan view. The sidewall structure 132 preferably contains polysilicon. In this case, the sidewall structure 132 can be formed simultaneously with the gate electrode 80 and the source electrode 94.

[0275] The SiC semiconductor device 61 includes an interlayer insulating layer 140 formed on the first main surface 63. The interlayer insulating layer 140 covers the active region 72 and the outer region 73. The interlayer insulating layer 140 is formed in a film shape along the active main surface 111 and the outer main surface 112.

[0276] The interlayer insulating layer 140 is formed along the sidewall structure 132 in the boundary region between the active region 72 and the outer region 73. The interlayer insulating layer 140 forms a part of the upper layer structure that covers the sidewall structure 132.

[0277] The periphery of the interlayer insulating layer 140 is exposed from the side surfaces 65A to 65D. The periphery of the interlayer insulating layer 140 is continuous with the side surfaces 65A to 65D. The periphery of the interlayer insulating layer 140 may be formed at an interval inward from the side surfaces 65A to 65D. In this case, the interlayer insulating layer 140 exposes the outer main surface 112 (outer insulating layer 131).

[0278] The interlayer insulating layer 140 may contain silicon oxide or silicon nitride. The interlayer insulating layer 140 may contain USG (Undoped Silicate Glass), PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

[0279] The interlayer insulating layer 140 includes a gate contact hole 141, a source contact hole 142, and a diode contact hole 143. The gate contact hole 141 exposes the gate wiring 85 in the active region 72. The gate contact hole 141 may be formed in a strip shape along the gate wiring 85. The opening edge portion of the gate contact hole 141 is formed in a curved shape toward the inside of the gate contact hole 141.

[0280] The source contact hole 142 exposes the source region 97, the contact region 98, and the trench source structure 91 in the active region 72. The source contact hole 142 may be formed in a strip shape extending along the trench source structure 91. The opening edge portion of the source contact hole 142 is formed in a curved shape toward the inside of the source contact hole 142.

[0281] The diode contact hole 143 exposes the diode region 121 in the outer region 73. The diode contact hole 143 may be formed in a strip shape (more specifically, an endless shape) extending along the diode region 121. The diode contact hole 143 may expose the outer well region 122 and / or the FL structure 123. The opening edge portion of the diode contact hole 143 is formed in a curved shape toward the inside of the diode contact hole 143.

[0282] The SiC semiconductor device 61 includes a first main surface electrode 150 formed on the first main surface 63. More specifically, the first main surface electrode 150 is formed on the interlayer insulating layer 140. The first main surface electrode 150 includes a gate main surface electrode 151 and a source main surface electrode 152 that are electrically insulated from each other.

[0283] A gate voltage is applied to the gate main surface electrode 151. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source main surface electrode 152. The source voltage may be a reference voltage (for example, GND voltage).

[0284] The gate main surface electrode 151 is formed in the active region 72. The gate main surface electrode 151 includes a gate pad 153 and gate fingers 154. The gate pad 153 is formed in a region on the first side surface 65A side in a plan view. More specifically, the gate pad 153 is formed along a region along the center of the first side surface 65A in a plan view. The gate pad 153 may be formed in a region along a corner connecting any two of the side surfaces 65A to 65D in a plan view. The gate pad 153 may be formed in a rectangular shape in a plan view.

[0285] The gate fingers 154 are drawn out from the gate pad 153 and extend in a strip shape along the periphery of the active region 72. In this form, the gate fingers 154 are formed along the first side surface 65A, the third side surface 65C, and the fourth side surface 65D so as to partition the inside of the active region 72 from three directions.

[0286] The gate fingers 154 have a pair of open ends 155 and 156. The pair of open ends 155 and 156 are formed in a region facing the gate pad 153 with the inside of the active region 72 interposed therebetween. In this form, the pair of open ends 155 and 156 are formed in a region along the second side surface 65B in a plan view.

[0287] The gate finger 154 enters the gate contact hole 141 from above the interlayer insulating layer 140. The gate finger 154 is electrically connected to the gate wiring 85 within the gate contact hole 141. Thus, the electrical signal from the gate pad 153 is transmitted to the gate electrode 80 and the gate wiring 85 via the gate finger 154.

[0288] The source main surface electrode 152 is formed in the active region 72 and the outer region 73. The source main surface electrode 152 includes a source pad 157, a source wiring 158, and a source connection portion 159. The source pad 157 is formed in the active region 72 at a distance from the gate main surface electrode 151. The source pad 157 is formed in a C shape in plan view so as to cover a C-shaped region partitioned by the gate main surface electrode 151.

[0289] The source pad 157 enters the source contact hole 142 and the source sub-trench 101 from above the interlayer insulating layer 140. The source pad 157 is electrically connected to the source region 97, the contact region 98, and the source electrode 94 within the source contact hole 142 and the source sub-trench 101.

[0290] The aforementioned source electrode 94 may be formed using a partial region of the source pad 157. The source electrode 94 may be formed by a portion that enters each source trench 92 in the source pad 157.

[0291] The source wiring 158 is formed in the outer region 73. The source wiring 158 extends in a strip shape along the active region 72. The source wiring 158 is formed in an annular shape (more specifically, endless) that surrounds the active region 72 in plan view.

[0292] The source wiring 158 enters the diode contact hole 143 from above the interlayer insulating layer 140. The source wiring 158 is electrically connected to the diode region 121 within the diode contact hole 143.

[0293] The source connection portion 159 connects the source pad 157 and the source wiring 158. The source connection portion 159 crosses the open ends 155 and 156 of the gate fingers 154 from the source pad 157 and is connected to the source wiring 158. The source connection portion 159 is drawn out from the active region 72 across the sidewall structure 132 to the outer region 73. The source connection portion 159 forms a part of the upper layer structure covering the sidewall structure 132.

[0294] The MISFET formed in the active region 72 includes an npn-type parasitic transistor in terms of its structure. When the avalanche current generated in the outer region 73 flows into the active region 72, the parasitic transistor is turned on. In this case, the operation of the MISFET becomes unstable due to latch-up. Therefore, in the SiC semiconductor device 61, an avalanche current absorption structure is formed by utilizing the structure of the source main surface electrode 152.

[0295] The avalanche current generated in the outer region 73 is absorbed by the source wiring 158 via the diode region 121. The avalanche current absorbed by the source wiring 158 reaches the source pad 157 via the source connection portion 159. When a conducting wire is electrically connected to the source pad 157, the avalanche current reaches the outside via the conducting wire.

[0296] Thereby, the driving of the parasitic transistor due to the avalanche current can be suppressed. Therefore, latch-up can be suppressed, and the stability of the MISFET can be enhanced.

[0297] Referring to FIGS. 14 and 15, the first main surface electrode 150 (gate main surface electrode 151 and source main surface electrode 152) has a laminated structure including a barrier layer 160 and a first Al layer 161 laminated in this order from the SiC chip 62 side. The first Al layer 161 is formed as a first buffer layer that relaxes the external force applied to the SiC chip 62 from the first main surface 63 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus).

[0298] The barrier layer 160 may have a single-layer structure including a Ti layer or a TiN layer. The barrier layer 160 may have a laminated structure including a Ti layer and a TiN layer laminated in this order from the SiC chip 62 side. The thickness of the barrier layer 160 may be 0.01 μm or more and 6 μm or less. The thickness of the barrier layer 160 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, or 4 μm or more and 6 μm or less.

[0299] The first Al layer 161 has a resistance value smaller than that of the barrier layer 160. The first Al layer 161 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The first Al layer 161 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in an arbitrary order.

[0300] The first Al layer 161 may have a single-layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. It is preferable that the first Al layer 161 has a single-layer structure composed of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0301] The thickness of the first Al layer 161 exceeds the thickness of the barrier layer 160. The thickness of the first Al layer 161 may be 0.05 μm or more and 10 μm or less. The thickness of the first Al layer 161 may be 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the first Al layer 161 is preferably 1 μm or more and 8 μm or less.

[0302] The SiC semiconductor device 61 includes an insulating layer 170 formed on the interlayer insulating layer 140. In FIG. 9, the insulating layer 170 is shown by hatching. The periphery of the insulating layer 170 is formed at an interval inward from the side surfaces 65A to 65D. Thereby, the insulating layer 170 exposes the periphery of the SiC chip 62 (more specifically, the interlayer insulating layer 140) in plan view.

[0303] The periphery of the insulating layer 170 partitions the dicing street DS between the side surfaces 65A to 65D. According to the dicing street DS, it is not necessary to physically cut the insulating layer 170 when cutting out the SiC semiconductor device 61 from the SiC wafer. Thereby, the SiC semiconductor device 61 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the insulating layer 170 can be suppressed. As a result, the insulating layer 170 can appropriately protect objects to be protected such as the SiC chip 102 and the first main surface electrode 150.

[0304] The width of the dicing street DS may be 1 μm or more and 25 μm or less. The width of the dicing street DS is the width in a direction orthogonal to the direction in which the dicing street DS extends. The width of the dicing street DS may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0305] The insulating layer 170 selectively covers the gate main surface electrode 151 and the source main surface electrode 152. The insulating layer 170 includes a pad opening 171. The pad opening 171 more specifically includes a gate pad opening 172 and a source pad opening 173. The gate pad opening 172 exposes the gate pad 153. The source pad opening 173 exposes the source pad 157. The planar shape of the gate pad opening 172 is arbitrary. The planar shape of the source pad opening 173 is arbitrary.

[0306] In this form, the insulating layer 170 has a laminated structure including a passivation layer 174 and a resin layer 175 laminated in this order from the SiC chip 62 side.

[0307] The passivation layer 174 may include at least one of a silicon oxide layer and a silicon nitride layer. The passivation layer 174 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The passivation layer 174 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. The passivation layer 174 preferably includes an insulating material different from the interlayer insulating layer 140. In this form, the passivation layer 174 has a single-layer structure composed of a silicon nitride layer.

[0308] The passivation layer 174 is formed in a film shape along the interlayer insulating layer 140. The passivation layer 174 covers the active region 72 and the outer region 73 with the interlayer insulating layer 140 interposed therebetween. The passivation layer 174 is drawn from the active region 72 across the sidewall structure 132 to the outer region 73. The passivation layer 174 forms a part of the upper layer structure covering the sidewall structure 132.

[0309] The passivation layer 174 has a first gate opening 176 and a first source opening 177. The first gate opening 176 exposes the gate pad 153. The first source opening 177 exposes the source pad 157. The planar shape of the first gate opening 176 is arbitrary. The planar shape of the first source opening 177 is arbitrary.

[0310] The thickness of the passivation layer 174 may be 0.1 μm or more and 20 μm or less. The thickness of the passivation layer 174 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0311] The resin layer 175 is formed in a film shape along the main surface of the passivation layer 174. The resin layer 175 extends from the active region 72 across the sidewall structure 132 to the outer region 73. The resin layer 175 forms a part of the upper layer structure covering the sidewall structure 132.

[0312] The resin layer 175 may contain a photosensitive resin. The photosensitive resin may be of a negative type or a positive type. The resin layer 175 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the resin layer 175 contains polybenzoxazole.

[0313] The periphery of the resin layer 175 exposes the periphery of the passivation layer 174 in this form. The periphery of the insulating layer 170 is formed by the periphery of the resin layer 175 and the periphery of the passivation layer 174. The resin layer 175 may cover the periphery of the passivation layer 174.

[0314] The resin layer 175 has a second gate opening 178 and a second source opening 179. The second gate opening 178 communicates with the first gate opening 176 of the passivation layer 174 and forms a gate pad opening 172 with the first gate opening 176. The second source opening 179 communicates with the first source opening 177 of the passivation layer 174 and forms a source pad opening 173 with the first source opening 177.

[0315] The inner wall of the second gate opening 178 may be flush with the inner wall of the first gate opening 176. The inner wall of the second gate opening 178 may be located outside the first gate opening 176 in a plan view. The inner wall of the second gate opening 178 may be located inside the first gate opening 176 in a plan view. That is, the resin layer 175 may cover the inner wall of the first gate opening 176.

[0316] The inner wall of the second source opening 179 may be flush with the inner wall of the first source opening 177. The inner wall of the second source opening 179 may be located outside the first source opening 177 in a plan view. The inner wall of the second source opening 179 may be located inside the first source opening 177 in a plan view. That is, the resin layer 175 may cover the inner wall of the first source opening 177.

[0317] The thickness of the resin layer 175 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 175 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0318] The SiC semiconductor device 61 includes an uneven structure 180 formed on the outer main surface 112. More specifically, the uneven structure 180 includes unevenness formed using the interlayer insulating layer 140 covering the outer main surface 112. Even more specifically, the uneven structure 180 includes anchor holes 181 formed in the interlayer insulating layer 140.

[0319] The anchor hole 181 is formed by digging down a portion that covers the outer region 73 in the interlayer insulating layer 140. The anchor hole 181 may be formed in a region between the diode region 121 and the side surfaces 65A to 65D in a plan view. In this form, the anchor hole 181 is formed in a region between the FL structure 123 and the side surfaces 65A to 65D in a plan view.

[0320] The anchor hole 181 may be partitioned by the interlayer insulating layer 140. In this form, the outer main surface 112 is exposed. The anchor hole 181 may be dug down with the outer main surface 112 facing the second main surface 64. The opening edge portion of the anchor hole 181 is formed in a curved shape toward the inside of the anchor hole 181.

[0321] The anchor hole 181 extends in a strip shape along the active region 72 in a plan view. In this form, the anchor hole 181 is formed in an annular shape (more specifically, endless shape) surrounding the active region 72 in a plan view. The number of the anchor holes 181 is arbitrary. One anchor hole 181 may be formed in the interlayer insulating layer 140, or a plurality of anchor holes 181 may be formed in the interlayer insulating layer 140.

[0322] The resin layer 175 has an anchor portion 182 that meshes with the anchor hole 181. In this form, the resin layer 175 meshes with the anchor hole 181 via the passivation layer 174. More specifically, the passivation layer 174 enters the anchor hole 181 from above the interlayer insulating layer 140. The passivation layer 174 is in contact with the outer main surface 112 inside the anchor hole 181. A recess 183 that is recessed toward the anchor hole 181 is formed in a portion that covers the anchor hole 181 on the main surface of the passivation layer 174.

[0323] A part of the resin layer 175 forms an anchor portion 182 within the recess 183 of the passivation layer 174. Thereby, since the connection strength of the resin layer 175 to the first main surface 63 can be increased, peeling of the resin layer 175 can be appropriately suppressed.

[0324] Referring to FIGS. 14 and 15, the SiC semiconductor device 61 includes a pad electrode 190 formed on the first main surface electrode 150. More specifically, the pad electrode 190 includes a gate pad electrode 191 and a source pad electrode 192.

[0325] The gate pad electrode 191 is formed on the gate main surface electrode 151 and is electrically connected to the gate main surface electrode 151. More specifically, the gate pad electrode 191 is formed on the gate pad 153 within the gate pad opening 172. The gate pad electrode 191 has a gate terminal surface 193 that is externally connected to a conducting wire.

[0326] The gate terminal surface 193 is located on the gate pad 153 side with respect to the main surface of the insulating layer 170 (resin layer 175). The gate terminal surface 193 may protrude above the main surface of the insulating layer 170 (resin layer 175). The gate terminal surface 193 may have an overlapping portion that covers the main surface of the insulating layer 170 (resin layer 175).

[0327] The source pad electrode 192 is formed on the source main surface electrode 152 and is electrically connected to the source main surface electrode 152. More specifically, the source pad electrode 192 is formed on the source pad 157 within the source pad opening 173. The source pad electrode 192 has a source terminal surface 194 that is externally connected to a conducting wire.

[0328] The source terminal surface 194 is located on the source pad 157 side with respect to the main surface of the insulating layer 170 (resin layer 175). The source terminal surface 194 may protrude above the main surface of the insulating layer 170 (resin layer 175). The source terminal surface 194 may have an overlapping portion that covers the main surface of the insulating layer 170 (resin layer 175).

[0329] The pad electrodes 190 (gate pad electrode 191 and source pad electrode 192) contain a metal material different from that of the first main surface electrode 150. In this form, the pad electrode 190 has a laminated structure including an Ni layer 195, a Pd layer 196, and an Au layer 197 laminated in this order from the side of the first main surface electrode 150. Ni, Pd, and Au each have a Young's modulus (rigidity modulus) exceeding that of Al. The Ni layer 195, Pd layer 196, and Au layer 197 may be plating layers formed by a plating method.

[0330] The pad electrode 190 only needs to contain at least one of the Ni layer 195, Pd layer 196, and Au layer 197. The pad electrode 190 may have a laminated structure in which at least two of the Ni layer 195, Pd layer 196, and Au layer 197 are laminated in an arbitrary order. The pad electrode 190 may have a single-layer structure composed of the Ni layer 195, Pd layer 196, or Au layer 197.

[0331] The gate pad electrode 191 preferably has a gate terminal surface 193 formed by the Au layer 197. The source pad electrode 192 preferably has a source terminal surface 194 formed by the Au layer 197. The pad electrode 190 preferably has a laminated structure including at least the Ni layer 195 and the Au layer 197 laminated in this order from the side of the first main surface electrode 150.

[0332] The thickness of the Ni layer 195 may be 0.1 μm or more and 10 μm or less. The thickness of the Ni layer 195 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0333] The thickness of the Pd layer 196 may be 0.1 μm or more and 10 μm or less. The thickness of the Pd layer 196 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0334] The thickness of the Au layer 197 may be 0.01 μm or more and 3 μm or less. The thickness of the Au layer 197 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less. The thickness of the Au layer 197 is preferably less than the thickness of the Ni layer 195. The thickness of the Au layer 197 is preferably less than the thickness of the Pd layer 196.

[0335] The SiC semiconductor device 61 includes a second main surface electrode 200 formed on the second main surface 64. The second main surface electrode 200 is formed as a drain electrode of the MISFET. In this form, the second main surface electrode 200 covers the entire area of the second main surface 64.

[0336] The second main surface electrode 200 may be formed at a distance inward from the side surfaces 65A to 65D, exposing the peripheral portion of the second main surface 64. In this case, when cutting out the SiC semiconductor device 61 from the SiC wafer, it is not necessary to physically cut the second main surface electrode 200. As a result, the SiC semiconductor device 61 can be smoothly cut out from the SiC wafer, and at the same time, peeling and deterioration of the second main surface electrode 200 can be suppressed. As a result, the second main surface electrode 200 can be appropriately connected to the second main surface 64.

[0337] Such a second main surface electrode 200 can be obtained, for example, by removing unnecessary portions of the second main surface electrode 200 by an etching method through a resist mask during the manufacturing process. Also, as another example, the second main surface electrode 200 can be obtained by forming a second main surface electrode 200 that partially covers the second main surface 64 by a lift-off method using a resist mask during the manufacturing process.

[0338] The second main surface electrode 200 includes a second Al layer 201 that covers the second main surface 64. The second Al layer 201 faces the first Al layer 161 of the gate main surface electrode 151 and the first Al layer 161 of the source main surface electrode 152 with the SiC chip 62 interposed therebetween. The second Al layer 201 is formed as a second buffer layer that relaxes an external force applied to the SiC chip 62 from the second main surface 64 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus).

[0339] The second Al layer 201 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The second Al layer 201 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in an arbitrary order. The second Al layer 201 may be formed by a sputtering method and / or a vapor deposition method.

[0340] The second Al layer 201 may have a single-layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. The Al-based metal material of the second Al layer 201 may be different from the Al-based metal material of the first Al layer 161. It is preferable that the second Al layer 201 has a single-layer structure composed of a pure Al layer.

[0341] The second Al layer 201 may have a thickness less than that of the first Al layer 161. The thickness of the second Al layer 201 may be 0.01 μm or more and 5 μm or less. The thickness of the second Al layer 201 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less.

[0342] In addition to the second Al layer 201, the second main surface electrode 200 further includes one or more electrode layers made of a metal material different from that of the second Al layer 201. In this form, the second main surface electrode 200 includes, as an example of a plurality of electrode layers, a Ti layer 202, a Ni layer 203, a Pd layer 204, an Au layer 205, and an Ag layer 206 laminated in this order from the side of the second main surface 64.

[0343] The Ti layer 202 is an ohmic electrode that forms an ohmic contact with the second main surface 64. The second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206 interposed therebetween.

[0344] Ti, Ni, Pd, Au, and Ag each have a Young's modulus (rigidity modulus) exceeding that of Al. The Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206 may be formed by a sputtering method, a vapor deposition method, and / or a plating method.

[0345] The second main surface electrode 200 may include at least one of the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206 as one or more electrode layers. It is preferable that the second Al layer 201 covers the second main surface 64 with at least the Ti layer 202 interposed therebetween.

[0346] When the second main surface electrode 200 includes at least one of the Ni layer 203, the Pd layer 204, and the Au layer 205, at least one of the Ni layer 203, the Pd layer 204, and the Au layer 205 may be an electroplated layer formed simultaneously with the Ni layer 195, the Pd layer 196, and the Au layer 197 of the pad electrode 190.

[0347] The thickness of the Ti layer 202 may be 0.01 μm or more and 3 μm or less. The thickness of the Ti layer 202 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less.

[0348] The thickness of the Ni layer 203 may be 0.1 μm or more and 10 μm or less. The thickness of the Ni layer 203 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the Ni layer 203 preferably exceeds the thickness of the Ti layer 202.

[0349] The thickness of the Pd layer 204 may be 0.1 μm or more and 10 μm or less. The thickness of the Pd layer 204 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The thickness of the Pd layer 204 preferably exceeds the thickness of the Ti layer 202.

[0350] The thickness of the Au layer 205 may be 0.01 μm or more and 3 μm or less. The thickness of the Au layer 205 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less. The thickness of the Au layer 205 is preferably less than the thickness of the Ni layer 203. The thickness of the Au layer 205 is preferably less than the thickness of the Pd layer 204.

[0351] The thickness of the Ag layer 206 may be 0.01 μm or more and 3 μm or less. The thickness of the Ag layer 206 may be 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less. The thickness of the Ag layer 206 is preferably less than the thickness of the Ni layer 203. The thickness of the Ag layer 206 is preferably less than the thickness of the Pd layer 204.

[0352] The second main surface electrode 200 may have the structure shown in FIGS. 17A to 17I.

[0353] FIG. 17A is a cross-sectional view schematically showing the second main surface electrode 200 according to the second exemplary form. Hereinafter, for the structures corresponding to the structures described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0354] Referring to FIG. 17A, in this form, the second main surface electrode 200 has a laminated structure including a second Al layer 201, a Ti layer 202, a Ni layer 203, a Pd layer 204, and an Au layer 205. The Ti layer 202, the Ni layer 203, the Pd layer 204, and the Au layer 205 are laminated in this order from the second main surface 64 side. The second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, the Pd layer 204, and the Au layer 205 interposed therebetween.

[0355] FIG. 17B is a cross-sectional view schematically showing the second main surface electrode 200 according to the third exemplary form. Hereinafter, for the structures corresponding to the structures described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0356] Referring to FIG. 17B, in this embodiment, the second main surface electrode 200 has a laminated structure including a second Al layer 201, a Ti layer 202, a Ni layer 203, an Au layer 205, and an Ag layer 206. The Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 are laminated in this order from the second main surface 64 side. The second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 interposed therebetween.

[0357] FIG. 17C is a cross-sectional view schematically showing the second main surface electrode 200 according to the fourth exemplary embodiment. Hereinafter, for structures corresponding to the structures described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0358] Referring to FIG. 17C, in this embodiment, the second main surface electrode 200 has a laminated structure including a second Al layer 201, a Ti layer 202, a Ni layer 203, and an Au layer 205. The Ti layer 202, the Ni layer 203, and the Au layer 205 are laminated in this order from the second main surface 64 side. The second Al layer 201 covers the second main surface 64 with the Ti layer 202, the Ni layer 203, and the Au layer 205 interposed therebetween.

[0359] FIG. 17D is a cross-sectional view schematically showing the second main surface electrode 200 according to the fifth exemplary embodiment. Hereinafter, for structures corresponding to the structures described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0360] Referring to FIG. 17D, in this embodiment, the second main surface electrode 200 has a laminated structure including a second Al layer 201 and a Ti layer 202. The Ti layer 202 is connected to the second main surface 64. The second Al layer 201 covers the second main surface 64 with the Ti layer 202 interposed therebetween.

[0361] FIG. 17E is a cross-sectional view schematically showing the second main surface electrode 200 according to the sixth exemplary embodiment. Hereinafter, for structures corresponding to the structures described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0362] Referring to FIG. 17E, in this embodiment, the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203, and an Au layer 205. The Ti layer 202, the Ni layer 203, and the Au layer 205 are laminated in this order from the side of the second main surface 64. The second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203, and covers the second main surface 64 with the Ti layer 202 interposed therebetween.

[0363] In this case, the pad electrode 190 preferably has a two-layer structure composed of a Ni layer 195 and an Au layer 197 laminated in this order from the side of the first main surface electrode 150. The Ni layer 203 and the Au layer 205 of the second main surface electrode 200 can be formed simultaneously with the Ni layer 195 and the Au layer 197 of the pad electrode 190 by electroplating.

[0364] FIG. 17F is a cross-sectional view schematically showing the second main surface electrode 200 according to the seventh exemplary embodiment. Hereinafter, structures corresponding to the structures described in FIGS. 6 to 16 are denoted by the same reference numerals, and the description thereof is omitted.

[0365] Referring to FIG. 17F, in this embodiment, the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203, an Au layer 205, and an Ag layer 206. The Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 are laminated in this order from the side of the second main surface 64. The second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203, and covers the second main surface 64 with the Ti layer 202 interposed therebetween.

[0366] In this case, the pad electrode 190 preferably has a two-layer structure composed of a Ni layer 195 and an Au layer 197 laminated in this order from the side of the first main surface electrode 150. The Ni layer 203 and the Au layer 205 of the second main surface electrode 200 can be formed simultaneously with the Ni layer 195 and the Au layer 197 of the pad electrode 190 by electroplating.

[0367] FIG. 17G is a cross-sectional view schematically showing the second main surface electrode 200 according to the eighth exemplary form. Hereinafter, for structures corresponding to the structures described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0368] Referring to FIG. 17G, in this form, the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203, a Pd layer 204, an Au layer 205, and an Ag layer 206. The Ti layer 202, the Ni layer 203, the Au layer 205, and the Ag layer 206 are laminated in this order from the second main surface 64 side. The second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203 and covers the second main surface 64 with the Ti layer 202 interposed therebetween.

[0369] In this case, it is preferable that the pad electrode 190 has a three-layer structure composed of a Ni layer 195, a Pd layer 196, and an Au layer 197 laminated in this order from the first main surface electrode 150 side. The Ni layer 203, the Pd layer 204, and the Au layer 205 of the second main surface electrode 200 can be formed simultaneously with the Ni layer 195, the Pd layer 196, and the Au layer 197 of the pad electrode 190 by a plating method.

[0370] FIG. 17H is a cross-sectional view schematically showing the second main surface electrode 200 according to the ninth exemplary form. Hereinafter, for structures corresponding to the structures described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0371] Referring to FIG. 17H, in this form, the second main surface electrode 200 includes a second Al layer 201, a Ti layer 202, a Ni layer 203, a Pd layer 204, and an Au layer 205. The Ti layer 202, the Ni layer 203, the Pd layer 204, and the Au layer 205 are laminated in this order from the second main surface 64 side. The second Al layer 201 is interposed between the Ti layer 202 and the Ni layer 203 and covers the second main surface 64 with the Ti layer 202 interposed therebetween.

[0372] In this case, the pad electrode 190 preferably has a three-layer structure composed of an Ni layer 195, a Pd layer 196, and an Au layer 197 laminated in this order from the side of the first main surface electrode 150. The Ni layer 203, Pd layer 204, and Au layer 205 of the second main surface electrode 200 can be formed simultaneously with the Ni layer 195, Pd layer 196, and Au layer 197 of the pad electrode 190 by electroplating.

[0373] FIG. 17I is a cross-sectional view schematically showing the second main surface electrode 200 according to the tenth exemplary embodiment. Hereinafter, for structures corresponding to those described in FIGS. 6 to 16, the same reference numerals are given and the description thereof is omitted.

[0374] Referring to FIG. 17I, in this embodiment, the second main surface electrode 200 includes a second Al layer 201 and a silicide layer 207. The silicide layer 207 is formed on the second main surface 64. The silicide layer 207 is formed by siliciding SiC exposed from the second main surface 64 with a metal material. The silicide layer 207 may include at least one of an FeSi2 layer, a NiSi layer, a NiSi2 layer, a CoSi2 layer, a CrSi2 layer, a WSi2 layer, a MoSi2 layer, a MnSi2 layer, a NbSi2 layer, a TiSi2 layer, and a VSi2 layer.

[0375] The second Al layer 201 covers the second main surface 64 with the silicide layer 207 interposed therebetween. The second main surface electrode 200 may include at least one of a Ti layer 202, an Ni layer 203, a Pd layer 204, an Au layer 205, and an Ag layer 206 in addition to the second Al layer 201 and the silicide layer 207. The lamination order of the second Al layer 201, the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206 is arbitrary. As a structure covering the silicide layer 207, any one of the lamination structures of the first to tenth exemplary embodiments may be adopted.

[0376] FIG. 18 is a view showing a semiconductor package 211 in which the SiC semiconductor device 61 shown in FIG. 6 is incorporated. In FIG. 18, the internal structure of the semiconductor package 211 is shown through the package body 212.

[0377] Referring to FIG. 18, in this form, the semiconductor package 211 is a three-terminal TO-220. The semiconductor package 211 includes a package body 212, a metal plate 213, a first terminal 214, a second terminal 215, a third terminal 216, a SiC semiconductor device 61, a conductive bonding material 217, a first wire 218, and a second wire 219.

[0378] The package body 212 is made of a molding resin. The package body 212 may include an epoxy resin as an example of the molding resin. The package body 212 is formed in a rectangular parallelepiped shape. The package body 212 includes a first surface 221 on one side and a second surface 222 on the other side, and four side surfaces 223A, 223B, 223C, 223D connecting the first surface 221 and the second surface 222.

[0379] More specifically, the four side surfaces 223A to 223D include a first side surface 223A, a second side surface 223B, a third side surface 223C, and a fourth side surface 223D. The first side surface 223A and the second side surface 223B face each other. The third side surface 223C and the fourth side surface 223D face each other.

[0380] The metal plate 213 may include at least one of Fe, Au, Ag, Cu, and Al. The metal plate 213 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed. The planar shape of the metal plate 213 is arbitrary. In this form, the metal plate 213 is formed in a quadrangular shape (rectangular shape) in plan view.

[0381] More specifically, the metal plate 213 integrally includes a pad portion 224 located within the package body 212 and a heat sink portion 225 located outside the package body 212. The heat sink portion 225 is drawn out of the package body 212 across the second side surface 223B from the pad portion 224. The heat sink portion 225 includes a through hole 225a. The through hole 225a is formed in a circular shape. The planar area of the heat sink portion 225 may exceed the planar area of the pad portion 224.

[0382] In this form, the metal plate 213 is disposed within the package body 212 so as to be exposed from the second surface 222. The metal plate 213 may be disposed within the package body 212 so as not to be exposed from the second surface 222.

[0383] The first terminal 214 may include at least one of Fe, Au, Ag, Cu, and Al. The first terminal 214 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed. The first terminal 214 is drawn out of the package body 212 across the first side surface 223A from within the package body 212.

[0384] The first terminal 214 is disposed at the central portion of the first side surface 223A in a plan view. The first terminal 214 is disposed in a region on the first surface 221 side with respect to the plate surface of the metal plate 213.

[0385] The first terminal 214 includes a first inner end portion 226, a first outer end portion 227, and a first strip portion 228. The first inner end portion 226 is connected to the metal plate 213 within the package body 212. The first outer end portion 227 is disposed outside the package body 212. The first strip portion 228 extends between the first inner end portion 226 and the first outer end portion 227 in a direction orthogonal to the first side surface 223A.

[0386] The second terminal 215 may contain at least one of Fe, Au, Ag, Cu, and Al. The second terminal 215 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed. The second terminal 215 is drawn out of the package body 212 across the first side surface 223A from inside the package body 212.

[0387] In a plan view, the second terminal 215 is arranged in a region on the third side surface 223C side with a space from the first terminal 214. The second terminal 215 is arranged in a region on the first surface 221 side with respect to the plate surface of the metal plate 213.

[0388] The second terminal 215 includes a second inner end portion 229, a second outer end portion 230, and a second strip portion 231. The second inner end portion 229 is arranged inside the package body 212 at a space from the metal plate 213. The second outer end portion 230 is arranged outside the package body 212. The second strip portion 231 extends between the second inner end portion 229 and the second outer end portion 230 in a direction orthogonal to the first side surface 223A.

[0389] The third terminal 216 may contain at least one of Fe, Au, Ag, Cu, and Al. The third terminal 216 may have an outer surface on which at least one of a Ni plating film, an Au plating film, an Ag plating film, and a Cu plating film is formed. The third terminal 216 is drawn out of the package body 212 across the first side surface 223A from inside the package body 212.

[0390] In a plan view, the third terminal 216 is arranged in a region on the fourth side surface 223D side with a space from the first terminal 214. The third terminal 216 is arranged in a region on the first surface 221 side with respect to the plate surface of the metal plate 213.

[0391] The third terminal 216 includes a third inner end portion 232, a third outer end portion 233, and a third strip portion 234. The third inner end portion 232 is disposed in the package body 212 at a distance from the metal plate 213. The third outer end portion 233 is disposed outside the package body 212. The third strip portion 234 extends between the third inner end portion 232 and the third outer end portion 233 in a direction orthogonal to the first side surface 223A.

[0392] The SiC semiconductor device 61 is disposed on the pad portion 224 of the metal plate 213 within the package body 212. The conductive bonding material 217 is interposed between the SiC semiconductor device 61 and the pad portion 224, and joins the second main surface electrode 200 of the SiC semiconductor device 61 to the pad portion 224. Thereby, the SiC semiconductor device 61 is electrically connected to the first terminal 214 via the metal plate 213.

[0393] The conductive bonding material 217 may be a metal paste or solder. The metal paste may contain at least one of Au, Ag, and Cu. The conductive bonding material 217 preferably consists of solder. The solder may be lead-free solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi.

[0394] The first conducting wire 218 consists of a metal wire (bonding wire) or a metal clip. The metal wire may be an Al wire, an Au wire, a Cu wire, or a solder wire. The solder wire may be a lead-free solder wire. The solder wire may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi. The metal clip may be an Al clip, an Au clip, or a Cu clip. In this form, the first conducting wire 218 consists of a solder wire.

[0395] The first conductor 218 is connected to the second inner end portion 229 of the second terminal 215 and the gate pad electrode 191 of the SiC semiconductor device 61 within the package body 212. Thereby, the SiC semiconductor device 61 is electrically connected to the second terminal 215.

[0396] In FIG. 18, an example in which one first conductor 218 is connected to the second inner end portion 229 and the gate pad electrode 191 is shown, but the number of the first conductors 218 is arbitrary. Two or more first conductors 218 may be connected to the second inner end portion 229 and the gate pad electrode 191.

[0397] The second conductor 219 is made of a metal wire (bonding wire) or a metal clip. The metal wire may be an Al wire, an Au wire, a Cu wire, or a solder wire. The solder wire may be a lead-free solder wire. The solder wire may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi. The metal clip may be an Al clip, an Au clip, or a Cu clip. In this form, the second conductor 219 is made of a solder wire.

[0398] The second conductor 219 is connected to the third inner end portion 232 of the third terminal 216 and the source pad electrode 192 of the SiC semiconductor device 61 within the package body 212. Thereby, the SiC semiconductor device 61 is electrically connected to the third terminal 216.

[0399] In FIG. 18, an example in which two second conductors 219 are connected to the third inner end portion 232 and the source pad electrode 192 is shown, but the number of the second conductors 219 is arbitrary. One or three or more second conductors 219 may be connected to the third inner end portion 232 and the source pad electrode 192.

[0400] The semiconductor package 211 can also take forms other than TO-220. The semiconductor package 211 may have forms such as SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package), or various forms similar thereto.

[0401] As described above, according to the SiC semiconductor device 61, the first Al layer 161 is formed as a first buffer layer that relaxes external forces on the first main surface 63 side, and the second Al layer 201 is formed as a second buffer layer that relaxes external forces on the second main surface 64 side. Thereby, external forces in the direction from the first main surface 63 toward the second main surface 64 and external forces in the direction from the second main surface 64 toward the first main surface 63 can be relaxed.

[0402] As an example, when mounting the SiC semiconductor device 61 on the pad portion 224 of the metal plate 213, the external forces applied to the SiC chip 62 can be relaxed by the first Al layer 161 and the second Al layer 201. Also, when bonding the first lead wire 218 and the second lead wire 219 to the pad electrodes 190 of the SiC semiconductor device 61, the external forces applied to the SiC chip 62 can be relaxed by the first Al layer 161 and the second Al layer 201. As a result, cracks in the SiC chip 62 can be suppressed.

[0403] The SiC semiconductor device 61 also includes pad electrodes 190 (gate pad electrode 191 and source pad electrode 192) externally joined to the first lead wire 218 and the second lead wire 219. The pad electrode 190 includes at least one of a Ni layer 195, a Pd layer 196, and an Au layer 197. Thereby, the first lead wire 218 and the second lead wire 219 can be appropriately connected to the pad electrode 190.

[0404] On the one hand, Ni, Pd, and Au each have a Young's modulus (rigidity modulus) that exceeds that of Al. Therefore, in the structure provided with the pad electrode 190, the external force applied during the joining of the first conductor 218 and the second conductor 219 cannot be appropriately relaxed.

[0405] Therefore, in the SiC semiconductor device 61, a first Al layer 161 containing Al is interposed between the SiC chip 62 and the pad electrode 190. According to the first Al layer 161, the external force applied to the SiC chip 62 can be relaxed from the first main surface 63 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus). Thus, the first conductor 218 and the second conductor 219 can be appropriately joined to the pad electrode 190, and at the same time, cracks in the SiC chip 62 can be suppressed.

[0406] In addition to the second Al layer 201, the SiC semiconductor device 61 includes a second main surface electrode 200 having one or more electrode layers made of a metal material different from that of the second Al layer 201. The one or more electrode layers include at least one of a Ti layer 202, a Ni layer 203, a Pd layer 204, an Au layer 205, and an Ag layer 206. Thereby, the adhesive force of the conductive joining material 217 to the second main surface electrode 200 can be appropriately increased. As a result, the SiC semiconductor device 61 can be appropriately mounted on the pad portion 224 of the metal plate 213.

[0407] On the other hand, Ti, Ni, Pd, Au, and Ag each have a Young's modulus (rigidity modulus) that exceeds that of Al. Therefore, in the structure in which the second main surface electrode 200 includes at least one of the Ti layer 202, the Ni layer 203, the Pd layer 204, the Au layer 205, and the Ag layer 206, the external force applied during the mounting of the SiC semiconductor device 61 or during the joining of the first conductor 218 and the second conductor 219 cannot be appropriately relaxed.

[0408] Therefore, in the SiC semiconductor device 61, in addition to at least one of the Ti layer 202, Ni layer 203, Pd layer 204, Au layer 205, and Ag layer 206, a second main surface electrode 200 including a second Al layer 201 is formed. According to the second Al layer 201, the external force applied to the SiC chip 62 can be relaxed from the second main surface 64 side by utilizing the cushioning property of Al having a relatively small Young's modulus (rigidity modulus). Therefore, the SiC semiconductor device 61 can be appropriately mounted on the pad portion 224, and at the same time, cracks in the SiC chip 62 can be suppressed.

[0409] The embodiment of the present invention can also be implemented in other forms.

[0410] In the above-described first embodiment, an example in which the insulating layer 17 has a laminated structure including the passivation layer 19 and the resin layer 20 has been described. However, the insulating layer 17 may have a single-layer structure composed of the passivation layer 19 or the resin layer 20.

[0411] In the above-described first embodiment, an example in which an SBD as an example of a diode is formed has been described. However, a p-type diode region 10 may be formed instead of the n-type diode region 10. In this case, a pn junction diode can be provided instead of the SBD.

[0412] In the above-described second embodiment, an example in which the insulating layer 170 has a laminated structure including the passivation layer 174 and the resin layer 175 has been described. However, the insulating layer 170 may have a single-layer structure composed of the passivation layer 174 or the resin layer 175.

[0413] In the above-described second embodiment, an example in which the gate electrode 80 and the gate wiring 85 including p-type polysilicon doped with p-type impurities are formed has been described. However, when the increase in the gate threshold voltage Vth is not emphasized, the gate electrode 80 and the gate wiring 85 may include n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon.

[0414] In this case, the low-resistance layer 86 may be formed by siliciding, with a metal material, a portion that forms the surface layer portion in the gate electrode 80 (n-type polysilicon). That is, the low-resistance layer 86 may include an n-type silicide. In the case of such a structure, the gate resistance can be reduced.

[0415] In the foregoing second embodiment, an example in which a MISFET as an example of an insulated gate type transistor is formed has been described. However, instead of the n + -type drain region 68, a p + -type collector region may be employed. According to this structure, instead of a MISFET, an IGBT (Insulated Gate Bipolar Transistor) can be provided. In this case, in the foregoing second embodiment, the "source" of the MISFET is read as the "emitter" of the IGBT, and the "drain" of the MISFET is read as the "collector" of the IGBT.

[0416] In each of the foregoing embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be employed. That is, a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0417] Examples of features extracted from this specification and the drawings are shown below.

[0418] In a post-process (assembly process), various external forces are applied to the semiconductor device. For example, when mounting the semiconductor device, a mounting machine equipped with a suction nozzle is used. The semiconductor device is transported to a connection target object while being suction-held by the suction nozzle, and then press-mounted to the connection target portion. At this time, an external force from the suction nozzle toward the connection target object and an external force from the connection target object toward the suction nozzle are applied to the semiconductor device.

[0419] After the semiconductor device is mounted, the conductive wire is press-bonded to the pad electrode by a capillary. At this time, an external force directed from the capillary toward the object to be connected and an external force directed from the object to be connected toward the capillary are applied to the semiconductor device. If an external force exceeding the strength of the chip is applied to the semiconductor device, cracks will occur in the chip. Hereinafter, a semiconductor device capable of relaxing the external force will be provided.

[0420] [A1] A chip having a first main surface on one side and a second main surface on the other side, a first main surface electrode including a first Al layer and formed on the first main surface, and formed on the first main surface electrode And a pad electrode connected to the conductive wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

[0421] According to this semiconductor device, the first Al layer is formed as a first buffer layer that relaxes the external force on the first main surface side, and the second Al layer is formed as a second buffer layer that relaxes the external force on the second main surface side. Thereby, the external force in the direction from the first main surface toward the second main surface and the external force in the direction from the second main surface toward the first main surface can be relaxed.

[0422] [A2] The semiconductor device according to A1, further including an insulating layer having a pad opening that covers the first main surface electrode on the first main surface and exposes a part of the first main surface electrode, and the pad electrode is formed on the first main surface electrode in the pad opening.

[0423] [A3] The semiconductor device according to A2, wherein the chip has a side surface connecting the first main surface and the second main surface, and the insulating layer has a periphery formed on the first main surface at a distance from the side surface.

[0424] [A4] The semiconductor device according to A2 or A3, wherein the insulating layer includes a resin layer.

[0425] [A5] The semiconductor device according to any one of A1 to A4, wherein the pad electrode includes a metal material different from that of the first main surface electrode.

[0426] [A6] The pad electrode includes at least one of a Ni layer, a Pd layer, and an Au layer, and the semiconductor device according to any one of A1 to A5.

[0427] [A7] The pad electrode includes a Ni layer and an Au layer laminated in this order from the first main surface electrode side, and the semiconductor device according to any one of A1 to A6.

[0428] [A8] The pad electrode includes a Ni layer, a Pd layer, and an Au layer laminated in this order from the first main surface electrode side, and the semiconductor device according to any one of A1 to A7.

[0429] [A9] The second main surface electrode includes one or more electrode layers made of a metal material different from the second Al layer, and the second Al layer covers one or more of the electrode layers, and the semiconductor device according to any one of A1 to A8.

[0430] [A10] One or more of the electrode layers include at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer, and the semiconductor device according to A9.

[0431] [A11] One or more of the electrode layers include an ohmic electrode layer that forms an ohmic contact at least with the second main surface, and the second Al layer covers at least the ohmic electrode layer, and the semiconductor device according to A9 or A10.

[0432] [A12] The second Al layer has a thickness less than that of the first Al layer, and the semiconductor device according to any one of A1 to A11.

[0433] [A13] The second Al layer includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer, and the semiconductor device according to any one of A1 to A12.

[0434] [A14] The second Al layer is made of a pure Al layer, and the semiconductor device according to any one of A1 to A13.

[0435] [A15] The semiconductor device according to any one of A1 to A14, wherein the first Al layer includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0436] [A16] The semiconductor device according to any one of A1 to A15, further including a diode formed on the first main surface, wherein the first main surface electrode forms an anode electrode electrically connected to the anode of the diode, and the second main surface electrode forms a cathode electrode electrically connected to the cathode of the diode.

[0437] [A17] The semiconductor device according to any one of A1 to A16, further including a MISFET formed on the first main surface, wherein the first main surface electrode includes a gate main surface electrode electrically connected to the gate of the MISFET and a source main surface electrode electrically connected to the source of the MISFET, the pad electrode includes a gate pad electrode formed on the gate main surface electrode and a source pad electrode formed on the source main surface electrode, and the second main surface electrode forms a drain electrode electrically connected to the drain of the MISFET.

[0438] [A18] The semiconductor device according to any one of A1 to A17, wherein the chip has a stacked structure including a semiconductor substrate and an epitaxial layer stacked in this order from the second main surface side to the first main surface side.

[0439] [A19] The semiconductor device according to any one of A1 to A18, wherein the thickness of the chip is 300 μm or less.

[0440] [A20] The semiconductor device according to any one of A1 to A19, wherein the chip is made of a SiC chip formed of a single crystal of SiC.

[0441] This application corresponds to Japanese Patent Application No. 2019-080227 filed with the Japan Patent Office on April 19, 2019, and the entire disclosure of this application is incorporated herein by reference. Although embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited only by the appended claims.

Explanation of Reference Numerals

[0442] 1 SiC semiconductor device 2 SiC chip 3 First main surface 4 Second main surface 5A First side surface 5B Second side surface 5C Third side surface 5D Fourth side surface 6 SiC semiconductor substrate 7 SiC epitaxial layer 14 First main surface electrode 16 First Al layer 17 Insulating layer 18 Pad opening 20 Resin layer 23 Pad electrode 25 Ni layer 26 Pd layer 27 Au layer 31 Second main surface electrode 32 Second Al layer 33 Ti layer 34 Ni layer 35 Pd layer 36 Au layer 37 Ag layer 61 SiC semiconductor device 62 SiC chip 63 First main surface 64 Second main surface 65A First side surface 65B Second side surface 65C Third side surface 65D Fourth side surface 66 SiC semiconductor substrate 67 SiC epitaxial layer 150 First main surface electrode 151 Gate main surface electrode 152 Source main surface electrode 161 First Al layer 170 Insulating layer 171 Pad opening 172 Gate pad opening 173 Source pad opening 175 Resin layer 190 Pad electrode 191 Gate pad electrode 192 Source pad electrode 195 Ni layer 196 Pd layer 197 Au layer 200 Second main surface electrode 201 Second Al layer 202 Ti layer 203 Ni layer 204 Pd layer 205 Au layer 206 Ag layer

Claims

1. An SiC chip having a first main surface on one side and a second main surface on the other side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and connected to a conducting wire, and a second main surface electrode including a second Al layer and formed on the second main surface. The SiC semiconductor device includes these components.

2. The SiC semiconductor device according to claim 1, further including an insulating layer having a pad opening that covers the first main surface electrode on the first main surface and exposes a part of the first main surface electrode. The pad electrode is formed on the first main surface electrode within the pad opening.

3. The SiC chip has a side surface connecting the first main surface and the second main surface. The insulating layer has a periphery formed at a distance from the side surface on the first main surface. The SiC semiconductor device according to claim 2 has this structure.

4. The insulating layer includes a resin layer. The SiC semiconductor device according to claim 2 or 3 has this structure.

5. The pad electrode includes a metal material different from that of the first main surface electrode. The SiC semiconductor device according to any one of claims 1 to 4 has this structure.

6. The pad electrode includes at least one of a Ni layer, a Pd layer, and an Au layer. The SiC semiconductor device according to any one of claims 1 to 5 has this structure.

7. The pad electrode includes a Ni layer and an Au layer laminated in this order from the first main surface electrode side. The SiC semiconductor device according to any one of claims 1 to 6 has this structure.

8. The pad electrode includes a Ni layer, a Pd layer, and an Au layer laminated in this order from the first main surface electrode side. The SiC semiconductor device according to any one of claims 1 to 7 has this structure.

9. The second main surface electrode includes one or more electrode layers made of a metal material different from that of the second Al layer. The second Al layer covers one or more of the electrode layers. The SiC semiconductor device according to any one of claims 1 to 8 has this structure.

10. One or more of the electrode layers include at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The SiC semiconductor device according to claim 9 has this structure.

11. One or more of the electrode layers include an ohmic electrode layer that forms an ohmic contact at least with the second main surface. The second Al layer covers at least the ohmic electrode layer. The SiC semiconductor device according to claim 9 or 10 has this structure.

12. The SiC semiconductor device according to any one of claims 1 to 11, wherein the second Al layer has a thickness less than that of the first Al layer.

13. The SiC semiconductor device according to any one of claims 1 to 12, wherein the second Al layer includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. device.

14. The SiC semiconductor device according to any one of claims 1 to 13, wherein the second Al layer is composed of a pure Al layer.

15. The SiC semiconductor device according to any one of claims 1 to 14, wherein the first Al layer includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

16. Further including a diode formed on the first main surface, wherein the first main surface electrode forms an anode electrode electrically connected to the anode of the diode, The SiC semiconductor device according to any one of claims 1 to 15, wherein the second main surface electrode forms a cathode electrode electrically connected to the cathode of the diode.

17. Further including a MISFET formed on the first main surface, wherein the first main surface electrode includes a gate main surface electrode electrically connected to the gate of the MISFET and a source main surface electrode electrically connected to the source of the MISFET, The pad electrode includes a gate pad electrode formed on the gate main surface electrode and a source pad electrode formed on the source main surface electrode, The SiC semiconductor device according to any one of claims 1 to 16, wherein the second main surface electrode forms a drain electrode electrically connected to the drain of the MISFET.

18. The SiC semiconductor device according to any one of claims 1 to 17, wherein the SiC chip has a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer stacked in this order from the second main surface side to the first main surface side.

19. The SiC semiconductor device according to any one of claims 1 to 18, wherein the thickness of the SiC chip is 300 μm or less.

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