Interface circuit and semiconductor device

Abstract

To provide an interface circuit that can both suppress the wrong operation of a protection element and improve the certainty of ESD protection operation with an effective structure.SOLUTION: An interface circuit (3) includes a first terminal (Tv) configured to be applied with power source voltage (Vcc), a second terminal (To, Ti) configured to be applied with an output signal (So) or an input signal (Si), a first protection element (11A) configured as a transistor with a first end connected to the second terminal and a second end connected to a ground end, and a control end control unit (4) including control elements (Tr1 to Trn) as two or more transistors that are connected in series between a control end of the first protection element and the ground end and have its control end connected in common to the first terminal.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to an interface circuit.

Background Art

[0002] ESD (Electro-Static Discharge) is a phenomenon in which electrostatic discharge occurs. When an ESD pulse enters the IC due to ESD, the IC may malfunction. Therefore, conventionally, a countermeasure component for suppressing malfunctions due to ESD may be provided in the IC.

[0003] Conventionally, it is known to use a MOS transistor (MOSFET (metal-oxide-semiconductor field-effect transistor)) as an ESD protection element (for example, Patent Document 1). When ESD occurs, by passing a surge current through the MOS transistor, the adverse effect on the IC is suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] Conventionally, the ESD protection element may malfunction during normal operation.

[0006] An object of the present disclosure is to provide an interface circuit that can effectively achieve both suppression of malfunction of a protection element and improvement in reliability of an ESD protection operation.

[0007] An interface circuit according to one aspect of the present disclosure includes a first terminal configured to be applied with a power supply voltage, a second terminal configured to be applied with an output signal or an input signal, A first protection element configured as a transistor having a first terminal connected to the second terminal and a second terminal connected to a ground terminal; A control terminal control unit having a control element as two or more transistors connected in series between the control terminal of the first protection element and the ground terminal, and having the control terminal commonly connected to the first terminal.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0009] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0010] <Comparative Example> Here, before describing the embodiments of the present disclosure, a comparative example for comparison will be described. FIG. 5 is a diagram showing a configuration of an interface circuit 30 according to a first comparative example. The interface circuit 30 is configured as an output circuit and includes an ESD protection unit 10, an output driver 20, and an output terminal To.

[0011] The ESD protection unit 10 is configured to perform a protection operation when an ESD pulse Ep is applied to the output terminal To, and includes a protection element 10A and a protection element 10B. The protection element 10A is composed of an N-channel MOSFET [metal-oxide-semiconductor field-effect transistor]. The drain of the protection element 10A is connected to the output terminal To. The source of the protection element 10A is connected to the ground terminal (the terminal to which the ground potential is applied). The gate-source of the protection element 10A is connected by a resistor 10C. The protection element 10B is composed of a P-channel MOSFET. The source of the protection element 10B is connected to the terminal to which the power supply voltage Vcc is applied. The drain of the protection element 10B is connected to the drain of the protection element 10A. The gate-source of the protection element 10B is short-circuited.

[0012] The output driver 20 includes a lower transistor 20A and an upper transistor 20B. The lower transistor 20A is composed of an N-channel MOSFET. The upper transistor 20B is composed of a P-channel MOSFET. The drain of the lower transistor 20A is connected to the drain of the upper transistor 20B. The source of the lower transistor 20A is connected to the ground terminal. The source of the upper transistor 20B is connected to the terminal to which the power supply voltage Vcc is applied.

[0013] The gate of the upper transistor 20B and the gate of the lower transistor 20A are connected to a switch driving unit (not shown). The upper transistor 20B and the lower transistor 20A are driven to switch complementarily by the switch driving unit. Thereby, during normal operation, an output signal So of a high level (power supply voltage Vcc) or a low level (ground potential) is generated at the output terminal To.

[0014] When an ESD pulse Ep is applied to the output terminal To, the gate voltage of the protection element 10A rises with respect to the ground terminal by the resistor 10C, so that the protection element 10A is turned on. At this time, the gate voltage of the lower transistor 20A also rises with respect to the ground terminal, and the lower transistor 20A is also turned on. As a result, a current flows through both the protection element 10A and the lower transistor 20A, and a protection operation is performed. That is, the output driver 20 also has a function of ESD protection.

[0015] During normal operation, if normal, the voltage between the gate and source of the protection element 10A is almost 0, and the protection element 10A is in an off state. However, due to the noise caused by the switching of the output driver 20, the protection element 10A may be turned on, and there is a possibility that a current flows from the protection element 10A toward the ground terminal. That is, there was a possibility that the protection element 10A malfunctioned.

[0016] FIG. 6 shows the configuration of the interface circuit 31 according to the second comparative example. The interface circuit 31 includes, as a difference from the first comparative example, an ESD protection unit 11, an inverter IV, and a level shifter LS. The ESD protection unit 11 has protection elements 11A and 11B. The difference between the ESD protection unit 10 in the first comparative example and the connection relationship of the protection elements 11A and 11B is that the gate of the protection element 11A is connected to the output terminal of the inverter IV. The input terminal of the inverter IV is connected to the output terminal of the level shifter LS.

[0017] An internal power supply voltage VDDL is input to the level shifter LS. The internal power supply voltage VDDL has a voltage value different from the power supply voltage Vcc as the power supply voltage of the interface circuit 31. The internal power supply voltage VDDL is level-shifted by the level shifter LS and inverted by the inverter IV. As a result, during normal operation, the gate voltage of the protection element 11A becomes almost 0V, and the protection element 11A is turned off. The protection element 11A maintains the off state regardless of the switching of the output driver 20, and malfunction can be suppressed.

[0018] On the other hand, when an ESD pulse Ep is applied to the output terminal To, the power supply voltage Vcc and the internal power supply voltage VDDL are not applied, and the gate voltage of the protection element 11A is in a floating state. At this time, due to the ESD pulse Ep, the gate voltage of the protection element 11A rises with respect to the ground terminal due to the resistance component of the transistors constituting the inverter IV, and the protection element 11A is turned on. Thereby, a protection operation is performed.

[0019] Therefore, according to the second comparative example, it is possible to achieve both suppression of malfunction and protection operation. However, depending on the specifications, control by the signal from the level shifter may not be allowed.

[0020] In such a case, the interface circuit 32 according to the third comparative example shown in FIG. 7 can be implemented. In the interface circuit 32, as a difference from the second comparative example, a control element Tr for controlling the gate of the protection element 11A is provided.

[0021] The control element Tr is composed of an N-channel MOSFET. The drain of the control element Tr is connected to the gate of the protection element 11A. The source of the control element Tr is connected to the ground terminal. The gate of the control element Tr is connected to the applied terminal of the power supply voltage Vcc.

[0022] According to such a configuration, since the power supply voltage Vcc is applied to the gate of the control element Tr, the control element Tr is turned on, the gate voltage of the protection element 11A becomes approximately 0V, and the protection element 11A maintains an off state. Thereby, malfunction during normal operation is suppressed.

[0023] On the other hand, when an ESD pulse Ep is applied to the output terminal To, although the power supply voltage Vcc is not applied, a voltage lower by only the forward voltage of the parasitic diode Di included in the protection element 11B is applied to the gate of the control element Tr from the voltage applied to the output terminal To. Since the current capacity of the control element Tr is high, there was a possibility that the gate voltage of the protection element 11A would not rise, the protection element 11A would not turn on, and the protection operation would not be performed. Then, current concentrated and flowed through the lower transistor 20A, which could have an adverse effect on the lower transistor 20A.

[0024] <Semiconductor device> In view of the above problems, the embodiments of the present disclosure described below are implemented. FIG. 1 is a diagram showing a configuration example of a semiconductor device. The semiconductor device 1 of this configuration example is an LSI in which a CMOS [complementary MOS] circuit (a logic / analog mixed circuit) mainly driven at 5 V or less is integrated. An I / O [input / output] circuit 10 responsible for an ESD protection function and a signal input / output function is arranged at the outermost peripheral part of the semiconductor device 1.

[0025] In addition to the I / O circuit 10, various internal circuits are integrated in the semiconductor device 1. Specifically in terms of this figure, in the semiconductor device 1, as various internal circuits, a logic circuit LOGIC, an analog circuit ANALOG, an interface circuit I / F, a non-volatile memory NVM, a volatile memory SRAM, a digital / analog converter DAC, an analog / digital converter ADC, and a regulator LDO are integrated.

[0026] The I / O circuit 10 may be arranged along the four sides of the semiconductor device 1 so as to surround the above internal circuits in a plan view of the semiconductor device 1. The semiconductor device 1 may be, for example, a controller mounted on various terminal devices

[0027] (such as an LED [light emitting diode] lamp, a motor, or a switch) via an in-vehicle network. (LED [light emitting diode] lamp, motor or switch, etc.) mounted on the con In-vehicle integrated communication I for controlling a trolley (such as an ECU [electronic control unit]) A C [integrated circuit] can be cited. In this case, the interface circuit I / F may conform to any in-vehicle network (for example, LIN [local interconnect network], CXPI [clock extension peripheral interface] and CAN [controller area network]) and may comply with it.

[0028] <Standard I / O cell> The I / O circuit 10 is configured by combining standard I / O cells. The standard I / O cell is a unit that constitutes the I / O circuit 10 and is configured by arranging various MOSFETs as described later. By appropriately wiring the standard I / O cell, an interface function with the outside of the device (ESD protection function and signal input / output function) can be provided.

[0029] FIG. 2 is a plan view showing a layout example of the standard I / O cell 2. In FIG. 2, the X direction and the Y direction orthogonal to each other are shown. The standard I / O cell 2 has an NMOS region 21, a PMOS region 22, and a G / A (gate array) section 23.

[0030] As shown in FIG. 2, the NMOS region 21 has a protection dedicated element region Ra and a protection element selection region Rb as regions where protection elements are arranged. The protection dedicated element region Ra and the protection element selection region Rb are surrounded by a guard ring GD1.

[0031] In the protection-only element region Ra, protection elements Ma that function only as ESD protection elements are arranged. The protection elements Ma are configured as N-channel MOSFETs, and multiple protection elements Ma are arranged side by side in the Y direction as shown in Fig. 2. In Fig. 2, 12 protection elements Ma are arranged as an example. As shown in Fig. 2, the protection element Ma has a gate Ga having a gate width Wa in the X direction and a gate length in the Y direction.

[0032] The protection element selection region Rb is adjacent to the protection-only element region Ra in the X direction. A protection element Mb that performs ESD protection is arranged in the protection element selection region Rb. The protection elements Mb are configured as N-channel MOSFETs, and multiple protection elements Mb are arranged side by side in the Y direction as shown in FIG. 2. In FIG. 2, 12 protection elements Mb are arranged as an example. As shown in FIG. 2, the protection element Mb has a gate Gb having a gate width Wb in the X direction and a gate length in the Y direction.

[0033] The multiple protection elements Ma are connected in parallel and placed in a location electrically closer to the outside than the protection elements Mb. This allows the surge current to flow through the protection elements Ma when ESD occurs, suppressing the impact on the inside of the IC. In addition, by making the gate width Wa of the protection elements Ma longer than the gate width Wb of the protection elements Mb, a large amount of surge current can be passed through the protection elements Ma at a location closer to the outside.

[0034] In the protection element selection region Rb, it is possible to select from among the multiple protection elements Mb either a protection element Mb that combines the function of ESD protection with the function of a driver element (driver / protection element) or a protection element Mb that only has the function of ESD protection (protection-only element). This selection is made by changing the wiring for the gate Gb.

[0035] In the example of FIG. 2, out of the 12 protection elements Mb, for example, one protection element Mb can be selected as a driver-cum-protection element, and the remaining 11 protection elements Mb can be selected as protection-only elements. Or, for example, all 12 protection elements Mb may be selected as driver-cum-protection elements. The number of driver-cum-protection elements is selected according to the required current capacity. When ESD occurs, a surge current flows through both the driver-cum-protection element and the protection-only element, and the function of protecting the inside of the IC works.

[0036] The PMOS region 22 is adjacent to the NMOS region 21 in the X direction. In the PMOS region 22, a plurality of protection elements Gc each constituted by a P-channel MOSFET are arranged side by side in the Y direction. The protection element Gc has a gate Gc. A part of the protection element Gc can be made to serve also as a driver element. The protection element Gc is surrounded by a guard ring GD2.

[0037] The G / A section 23 is adjacent to the PMOS region 22 in the X direction. The G / A section 23 has an NMOS region 231 and a PMOS region 232. In the NMOS region 231, a plurality of NMOS transistors Md each constituted by an N-channel MOSFET are arranged side by side in the Y direction. The NMOS transistor Md has a gate Gd. The NMOS transistor Md is surrounded by a guard ring GD3. In the PMOS region 232, a plurality of PMOS transistors Me each constituted by a P-channel MOSFET are arranged side by side in the Y direction. The PMOS transistor Me has a gate Ge. The PMOS transistor Me is surrounded by a guard ring GD4. By appropriately wiring the G / A section 23, an interface circuit for various functions can be configured.

[0038] <Output Circuit> FIG. 3 is a diagram showing the configuration of the interface circuit 3 according to an exemplary embodiment of the present disclosure. The interface circuit 3 is configured as an output circuit and includes an ESD protection unit 11, an output driver 20, and a gate control unit (control terminal control unit) 4. The difference from the above-described third comparative example (FIG. 7) is that the gate control unit 4 is provided. Note that the interface circuit 3 has a power supply terminal Tv. A power supply voltage Vcc is applied to the power supply terminal Tv.

[0039] The interface circuit 3 is configured using the above-described standard I / O cell 2. The protection element Ma in the protection dedicated element region Ra is used for the protection element 11A. The protection element Mb in the protection element selection region Rb is used for the lower transistor 20A. That is, the protection element Mb serves as both a protection element and a driver element. The protection element Mc in the PMOS region 22 is used for the protection elements 11B and the upper transistor 20B, respectively.

[0040] The gate control unit 4 is configured to control the gate of the protection element 11A and is composed of a plurality of control elements Tr1 to Trn formed by N-channel MOSFETs. That is, n is an integer of 2 or more (for example, n = 10). The control elements Tr1 to Trn are connected in series between the gate of the protection element 11A and the ground terminal. Each gate of the control elements Tr1 to Trn is commonly connected to the power supply terminal Tv.

[0041] With such a configuration, during normal operation, the power supply voltage Vcc is applied to each gate of the control elements Tr1 to Trn, so that the control elements Tr1 to Trn are in an on state, the gate voltage of the protection element 11A becomes almost 0V, and the protection element 11A is in an off state. Therefore, it is possible to suppress malfunction of the protection element 11A due to the influence of noise or the like caused by the switching of the output driver 20.

[0042] Also, when an ESD pulse Ep is applied to the output terminal To, although the power supply voltage Vcc is not applied, a voltage reduced by only the forward voltage of the parasitic diode Di (forward in the power supply terminal Tv side) of the protection element 11B from the voltage of the output terminal To is applied to each gate of the control elements Tr1 to Trn. As a result, the control elements Tr1 to Trn are turned on. However, since the control elements Tr1 to Trn are connected in series, the current capacity becomes low. Therefore, it is possible to suppress the gate voltage of the protection element 11A from decreasing and the protection element 11A from turning on, and prevent the protection operation from not being performed. That is, it is possible to improve the certainty of the ESD protection operation while suppressing malfunction.

[0043] In particular, a protection element Ma (FIG. 2) having a long gate width Wa is used for the protection element 11A, and a protection element Mb having a short gate width Wb is used for the lower transistor 20A. Therefore, by ensuring the protection operation of the protection element 11A, it is possible to suppress the current from concentrating and flowing through the protection element Mb (lower transistor 20A) having the short gate width Wb, and suppress the adverse effect on the lower transistor 20A.

[0044] Here, an NMOS transistor Md disposed in the NMOS region 231 of the G / A section 23 in the standard I / O cell 2 is used for the control elements Tr1 to Trn. In the standard I / O cell 2, versatility is provided so that various functional interface circuits can be configured only by performing wiring recombination on the G / A section 23. For example, assuming that the NMOS transistor Md is used as the control element Tr (FIG. 7) in the third comparative example, in the interface circuit 3 of the present embodiment, the gate control section 4 can be realized by using the NMOS transistor Md (dummy transistor) that was not used in the G / A section 23 in the third comparative example. Thereby, an increase in cell area can be avoided.

[0045] <Input Circuit> FIG. 4 is a diagram showing the configuration of the interface circuit 5 according to an exemplary embodiment of the present disclosure. The interface circuit 5 is configured as an input circuit and includes an ESD protection unit 11, an inverter 6, and a gate control unit 4. The difference between the interface circuit 5 and the interface circuit 3 (FIG. 3) is the inverter 6. Further, the interface circuit 5 has an input terminal Ti together with a power supply terminal Tv. The input terminal Ti is replaced with the output terminal To in the interface circuit 3.

[0046] The inverter 6 has a CMOS structure and includes an NMOS transistor 6A and a PMOS transistor 6B. The source of the PMOS transistor 6B is connected to the power supply terminal Tv. The drain of the PMOS transistor 6B is connected to the drain of the NMOS transistor 6A. The source of the NMOS transistor 6A is connected to the ground terminal. The gates of the NMOS transistor 6A and the PMOS transistor 6B are commonly connected to the input terminal Ti. The NMOS transistor Md and the PMOS transistor Me in the G / A part 23 of the standard I / O cell 2 are respectively used for the NMOS transistor 6A and the PMOS transistor 6B.

[0047] With such a configuration, the input signal Si input to the input terminal Ti is inverted by the inverter 6. During normal operation, the gate control unit 4 suppresses the malfunction of the protection element 11A due to the influence of noise or the like caused by the input signal Si. Further, even when an ESD pulse Ep is applied to the input terminal Ti, the configuration of the gate control unit 4 suppresses the protection function of the protection element 11A from not working.

[0048] <Others> Various technical features disclosed in this specification can be variously modified in addition to the above embodiments without departing from the gist of the technical creation. That is, the above embodiments should be considered as illustrative in all respects and not restrictive, and the technical scope of the present invention is not limited to the above embodiments, but should be understood to include all modifications belonging to the meaning and scope equivalent to the claims.

[0049] For example, in the interface circuit of the above embodiment, although the transistor used was a MOS transistor, it can be appropriately replaced with a bipolar transistor or the like.

[0050] <Appendix> As described above, an interface circuit (3) according to one aspect of the present disclosure includes a first terminal (Tv) configured to be applied with a power supply voltage (Vcc), a second terminal (To, Ti) configured to be applied with an output signal (So) or an input signal (Si), a first protection element (11A) configured as a transistor having a first end connected to the second terminal and a second end connected to a ground terminal, and a control terminal control unit (4) having control elements (Tr1 to Trn) as two or more transistors connected in series between the control terminal of the first protection element and the ground terminal, and having a control terminal commonly connected to the first terminal. (First configuration)

[0051] According to such a configuration, during normal operation, malfunction of the first protection element is suppressed by the control terminal control unit. Further, when an ESD pulse is applied to the second terminal, since the current capacity of the control terminal control unit is low, it is possible to suppress the protection operation of the first protection element from not being performed.

[0052] Also, in the above first configuration, it has a second protection element (11B) having a first end connected to the first terminal and a second end connected to the first end of the first protection element, The second protection element may include a parasitic diode (Di) whose forward direction is the first terminal side (second configuration).

[0053] In the first or second configuration, the interface circuit is configured using standard I / O cells (2); The standard I / O cell has a G / A section (23) in which a used MOS transistor and an unused MOS transistor are arranged, The two or more control elements may be configured to use the MOS transistors used above (third configuration).

[0054] In any one of the first to third configurations, the control element may be configured by an N-channel MOSFET (fourth configuration).

[0055] In any one of the first to fourth configurations, an output driver (20) may be further provided, and an output end of the output driver may be connected to the second terminal (fifth configuration).

[0056] In the fifth configuration, the interface circuit is configured using standard I / O cells (2); The standard I / O cell is a protection-only element region (Ra) in which a plurality of first MOS transistors (Ma) dedicated for protection are arranged in parallel; a protection element selection region (Rb) in which a plurality of second MOS transistors (Mb) are arranged side by side, the second MOS transistors (Mb) being selectable as either a protection function and a driver element function or a protection function only; having The gate width (Wb) of the second MOS transistor is shorter than the gate width (Wa) of the first MOS transistor, The first protection element includes the first MOS transistor, The second MOS transistor may be used as a lower transistor (20A) included in the output driver (sixth configuration).

[0057] Also, in any of the configurations from the first to the sixth, an inverter (6) may be further provided, and the input terminal of the inverter may be connected to the second terminal to which the input signal is applied (seventh configuration).

[0058] Also, in any of the configurations from the first to the seventh, the first protection element may be composed of an N-channel MOSFET (eighth configuration).

[0059] Also, a semiconductor device (1) according to an aspect of the present disclosure includes an interface circuit having any of the configurations from the first to the eighth (ninth configuration).

Industrial Applicability

[0060] The present disclosure can be used, for example, in interface circuits of various semiconductor devices.

Explanation of Reference Numerals

[0061] 1 Semiconductor device 2 Standard I / O cell 3 Interface circuit 4 Gate control unit 5 Interface circuit 6 Inverter 6A NMOS transistor 6B PMOS transistor 10 ESD protection unit 10A, 10B Protection elements 10C Resistor 11 ESD protection unit 11A, 11B Protection elements 20 Output driver 20A Lower transistor 20B Upper transistor 21 NMOS region 22 PMOS region 23 G / A section 30 - 32 Interface circuit 231 NMOS region 232 PMOS region GD1~GD4 Guard ring Ga~Ge Gate IV Inverter LS Level shifter Ma~Mc Protection element Md NMOS transistor Me PMOS transistor Ra Dedicated protection element region Rb Protection element selection region Ti Input terminal To Output terminal Tr Control element Tr1~Trn Control elements Tv Power supply terminal

Claims

1. A first terminal configured to receive a power supply voltage; a second terminal configured to receive an output signal or an input signal; a first protection element configured as a transistor having a first end connected to the second terminal and a second end connected to a ground end; a control terminal control unit having two or more control elements as transistors connected in series between a control terminal of the first protection element and the ground terminal, the control terminals of which are commonly connected to the first terminal; An interface circuit comprising:

2. a second protection element having a first end connected to the first terminal and a second end connected to the first end of the first protection element; 2. The interface circuit according to claim 1, wherein the second protection element includes a parasitic diode having a forward direction toward the first terminal.

3. the interface circuit is constructed using standard I / O cells; The standard I / O cell has a G / A portion in which a used MOS transistor and an unused MOS transistor are arranged, 2. The interface circuit according to claim 1, wherein the two or more control elements are made of MOS transistors.

4. 2. The interface circuit according to claim 1, wherein the control element is an N-channel MOSFET.

5. further comprising an output driver; 2. The interface circuit according to claim 1, wherein an output end of the output driver is connected to the second terminal.

6. the interface circuit is constructed using standard I / O cells; The standard I / O cell comprises: a protection-only element region in which a plurality of first MOS transistors dedicated for protection are arranged side by side; a protection element selection region in which a plurality of second MOS transistors are arranged side by side, the second MOS transistors being selectable as either a protection function and a driver element function or a protection function only; having a gate width of the second MOS transistor is shorter than a gate width of the first MOS transistor; The first protection element includes the first MOS transistor, 6. The interface circuit according to claim 5, wherein the second MOS transistor is used as a lower transistor included in the output driver.

7. Further comprising an inverter; 2. The interface circuit according to claim 1, wherein an input end of the inverter is connected to the second terminal to which the input signal is applied.

8. 2. The interface circuit according to claim 1, wherein the first protection element is configured by an N-channel MOSFET.

9. A semiconductor device comprising the interface circuit according to any one of Claims 1 to 8.

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