Semiconductor device

Abstract

To achieve downsizing of a chip size and power consumption reduction.SOLUTION: A semiconductor device includes: a second transistor that has a control wire connected to a gate of a first transistor, a first terminal for receiving a first voltage for turning on the first transistor, a second terminal, and a first gate connected to the control wire; a third transistor that has a third terminal connected to the second terminal, a fourth terminal for controlling a voltage of the control wire, and a second gate, and is turned on by a first control signal inputted to the second gate upon turning on a plurality of first transistors; a fourth transistor that has fifth and sixth terminals and a third gate, and is turned on by a second control signal inputted to the third gate when the third transistor is turned on; and a capacitor that boosts a second voltage outputted from the fourth terminal in a state in which the first transistor and the second transistor are on to a third voltage higher than the second voltage by capacitive coupling and supplies the voltage to the control wire.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device.

Background Art

[0002] The NAND flash memory is highly integrated, and the ratio of the chip size of the high breakdown voltage transistors used for data writing tends to increase. In particular, as the degree of high integration progresses, the area of the core circuit including the word line switch transistor that drives the word line and the control line and the circuit that controls the gate voltage of the word line switch transistor increases, making it difficult to reduce the chip size.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Therefore, one embodiment of the present invention provides a semiconductor device capable of reducing the chip size.

Means for Solving the Problems

[0005] In order to solve the above problems, according to one embodiment of the present invention, a control wiring connected to the gate of the first transistor, a first terminal and a second terminal that are each a source or a drain, and a first gate to which the control wiring is connected, a second transistor to which a first voltage for turning on the first transistor is input to the first terminal; A third transistor having a third terminal and a fourth terminal, each being a source or a drain, and a second gate, wherein the third terminal is connected to the second terminal, the fourth terminal controls the voltage of the control wiring, and is turned on by a first control signal input to the second gate when the first transistor is turned on. A fourth transistor having a fifth terminal and a sixth terminal, each being a source or a drain, and a third gate, which is turned on by a second control signal input to the third gate when the third transistor is turned on and is turned off by the second control signal input to the third gate when the third transistor is turned off. A capacitor that boosts the second voltage output from the fourth terminal in a state where the first transistor and the second transistor are turned on to a third voltage higher than the second voltage by capacitive coupling and supplies the boosted voltage to the control wiring. A semiconductor device is provided.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. Hereinafter, the description will focus on the main components of the semiconductor device, but there may be components and functions that are not illustrated or described in the semiconductor device. The following description does not exclude components and functions that are not illustrated or described.

[0008] (Schematic Configuration of Memory System) FIG. 1 is a block diagram showing a schematic configuration of a memory system including a semiconductor device according to an embodiment. In this specification, an example in which the semiconductor device according to the embodiment is applied to a semiconductor memory device will be mainly described.

[0009] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0010] The memory system 3 is, for example, a memory card such as an SD TM card, UFS (universal flash storage), and SSD (solid state drive). The memory system 3 is configured to be connected to an external host device (not shown).

[0011] The memory controller 2 is configured by an integrated circuit such as an SoC (system-on-a-chip), for example. The memory controller 2 controls the semiconductor memory device 1 based on a request from the host device. Specifically, for example, the memory controller 2 writes data requested to be written from the host device into the semiconductor memory device 1. Also, the memory controller 2 reads data requested to be read from the host device from the semiconductor memory device 1 and transmits it to the host device.

[0012] The semiconductor memory device 1 is, for example, a NAND type flash memory. The semiconductor memory device 1 stores data non-volatilely. The semiconductor memory device 1 is connected to the memory controller 2 via the NAND bus B.

[0013] The NAND bus B is a bus compliant with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0014] (Internal configuration of the semiconductor memory device) Hereinafter, with reference to the block diagram shown in FIG. 1, the internal configuration of the semiconductor memory device 1 according to the embodiment will be described. The semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0015] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The block BLK is a set of a plurality of memory cell transistors capable of storing data non-volatilely and is used, for example, as an erasure unit of data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. One memory cell transistor is associated with, for example, one bit line and one word line.

[0016] The command register 11 holds the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes, for example, an instruction for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.

[0017] The address register 12 holds the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. For example, the page address PA, the block address BA, and the column address CA are used for the selection of the word line, the block BLK, and the bit line, respectively.

[0018] Sequencer 13 controls the operation of the entire semiconductor memory device 1. For example, based on the command CMD held in the command register 11, sequencer 13 controls the driver module 14, row decoder module 15, sense amplifier module 16, etc. to execute read operations, write operations, erase operations, etc.

[0019] Driver module 14 generates the voltages used in read operations, write operations, erase operations, etc. Then, based on the page address PA held in the address register 12, for example, driver module 14 applies the generated voltage to the signal line corresponding to the selected word line.

[0020] Row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. Then, row decoder module 15 transfers the voltage applied to the signal line corresponding to the selected word line, for example, to the selected word line in the selected block BLK.

[0021] Sense amplifier module 16 transfers data DAT between the memory controller 2 and the memory cell array 10. Data DAT includes write data and read data. More specifically, in a write operation, sense amplifier module 16 transfers the write data received from the memory controller 2 to the memory cell array 10. Also, in a read operation, sense amplifier module 16 executes a determination of the data stored in the memory cell transistor based on the voltage of the bit line. Then, sense amplifier module 16 transfers the result of the determination to the memory controller 2 as read data.

[0022] (Circuit configuration of the memory cell array) FIG. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device according to the embodiment. In FIG. 2, one block BLK out of a plurality of blocks BLK included in the memory cell array 10 is shown. In the example shown in FIG. 2, the block BLK includes, for example, five string units SU0 to SU4.

[0023] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage layer, and holds data non-volatilely. Each of the selection transistors ST1 and ST2 is used for selecting the string unit SU during various operations. In the following description, the memory cell transistors MT0 to MT7 are also each referred to as a memory cell transistor MT.

[0024] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. One end of the selection transistor ST1 is connected to the associated bit line BL, and the other end of the selection transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. One end of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The other end of the selection transistor ST2 is connected to the source line SL.

[0025] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are respectively connected to the word lines WL0 to WL7. The gates of the selection transistors ST1 in the string units SU0 to SU4 are respectively connected to the selection gate lines SGD0 to SGD4. On the other hand, the gates of the plurality of selection transistors ST2 are commonly connected to the selection gate line SGS. However, it is not limited to this, and the gates of the plurality of selection transistors ST2 may be respectively connected to a plurality of different selection gate lines for each string unit SU. In the following description, when the word lines WL0 to WL7 are not distinguished, they are simply referred to as the word line WL. Also, when the selection gate lines SGD0 to SGD4 are not distinguished, they are simply referred to as the selection gate line SGD.

[0026] Each of the bit lines BL0 to BLm is commonly connected to one NAND string NS included in each string unit SU in a plurality of blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared among a plurality of blocks BLK, for example.

[0027] A set of a plurality of memory cell transistors MT connected to a common word line WL within one string unit SU is called a cell unit CU, for example. For example, the storage capacity of the cell unit CU including the memory cell transistors MT each storing 1-bit data is defined as "1 page of data". The cell unit CU can have a storage capacity of 2 pages of data or more according to the number of bits of data stored by the memory cell transistor MT.

[0028] Note that the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT included in each NAND string NS, as well as the number of selection transistors ST1 and ST2, can be designed to be any number respectively.

[0029] (Cross-sectional Structure of Semiconductor Memory Device) Next, the cross-sectional structure of the semiconductor memory device 1 according to the embodiment will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the embodiment. In FIG. 3, a cross-sectional structure including two string units SU out of five string units SU included in one block BLK is shown.

[0030] In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate on which the semiconductor memory device 1 is formed.

[0031] The memory cell array 10 includes conductor layers 21, 22, 24, and 25 provided above the semiconductor substrate 20, a plurality of conductor layers 23, and a plurality of memory pillars MP (only two are shown in FIG. 3). In the following description, the direction in which the memory cell array 10 is provided with respect to the semiconductor substrate 20 is defined as the upward direction. Also, the opposite direction is defined as the downward direction.

[0032] On the semiconductor substrate 20, a wiring layer region WR is disposed. The wiring layer region WR has a plurality of wiring layers D0, D1, D2 laminated via contacts C0, C1, C2. The peripheries of the plurality of wiring layers D0, D1, D2 are covered with an insulator layer. In FIG. 3, an example in which the wiring layer region has three wiring layers D0, D1, D2 is shown, but the number of wiring layers is arbitrary. At least a part of peripheral circuits such as a row decoder is disposed in the wiring layers D0, D1, D2.

[0033] On the wiring layer region WR, a conductor layer 21 is laminated. The conductor layer 21 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 21 is used as a source line SL. The conductor layer 21 is composed of a conductive material, for example, an N-type semiconductor doped with impurities, or a metal material such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), a laminated film of tantalum nitride (TaN) and tantalum (Ta), a laminated film of titanium (Ti), titanium nitride (TiN) and tungsten (W), or a laminated film of titanium nitride (TiN) and tungsten silicide (WSi). Further, the conductor layer 21 may have a laminated structure of a semiconductor and a metal material, such as a laminated film of titanium nitride (TiN), tungsten silicide (WSi) and poly-Si.

[0034] An insulator layer 31 is provided on the conductor layer 21. A conductor layer 22 is laminated on the insulator layer 31. The conductor layer 22 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 22 is used as a select gate line SGS. The conductor layer 22 contains, for example, tungsten (W).

[0035] An insulator layer 32 is provided on the conductor layer 22. Eight conductor layers 23 and eight insulator layers 33 are alternately laminated one by one on the insulator layer 32. The conductor layer 23 is formed, for example, in a plate shape extending along the XY plane. The eight laminated conductor layers 23 are used as word lines WL0 to WL7 in order from the conductor layer 21 side. The conductor layer 23 contains, for example, tungsten (W).

[0036] A conductor layer 24 and an insulator layer 34 are laminated in this order on the uppermost insulator layer 33. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane. The laminated conductor layer 24 is used as a select gate line SGD. The conductor layer 24 contains, for example, tungsten (W). The conductor layer 24 is electrically separated for each string unit SU by, for example, a slit SHE.

[0037] An insulator layer 34 is provided on the conductor layer 24. A conductor layer 25 is provided on the insulator layer 34. The conductor layer 25 is formed, for example, in a line shape extending in the Y direction and functions as a bit line BL. The conductor layer 25 contains, for example, copper (Cu).

[0038] A plurality of memory pillars MP are provided to extend along the Z direction below the conductor layer 25 and penetrate the conductor layers 22 and 24 and the plurality of conductor layers 23. Also, the bottom of each of the memory pillars MP is located in a layer lower than the insulator layer 31 and contacts the conductor layer 21.

[0039] Each of the memory pillars MP includes, for example, a core member 35, a semiconductor film 36, a tunnel insulating film 37, a charge storage film 38, a block insulating film 39, and a semiconductor portion 26.

[0040] The core member 35 is provided to extend, for example, along the Z direction. The upper end of the core member 35 is included in a layer above the conductor layer 24, and the lower end of the core member 35 is included in a layer below the conductor layer 22. The core member 35 contains, for example, silicon oxide (SiO2).

[0041] The semiconductor film 36 is provided to cover the side surface and the lower surface of the core member 35. The upper end of the semiconductor film 36 reaches a position equivalent to the position of the upper end of the core member 35. The lower end of the semiconductor film 36 contacts the conductor layer 21. The semiconductor film 36 contains, for example, polysilicon.

[0042] The tunnel insulating film 37 covers the side surface of the semiconductor film 36. The tunnel insulating film 37 contains, for example, silicon oxide (SiO2).

[0043] The charge storage film 38 covers the side surface of the tunnel insulating film 37. The charge storage film 38 contains, for example, an insulator capable of storing charges. The insulator is, for example, silicon nitride (SiN).

[0044] The block insulating film 39 covers the side surface of the charge storage film 38. The block insulating film 39 contains, for example, silicon oxide (SiO2).

[0045] The semiconductor part 26 is provided in contact with the semiconductor film 36 and covering the upper end of the core member 35. At the upper end of the semiconductor part 26, a conductor layer 27 functioning as a columnar contact CV is provided. The upper end of the conductor layer 27 is in contact with the conductor layer 25. The conductor layer 25 has a line-shaped bit line BL extending in the Y direction. In the conductor layer 25, for example, a plurality of bit lines BL are arranged at a predetermined interval in the front-back direction of FIG. 3. Each memory pillar MP corresponding to each bit line BL is electrically connected through the corresponding conductor layer 27.

[0046] On the conductor layer 25, a conductor layer 28 is arranged via an insulator layer. On the conductor layer 28, a conductor layer 29 is arranged via an insulator layer. In the conductor layers 28 and 29, for example, at least a part of the peripheral circuit of the memory cell array 10 is arranged. FIG. 3 shows an example in which two conductor layers 28 and 29 are stacked above the conductor layer where the bit lines are arranged, but the number of wiring layers is arbitrary. In this specification, the conductor layer 25 including the bit line may be referred to as a wiring layer M0, the conductor layer 28 above it as a wiring layer M1, and the conductor layer 29 above it as a wiring layer M2.

[0047] In the structure of the memory pillar MP described above, the portion where the memory pillar MP intersects with the conductor layer 22 functions as a selection transistor ST2. Also, the portion where the memory pillar MP intersects with the conductor layer 23 functions as a memory cell transistor MT. Also, the portion where the memory pillar MP intersects with the conductor layer 24 functions as a selection transistor ST1. Also, the semiconductor film 36 functions as the channel of each of the memory cell transistors MT0 to MT7, and the selection transistors ST1 and ST2. Also, the charge storage film 38 functions as the charge storage layer of the memory cell transistor MT.

[0048] (Overall Configuration of Row Decoder Module) Next, a configuration example of the row decoder module 15 included in the peripheral circuit PERI will be described.

[0049] The overall configuration of the row decoder module 15 will be described with reference to FIG. 4. FIG. 4 is a circuit diagram for explaining an example of the configuration of the row decoder module, driver module, and memory cell array 10 of the semiconductor memory device according to the embodiment.

[0050] The row decoder module 15 includes row decoders RD0 to RDn. The row decoders RD0 to RDn are used for selecting the block BLK. The row decoders RD0 to RDn are respectively associated with the blocks BLK0 to BLKn.

[0051] Each row decoder RD includes, for example, a block decoder BD, and transfer transistors TW0 to TW7, TS, and TD0 to TD4. The transfer transistors TW0 to TW7, TS, and TD0 to TD4 are, for example, high-voltage-resistant N-channel type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The transfer transistors TW0 to TW7 are respectively associated with the word lines WL0 to WL7. In the following description, when the transfer transistors TW0 to TW7 are not distinguished, they are simply referred to as the transfer transistor TW. The transfer transistors TS and TD0 to TD4 are respectively associated with the select gate lines SGS and SGD0 to SGD4. In the following description, when the transfer transistors TD0 to TD4 are not distinguished, they are simply referred to as the transfer transistor TD. Also, a high-voltage-resistant MOSFET is a MOSFET having a physical film thickness of the gate insulating film of 10 nm or more. The voltage between the gate and source of the high-voltage-resistant N-channel type MOSFET can be, for example, 10 V or more.

[0052] The block decoder BD decodes the block address BA. The block decoder BD applies, for example, a voltage of "H (High)" level and a voltage of "L (Low)" level to the transfer gate line BLKSEL based on the result of the decoding. In this specification, the transfer gate line BLKSEL may sometimes be simply referred to as a control wiring.

[0053] Transfer transistors TW0 to TW7, TS, and TD0 to TD4 respectively connect the driver module 14 to the corresponding block BLK via signal lines CG0 to CG7, CGS, and CGD0 to CGD4. In the following description, when not distinguishing signal lines CG0 to CG7, CGS, and CGD0 to CGD4, they are simply referred to as signal line CG.

[0054] More specifically, in each row decoder RD, the gate of each transfer transistor TD is connected to the transfer gate line BLKSEL. The first end of each transfer transistor TD is connected to the driver module 14 via the corresponding signal line CG among signal lines CGD0 to CGD4. The second end of the transfer transistor TD is connected to the corresponding selection gate line SGD among selection gate lines SGD0 to SGD4.

[0055] The gate of each transfer transistor TW is connected to the transfer gate line BLKSEL. The first end of each transfer transistor TW is connected to the driver module 14 via the corresponding signal line CG among signal lines CG0 to CG7. The second end of each transfer transistor TW is connected to the corresponding word line WL among word lines WL0 to WL7.

[0056] The gate of the transfer transistor TS is connected to the transfer gate line BLKSEL. The first end of the transfer transistor TS is connected to the driver module 14 via the signal line CGS. The second end of the transfer transistor TS is connected to the selection gate line SGS.

[0057] When a voltage of "H" level is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD are turned on. As a result, the voltages of each signal line CG0 to CG7, CGS, and CGD0 to CGD4 are transferred to the word lines WL0 to WL7, the selection gate line SGS, and the selection gate lines SGD0 to SGD4 via the transfer transistors TW0 to TW7, TS, and TD0 to TD4 respectively. When a voltage of "L" level is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD are turned off.

[0058] (Basic Configuration of Block Decoder BD) The configuration of a plurality of block decoders BD included in each row decoder RD will be described with reference to FIG. 5. FIG. 5 is a circuit diagram showing the basic configuration of the block decoder BD included in the semiconductor memory device according to the embodiment.

[0059] As shown in FIG. 5, the block decoder BD includes a logic circuit LC, an AND circuit, inverters INV1 and INV2, and transistors T1, T2, T3, and T4. Transistors T1, T2, and T4 are, for example, N-channel MOSFETs. Transistor T3 is, for example, a P-channel MOSFET. Transistors T2, T3, and T4 are high-voltage MOSFETs having a thicker physical film thickness of the gate insulating film than that of transistor T1. The physical film thickness of the gate insulating film of each of transistors T2, T3, and T4 is, for example, 10 nm or more. Also, the gate-source voltage of each of transistors T2, T3, and T4 can be, for example, a voltage of 10 V or more. On the other hand, the physical film thickness of the gate insulating film of transistor T1 is, for example, thinner than 10 nm. Also, the gate-source voltage of transistor T1 is, for example, a voltage lower than 10 V. In this specification, transistor T4 may be referred to as the second transistor, transistor T3 may be referred to as the third transistor, and transistor T2 may be referred to as the fourth transistor. Also, the transistors TD0 to TD4, TW0 to TW7, and TS in FIG. 4 may be collectively referred to as the first transistor.

[0060] The block address BA is input from the address register 12 to the first input section of the logic circuit LC. For example, the power supply voltage VDD is applied to the second input section of the logic circuit LC. The logic circuit LC is driven by the power supply voltage VDD. A signal based on the block address BA is output from the output section of the logic circuit LC. When the block address BA input to the logic circuit LC is the block address BA assigned to the block BLK corresponding to the logic circuit LC, a signal at the "H" level is output from the output section of the logic circuit LC. When the block address BA input to the logic circuit LC is not the block address BA assigned to the block BLK corresponding to the logic circuit LC, a signal at the "L" level is output from the output section of the logic circuit LC.

[0061] The first input section of the AND circuit is connected to the first output section of the logic circuit LC. For example, the power supply voltage VDD is applied to the second input section of the AND circuit. The AND circuit is driven by the power supply voltage VDD. A signal based on the logical product operation of the signal output from the output section of the logic circuit LC is output from the output section of the AND circuit.

[0062] The first input section of the inverter INV1 is connected to the output section of the AND circuit. For example, the power supply voltage VDD is applied to the second input section of the inverter INV1. The inverter INV1 is driven by the power supply voltage VDD. The output section of the inverter INV1 is connected to the node N1. An inverted signal of the signal output from the output section of the AND circuit is output from the output section of the inverter INV1.

[0063] The first input section of the inverter INV2 is connected to the node N1. For example, the power supply voltage VDD is applied to the second input section of the inverter INV2. The inverter INV2 is driven by the power supply voltage VDD. An inverted signal of the signal output from the output section of the inverter INV1 is output from the output section of the inverter INV2.

[0064] The first terminal (e.g., drain) of transistor T1 is connected to the output of inverter INV2. The power supply voltage VDD is applied to the gate of transistor T1. The second terminal (e.g., source) of transistor T1 is connected to the first terminal (e.g., drain) of transistor T2.

[0065] The first terminal of transistor T2 is connected to the second terminal (e.g., source) of transistor T1. The power supply voltage VDD is applied to the gate of transistor T2. The second terminal of transistor T2 is connected to the transfer gate line BLKSEL.

[0066] The first terminal (e.g., drain) of transistor T3 is connected to the transfer gate line BLKSEL. The gate of transistor T3 is connected to node N1. The second terminal (e.g., source) of transistor T3 is connected to transistor T4 together with the back gate of transistor T3.

[0067] The first terminal (e.g., source) of transistor T4 is connected to the second terminal of transistor T3 and the back gate of transistor T3. The gate of transistor T4 is connected to the transfer gate line BLKSEL. A voltage VRDEC is applied to the second terminal (e.g., drain) of transistor T4. A high voltage is applied to the second terminal of transistor T4, which can transfer the voltage supplied to the transfer gate line BLKSEL through transistors T3 and T4 to the word line WL, the select gate line SGS, and the select gate line SGD so that the voltages supplied to the corresponding signal lines CG can be transferred.

[0068] Transistor T4 switches whether to boost the voltage of the gate connected to the transfer gate line BLKSEL according to the voltage VRDEC used to boost the transfer gate line BLKSEL. Transistor T3 turns on when boosting the transfer gate line BLKSEL and turns off otherwise. Transistor T2 sets the selected transfer gate line BLKSEL to a high level. Transistor T2 turns on or off in conjunction with transistor T3.

[0069] With the above configuration, when the corresponding block BLK is selected, the block decoder BD outputs a signal of "H" level to the transfer gate line BLKSEL. When the corresponding block BLK is not selected, the block decoder BD outputs a signal of "L" level to the transfer gate line BLKSEL.

[0070] As shown in FIGS. 1 and 4, each row decoder RD in the row decoder module 15 has a plurality of block decoders BD, and each block decoder BD is associated with one of the blocks. As shown in FIG. 5, each block decoder BD switches and controls the on or off of the corresponding transfer transistors TW0 to TW7, TS, and TD0 to TD4 at the corresponding transfer gate line BLKSEL. In this specification, the transfer transistors TW0 to TW7, TS, and TD0 to TD4 may be collectively referred to as a switch circuit group or a word line switch (fourth transistor) WLSW. Each row decoder RD has a plurality of switch circuit groups (word line switches) WLSW corresponding to a plurality of block decoders BD.

[0071] (First Embodiment) The semiconductor device according to the first embodiment has a block decoder BD with a configuration different from that of the block decoder BD in FIG. 5. FIG. 6 is a circuit diagram of the main part of the block decoder BD according to the first embodiment. In FIG. 6, the components common to FIG. 5 are denoted by the same reference numerals, and the differences will be mainly described below. The block decoder BD according to the first embodiment has the same logic circuit LC, AND circuit, inverters INV1 and INV2, and transistor T1 as in FIG. 5, but they are omitted in FIG. 6.

[0072] As shown in FIG. 6, the block decoder BD according to the first embodiment controls the voltage of the transfer gate line BLKSEL using the first voltage VRDEC generated by the driver module 14 or the like. The block decoder BD according to the first embodiment has capacitors Ca1 and a rectifier circuit 4 in addition to transistors T1 to T4.

[0073] The capacitor Ca1 boosts the transfer gate line BLKSEL by capacitive coupling. The capacitor Ca1 can apply various forms such as a MOS capacitor or a capacitance between wirings as will be described later. Also, the capacitance between wirings can be configured by, for example, MIM (Metal Insulator Metal), or MOM (Metal Oxide Metal), etc.

[0074] The rectifier circuit 4 prevents the current due to the boosted voltage of the transfer gate line BLKSEL from flowing backward between the drain and source of the transistor T3. The rectifier circuit 4 is composed of one or more diodes. Note that the diode may be configured by short-circuiting the drain and gate of a MOS transistor. In the first embodiment, an example in which the rectifier circuit 4 is composed of two diodes (first diode, second diode) DD1, DD2 connected in series will be described. The anode of the diode DD1 is connected to the drain of the transistor T3. The cathode of the diode DD1 is connected to the anode of the diode DD2. The cathode of the diode DD2 is connected to the transfer gate line BLKSEL.

[0075] The transfer gate line BLKSEL is set to a voltage level corresponding to the voltage at one end of the capacitor Ca1. A second voltage Vz whose voltage level can be varied is applied to one end of the capacitor Ca1. The second voltage Vz is generated at the driver module 14 or other locations. The other end of the capacitor Ca1 is connected to an intermediate node Va that connects the cathode of the diode DD1 and the anode of the diode DD2.

[0076] FIG. 7 is a cross-sectional view when the capacitor Ca1 is composed of MOS capacitors. In an N-type well region 6 disposed on a P-type silicon substrate 5, two diffusion regions 7a and 7b connected to one end of the capacitor Ca1 are disposed. Above between these two diffusion regions 7a and 7b, a gate electrode layer 9 connected to the other end of the capacitor Ca1 is disposed via a gate insulating film 8. The gate electrode layer 9 may be made of a metal material or polysilicon. The thickness of the gate insulating film 8 is arbitrary. Transistors T2 to T4 in the block decoder BD are high breakdown voltage transistors, and the gate insulating film 8 is made thicker than that of the low breakdown voltage transistor T1. The gate insulating film 8 of the MOS capacitor Ca1 shown in FIG. 7 may be the same as that of the high breakdown voltage transistors T2 to T4, or may be the same as that of the low breakdown voltage transistor T1. By adjusting at least one of the film thickness or the material of the gate insulating film 8, the capacitance of the capacitor Ca1 can be adjusted. Thus, the gate insulating film 8 of the MOS capacitor Ca1 has a film thickness, for example, equal to or less than that of transistors T1 to T3.

[0077] FIG. 8 is a diagram showing voltage changes in the second voltage Vz and the transfer gate line BLKSEL. FIG. 8 shows the voltage waveforms of the second voltage Vz, the voltage of the intermediate node Va between the diodes DD1 and DD2, and the voltage Vy of the transfer gate line BLKSEL.

[0078] At time t1, the transistor T1 is turned on, and the selected transfer gate line BLKSEL becomes high level. The voltage of the transfer gate line BLKSEL at this time becomes Vpgmh - 2Vfb. Vpgmh is the voltage VRDEC externally supplied to the transistor T4 in the block decoder BD. Since two diodes DD1 and DD2 are connected between the gate of the transistor T4 and the transfer gate line BLKSEL, the transfer gate line BLKSEL has a voltage level (Vpgmh - Vfb) obtained by subtracting the forward voltage Vfb of these diodes DD2 from the voltage Vpgmh. Thus, the intermediate node Va has a voltage higher than that of the transfer gate line BLKSEL by the forward voltage Vfb of the diode DD2.

[0079] At time t2, when the second voltage Vz is pulled up, due to the capacitive coupling of capacitor Ca1, the voltage of the intermediate node Va is pulled up to Vpgmh + α. At this time, the voltage of the transfer gate line BLKSEL becomes a voltage (Vpgmh + α - Vfb) that is lower than the voltage of the intermediate node Va, Vpgmh + α, by the forward voltage Vfb.

[0080] Thereafter, when the second voltage Vz is pulled down at time t3, due to the capacitive coupling of capacitor Ca1, the voltage of the intermediate node Va is also pulled down. The voltage of the intermediate node Va becomes a voltage that is lower than the voltage Vpgmh supplied externally to transistor T4 by Vfb. At this time, the voltage Vy of the transfer gate line BLKSEL becomes a voltage that is lower than the voltage of the intermediate node Va by the forward voltage Vfb.

[0081] Thereafter, when the second voltage Vz is pulled up at time t4, similar to time t2, as the voltage of the intermediate node Va is pulled up, the voltage of the transfer gate line BLKSEL is pulled up to (Vpgmh + α - Vfb).

[0082] For example, assuming the forward voltage Vfb of diodes DD1 and DD2 is 0.8V, the transfer gate line BLKSEL can be boosted to a voltage that is 0.8V lower than the voltage increase of the intermediate node Va due to the capacitive coupling of capacitor Ca1.

[0083] In this way, by periodically raising and lowering the voltage level of the second voltage Vz applied to one end of capacitor Ca1, the voltage level of the transfer gate line BLKSEL can be periodically boosted.

[0084] FIG. 9 is a diagram showing the on-current characteristics of transfer transistors TW0 to TW7, TS, and TD0 to TD4 according to the first embodiment. The horizontal axis in FIG. 9 is the gate voltage [V] of each transfer transistor (word line switch), and the vertical axis is the on-current [A]. In FIG. 9, three curves w1, w2, and w3 showing the on-current characteristics when the substrate bias voltage Vbs of each transfer transistor TW0 to TW7, TS, and TD0 to TD4 is changed in three ways (around Vbs = -10V, around -15V, around -20V) are shown. Regardless of the substrate bias voltage Vbs, the on-current tends to increase as the gate voltage supplied by the transfer gate line BLK increases. For example, when the substrate bias voltage Vbs is around -20V, if the second voltage Vz is raised from Vpgmh to Vpgmh + α, the on-current moves from plot p1 to plot p2 in FIG. 9. Thus, the on-current can be increased by raising the second voltage Vz.

[0085] FIG. 10 is a plan view and a cross-sectional view showing the structures of diodes DD1 and DD2. Each of the diodes DD1 and DD2 is formed, for example, by joining a P-type diffusion region 42 and an N-type diffusion region 43 disposed in an N-well region 41 on a P-Si substrate 40. In the example of FIG. 10, the N-type diffusion region 43 is disposed so as to surround the periphery of the P-type diffusion region 42. An anode electrode is connected to the P-type diffusion region 42, and a cathode electrode is connected to the N-type diffusion region 43.

[0086] The diodes DD1 and DD2 may have a structure in which the drain and gate of the MOS transistor are short-circuited. FIG. 11 is a cross-sectional view when the diodes DD1 and DD2 are composed of MOS transistors. In this case, the gate 46g and the drain 46d of the MOS transistor 46 disposed in the N-well region 45 on the P-type substrate 44 are short-circuited. FIG. 11 shows the cross-sectional structure of the diode DD2. A voltage Va is applied to the short-circuited gate 46g and drain 46d. Since the source 46s is connected to the transfer gate line BLKSEL, the voltage becomes Vy. A capacitor Ca1 having the gate insulating film 47 of the MOS transistor 46 as a dielectric layer is disposed. One electrode 48 of the capacitor Ca1 is connected to the P-type diffusion region 49 disposed in the vicinity of the MOS transistor 46. A voltage Vz is applied to this electrode 48. The other electrode 50 of the capacitor Ca1 is connected to the gate 46g and the drain 46d of the diode-connected MOS transistor 46.

[0087] FIG. 12 is a circuit diagram of the block decoder BD according to the first modification of the first embodiment. The semiconductor device according to the first modification shown in FIG. 12 is characterized in that the capacitor Ca1 of the block decoder BD in FIG. 6 is replaced with two capacitors Ca1a and Ca1b connected in parallel. By connecting two capacitors Ca1a and Ca1b in parallel between the node to which the second voltage Vz is applied and the intermediate node Va, it becomes difficult for the individual capacitors Ca1a and Ca1b to cause dielectric breakdown. Also, compared with FIG. 6, the area of each of the capacitors Ca1a and Ca1b can be reduced.

[0088] FIG. 13 is a cross-sectional view of two capacitors Ca1a and Ca1b included in a block decoder BD according to a first modification example. An IPD (Inter-Poly Dielectric) film 57 is disposed via a first conductive layer 56 on a gate insulating film 55 disposed on an N-well region 54 on a P-Si substrate 53, and a second conductive layer 58 is disposed thereon. The first conductive layer 56 and the second conductive layer 58 may be polysilicon layers or metal layers. By sandwiching the IPD film 57 between the first conductive layer 56 and the second conductive layer 58, a first capacitor Ca1 is formed. Further, by sandwiching the gate insulating film 55 between the second conductive layer 58 and a source / drain diffusion layer 59, a second capacitor Ca1 connected in parallel to the first capacitor Ca1 is formed.

[0089] FIG. 14 is a circuit diagram of a block decoder BD according to a second modification example of the first embodiment. The semiconductor device according to the second modification example shown in FIG. 14 is characterized in that three or more capacitors Ca1 are connected in parallel between a node to which a second voltage Vz is applied and an intermediate node Va. Thereby, as compared with FIG. 12, it becomes difficult for each capacitor Ca1 to cause dielectric breakdown.

[0090] In FIG. 14, three or more capacitors Ca1 are connected in parallel between a wiring to which the second voltage Vz is applied and a wiring of the intermediate node Va.

[0091] FIG. 15 is a cross-sectional view of the capacitor Ca1 according to the second modification. The capacitor Ca1 according to the second modification is disposed in the wiring layer region WR shown in FIG. 3. In the wiring layer region WR, wiring layers D0 and D1 are laminated. For example, in the wiring layer D1, a wiring layer D1a to which a voltage Vy is applied and a wiring layer D1b to which a second voltage Vz is applied are alternately arranged. The wiring layer D1a to which the voltage Vy is applied is a wiring layer connected to the transfer gate line BLKSEL. The capacitor Ca1 is disposed between the wiring layer D1a to which the voltage Vy is applied and the wiring layer D1b to which the second voltage Vz is applied, which are adjacent to each other in the substrate surface direction. In this way, by connecting the capacitor Ca1 between two adjacent wiring layers D1a and D1b in the substrate surface direction, the number of capacitors Ca1 can be increased with a small area, and dielectric breakdown of each capacitor Ca1 can be prevented.

[0092] FIG. 15 shows an example in which a plurality of transfer transistors 63 are arranged in a P-type well region 62 disposed in a part of an N-type well region 61 disposed on a P-type silicon substrate 60. Two transfer transistors 63 adjacent to each other in the substrate surface direction share a drain region 63d or a source region 63s. Each of the drain regions 63d and source regions 63s of each transfer transistor 63 is connected to a separate electrode provided in the wiring layer D0 via a contact 64.

[0093] Thus, in the block decoder BD according to the first embodiment, the second voltage Vz whose voltage level changes periodically is applied to one end of the capacitor Ca1, and the other end of the capacitor Ca1 is connected to the intermediate node Va of two diodes DD1 and DD2 connected in series between the drain of the transistor T3 and the transfer gate line BLKSEL. Thereby, the voltage level of the transfer gate line BLKSEL can be periodically increased by the capacitive coupling of the capacitor Ca1. Therefore, the voltage level of the transfer gate line BLKSEL can be boosted in accordance with the timing of writing data to the NAND string.

[0094] According to this embodiment, since the periodic boosting operation of the transfer gate line BLKSEL can be performed only by the capacitor Ca1, the circuit configuration of the block decoder BD can be simplified. Also, since boosting is performed by capacitive coupling, the voltage level of the transfer gate line BLKSEL can be switched quickly with low power consumption.

[0095] Also, since the diodes DD1 and DD2 are connected between the drain of the transistor T3 and the transfer gate line BLKSEL, even when the transfer gate line BLKSEL is boosted, there is no risk of current flowing from the transfer gate line BLKSEL to the drain of the transistor T3, and the operation during boosting of the transfer gate line BLKSEL can be stabilized.

[0096] (Second Embodiment) FIG. 16 is a circuit diagram of the block decoder BD according to the second embodiment. In FIG. 16, the components common to FIG. 6 are denoted by the same reference numerals, and the differences will be mainly described below.

[0097] The block decoder BD according to the second embodiment shown in FIG. 16 includes a capacitor Ca2 connected at a different location from that in FIG. 6. Also, the block decoder BD according to the second embodiment is different from FIG. 6 in that one diode DD1 is connected between the drain of the transistor T3 and the transfer gate line BLKSEL.

[0098] The block decoder BD according to the second embodiment includes a capacitor Ca2 connected to the gate of the transfer transistor 63. A second voltage Vz is applied to one end CG2 of the capacitor Ca2, and the other end CG1 of the capacitor Ca2 is connected to the gate of the transfer transistor 63. As shown in FIG. 4, the transfer gate line BLKSEL is connected to the gates of a plurality of transfer transistors 63. The above-described capacitor Ca2 is separately connected to each of the gates of the plurality of transfer transistors 63. That is, the capacitor Ca2 is provided for each of the plurality of transfer transistors 63. The plurality of transfer transistors are more specifically the transfer transistors TW0 to TW7, TS, and TD0 to TD4, etc.

[0099] Figure 17 is a cross-sectional view of the capacitor Ca2 included in the block decoder BD according to the second embodiment. Figure 17 shows a cross-sectional view of the transfer transistor 63 having a gate to which the other end of the capacitor Ca2 is connected. The transfer transistor 63 is provided in a plurality of P-type well regions 62 arranged in a part of the N-type well region 61 on the P-type silicon substrate 60. A gate insulating film 65 is disposed on the P-type well region 62, and a first polysilicon layer 66 is disposed thereon. An IPD film 67 is disposed on the first polysilicon layer 66, and a second polysilicon layer 68 is disposed thereon.

[0100] The capacitor Ca2 has a structure in which the IPD film 67 is sandwiched between the first polysilicon layer 66 and the second polysilicon layer 68. The transfer transistor 63 uses the first polysilicon layer 66 as a gate. A gate electrode CG1 is connected to the first polysilicon layer 66. An electrode CG2 is connected to the second polysilicon layer 68. The gate electrode CG1 is connected to the transfer gate line BLKSEL, and a voltage Vy is applied thereto. A second voltage Vz is applied to the electrode CG2.

[0101] When the voltage level of the second voltage Vz is raised, the gate voltage CG1 of the transfer transistor 63 is raised by the capacitive coupling of the capacitor Ca2. Since the transfer gate line BLKSEL is connected to the gate of the transfer transistor 63, when the gate voltage of the transfer transistor 63 rises, the voltage Vy of the transfer gate line BLKSEL also rises. A diode is connected between the drain of the transistor T3 and the transfer gate line BLKSEL. Therefore, even when the voltage Vy of the transfer gate line BLKSEL rises, it is possible to prevent current from flowing from the transfer gate line BLKSEL to the drain of the transistor T3.

[0102] Figure 18 is a diagram showing changes in the voltage levels of the voltages CG1 and CG2 in Figure 17. As described above, the voltage CG1 is the voltage Vy of the transfer gate line BLKSEL. The voltage CG2 is the second voltage Vz applied to one end of the capacitor Ca2.

[0103] When the voltage level of the voltage CG2 (second voltage Vz) rises at time t1, the voltage level of the voltage CG1 (transfer gate line BLKSEL) also rises due to the capacitive coupling of the capacitor Ca2. Then, when the voltage level of the voltage CG1 further rises at time t2, the voltage level of the voltage CG1 also further rises due to the capacitive coupling of the capacitor Ca2.

[0104] FIG. 19 is a diagram showing the on-current characteristics of the transfer transistor 63 according to the second embodiment. The horizontal axis in FIG. 19 is the gate voltage [V] of each transfer transistor 63 (word line switch), and the vertical axis is the on-current [A]. In FIG. 19, curves w4, w5, and w6 showing the on-current characteristics when the substrate bias voltage Vbs of each transfer transistor TW0 to TW7, TS, and TD0 to TD4 is changed in three ways are illustrated. Regardless of the substrate bias voltage Vbs, the on-current tends to increase as the gate voltage increases. For example, when the substrate bias voltage Vbs = 24V, when the second voltage Vz is raised from Vpgmh to Vpgmh + α, the on-current surely increases as shown by the plot p4 from the plot p3 in FIG. 19.

[0105] Thus, in the second embodiment, by connecting the capacitor Ca2 to the gate of each transfer transistor 63 and raising the voltage CG1 (second voltage Vz) applied to one end of the capacitor Ca2, the gate voltage of each transfer transistor 63 can be quickly raised. Thereby, the voltage level of the transfer gate line BLKSEL can be boosted without complicating the configuration of the block decoder BD.

[0106] (Third Embodiment) In the first and second embodiments described above, the capacitive coupling of the capacitors Ca1 and Ca2 is used inside the block decoder BD to generate the boosted voltage for the transfer gate line BLKSEL, whereas the third embodiment is characterized in that the boosted voltage is generated on the front stage side of the row decoder RD incorporating the block decoder BD.

[0107] FIG. 20 is a block diagram showing the configuration on the transmission path of the voltage VRDEC supplied to each block decoder BD. On the above-described transmission path, a voltage supply circuit (first booster circuit) 71, a first multiplexer 72, a second multiplexer 73, a local charge pump (second booster circuit) 74, and a row decoder module 15 are connected. The voltage supply circuit 71, the first multiplexer 72, the second multiplexer 73, the local charge pump 74, and the row decoder RD are built in, for example, the driver module 14.

[0108] The voltage supply circuit 71 generates a voltage of a predetermined voltage level. The first multiplexer 72 divides the voltage generated by the voltage supply circuit 71 into a plurality of lines. The second multiplexer 73 further divides each of the plurality of lines divided by the first multiplexer 72 into a plurality of lines. Each line divided by the second multiplexer 73 is, for example, for each block decoder BD.

[0109] The local charge pump 74 is provided, for example, for each row decoder module 15 in FIG. 4, and boosts the voltage VRDEC applied to the corresponding block decoder BD as necessary.

[0110] The block decoder BD according to the third embodiment is configured in the same manner as in FIG. 5. The local charge pump 74 generates the voltage VRDEC and supplies it to the corresponding block decoder BD. The local charge pump 74 raises the voltage level of the voltage VRDEC as necessary. Specifically, the voltage level of the voltage VRDEC is boosted during data writing. The voltage VRDEC generated by the local charge pump 74 is applied to the drain of the transistor T4 in FIG. 5. The block decoder BD supplies a voltage corresponding to the voltage VRDEC to the transfer gate line BLKSEL. Thus, since each block decoder BD according to the third embodiment does not have a booster circuit such as the block decoder BD according to the first and second embodiments, the circuit scale of the block decoder BD can be reduced compared to the first and second embodiments.

[0111] FIG. 21 is a diagram showing a path from the input of the second multiplexer 73 in FIG. 20 to the word lines for one control signal line CGN. Each row decoder RD in the row decoder module 15 has a plurality of switch circuit groups (word line switches) WLSW corresponding to each of the plurality of block decoders BD as described above.

[0112] As shown in FIG. 21, among the word lines of all blocks, the word lines located in the same layer are each connected to one control signal line CGI. The number of control signal lines CGI is the same as the number of word lines in one block BLK. The plurality of control signal lines CGI correspond to one control signal line CGN output from the first multiplexer 72. The second multiplexer 73 has a plurality of second multiplexer units 73a, and each of the plurality of second multiplexer units 73a selects whether to supply the voltage transmitted on one control signal line CGN to the control signal line CGI corresponding to any of the word lines.

[0113] FIG. 21 shows an example in which there are 9 control signal lines CGI and 9 blocks for one control signal line CGN, and 9×9 = 81 word lines WL. Typically, for several to several tens of control signal lines CGN, several tens to several hundreds of control signal lines CGI, several thousands of blocks, and tens of thousands or more word lines are provided. Therefore, the typical magnitude relationship of the number of control signal lines CGN, CGI, and word lines WL is CGN < CGI < WL. The same applies to the other control signal lines SGDN, SGDI, SGD, SGSN, SGSI, and SGS. For example, the number of the other control signal lines is SGDN < SGDI < SGD, and SGSN < SGSI < SGS. Hereinafter, the control signal lines CGN, SGDN, and SGSN are collectively referred to as control signal lines GN.

[0114] FIG. 22 is a diagram showing a wiring path from the voltage supply circuit 71 to the low decoder module 15. For a plurality of control signal lines GN, numbers are attached after GN for distinction. In FIG. 22, an example having eight control signal lines GN is shown, but the number of control signal lines GN is arbitrary.

[0115] The second multiplexer 73 has a switch group SW10 to SW17 including a plurality of switches. Each of the switch groups SW10 to SW17 has the same configuration. A control signal line GN0 is commonly connected to the input end of each switch of the switch group SW10. The output ends of the switches of the switch group SW10 are connected to the control signal lines SGDI, CGI, and SGSI, respectively. The switch group SW10 determines whether to supply the voltage supplied via the control signal line GN0 to any of the control signal lines. For example, when the read voltage VCGRV is transmitted by the control signal line GN0, each switch of the switch group SW10 is controlled to supply the read voltage VCGRV to the control signal line CGI corresponding to the word line WL to be read.

[0116] Similarly, as shown in FIG. 22, the input ends of the switches of the switch groups SW10 to SW17 are connected to the control signal lines GN0 to GN7, respectively. Also, as shown in FIG. 22, the output ends of the switch groups SW10 to SW17 are connected to the control signal lines SGDI, CGI, and SGSI.

[0117] The switch groups SW10 to SW17 are each controlled such that the voltage transmitted by the control signal lines GN0 to GN7 is supplied to the control signal lines SGDI, CGI, and SGSI corresponding to the control signal lines SGD, WL, and SGS in the memory cell array 10 to be supplied. Thus, voltages corresponding to the respective control signal lines SGDI, SGSI, and CGI are supplied from the second multiplexer 73. For example, during a write operation, each switch of the switch group through which the voltage VPASS is transmitted by the control signal line GN is controlled to supply the voltage VPASS to a plurality of control signal lines CGI corresponding to non-selected word lines.

[0118] FIG. 23 is a block diagram showing the connection relationship between the voltage supply circuit 71 and the local charge pump 74. The voltage supply circuit 71 includes a main charge pump 75, a first voltage generation unit 76, and a second voltage generation unit 77.

[0119] The main charge pump 75 generates a voltage VPGMH supplied to a plurality of first voltage generation units 76 and a plurality of second voltage generation units 77, and a voltage VPGM supplied to the first multiplexer 72.

[0120] The first voltage generation unit 76 and the second voltage generation unit 77 are provided for each row decoder module 15, that is, in association with a plurality of block decoders BD in the row decoder module 15. That is, each of the plurality of first voltage generation units 76 generates a voltage VRDEC_PB for the corresponding block decoder BD. Similarly, each of the plurality of second voltage generation units 77 generates a voltage VRDEC_HVSW for the corresponding block decoder BD. The voltage VRDEC_VSW generated by each of the plurality of second voltage generation units 77 is input to the gates of the transistors included in the first multiplexer 72 and the second multiplexer 73.

[0121] The local charge pump 74 generates a voltage VRDEC for boosting the transfer gate line of the corresponding block decoder BD using the voltage VRDEC_PB generated by the first voltage generation unit 76.

[0122] FIG. 24 is a circuit diagram showing an example of the internal configuration of the local charge pump 74. As shown in FIG. 24, the local charge pump 74 includes first to fourth transistors Q1 to Q4, and first and second capacitors Ca11 and C12. The first to fourth transistors Q1 to Q4 are all NMOS transistors. The drain of the first transistor Q1 and the drain of the third transistor Q3 are connected to the input voltage node VIN. The source of the first transistor Q1 is connected to the drain of the second transistor Q2, and the source of the second transistor Q2 is connected to the output voltage node VOUT. The source of the third transistor Q3 is connected to the drain of the fourth transistor Q4, and the source of the fourth transistor Q4 is connected to the output voltage node VOUT. The gate of the first transistor Q1 is connected to the source of the third transistor Q3 and the drain of the fourth transistor Q4. The gate of the fourth transistor Q3 is connected to the source of the first transistor Q1 and the drain of the second transistor Q2. The inverted clock signal KLC is input to the first electrode of the first capacitor Ca11, and the gate of the third transistor Q3, the source of the first transistor Q1, and the drain of the second transistor Q2 are connected to the second electrode of the first capacitor Ca11. The clock signal CLK is input to the first electrode of the second capacitor Ca12, and the gate of the first transistor Q1, the source of the third transistor Q3, and the drain of the fourth transistor Q4 are connected to the second electrode of the second capacitor Ca11. The voltage VRDEC_PB generated by the first voltage generation unit 76 is applied to the input voltage node VIN.

[0123] Note that FIG. 24 shows only an example of the internal configuration of the local charge pump 74. The local charge pump 74 may have an internal configuration different from that shown in FIG. 24.

[0124] FIG. 25 is a voltage waveform diagram of signals input to and output from the local charge pump 74. In FIG. 25, there are shown the voltage waveforms of the clock signal CLK, the inverted clock signal KLC, the voltage VRDEC_PB input to the input voltage node, the voltage NN1 of the second electrode of the first capacitor Ca11, the voltage NN2 of the second electrode of the second capacitor Ca11, and the voltage VOUT output from the output voltage node. As shown in FIG. 25, as the number of clocks of the clock signal CLK increases, the voltage VOUT gradually rises.

[0125] FIG. 26 is a voltage waveform diagram of the block decoder BD according to the third embodiment. In FIG. 26, there are shown the voltage waveform w1 when the voltage of the transfer gate line BLKSEL in the block decoder BD of FIG. 23 is boosted by the local charge pump 74, the voltage waveform w2 when it is not boosted, and the voltage waveforms of the word lines connected to the word line switch WLSW after boosting w3a, w3b and before boosting w4a, w4b. The voltage waveforms w3a, w4a show the voltage waveforms of the word lines located near the block decoder BD, and the voltage waveforms w3b, w4b show the voltage waveforms of the word lines located far from the block decoder BD.

[0126] As shown in FIG. 26, when the voltage VRDEC is boosted by the local charge pump 74 of FIG. 23, the voltage of the transfer gate line BLKSEL in the block decoder is boosted by about 1 volt, and the voltage level of the word line is also boosted.

[0127] Thus, in the third embodiment, since the local charge pump 74 for boosting the voltage supplied to each block decoder BD in the row decoder module 15 is provided on the front stage side of the row decoder module 15, the overall circuit size of the semiconductor memory device can be reduced without providing an additional boosting function to each block decoder BD.

[0128] [Appendix] [Item 1] The control wiring connected to the gate of the first transistor, A second transistor having a first terminal and a second terminal that are respectively a source or a drain, and a first gate to which the control wiring is connected, wherein a first voltage for turning on the first transistor is input to the first terminal, A third transistor having a third terminal and a fourth terminal that are respectively a source or a drain, and a second gate, wherein the third terminal is connected to the second terminal, the fourth terminal controls the voltage of the control wiring, and is turned on by a first control signal input to the second gate when the first transistor is turned on, A fourth transistor having a fifth terminal and a sixth terminal that are respectively a source or a drain, and a third gate, wherein the fourth transistor is turned on by a second control signal input to the third gate when the third transistor is turned on, and is turned off by the second control signal input to the third gate when the third transistor is turned off, A capacitor that boosts a second voltage output from the fourth terminal to a third voltage higher than the second voltage by capacitive coupling and supplies the boosted voltage to the control wiring in a state where the first transistor and the second transistor are turned on. A semiconductor device. [Item 2] The semiconductor device according to item 1, further comprising a rectifying circuit that prevents current due to the boosted voltage of the control wiring from flowing between the drain and the source of the third transistor. The semiconductor device according to item 1. [Item 3] The second transistor and the fourth transistor are N-type MOS (Metal Oxide Semiconductor) transistors, The third transistor is a P-type MOS transistor, The rectifying circuit is disposed between the drain of the P-type MOS transistor and the control wiring. The semiconductor device according to item 2. [Item 4] The rectifying circuit is a diode having an anode connected to the drain of the third transistor and a cathode connected to the control wiring, or a MOS transistor connected in a diode configuration. The semiconductor device according to item 2 or 3. [Item 5] The rectifier circuit has a first diode and a second diode connected in series between the drain of the third transistor and the control wiring. The capacitor boosts the voltage level of an intermediate node to which the cathode of the first diode and the anode of the second diode are connected by capacitive coupling. The semiconductor device according to item 4. [Item 6] One end of the capacitor is connected to the intermediate node. A second voltage whose voltage level can be varied is applied to the other end of the capacitor. The semiconductor device according to item 5. [Item 7] The control wiring has a voltage level corresponding to the voltage at one end of the capacitor. A second voltage whose voltage level can be varied is applied to one end of the capacitor. The semiconductor device according to any one of items 1 to 6. [Item 8] The second voltage is a clock signal whose voltage level changes periodically. The control wiring is repeatedly boosted in synchronization with the period of the clock signal. The semiconductor device according to item 7. [Item 9] A plurality of the capacitors are provided in parallel between the control wiring and the application node of the second voltage. The semiconductor device according to item 7 or 8. [Item 10] The capacitor is a MOS capacitor having a gate insulating film with a film thickness equal to or less than the film thickness of the gate insulating films of the second to fourth transistors. The semiconductor device according to any one of items 1 to 9. [Item 11] The control wiring includes a plurality of fifth transistors connected to respective gates. Each of the plurality of fifth transistors allows a larger on-current to flow between the drain and the source when the control wiring is boosted than when it is not boosted. The semiconductor device according to any one of Items 1 to 10. [Item 12] A fifth transistor in which the control wiring is connected to the gate; A dielectric layer and a conductive layer laminated on the gate of the fifth transistor. The capacitor includes the gate of the fifth transistor, the dielectric layer, and the conductive layer. A second voltage with a variable voltage level is applied to the conductive layer. The gate voltage of the fifth transistor is variably controlled by the capacitive coupling of the capacitor. The semiconductor device according to any one of Items 1 to 4. [Item 13] A decoder that selects a control wiring to be boosted from among a plurality of control wirings; For each of the plurality of control wirings, the decoder includes the second transistor, the third transistor, the fourth transistor, and the capacitor. The semiconductor device according to any one of Items 1 to 12. [Item 14] A plurality of memory strings each having a plurality of memory cell transistors and control transistors connected in series; A plurality of first wirings respectively connected to the gates of the plurality of memory cell transistors and control transistors; A plurality of transfer transistors that switch whether to drive the plurality of first wirings; The decoder switches whether to drive each gate line of the plurality of transfer transistors in the selected memory string as the control wiring. The semiconductor device according to Item 13. [Item 15] A voltage supply circuit that generates a first voltage commonly used to boost a plurality of control wirings; A boost circuit provided corresponding to the plurality of control wirings, and generating a second voltage higher than the first voltage based on the first voltage; A plurality of decoders for controlling whether to boost the corresponding control wiring based on the second voltage; and the semiconductor device includes the boost circuit and the plurality of decoders. Semiconductor device. [Item 16] A plurality of memory strings each having a plurality of memory cell transistors and control transistors connected in series; A memory cell array for erasing data for each of a plurality of blocks each having the plurality of memory strings; and the semiconductor device includes the memory cell array and the plurality of memory strings. The plurality of decoders are provided corresponding to the plurality of blocks. The semiconductor device according to Item 15. [Item 17] Each of the plurality of decoders A first transistor for switching whether to boost the voltage of a gate connected to the corresponding control wiring according to the corresponding second voltage; A second transistor that turns on when boosting the corresponding control wiring; A third transistor that turns off when boosting the corresponding control wiring; and the semiconductor device includes the first transistor, the second transistor, and the third transistor. The semiconductor device according to Item 16. [Item 18] The first transistor, the second transistor, and the third transistor are high-voltage transistors. The semiconductor device according to any one of Items 1 to 14 or 17. Aspects of the present disclosure are not limited to the individual embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described content. That is, various additions, changes, and partial deletions are possible without departing from the conceptual ideas and spirits of the present disclosure derived from the content defined in the claims and their equivalents.

Description of Reference Numerals

[0129] 1 Semiconductor memory device, 2 Memory controller, 3 Memory system, 4 Rectifier circuit, 5 P-type silicon substrate, 6 N-type well region, 7a Diffusion region, 7b Diffusion region, 8 Gate insulating film, 9 Gate electrode layer, 10 Memory cell array, 11 Command register, 12 Address register, 13 Sequencer, 14 Driver module, 15 Row decoder module, 16 Sense amplifier module, 20 Semiconductor substrate, 21 - 25 Conductor layers, 26 Semiconductor part, 27 - 29 Conductor layers, 28 Conductor layer, 29 Conductor layer, 31 - 34 Insulator layers, 35 Core member, 36 Semiconductor film, 37 Tunnel insulating film, 38 Charge storage film, 39 Block insulating film, 40 P-Si substrate, 41 N well region, 42 P-type diffusion region, 43 N-type diffusion region, 44 P-type substrate, 45 N well region, 46 MOS transistor, 46d Drain, 46g Gate, 46s Source, 47 Gate insulating film, 48 Electrode, 49 P-type diffusion region, 50 Electrode, 53 P-Si substrate, 54 N well region, 55 Gate insulating film, 56 First conductive layer, 57 IPD film, 58 Second conductive layer, 59 Drain diffusion layer, 60 P-type silicon substrate, 61 N-type well region, 62 P-type well region, 63 Transfer transistor, 63d Drain region, 63s Source region, 64 Contact, 65 Gate insulating film, 66 First polysilicon layer, 67 IPD film, 68 Second polysilicon layer, 71 Voltage supply circuit, 72 First multiplexer, 73 Second multiplexer, 73a Second multiplexer part, 74 Local charge pump, 75 Main charge pump, 76 First voltage generation unit, 77 Second voltage generation unit

Claims

1. A control wiring connected to the gate of the first transistor, a first terminal and a second terminal each being a source or a drain, and a first gate to which the control wiring is connected, wherein a first voltage for turning on the first transistor is input to the first terminal, a second transistor; a third terminal and a fourth terminal each being a source or a drain, and a second gate, wherein the third terminal is connected to the second terminal, the fourth terminal controls the voltage of the control wiring, and a third transistor that is turned on by a first control signal input to the second gate when the first transistor is turned on; a fifth terminal and a sixth terminal each being a source or a drain, and a third gate, wherein the third transistor is turned on by a second control signal input to the third gate when the third transistor is turned on, and is turned off by the second control signal input to the third gate when the third transistor is turned off, a fourth transistor; a capacitor that boosts a second voltage output from the fourth terminal in a state where the first transistor and the second transistor are turned on to a third voltage higher than the second voltage by capacitive coupling and supplies the boosted voltage to the control wiring. A semiconductor device.

2. A semiconductor device according to claim 1, further comprising a rectifying circuit that prevents a current due to the boosted voltage of the control wiring from flowing between the drain and the source of the third transistor. The semiconductor device according to claim 1.

3. The second transistor and the fourth transistor are N-type MOS (Metal Oxide Semiconductor) transistors, the third transistor is a P-type MOS transistor, and the rectifying circuit is disposed between the drain of the P-type MOS transistor and the control wiring. The semiconductor device according to claim 2.

4. The semiconductor device according to claim 2, wherein the rectifying circuit is a diode having an anode connected to the drain of the third transistor and a cathode connected to the control wiring, or a MOS transistor connected in a diode configuration. The semiconductor device according to claim 2.

5. The rectifying circuit has a first diode and a second diode connected in series between the drain of the third transistor and the control wiring, and the capacitor boosts the voltage level of an intermediate node to which the cathode of the first diode and the anode of the second diode are connected by capacitive coupling. The semiconductor device according to claim 4.

6. One end of the capacitor is connected to the intermediate node, and a second voltage whose voltage level can be varied is applied to the other end of the capacitor. The semiconductor device according to claim 5.

7. The control wiring has a voltage level corresponding to the voltage at one end of the capacitor, and a second voltage whose voltage level can be varied is applied to one end of the capacitor. The semiconductor device according to claim 1.

8. The second voltage is a clock signal whose voltage level changes periodically, and the control wiring is repeatedly boosted in synchronization with the period of the clock signal. The semiconductor device according to claim 7.

9. A plurality of the capacitors are provided in parallel between the control wiring and the node to which the second voltage is applied. The semiconductor device according to claim 7.

10. The capacitor is a MOS capacitor having a gate insulating film with a film thickness equal to or less than the film thickness of the gate insulating films of the second to fourth transistors. The semiconductor device according to claim 1.

11. The semiconductor device includes a plurality of the first transistors to which the control wiring is connected to respective gates, and each of the plurality of the first transistors allows a larger on-current to flow between drain and source when the control wiring is boosted than when it is not boosted. The semiconductor device according to claim 1.

12. The semiconductor device includes a dielectric layer and a conductive layer laminated on the gate of the first transistor, the capacitor includes the gate of the first transistor, the dielectric layer, and the conductive layer, a second voltage whose voltage level can be varied is applied to the conductive layer, and the gate voltage of the first transistor is variably controlled by capacitive coupling of the capacitor. The semiconductor device according to claim 1.

13. The semiconductor device includes a decoder that selects a control wiring to be boosted from among a plurality of control wirings, and the decoder has the second transistor, the third transistor, the fourth transistor, and the capacitor for each of the plurality of control wirings. The semiconductor device according to claim 1.

14. a plurality of memory strings each having a plurality of memory cell transistors and control transistors connected in series, and a plurality of first wirings respectively connected to the gates of the plurality of memory cell transistors and control transistors. A plurality of transfer transistors that switch whether to drive the plurality of first wirings. The decoder switches whether to drive each gate line of the plurality of transfer transistors in the selected memory string as the control wiring. The semiconductor device according to claim 13.

15. A voltage supply circuit that generates a first voltage commonly used to boost a plurality of control wirings. A boosting circuit provided corresponding to the plurality of control wirings, which generates a second voltage higher than the first voltage based on the first voltage. A plurality of decoders that control whether to boost the corresponding control wiring based on the second voltage. Semiconductor device.

16. A plurality of memory strings each having a plurality of memory cell transistors and control transistors connected in series. A memory cell array that erases data for each of a plurality of blocks each having the plurality of memory strings. The plurality of decoders are provided in association with the plurality of blocks. The semiconductor device according to claim 15.

17. Each of the plurality of decoders A first transistor that switches whether to boost the voltage of a gate connected to the corresponding control wiring according to the corresponding second voltage. A second transistor that turns on when boosting the corresponding control wiring. A third transistor that turns off when boosting the corresponding control wiring. The semiconductor device according to claim 16.

18. The first transistor, the second transistor, and the third transistor are high breakdown voltage transistors. The semiconductor device according to claim 1.

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