Multilayer printed circuit board for interconnecting pin and semiconductor die and correspondent method for interconnection
The multilayer printed circuit board with integrated pin holders and die contacts addresses defects in pin interconnection by enhancing stability and reliability, leading to improved performance in vehicle power modules.
Patent Information
- Application Number
- JP2024230089
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-16
- Filing Date
- 2024-12-26
- Publication Date
- 2025-07-15
AI Technical Summary
Existing pin and pin holder interconnection methods in semiconductor dies, particularly in vehicle power modules, are prone to defects such as solder splashing, pin tilt deformation, and holder breakage, leading to poor product performance and unusable products.
A multilayer printed circuit board with embedded pin holders and die contacts, featuring interconnect structures and auxiliary connectors, which are integrated into the substrate layers to provide stable and secure connections between pins and semiconductor dies.
The solution enhances mechanical stability, reduces the risk of damage during insertion, and improves interconnection reliability, resulting in higher-quality power modules with reduced defects.
Smart Images
Figure 2025106226000001_ABST
Abstract
Description
Technical Field
[0001] (Cross - reference to related applications) This application is a translation of Chinese Patent Application No. 202311861348.5, filed on December 29, 2023, entitled "MULTILAYER PRINTED CIRCUIT BOARD FOR INTERCONNECTING PIN(S)AND SEMICONDUCTOR DIE(S)AND CORRESPONDING METHOD FOR INTERCONNECTION", and claims its priority, which is incorporated herein by reference in the broadest extent permitted by law.
[0002] (Field of the Invention) The present disclosure relates to the packaging of power modules, and more specifically, to a multilayer printed circuit board for interconnecting pins and semiconductor dies in the packaging process of power modules, and a corresponding method for interconnection.
Background Art
[0003] Pin interconnection is a common interconnection mode for connecting semiconductor dies (especially semiconductor dies applied to vehicle power modules) to general - purpose circuit boards (usually printed circuit boards), and plays a very important interconnection role in the final product. However, pins and pin holders are one of the most fragile parts in the final product. Different from wiring, pins and pin holders not only have to withstand the pushing - in / inserting force in the interconnection process, but also face various situations that may occur in the welding process, so they are very vulnerable to damage. The welding process of pins and pin holders is complex, and therefore, various defects often occur, including, for example, solder splashing, pin tilt deformation, holder deformation, holder breakage, etc.
[0004] In short, pins and pin holders are important and key components for interconnecting semiconductor dies, and any defect or damage to them will have an adverse effect on the final product. Therefore, it is urgent to propose a technical solution for interconnection that can avoid defects and failures of pins and pin holders.
[0005] Therefore, the present application proposes a multilayer printed circuit board for interconnecting pins and semiconductor dies, and a corresponding method for interconnection, which can solve the above problems.
Summary of the Invention
[0006] One of the objectives of the present disclosure is to provide an improved multilayer printed circuit board for interconnecting pins and semiconductor dies, and a corresponding method for interconnection.
[0007] According to one aspect of the present disclosure, a multilayer printed circuit board for interconnecting pins and semiconductor dies is provided. The multilayer printed circuit board is a multilayer substrate comprising a bottom substrate layer, one or more core substrate layers, and a top substrate layer stacked in sequence, wherein each of the substrate layers is made of an insulating material. The multilayer substrate further comprises pin holders embedded in the multilayer substrate, each having an end exposed from the top surface of the top substrate layer for inserting a pin into the pin holder; die contacts embedded in the multilayer substrate, each having an end exposed from the bottom surface of the bottom substrate layer for electrically coupling with a contact of the semiconductor die; and a first interconnection structure embedded in the multilayer substrate, each being connected between a corresponding pin holder and a corresponding die contact to electrically couple both of them.
[0008] According to one or more embodiments of the present disclosure, each pin holder extends in a direction perpendicular to the multilayer substrate and includes a tubular cavity adapted to insert one end of a pin, and a first flange disposed at one end of the tubular cavity and protruding laterally with respect to the tubular cavity, the first flange being disposed on the top surface of the top substrate layer.
[0009] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes auxiliary connectors embedded in the multilayer substrate and extending in a direction perpendicular to the multilayer substrate, each having one end electrically coupled to a corresponding pin holder and another end electrically connected to a corresponding die contact, and each of the auxiliary connectors includes a columnar body extending in a direction perpendicular to the multilayer substrate, and a second flange disposed at one end of the columnar body and protruding laterally with respect to the columnar body.
[0010] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes flange interconnects, each of which is connected between and electrically couples a second flange of a corresponding auxiliary connector and a corresponding pin holder.
[0011] According to one or more embodiments of the present disclosure, the auxiliary connector includes a first auxiliary connector, and the second flange of the first auxiliary connector and the flange interconnect connected thereto are disposed between the top substrate layer and the adjacent core substrate layer. The flange interconnect connected to the second flange of the first auxiliary connector is also connected to the tubular cavity of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the first auxiliary connector.
[0012] According to one or more embodiments of the present disclosure, the second flange of the first auxiliary connector and the corresponding flange interconnect connected to each other are integrally formed by the same metal layer.
[0013] According to one or more embodiments of the present disclosure, the auxiliary connector includes a second auxiliary connector, and the second flange of the second auxiliary connector and the flange interconnect that is connected thereto are disposed on the top surface of the top substrate layer. The flange interconnect that is connected to the second flange of the second auxiliary connector is also connected to the first flange of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the second auxiliary connector.
[0014] According to one or more embodiments of the present disclosure, the second flange of the second auxiliary connector, the corresponding flange interconnect, and the first flange of the corresponding pin holder that are connected to each other are integrally formed by the same metal layer.
[0015] According to one or more embodiments of the present disclosure, the multilayer printed circuit board is a second interconnect structure embedded in the multilayer substrate, and further includes a second interconnect structure that is connected between at least two die contacts to electrically couple each of the at least two die contacts.
[0016] According to one or more embodiments of the present disclosure, at least a portion of the first interconnect structure, the second interconnect structure, and / or the die contacts is formed by a thick copper embedding process.
[0017] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes an embedded spacer that extends from the bottom surface of the top substrate layer through one or more core substrate layers and the bottom substrate layer and extends beyond the bottom surface of the bottom substrate layer by a first length, and the first length depends on the thickness of the semiconductor die.
[0018] According to one or more embodiments of the present disclosure, the first length is equal to the sum of the thickness of the semiconductor die and the thickness of the die attachment layer, and the die attachment layer is used to attach the semiconductor die and the multilayer printed circuit board to each other.
[0019] According to one or more embodiments of the present disclosure, a multilayer printed circuit board further includes a negative temperature coefficient contact embedded in the multilayer substrate, the negative temperature coefficient contact being exposed from an opening disposed at the center of the bottom substrate layer for coupling to a negative temperature coefficient sensor.
[0020] According to one or more embodiments of the present disclosure, a die contact includes a thick copper contact and / or a thin copper contact, and the die contact is used as one or more of a gate-substrate contact, a source-substrate contact, a gate pad contact, and / or a source pad contact.
[0021] According to another aspect of the present disclosure, there is provided a pin including a rod-shaped body having a first end that is pointed and adapted to be inserted into a pin holder, and an elastic portion, and a second end that is adapted to be inserted into a through hole, and a stopper disposed at a specific distance from the first end of the rod-shaped body and protruding laterally with respect to the rod-shaped body. The pin is adapted to be mounted in a pin holder within the multilayer printed circuit board described above, and when the first end of the pin is inserted into the pin holder, the stopper rests on the top of the first flange of the pin holder.
[0022] According to another aspect of the present disclosure, there is provided a power module including a carrier substrate, a semiconductor die mounted on the carrier substrate, a multilayer printed circuit board as described above, the multilayer printed circuit board being mounted on the semiconductor die and electrically coupled to the semiconductor die through a die contact of the multilayer printed circuit board, an enclosure enclosing the carrier substrate, the semiconductor die, and the multilayer printed circuit board, and a pin inserted into a pin holder within the multilayer printed circuit board and exposed from one side of the enclosure.
[0023] According to another aspect of the present disclosure, a method for interconnecting pins and a semiconductor die is provided, the method including attaching the semiconductor die onto a carrier substrate, attaching the above-described multilayer printed circuit board onto the semiconductor die, inserting the pins into pin holders within the multilayer printed circuit board, and encapsulating the carrier substrate, the semiconductor die, and the multilayer printed circuit board with an insulating material to form an enclosure.
[0024] According to another aspect of the present disclosure, a method for interconnecting pins and a semiconductor die is provided, the method including attaching the above-described multilayer printed circuit board onto the semiconductor die, attaching the semiconductor die onto a carrier substrate, inserting the pins into pin holders within the multilayer printed circuit board, and encapsulating the carrier substrate, the semiconductor die, and the multilayer printed circuit board with an insulating material to form an enclosure.
[0025] According to one or more embodiments of the present disclosure, attaching the multilayer printed circuit board onto the semiconductor die includes coating an attachment material on the contacts of the semiconductor die, installing the multilayer printed circuit board onto the semiconductor die such that the contacts of the bottom substrate layer of the multilayer printed circuit board and the contacts of the semiconductor die are in contact with each other via the attachment material, and performing a sintering process, a welding process, and / or a curing process to cure the attachment material.
[0026] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings.
Brief Description of the Drawings
[0027] The accompanying drawings, which form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.
[0028] This disclosure can be more clearly understood from the following embodiments for carrying out the invention with reference to the accompanying drawings.
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[0029] Note that in the embodiments described below, the same reference numerals may be commonly used among different drawings to indicate the same parts having the same functions, and repeated descriptions thereof may be omitted. In some cases, similar reference numbers and letters are used to indicate similar items, and thus, once an item is defined in one drawing, it does not need to be further considered in subsequent drawings.
[0030] Also, for ease of understanding, the positions, dimensions, ranges, etc. of the various structures shown in the drawings may not represent the actual positions, dimensions, ranges, etc. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, etc. disclosed in the drawings and the like.
Embodiments for Carrying Out the Invention
[0031] In automotive applications, the pin interconnect process is often used when interconnecting a power module containing semiconductor dies with a general-purpose circuit board (such as a printed circuit board). For example, first, the semiconductor dies are attached onto a carrier substrate, and pin holders are mounted onto the carrier substrate. Next, pins are inserted into the pin holders on the carrier substrate and welded, for example, by reflow soldering. Finally, the semiconductor dies and the carrier substrate are encapsulated with an insulating material such as epoxy resin to obtain a power module having pins for further attachment to a general-purpose circuit board. However, the pins and pin holders in the power module obtained by such a manufacturing process often have various defects, such as poor contact between the pins and pin holders caused by poor soldering, damage or excessive inclination of the pin holders, and solder overflow. These defects lead to a decrease in product performance or even unusable products, which urgently need to be solved.
[0032] Therefore, the inventors of the present application propose a completely new technical solution for interconnecting pins and semiconductor dies, that is, using a dedicated multilayer printed circuit board to interconnect pins and semiconductor dies. Specifically, as proposed by the present disclosure, a multilayer printed circuit board for interconnecting pins and semiconductor dies includes pin holders embedded therein and contacts for coupling to the semiconductor dies. When it is necessary to interconnect pins and semiconductor dies, the multilayer printed circuit board is first attached onto the semiconductor die through the contacts of the semiconductor die, and then pins are inserted into the pin holders within the multilayer printed circuit board, thus realizing the interconnection between the semiconductor die and the pins. In addition, as proposed by the present disclosure, it is also possible to arrange other interconnect structures within the multilayer printed circuit board for interconnecting pins and semiconductor dies, and therefore, the multilayer printed circuit board can provide other interconnect functions for the semiconductor die.
[0033] In the following, one or more detailed embodiments of a completely new technical solution for interconnecting the pins of the present disclosure with the semiconductor die will be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements, mathematical formulas, and numerical values of the parts and steps described in these embodiments do not limit the scope of the present disclosure unless otherwise specified.
[0034] The description of at least one of the following exemplary embodiments is in fact merely illustrative and imposes no limitation on the present disclosure and its applications or uses. That is, the structures and methods in this specification are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will understand that they merely illustrate an exemplary and not an exhaustive manner for implementing the present disclosure. Further, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific parts.
[0035] Techniques, methods, and devices known to those skilled in the relevant art may not be discussed in detail, but they should be considered as part of the approved specification where appropriate.
[0036] In all the examples shown and discussed in this specification, any specific values should be construed as illustrative only and not as a limitation. Therefore, other examples of the exemplary embodiments can have different values.
[0037] FIG. 1A schematically shows a cross-sectional view of a multilayer printed circuit board 100 for interconnecting pins and a semiconductor die according to one or more embodiments of the present disclosure.
[0038] As shown in FIG. 1A, a multilayer printed circuit board 100 for interconnecting pins and a semiconductor die according to one or more embodiments of the present disclosure can include a multilayer substrate 102, which is composed of a bottom substrate layer 104, one or more core substrate layers 106, and a top substrate layer 108 stacked in sequence. Each substrate layer includes an insulating material, which can include any material suitable for forming an insulating substrate layer of a printed circuit board, such as polyimide or epoxy resin. In addition, the materials of the respective substrate layers of the multilayer substrate 102 can be the same or different from each other.
[0039] In one or more preferred embodiments, the hardness and mechanical strength of the bottom substrate layer 104 and the top substrate layer 108 may be better than those of the core substrate layer 106, and thus provide better mechanical support for the entire multilayer printed circuit board 100.
[0040] FIG. 1A schematically shows three core substrate layers 106, as well as the shape, size, and thickness of each substrate layer, which is understood by those skilled in the art not to be intended to constitute any limitation. A multilayer printed circuit board 100 for interconnecting pins and a semiconductor die according to one or more embodiments of the present disclosure can include any number of core substrate layers, and the shape, size, thickness, and material of each substrate layer can be arbitrarily set as needed.
[0041] FIG. 1B and FIG. 1C schematically show a top view and a bottom view of the multilayer printed circuit board 100 shown in FIG. 1A, respectively. FIG. 1B shows the details of the top substrate layer 108 in more detail, and FIG. 1C shows the details of the bottom substrate layer 104 in more detail. The cross-sectional view of FIG. 1A is taken along line A-A of FIGS. 1B and 1C.
[0042] Referring to FIGS. 1A - 1C in combination, a multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to one or more embodiments of the present disclosure can further include a pin holder 110 embedded in a multilayer substrate 102. Each pin holder 110 has an end exposed from the top surface of the top substrate layer 108 for inserting a pin into the pin holder. A multilayer printed circuit board 100 according to one or more embodiments of the present disclosure can further include a die contact 120 embedded in the multilayer substrate 102 and a first interconnect structure 130 embedded in the multilayer substrate 102. As shown in FIG. 1C, each die contact 120 has an end exposed from the bottom surface of the bottom substrate layer 104 for being electrically coupled to a contact of a semiconductor die. Each of the first interconnect structures 130 can be connected to electrically couple both a corresponding pin holder 110 and a corresponding die contact 120 therebetween.
[0043] In a multilayer printed circuit board 100 according to one or more embodiments of the present disclosure, a pin holder 110 for inserting pins and a die contact 120 for coupling a semiconductor die are embedded in a multilayer substrate 102 of the multilayer printed circuit board 100. Further, the pin holder 110 and the die contact 120 are further interconnected through a first interconnect structure 130. When the multilayer printed circuit board 100 according to the present disclosure is used to interconnect a pin and a semiconductor die, the interconnection between the pin and the semiconductor die can be realized by attaching the multilayer printed circuit board 100 and the semiconductor die to each other through surface contact and then inserting the pin into the pin holder 110 in the multilayer printed circuit board 100. Such an interconnection solution can achieve many beneficial technical effects. On the one hand, compared with the prior art in which the pin holder is fixed on the carrier substrate, the solution of the present disclosure embeds the pin holder 110 in the multilayer substrate 102, so that the pin holder 110 is more stable and less likely to tilt, thus avoiding the occurrence of the problem that the pin holder may be damaged during pin insertion. On the other hand, the multilayer printed circuit board 100 and the semiconductor die are interconnected by surface contact, which can also improve the interconnection effect.
[0044] In one or more embodiments according to the present disclosure, the pin holder 110 can be electrically coupled to the corresponding die contact 120 through one or more first interconnect structures 130. For example, as shown in FIG. 1A, the pin holder 110 at the left end in the figure is electrically coupled to the die contact 120 through one first interconnect structure 130, while another pin holder 110 adjacent to the pin holder 110 at the left end is electrically coupled to the die contact 120 through two first interconnect structures 130 respectively arranged between different core substrate layers.
[0045] In one or more embodiments according to the present disclosure, the first interconnect structure 130 and the die contacts 120 can be formed by various processes known in the art for manufacturing conductive components within a printed circuit board. For example, they can be formed by thin copper layers disposed between various substrate layers, or can be formed by thick copper blocks embedded within the substrate layer by a thick copper embedding process (also called Cu inlay).
[0046] In one or more embodiments according to the present disclosure, the die contacts 120 can include thick copper contacts and / or thin copper contacts. The thick copper contacts can be used, for example, as source contacts that need to conduct a larger current, and the thin copper contacts can be used, for example, as gate contacts that need to conduct a smaller current. In one or more preferred embodiments, the die contacts 120 can be used as one or more of the following: gate - substrate contacts, source - substrate contacts, gate pad contacts, and / or source pad contacts, etc.
[0047] The number, distribution, shape, and size of the pin holders 110, die contacts 120, and corresponding first interconnect structures 130 are shown in FIGS. 1A - 1C, which is understood by those skilled in the art not to be intended as any limitation. The multilayer printed circuit board 100 according to one or more embodiments of the present disclosure can include pin holders 110, die contacts 120, and / or first interconnect structures 130 of any number, any distribution, any shape, and any size. Additionally, the die contacts 120 and the first interconnect structures 130 according to one or more embodiments of the present disclosure are not limited to being made of copper and can include any material suitable for forming conductive contacts.
[0048] Continuing to refer to FIGS. 1A and 1B, in one or more embodiments according to the present disclosure, each pin holder 110 can include a tubular cavity 112 and a first flange 114. The tubular cavity 112 can extend in a direction perpendicular to the multilayer substrate 102 and is adapted to receive one end of the pin 10 therein. The first flange 114 can be disposed at one end of the tubular cavity 112 and can protrude laterally with respect to the tubular cavity 112. As shown in FIG. 1A, the first flange 114 functions as an end of the pin holder 110 that is disposed on the top surface of the top substrate layer 108 and is exposed from the top surface of the top substrate layer 108. To be adapted to insert the pin 10 into the pin holder, the inner diameter of the tubular cavity 112 of the pin holder 110 matches the diameter of the insertion end of the pin 10, and the first flange 114 can be formed in an annular shape having an inner diameter that matches the inner diameter of the tubular cavity 112 and an outer diameter that is larger than the inner diameter, as clearly shown in FIG. 1B.
[0049] In one or more embodiments according to the present disclosure, by disposing the first flange 114 at one end of the tubular cavity 112 of the pin holder 110, with the help of the interaction between the first flange 114 and the top substrate layer 108, the pin holder 110 can be more firmly supported by the multilayer substrate 102.
[0050] FIG. 2A schematically shows a front view of a pin 10 according to one or more embodiments of the present disclosure, which is adapted to a pin holder 110 within a multilayer printed circuit board 100 according to one or more embodiments of the present disclosure. FIG. 2B shows a side view of the pin 10.
[0051] As shown in FIGS. 2A and 2B, the pin 10 according to one or more embodiments of the present disclosure can include an elongated rod-shaped body 12. The first end of the rod-shaped body 12 is pointed and adapted to be inserted into the pin holder 110. The second end of the rod-shaped body 12 includes an elastic portion 16 and is adapted to fit into a through hole. The through hole includes, for example, a through hole disposed in a general-purpose circuit board (such as a printed circuit board) to which the pin is connected. The pin 10 can further include a stopper 14. The stopper 14 is disposed at a position of a specific distance L1 from the first end of the rod-shaped body 12 and protrudes laterally with respect to the rod-shaped body 12. The distance L1 of the stopper 14 from the first end of the rod-shaped body 12 can depend on the height of the pin holder. In one or more preferred embodiments, the distance L1 of the stopper 14 from the first end of the rod-shaped body 12 can be the same as or slightly smaller than the height of the pin holder. In one or more preferred embodiments, the stopper 14 can include two semi-cylindrical protrusions disposed opposite to both ends of the rod-shaped body 12. The radius W1 of such semi-cylindrical protrusions can depend on the size of the flange of the pin holder and can be equal to or slightly smaller than the width W0 of the annular flange of the pin holder (as shown in FIG. 1B), for example.
[0052] In one or more embodiments according to the present disclosure, when the first end of the pin 10 is inserted into the pin holder 110, the stopper 14 of the pin 10 can lean against the top of the first flange 114 of the pin holder 110. On the one hand, the mutual inclination between the stopper 14 of the pin 10 and the first flange 114 of the pin holder 110 can provide more mechanical support for the pin 10, which will be considered in more detail later and can make the pin 10 inserted more firmly. On the other hand, the stopper 14 of the pin 10 can also prevent the pin 10 from being inserted too deeply into the pin holder and can ensure that the pin 10 is inserted at an appropriate depth.
[0053] Figure 3 shows a schematic size comparison between a conventional pin 20 and a pin 10 according to one or more embodiments of the present disclosure.
[0054] As described above, existing techniques for pin interconnection place a pin holder on a carrier substrate. However, in one or more embodiments of the present application, the pin holder is disposed within a multilayer printed circuit board attached on a semiconductor die. Thus, on the premise that the overall thickness of the power module remains unchanged, the presence of the multilayer printed circuit board according to one or more embodiments of the present disclosure enables the height of the pin holder to be made higher, enables the pins to be made shorter, and these changes can also improve the effect of pin interconnection.
[0055] As shown in Figure 3, the height H1 of the pin 10 according to one or more embodiments of the present disclosure can be made smaller than the height H0 of the conventional pin 20. In one or more preferred embodiments, the height H1 of the pin 10 according to one or more embodiments of the present disclosure can be made approximately 1.3 mm smaller than the height H0 of the conventional pin 20. This is because the thickness of the bottom substrate layer of the multilayer printed circuit board can be made approximately 1 mm, and the total thickness of the semiconductor die and the die attachment layer for attaching the semiconductor die to the multilayer printed circuit board can be made approximately 0.3 mm. Thus, the height H1 of the pin 10 according to one or more embodiments of the present disclosure can be made approximately 1 mm + 0.3 mm = 1.3 mm lower than that of the conventional pin.
[0056] Continuing to refer to FIG. 3, a conventional pin holder 22 into which a conventional pin 20 is inserted and a pin holder 110 according to one or more embodiments of the present disclosure into which a pin 10 according to one or more embodiments of the present disclosure is inserted are also schematically shown. The height of the pin holder 22 is D0, and the height of the pin holder 110 is D1. When the pin 10 is inserted into the pin holder 110, if the upper end of the pin 10 receives a lateral acting force F1, the portion of the pin 10 inserted into the pin holder 110 will receive a corresponding acting force f1. It is expected that the acting force f1 should be made as small as possible to prevent damage to the pin. The acting force f1 received by the portion of the pin 10 inserted into the pin holder 110 is given by the formula: F1 * (H1 - D1)=f1 * satisfies D1, where H1 is the height of the pin 10 and D1 is the height of the pin holder 110. From this formula, it can be seen that the smaller the height of the pin and the larger the height of the pin holder, the smaller the corresponding acting force f1 applied to the portion of the pin inserted into the pin holder when the upper end of the pin receives a lateral acting force. For example, if the traditional pin 20 has a height H0 = 14.8 mm and the corresponding pin holder 22 has a height D0 = 2.8 mm, the inserted portion of the pin 20 receives an acting force
[0057]
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[0058]
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[0059] Returning to FIGS. 1A - 1C, a multilayer printed circuit board 100 for interconnecting pins and a semiconductor die according to one or more embodiments of the present disclosure may further include auxiliary connectors 140A / 140B that are embedded in the multilayer substrate 102 and extend in a direction perpendicular to the multilayer substrate 102. Each auxiliary connector has one end electrically coupled to a corresponding pin holder 110 and another end electrically connected to a corresponding die contact 120.
[0060] In one or more embodiments according to the present disclosure, as shown in FIG. 1A, each auxiliary connector 140A / 140B may include a columnar body 144 and a second flange 142 disposed at one end of the columnar body 144. The columnar body 144 extends in a direction perpendicular to the multilayer substrate 102 and can be connected to the die contact 120. The second flange 142 protrudes laterally with respect to the columnar body 144.
[0061] As shown in FIGS. 1A and 1B, the multilayer printed circuit board 100 according to one or more embodiments of the present disclosure may further include flange interconnects 146, each of which can connect between the second flange 142 of a corresponding auxiliary connector 140A / 140B and a corresponding pin holder 110, thereby electrically coupling the corresponding auxiliary connector 140A / 140B to the corresponding pin holder 110.
[0062] In one or more embodiments according to the present disclosure, the auxiliary connector may include a first auxiliary connector 140A. The second flange 142 of the first auxiliary connector 140A and the flange interconnect 146 connected thereto are disposed between the top substrate layer 108 and the adjacent core substrate layer 106. The flange interconnect 146 connected to the second flange 142 of the first auxiliary connector 140A can also be connected to the tubular cavity 112 of the corresponding pin holder 110, thereby electrically coupling the corresponding pin holder 110 to the first auxiliary connector 140A.
[0063] Since the flange interconnect 146 connected to the second flange 142 of the first auxiliary connector 140A is disposed under the top substrate layer 108, the flange interconnect 146 is not originally visible in the top view of the top substrate layer 108 shown in FIG. 1B. However, in order to clearly show its shape, in the top view of FIG. 1B, the flange interconnect 146 is shown as a dotted line in a see-through state.
[0064] In one or more preferred embodiments, the second flange 142 of the first auxiliary connector 140A and the corresponding flange interconnect 146, which are connected to each other, can be integrally formed by the same metal layer.
[0065] In one or more embodiments according to the present disclosure, the auxiliary connector can include a second auxiliary connector 140B. The second flange 142 of the second auxiliary connector 140B and the flange interconnect 146 connected thereto are disposed on the top surface of the top substrate layer 108. The flange interconnect 146 connected to the second flange 142 of the second auxiliary connector 140B can also be connected to the first flange 114 of the corresponding pin holder 110, thereby electrically coupling the corresponding pin holder 110 to the second auxiliary connector 140B.
[0066] In one or more preferred embodiments, the second flange 142 of the second auxiliary connector 140B, the corresponding flange interconnect 146, and the first flange 114 of the corresponding pin holder 110, which are connected to each other, are integrally formed by the same metal layer.
[0067] In one or more embodiments according to the present disclosure, the first flange of one pin holder can be connected to the plurality of second flanges of the plurality of auxiliary connectors respectively through a plurality of flange interconnects. As shown in FIG. 1B, the first flange 114' of the pin holder is connected to the two second flanges 142' of the two auxiliary connectors 140B' respectively through two flange interconnects 146' extending in opposite directions. Therefore, the pin holder can be electrically connected to at least two auxiliary connectors 140B', and then can be electrically coupled to at least two die contacts.
[0068] Although the first auxiliary connector 140A and the second auxiliary connector 140B are shown in FIGS. 1A-1C, it is understood by those skilled in the art that this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to one or more embodiments of the present disclosure can include only the first auxiliary connector 140A, can include only the second auxiliary connector 140B, or can include both the first auxiliary connector 140A and the second auxiliary connector 140B.
[0069] In one or more embodiments according to the present disclosure, the pin holder 110 can be electrically coupled to the die contact either through the first interconnect structure or through the flange interconnect and the auxiliary connector. This provides high flexibility for the interconnect design of the multilayer printed circuit board. Therefore, various different interconnect structures can be flexibly arranged within the multilayer printed circuit board according to the needs of the application, the area and space can be fully utilized, and the hardware consumption can be reduced.
[0070] Continuing to refer to FIGS. 1A and 1B, in one or more embodiments according to the present disclosure, the multilayer printed circuit board 100 can further include a second interconnect structure 150 embedded within the multilayer substrate 102. Each second interconnect structure 150 can be connected between at least two die contacts 120 to electrically couple these contacts to each other. The second interconnect structure 150 can be formed by various processes known in the art for manufacturing conductive components within a printed circuit board. For example, they can be formed by thin copper layers disposed between various substrate layers, or they can be formed by thick copper blocks embedded within the substrate layer through a thick copper embedding process (also referred to as Cu inlay).
[0071] In one or more preferred embodiments, at least a portion of the first interconnect structure 130, the second interconnect structure 150, and / or the die contacts 120 according to one or more embodiments of the present disclosure is formed by a thick copper embedding process.
[0072] In the multilayer printed circuit board 100 according to one or more embodiments of the present disclosure, in addition to connection structures (such as the first interconnect structure 130, the auxiliary connectors 140A / 140B, the flange connectors 146, etc.) for connecting the pin holders 110 and the die contacts 120, an interconnect structure (such as the second interconnect structure 150) for realizing connections between various die contacts 120 can also be included. The second interconnect structure 150 enables the interconnection of various contacts of a semiconductor die to be attached through the multilayer printed circuit board 100 without using pins. It creates one or more possible connection modes between various contacts of the semiconductor die, thus providing more possibilities for the overall design of the power module.
[0073] The number, distribution, shape, and size of the auxiliary connectors 140A / 140B, the flange interconnect 146, and the second interconnect structure 150 are shown in FIGS. 1A-1C, but it will be understood by those skilled in the art that this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to one or more embodiments of the present disclosure can include auxiliary connectors 140A / 140B, flange interconnects 146, and / or second interconnect structures 150 of any number, any distribution, any shape, and any size. Additionally, the flange interconnect 146 and the second interconnect structure 150 according to one or more embodiments of the present disclosure are not limited to being made of copper and can include any material suitable for forming conductive components.
[0074] Continuing to refer to FIGS. 1A-1C, the multilayer printed circuit board 100 according to one or more embodiments of the present disclosure is disposed at an idle position within the multilayer substrate 102 where no other conductive components are disposed and can optionally include an embedded spacer 160 made of an insulating material having a certain mechanical strength for strengthening the mechanical support for the multilayer printed circuit board 100. As shown in FIG. 1A, each embedded spacer 160 extends from the bottom surface of the top substrate layer 108 through the core substrate layer 106 and the bottom substrate layer 104 and extends beyond the bottom surface of the bottom substrate layer 104 by a first length, which can depend on the thickness of the semiconductor die to which the multilayer printed circuit board 100 is attached.
[0075] In one or more preferred embodiments, when the multilayer printed circuit board 100 is attached onto the semiconductor die, one end of each embedded spacer 160 that extends beyond the bottom substrate layer 104 leans against the top of the support structure for supporting the semiconductor die in order to strengthen the mechanical support for the multilayer printed circuit board 100. Thus, the first length of the embedded spacer 160 that extends beyond the bottom substrate layer 104 can be equal to or slightly greater than the sum of the thickness of the semiconductor die and the thickness of the die attachment layer, where the die attachment layer refers to the material layer for attaching the semiconductor die and the multilayer printed circuit board to each other.
[0076] Continuing to refer to FIGS. 1A - 1C, the multilayer printed circuit board 100 according to one or more embodiments of the present disclosure can further optionally include a negative temperature coefficient (NTC) contact 170 embedded in the multilayer substrate 102. The negative temperature coefficient contact 170 can be exposed from an opening 180 disposed at the center of the bottom substrate layer 104 for being coupled to a negative temperature coefficient sensor. The temperature sensor can be disposed within the opening 180 for detecting the temperature of the power module.
[0077] The number, distribution, shape, and size of the embedded spacers 160, negative temperature coefficient contacts 170, etc. are shown in FIGS. 1A - 1C, but it is understood by those skilled in the art that this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to one or more embodiments of the present disclosure can include embedded spacers 160, negative temperature coefficient contacts 170, etc. having any number, any distribution, any shape, and any size.
[0078] The multilayer printed circuit board 100 shown in FIGS. 1A to 1C includes various components, but this is merely for showing various components as comprehensively as possible in the same set of drawings and is not intended to constitute any limitation, which should be understood by those skilled in the art. The multilayer printed circuit board 100 according to one or more embodiments of the present invention can include only a part of the various components shown in FIGS. 1A to 1C. In addition, the number, distribution, shape, and size of the various components shown in FIGS. 1A to 1C are used only for illustration and are not intended to constitute any limitation. The multilayer printed circuit board 100 according to one or more embodiments of the present disclosure can include the above components in any number, any distribution, any shape, and any size.
[0079] Also, although various components are included in the same cross-sectional view of FIG. 1A, this is merely for showing various components as comprehensively as possible in the same drawing and is not intended to constitute any limitation, which should be understood by those skilled in the art. A plurality of different components of the multilayer printed circuit board 100 according to one or more embodiments of the present disclosure may not appear in the same cross-sectional view. Therefore, the cross-sectional view of the multilayer printed circuit board 100 can include only a part of the components shown in FIG. 1A.
[0080] A method for interconnecting pins and semiconductor dies according to one or more embodiments of the present disclosure will be described below with reference to FIGS. 4 and 5A to 5E. FIG. 4 shows an exemplary flowchart of a method for interconnecting pins and semiconductor dies according to one or more embodiments of the present disclosure, and FIGS. 5A to 5E schematically show schematic cross-sectional views of devices corresponding to a part of the steps of the method shown in FIG. 4. Those skilled in the art will understand that the method for interconnecting pins and semiconductor dies described in connection with FIGS. 4 and 5A to 5E uses a multilayer printed circuit board for interconnection according to one or more embodiments of the present disclosure. Therefore, the corresponding description of the above multilayer printed circuit board also applies here.
[0081] As shown in FIG. 4, a method 300 for interconnecting pins and a semiconductor die according to one or more embodiments of the present disclosure can include steps S310, S320, S330, and S340.
[0082] In step S310, as shown in FIG. 5A, a semiconductor die 200 is mounted on a carrier substrate 30. In one or more embodiments according to the present disclosure, the carrier substrate 30 can be a ceramic substrate covered with copper, such as a direct bonded copper (DBC) ceramic substrate or an active metal brazing (AMB) ceramic substrate, or any other type of carrier substrate.
[0083] In one or more embodiments according to the present disclosure, the semiconductor die 200 can include a plurality of contacts 202 and 204. In one or more preferred embodiments, the contact 204 having a smaller area can include a gate contact, and the contact 202 having a larger area can include a source contact.
[0084] The number, distribution, shape, and size of the contacts of the semiconductor die 200 are schematically shown in FIG. 5A, but it will be understood by those skilled in the art that this is not intended to constitute any limitation. The semiconductor die 200 according to one or more embodiments of the present disclosure can include contacts of any number, any distribution, any shape, and any size.
[0085] In step S320, a multilayer printed circuit board 100 according to one or more embodiments of the present disclosure is mounted on the semiconductor die 200.
[0086] In one or more embodiments according to the present disclosure, attaching the multilayer printed circuit board 100 to the semiconductor die 200 can be achieved through steps S322, S324, and S326 described below.
[0087] In step S322, as shown in FIG. 5B, the attachment material 206 is coated onto the contacts 202 and 204 of the semiconductor die 200. The attachment material 206 can include, for example, a sintered product, solder, gel, and the like.
[0088] In step S324, as shown in FIG. 5C, the multilayer printed circuit board 100 is placed on the semiconductor die 200 such that the contact 120 of the multilayer printed circuit board 100 exposed from the bottom substrate layer 104 and the contacts 202 and 204 of the semiconductor die 200 are in contact with each other via the attachment material 206.
[0089] In one or more preferred embodiments, the negative temperature coefficient contact 170 can be coupled to the negative temperature coefficient sensor 208.
[0090] In one or more preferred embodiments, one end of each embedded spacer 160 in the multilayer printed circuit board 100 protruding from the bottom substrate layer 104 leans against the top of the carrier substrate 30 under the semiconductor die 200, thereby providing better mechanical support for the multilayer printed circuit board 100.
[0091] In step S326, a sintering process, a welding process, and / or a curing process is performed to cure the attachment material 206, thereby fixing and attaching the multilayer printed circuit board 100 and the semiconductor die 200 to each other. In one or more preferred embodiments, as shown in FIG. 5C, the sintering tool 40 can be used to press the printed circuit board 100 against the semiconductor die 200, thereby improving the strength of the attachment.
[0092] Continuing to refer to FIG. 4, in step S330, the pin 10 is inserted into the pin holder 110 of the multilayer printed circuit board 100 as shown in FIG. 5D.
[0093] In step S340, as shown in FIG. 5E, the carrier substrate 30, the semiconductor die 200, and the multilayer printed circuit board 100 are encapsulated by molding or potting with an epoxy resin to form an enclosure 50, thereby obtaining a packaged power module.
[0094] The order of execution of steps S310 and S320 of method 300 for interconnecting pins and a semiconductor die, shown in FIG. 4, can be interchanged. FIG. 6 shows another method 300' for interconnecting pins and a semiconductor die according to one or more embodiments of the present disclosure, which is a modified embodiment of method 300 for interconnecting pins and a semiconductor die shown in FIG. 4. The main difference between method 300' shown in FIG. 6 and method 300 shown in FIG. 4 is that step S320 is performed first, and then step S310 is performed. Except for the different order of execution of the steps, all the content described above with respect to method 300 of FIG. 4 can be applied to the corresponding features of method 300' shown in FIG. 6.
[0095] As shown in FIG. 6, a method 300' for interconnecting pins and a semiconductor die according to one or more embodiments of the present disclosure can include steps S320, S310, S330, and S340.
[0096] In step S320, a multilayer printed circuit board 100 according to one or more embodiments of the present disclosure is attached onto the semiconductor die 200.
[0097] In step S310, the semiconductor die 200 is attached onto the carrier substrate 30.
[0098] In step S330, the pins 10 are inserted into the pin holders 110 of the multilayer printed circuit board 100.
[0099] In step S340, the carrier substrate 30, the semiconductor die 200, and the multilayer printed circuit board 100 are encapsulated by being molded or potted with an epoxy resin to form the enclosure 50, thereby obtaining a packaged power module.
[0100] FIG. 5E schematically illustrates a power module according to one or more embodiments of the present disclosure. The power module can be manufactured, for example, by the method 300 for interconnecting the pins and the semiconductor die shown in FIG. 4 or by the method 300' for interconnecting the pins and the semiconductor die shown in FIG. 6.
[0101] As shown in FIG. 5E, the power module includes a carrier substrate 30, a semiconductor die 200 disposed on the carrier substrate 30, a multilayer printed circuit board 100 according to one or more embodiments of the present disclosure, which is disposed on the semiconductor die 200 and is electrically coupled to the semiconductor die 200 through its die contacts, an enclosure 50 that encapsulates the carrier substrate 30, the semiconductor die 200, and the multilayer printed circuit board 100, and pins 10 that are inserted into pin holders in the multilayer printed circuit board 100 and are exposed from one side of the enclosure 50.
[0102] FIG. 7A shows a schematic three-dimensional modeling model of a power module according to one or more embodiments of the present disclosure. Referring to FIG. 7A, a packaged power module is shown in which the pins 10 are exposed from one side of the enclosure 50 for further connection to a general-purpose circuit board.
[0103] FIG. 7B shows a perspective view of a part of the components in the multilayer printed circuit board for interconnecting the pins and the semiconductor die in the power module of FIG. 7A. Referring to FIG. 7B, the pins 10, the pin holders 110, the auxiliary connectors 140, and the flange connectors 146 are shown, and the gate contacts 120a and the source contacts 120b that function as die contacts are also shown.
[0104] FIG. 7C shows a bottom view of a multilayer printed circuit board for interconnecting pins and semiconductor dies in the power module of FIG. 7A. As shown in FIG. 7C, the multilayer printed circuit board according to one or more embodiments of the present disclosure includes source-substrate contacts 120c, gate-substrate contacts 120d, source pad contacts 120e, and gate pad contacts 120f that are exposed from its bottom substrate layer and function as die contacts, and a negative temperature coefficient contact 170 that is exposed from an opening in the bottom substrate layer.
[0105] It is understood by those skilled in the art that the above modeling models shown in FIGS. 7A-7C are for the convenience of those skilled in the art to better understand the technical concept of the present disclosure and are not intended to constitute any limitation.
[0106] The terms "front", "back", "top", "bottom", "above" and "below" in this specification and the claims are used for convenience, if any, and are not necessarily used to describe a certain relative position. Such terms are interchangeable under appropriate circumstances, and thus it should be understood that one or more embodiments of the present disclosure described in this specification can operate in orientations other than those illustrated or otherwise described in this specification.
[0107] As used in this specification, the term "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be reproduced exactly. The embodiments illustrated in this specification should not be construed as necessarily being more preferred or advantageous than other embodiments. Furthermore, the present disclosure is not limited by any explicit or implied theory given in the above technical field, background art, summary of the invention, or mode for carrying out the invention.
[0108] As used herein, the term "substantially" means including any slight variations caused by design or manufacturing defects, tolerances of devices or elements, environmental effects, and / or other factors. The term "substantially" also allows for differences between a complete or ideal situation caused by parasitic effects, noise, and other practical considerations that may exist in an actual implementation.
[0109] In addition, the foregoing description may refer to elements or nodes or mechanisms that are "connected" or "coupled" to each other. As used herein, "connected" means that one element / node / mechanism is directly connected (or directly interacts) electrically, mechanically, logically, or otherwise with another element / node / mechanism, unless otherwise explicitly described. Similarly, "coupled" means that although two mechanisms may not be directly connected, one element / node / mechanism can be connected, directly or indirectly through intervening means, mechanically, electrically, logically, or otherwise, with another element / node / mechanism to enable interaction. That is, "coupled" is intended to include both direct and indirect connections of elements or other mechanisms, including connections through one or more intervening elements.
[0110] In addition, similar terms such as "first" and "second" can also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first", "second", and other such numerical terms, including structures or elements, do not implicitly imply an order or arrangement, unless the context clearly indicates otherwise.
[0111] Also, as used herein, the term "including / include / comprising / comprise / containing / contain" is used to identify the presence of the recited features, elements, steps, operations, units and / or components, but it should also be understood that it does not exclude the presence or addition of one or more other features, elements, steps, operations, units and / or components and / or combinations thereof.
[0112] In the present disclosure, the term "providing / provide" is used broadly to encompass all means of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing", "creating / manufacturing", "placing / arranging", "installing / assembling", and / or "ordering" the object, etc.
[0113] Those skilled in the art should recognize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be executed at least partially overlapping in time. Further, alternative embodiments can include multiple instances of specific operations, and the arrangement of operations can be varied in other various embodiments. However, other modifications, variations, and substitutions are also possible. Therefore, the present specification and drawings should be regarded as illustrative rather than restrictive.
[0114] Although some specific embodiments of the present disclosure are described in detail through examples, it should be understood by those skilled in the art that the above examples are merely for illustration and are not intended to limit the scope of the present disclosure. One or more embodiments disclosed herein can be arbitrarily combined without departing from the spirit and scope of the present disclosure. Those skilled in the art will also understand that various modifications can be made to one or more embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims
1. A multilayer printed circuit board for interconnecting one or more pins and one or more semiconductor dies, comprising a multilayer substrate having a bottom substrate layer, one or more core substrate layers, and a top substrate layer laminated in sequence, each of the substrate layers being made of an insulating material; one or more pin holders embedded in the multilayer substrate, each having an end exposed from the top surface of the top substrate layer for inserting one of the one or more pins into the one or more pin holders; one or more die contacts embedded in the multilayer substrate, each having an end exposed from the bottom surface of the bottom substrate layer for electrically coupling with a contact of one of the one or more semiconductor dies; one or more first interconnect structures embedded in the multilayer substrate, each connected between a corresponding pin holder and a corresponding die contact and electrically coupling them; A multilayer printed circuit board comprising the above.
2. Each pin holder comprises a tubular cavity extending in a direction perpendicular to the multilayer substrate and adapted to receive one end of a pin; a first flange disposed at one end of the tubular cavity and protruding laterally with respect to the tubular cavity, the first flange being disposed on the top surface of the top substrate layer. The multilayer printed circuit board according to Claim 1.
3. One or more auxiliary connectors embedded in the multilayer substrate and extending in the direction perpendicular to the multilayer substrate, each having one end electrically coupled to a corresponding pin holder and another end electrically connected to a corresponding die contact. The multilayer printed circuit board further comprises Each of the one or more auxiliary connectors a columnar body extending in the direction perpendicular to the multilayer substrate; a second flange disposed at one end of the columnar body and protruding laterally with respect to the columnar body. The multilayer printed circuit board according to Claim 2.
4. One or more flange interconnects, each connected between and electrically coupling a second flange of a corresponding auxiliary connector and a corresponding pin holder, and further comprising one or more flange interconnects, the multilayer printed circuit board according to claim 3.
5. The one or more auxiliary connectors include a first auxiliary connector, and a second flange of the first auxiliary connector and a flange interconnect connected thereto are disposed between the top substrate layer and an adjacent core substrate layer. The flange interconnect connected to the second flange of the first auxiliary connector is also connected to a tubular cavity of a corresponding pin holder, thereby electrically coupling the corresponding pin holder to the first auxiliary connector, the multilayer printed circuit board according to claim 4.
6. The second flange of the first auxiliary connector and the corresponding flange interconnect, which are connected to each other, are integrally formed by the same metal layer, the multilayer printed circuit board according to claim 5.
7. The one or more auxiliary connectors include a second auxiliary connector, and a second flange of the second auxiliary connector and a flange interconnect connected thereto are disposed on the top surface of the top substrate layer. The flange interconnect connected to the second flange of the second auxiliary connector is also connected to a first flange of a corresponding pin holder, thereby electrically coupling the corresponding pin holder to the second auxiliary connector, the multilayer printed circuit board according to claim 4.
8. The second flange of the second auxiliary connector, the corresponding flange interconnect, and the first flange of the corresponding pin holder, which are connected to each other, are integrally formed by the same metal layer, the multilayer printed circuit board according to claim 7.
9. One or more second interconnect structures embedded in the multilayer substrate, each connected between at least two die contacts to electrically couple the at least two die contacts, and further comprising one or more second interconnect structures, the multilayer printed circuit board according to claim 1.
10. The multilayer printed circuit board according to claim 9, wherein at least a part of the one or more first interconnect structures, the one or more second interconnect structures, and / or the one or more die contacts is formed by a thick copper embedded process.
11. One or more embedded spacers, each extending from the bottom surface of the top substrate layer through the one or more core substrate layers and the bottom substrate layer, and extending beyond the bottom surface of the bottom substrate layer by a first length, further comprising one or more embedded spacers. The multilayer printed circuit board according to claim 1, wherein the first length depends on the thickness of the one or more semiconductor dies.
12. The first length is equal to the sum of the thickness of the one or more semiconductor dies and the thickness of the die attachment layer, and the die attachment layer is used to attach the one or more semiconductor dies and the multilayer printed circuit board to each other. The multilayer printed circuit board according to claim 11.
13. A negative temperature coefficient contact embedded in the multilayer substrate, further comprising a negative temperature coefficient contact exposed from an opening disposed at the center of the bottom substrate layer for coupling to a negative temperature coefficient sensor. The multilayer printed circuit board according to claim 1.
14. The one or more die contacts comprise thick copper contacts and / or thin copper contacts. The one or more die contacts are used as one or more of gate-substrate contacts, source-substrate contacts, gate pad contacts, and / or source pad contacts. The multilayer printed circuit board according to claim 1.
15. A power module, a carrier substrate, one or more semiconductor dies mounted on the carrier substrate, a multilayer printed circuit board, a multilayer substrate comprising a bottom substrate layer, one or more core substrate layers, and a top substrate layer stacked in sequence, each of the substrate layers being made of an insulating material. One or more pin holders embedded in the multilayer substrate, each having an end exposed from the top surface of the top substrate layer for inserting one or more pins into the one or more pin holders. One or more die contacts embedded in the multilayer substrate, each having an end exposed from the bottom surface of the bottom substrate layer for electrical coupling to the contacts of the one or more semiconductor dies. One or more first interconnect structures embedded in the multilayer substrate, each being connected between a corresponding pin holder and a corresponding die contact and electrically coupling them. A multilayer printed circuit board mounted on the one or more semiconductor dies and electrically coupled to the one or more semiconductor dies through the one or more die contacts of the multilayer printed circuit board. An enclosure encapsulating the carrier substrate, the one or more semiconductor dies, and the multilayer printed circuit board. One or more pins inserted into the one or more pin holders in the multilayer printed circuit board and exposed from one side of the enclosure. A power module comprising the above.
16. Each of the one or more pins Is a rod-shaped body having a first end that is pointed and adapted to be inserted into a pin holder, an elastic part, and a second end that is adapted to be inserted into a through hole. A stopper disposed at a specific distance from the first end of the rod-shaped body and protruding laterally with respect to the rod-shaped body. The power module according to claim 15, wherein when the first end of one of the one or more pins is inserted into one of the one or more pin holders, the stopper rests on the top of the first flange of the pin holder.
17. A method for interconnecting one or more pins and one or more semiconductor dies, comprising: Attaching the one or more semiconductor dies onto a carrier substrate; Attaching a multilayer printed circuit board onto the one or more semiconductor dies, the multilayer printed circuit board being A multilayer substrate comprising a bottom substrate layer, one or more core substrate layers, and a top substrate layer laminated in sequence, each of the substrate layers being made of an insulating material. One or more pin holders embedded in the multilayer substrate, each having an end exposed from the top surface of the top substrate layer for inserting one or more pins into the one or more pin holders, one or more pin holders; One or more die contacts embedded in the multilayer substrate, each having an end exposed from the bottom surface of the bottom substrate layer for being electrically coupled to the contacts of the one or more semiconductor dies, one or more die contacts; One or more first interconnect structures embedded in the multilayer substrate, each being connected between a corresponding pin holder and a corresponding die contact and electrically coupling them, and attaching a multilayer printed circuit board comprising: Inserting the one or more pins into the one or more pin holders within the multilayer printed circuit board; Encapsulating the carrier substrate, the one or more semiconductor dies, and the multilayer printed circuit board with an insulating material to form an enclosure; A method comprising.
18. Attaching the multilayer printed circuit board onto the one or more semiconductor dies, Coating an attachment material on the contacts of the one or more semiconductor dies; Placing the multilayer printed circuit board onto the one or more semiconductor dies such that the contacts of the bottom substrate layer of the multilayer printed circuit board and the contacts of the one or more semiconductor dies are in contact with each other via the attachment material; Performing a sintering process, a welding process, and / or a curing process to cure the attachment material, the method according to claim 17.