Array substrate

Abstract

To achieve an array substrate in which a pixel pitch is small while suppressing increase in the lamination number of thin films.SOLUTION: An array substrate 21 includes: a gate wiring 25 extending in a first direction and made of a gate metal film; a source wiring 26 extending in a second direction and made of a source metal film; and a first TFT 27 and a second TFT 29 disposed alternately side by side along the first direction in a plan view. A first semiconductor part 27C for constituting the first TFT 27 comprises a first semiconductor film. A second semiconductor part 29C for constituting the second TFT 29 comprises a second semiconductor film disposed on an upper layer of the first semiconductor film via an insulation film 32, and is disposed between the first semiconductor parts 27C arranged side by side in the first direction in a plan view. A first gate electrode 27G for constituting the first TFT 27 and a second gate electrode 29G for constituting the second TFT 29 are made of the same gate metal film. A first source electrode 27S and a first drain electrode 27D for constituting the first TFT 27, and a second source electrode 29S and a second drain electrode 29D for constituting the second TFT 29 are made of the same source metal film.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] This technology relates to an array substrate.

Background Art

[0002] In display panels such as liquid crystal panels and organic EL (electro-luminescence) panels, it is known that TFTs (thin film transistors) are used as switching elements. TFTs are known to be formed by laminating various thin films using photolithography in an array substrate (active matrix substrate, TFT substrate) constituting the display panel, and an example thereof is disclosed in Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] In the array substrate described in Patent Document 1, in the pixel portion, the first TFT and the second TFT are laminated along the vertical direction of the main surface of the substrate. More specifically, on the upper layer of the gate electrode, gate insulating film, semiconductor film, source electrode, and drain electrode constituting the first TFT, the gate electrode, gate insulating film, semiconductor film, source electrode, and drain electrode constituting the second TFT are laminated. Thereby, it is said that the occupied area in the plane of the TFT can be reduced, and the light transmittance and aperture ratio can be improved.

Summary of the Invention

Problems to be Solved by the Invention

[0005] If the method described in Patent Document 1 is used, it is considered that the pixel pitch can be reduced and the display panel can be made high-definition. However, when this method is used, there is a problem that the number of laminated thin films increases significantly and the manufacturing process becomes redundant.

[0006] The technology described in the present specification has been completed based on the above circumstances, and an object thereof is to realize an array substrate with a small pixel pitch while suppressing an increase in the number of stacked thin films.

Means for Solving the Problems

[0007] (1) The array substrate related to the technology described in the present specification is disposed on the upper layer side of an insulating substrate, includes a plurality of gate wirings made of a gate metal film that extend in a first direction, a plurality of source wirings made of a source metal film that extend in a second direction intersecting the first direction, and a plurality of first TFTs and a plurality of second TFTs that are alternately arranged side by side along the first direction in a plan view. The plurality of first semiconductor portions constituting the plurality of first TFTs are made of a first semiconductor film, the plurality of second semiconductor portions constituting the plurality of second TFTs are made of a second semiconductor film disposed via an insulating film on the upper layer of the first semiconductor film, and are disposed between the first semiconductor portions arranged in the first direction in a plan view. The plurality of first gate electrodes constituting the plurality of first TFTs and the plurality of second gate electrodes constituting the plurality of second TFTs are made of the same gate metal film, and the plurality of first source electrodes and plurality of first drain electrodes constituting the plurality of first TFTs, and the plurality of second source electrodes and plurality of second drain electrodes constituting the plurality of second TFTs are made of the same source metal film.

[0008] (2) Further, in addition to the above (1), in the array substrate, the length of the second semiconductor portion in the first direction may be different from the length of the first semiconductor portion in the first direction.

[0009] (3) Further, in addition to the above (1) or (2), in the array substrate, the film thickness of the second semiconductor film may be different from the film thickness of the first semiconductor film.

[0010] (4) Further, in addition to any one of the above (1) to (3), in the array substrate, the material of the second semiconductor film may be a material having a composition different from that of the first semiconductor film.

[0011] (5) Further, in addition to any one of (1) to (4) above, for the array substrate, the length of the first gate electrode in the second direction may be different from the length of the second gate electrode in the second direction.

[0012] (6) Further, in addition to any one of (1) to (5) above, for the array substrate, the plurality of first TFTs and the plurality of second TFTs may be arranged alternately along the second direction in a plan view, and the plurality of second semiconductor portions may be arranged between two of the first semiconductor portions arranged along the second direction in a plan view.

[0013] (7) Further, in addition to any one of (1) to (6) above, for the array substrate, the gate metal film may be arranged on the upper layer side of the first semiconductor film and the second semiconductor film.

[0014] (8) Further, in addition to any one of (1) to (6) above, for the array substrate, the gate metal film may be arranged on the lower layer side of the first semiconductor film and the second semiconductor film.

[0015] (9) Further, in addition to any one of (1) to (8) above, for the array substrate, the materials of the first semiconductor film and the second semiconductor film may be oxide semiconductor materials containing at least one metal element among In, Ga, and Zn.

[0016] (10) Further, in addition to (9) above, for the array substrate, the length of the first semiconductor portion in the first direction may be greater than the length of the second semiconductor portion in the first direction.

[0017] (11) Further, in addition to (9) or (10) above, for the array substrate, the content rate of at least one metal element among In, Ga, and Zn in the oxide semiconductor material of the first semiconductor film may be greater than that of the oxide semiconductor material of the second semiconductor film.

Advantages of the Invention

[0018] According to the technology described in the specification of the present application, an array substrate with a small pixel pitch can be realized while suppressing an increase in the number of stacked thin films.

Brief Description of the Drawings

[0019]

Figure 1

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Figure 11

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Figure 15

Modes for Carrying Out the Invention

[0020] <Embodiment 1> The liquid crystal panel 11 (an example of a display panel) according to Embodiment 1 will be described with reference to FIGS. 1 to 8. Note that the X-axis, Y-axis, and Z-axis are shown in the drawings, and the axial directions are drawn so as to be common directions in each drawing.

[0021] As shown in FIG. 1, the liquid crystal panel 11 has, within its plane, a display area (active area) AA that can display an image and is arranged on the central side, and a non-display area (non-active area) NAA that is arranged on the outer peripheral side so as to surround the display area AA and forms a frame shape (a frame-like shape) when viewed in plan. In FIG. 1, a dashed-dotted line represents the outer shape of the display area AA, and the area outside the dashed-dotted line is the non-display area NAA. The planar shape of the liquid crystal panel 11 is not limited, but in the present embodiment, it has an overall vertically long rectangular shape, the short side direction coincides with the X-axis direction, the long side direction coincides with the Y-axis direction of each drawing, and the plate thickness direction coincides with the Z-axis direction.

[0022] As shown in FIG. 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. Between the pair of substrates 20 and 21, at least a liquid crystal layer 22 and a seal portion 23 that seals (seals) the liquid crystal layer 22 are interposed. The liquid crystal layer 22 contains liquid crystal molecules, which are substances whose optical properties change with the application of an electric field. The seal portion 23 forms a rectangular frame shape as a whole when viewed in plan, and surrounds the liquid crystal layer 22 in the non-display area NAA. The seal portion 23 holds a gap (cell gap) corresponding to the thickness of the liquid crystal layer 22. Polarizing plates 24 are respectively attached to the outer surface sides of the pair of substrates 20 and 21.

[0023] Of the pair of substrates 20 and 21, the one arranged on the front side (display surface side) is the counter substrate (CF substrate) 20, and the one arranged on the back side is the array substrate (active matrix substrate, TFT substrate) 21. Both the counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface side (liquid crystal layer 22 side) of a glass substrate that is substantially transparent and has excellent light transmittance.

[0024] On the back side of the liquid crystal panel 11 (the array substrate 21 side), a backlight device for irradiating the liquid crystal panel 11 with light is provided. The liquid crystal panel 11 according to the present embodiment is used, for example, in a head-mounted display and has extremely high definition. The pixel density of the liquid crystal panel 11 is, for example, in the range of about 1000 ppi to 1800 ppi.

[0025] The array substrate 21 is larger than the counter substrate 20 and a part of it protrudes beyond the counter substrate 20. A flexible substrate 13 is mounted on the protruding portion 21A of the array substrate 21. The flexible substrate 13 is configured to have a plurality of wiring patterns formed on a base material having insulation and flexibility. One end side of the flexible substrate 13 is connected to the array substrate 21, and the other end side is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0026] In the display area AA of the array substrate 21, as shown in FIG. 3, a plurality of gate wirings (scanning wirings) 25 and source wirings (image wirings) 26 forming a lattice pattern are arranged. The gate wiring 25 extends generally along the X-axis direction (an example of the first direction) across the display area AA. A plurality of gate wirings 25 are arranged side by side at intervals in the Y-axis direction. A scanning signal output from a first circuit portion 14A described later is supplied to the plurality of gate wirings 25. The source wiring 26 extends generally along the Y-axis direction (an example of the second direction) across the display area AA and intersects the gate wiring 25. A plurality of source wirings 26 are arranged at intervals in the X-axis direction. An image signal output from a second circuit portion 14B described later is distributed to the source wiring 26.

[0027] Near the intersection of the gate wiring 25 and the source wiring 26, a pixel electrode 28 and one of the first TFT 27 or the second TFT 29 are provided. The TFTs 27, 29 and the pixel electrode 28 are regularly arranged in plural along the X-axis direction and the Y-axis direction. Also, the first TFT 27 and the second TFT 29 are arranged alternately along the X-axis direction. The gate wiring 25, the source wiring 26 and the pixel electrode 28 are connected to the TFTs 27, 29. The TFTs 27, 29 are switching elements that charge the pixel electrode 28 to a potential based on the image signal supplied to the source wiring 26 when driven based on the scanning signal supplied to the gate wiring 25.

[0028] As shown in FIG. 1, a circuit portion (peripheral circuit portion) 14 is provided in the non-display area NAA of the array substrate 21. The circuit portion 14 includes a first circuit portion 14A and a second circuit portion 14B. A pair of the first circuit portions 14A are arranged so as to sandwich the display area AA from both sides in the X-axis direction, but it may be provided on only one side. The first circuit portion 14A is a GDM (Gate Driver Monolithic) circuit that supplies a scanning signal to the gate wiring 25. The second circuit portion 14B is arranged at a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit portion 14B divides the image signal (source signal) supplied by the source driver 14C and distributes it to each source wiring 26.

[0029] Subsequently, the planar layout pattern of the display area AA of the array substrate 21 will be described with reference to FIGS. 4 and 5. As shown in FIG. 4, the pixel electrode 28 is arranged in a region surrounded by two gate wirings 25 spaced apart in the Y-axis direction and two source wirings 26 spaced apart in the X-axis direction. The pixel electrode 28 has a vertically long rectangular shape when viewed in plan according to the planar shape of this region. The source wiring 26 is partially widened, and the widened portion constitutes the source electrodes 27S, 29S of the TFTs 27, 29.

[0030] The first TFT 27 includes a first semiconductor portion 27C, a first gate electrode 27G, a first source electrode 27S, and a first drain electrode 27D. The second TFT 29 includes a second semiconductor portion 29C, a second gate electrode 29G, a second source electrode 29S, and a second drain electrode 29D.

[0031] The gate wiring 25 is composed of a top gate wiring 25A arranged on the upper layer side of the semiconductor portions 27C and 29C and a bottom gate wiring 25B arranged on the lower layer side as will be described later. The top gate wiring 25A is narrower than the bottom gate wiring 25B and is arranged to overlap the central portion of the bottom gate wiring 25B. The top gate wiring 25A and the bottom gate wiring 25B are connected to each other, and the scanning signal supplied to the gate wiring 25 is supplied to both the top gate wiring 25A and the bottom gate wiring 25B to be at the same potential. However, the gate wiring 25 may be composed of only the top gate wiring 25A without including the bottom gate wiring 25B.

[0032] The portion of the top gate wiring 25A that overlaps the first semiconductor portion 27C also serves as the first top gate electrode 27G1, and the portion that overlaps the second semiconductor portion 29C also serves as the second top gate electrode 29G1 as shown in FIG. 5. Further, the portion of the bottom gate wiring 25B that overlaps the first semiconductor portion 27C also serves as the first bottom gate electrode 27G2, and the portion that overlaps the second semiconductor portion 29C also serves as the second bottom gate electrode 29G2. As shown in FIG. 4, the drain electrodes 27D and 29D are provided on the opposite side of the source electrodes 27S and 29S across the gate wiring 25 (which also serves as the gate electrodes 27G and 29G) in the Y-axis direction at positions overlapping the pixel electrode 28.

[0033] The semiconductor portions 27C and 29C are provided such that one end is connected to the source electrodes 27S and 29S and the other end is connected to the drain electrodes 27D and 29D. As shown in FIG. 5, the semiconductor portions 27C and 29C are vertically long as a whole when viewed in plan, and are bent such that the overlapping portions with the gate wiring 25 (which also serves as the gate electrodes 27G and 29G) are inclined with respect to the Y-axis direction.

[0034] The first semiconductor part 27C and the second semiconductor part 29C according to this embodiment have the same planar shape and planar size, but they may be different. The second semiconductor part 29C is arranged between the first semiconductor parts 27C when viewed in the plane. The first semiconductor part 27C is made of a first semiconductor film and is arranged at a predetermined interval L1 along the X-axis direction. The second semiconductor part 29C is made of a second semiconductor film arranged in a layer different from the first semiconductor film and is arranged at a predetermined interval L2 along the X-axis direction.

[0035] Therefore, as shown in FIG. 8, the first semiconductor part 27C and the second semiconductor part 29C are made of different semiconductor films (the first semiconductor film and the second semiconductor film) and are alternately arranged in different layers. Thereby, the interval L3 between the adjacent first semiconductor part 27C and the second semiconductor part 29C becomes sufficiently smaller than the interval L1 between the first semiconductor parts 27C and the interval L2 between the second semiconductor parts 29C (that is, L3 < L1 and L3 < L2). The intervals L1 and L2 according to this embodiment are the same, but they may be different.

[0036] Subsequently, the cross-sectional structure of the array substrate 21 will be described in detail with reference to FIGS. 6 to 8. In the display area AA of the array substrate 21, a first TFT 27 is provided as shown in FIG. 6, and a second TFT 29 is provided as shown in FIG. 7. The semiconductor parts 27C and 29C are respectively sandwiched from above and below by top gate electrodes 27G1 and 29G1 and bottom gate electrodes 27G2 and 29G2, and the TFTs 27 and 29 have a double gate structure. By adopting the double gate structure, a channel region can be stably formed in the semiconductor parts 27C and 29C. However, the TFTs 27 and 29 may have a top gate structure having only the top gate electrodes 27G1 and 29G1.

[0037] The array substrate 21 is formed by laminating various films on a glass substrate 21GS (an example of an insulating substrate). The glass substrate 21GS contains, for example, non-alkali glass as a main material. The array substrate 21 includes two types of TFTs 27 and 29 in which the semiconductor portions 27C and 29C are arranged in different layers. On the array substrate 21, in order from the lower layer side (the glass substrate 21GS side), there are a light-shielding portion 40, a base coat film 41, bottom gate electrodes 27G2 and 29G2 and a bottom gate wiring 25B made of a first gate metal film, a first insulating film 31, a first semiconductor portion 27C made of a first semiconductor film, a second insulating film 32, a second semiconductor portion 29C made of a second semiconductor film, a third insulating film 33, top gate electrodes 27G1 and 29G1 and a top gate wiring 25A made of a second gate metal film, a fourth insulating film 34, source electrodes 27S and 29S made of a source metal film, drain electrodes 27D and 29D, and a source wiring 26, a planarization film 37, a pixel electrode 28 made of a first transparent conductive film, a fifth insulating film 38, and a common electrode 39 made of a second transparent conductive film are laminated and formed. In the plan views of FIGS. 4 and 5, the common electrode 39 is omitted in order to clarify other portions.

[0038] The light-shielding portion 40, the first gate metal film, the second gate metal film, and the source metal film are a single-layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials, and have conductivity and light-shielding properties.

[0039] The first transparent conductive film and the second transparent conductive film are made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0040] The base coat film 41, the first insulating film 31, the second insulating film 32, the third insulating film 33, the fourth insulating film 34, and the fifth insulating film 38 are made of an inorganic material (inorganic resin material), and are, for example, a single-layer film or a laminated film of SiO (silicon oxide) or SiN (silicon nitride).

[0041] The planarization film 37 is made of an organic material (organic resin material), and is made of, for example, PMMA (acrylic resin). The planarization film 37 usually has a larger film thickness than other insulating films made of inorganic materials.

[0042] The first semiconductor film and the second semiconductor film are made of an oxide semiconductor material. The oxide semiconductor material has a higher electron mobility compared to an amorphous silicon semiconductor material. Also, the oxide semiconductor material has the characteristic that its resistance value is high in a state where no voltage is applied (off state) compared to a polysilicon semiconductor material, and the manufacturing process of doping impurities into an intrinsic semiconductor film, such as in the case of a polysilicon semiconductor material, becomes unnecessary.

[0043] The film thickness and composition of the first semiconductor film and the second semiconductor film according to this embodiment are the same, but they may be different as described later in Embodiment 2. By using an oxide semiconductor material, it becomes easy to change the composition ratio between the two semiconductor films or to adjust the degree of deoxidation or hydrogen diffusion.

[0044] As the oxide semiconductor material, for example, an oxide semiconductor material containing at least one metal element among In, Ga, and Zn can be used. The oxide semiconductor material may be amorphous or crystalline, and is, for example, a semiconductor of the In-Ga-Zn-O system (for example, indium gallium zinc oxide). Also, for example, an In-Sn-Zn-O system semiconductor (for example, In2O3-SnO2-ZnO; InSnZnO), an In-W-Zn-O system semiconductor, an In-W-Sn-Zn-O system semiconductor, an In-Al-Zn-O system semiconductor, an In-Al-Sn-Zn-O system semiconductor, a Zn-O system semiconductor, an In-Zn-O system semiconductor, a Zn-Ti-O system semiconductor, a Mg-Zn-O system semiconductor, an In-Ga-Sn-O system semiconductor, an In-Ga-O system semiconductor, a Zr-In-Zn-O system semiconductor, a Hf-In-Zn-O system semiconductor, an Al-Ga-Zn-O system semiconductor, a Ga-Zn-O system semiconductor, an In-Ga-Zn-Sn-O system semiconductor.

[0045] As shown in FIG. 8, a second insulating film 32 is interposed between a first semiconductor portion 27C made of a first semiconductor film and a second semiconductor portion 29C made of a second semiconductor film to insulate them. In the first TFT 27, the gate insulating film between the first semiconductor portion 27C and the first top gate electrode 27G1 is the second insulating film 32 and the third insulating film 33 as shown in FIG. 6. Also, the gate insulating film between the first semiconductor portion 27C and the first bottom gate electrode 27G2 is the first insulating film 31. On the other hand, in the second TFT 29, the gate insulating film between the second semiconductor portion 29C and the top gate electrode 29G1 is the third insulating film 33 as shown in FIG. 7. Also, the gate insulating film between the second semiconductor portion 29C and the second bottom gate electrode 29G2 is the first insulating film 31 and the second insulating film 32. Therefore, the number of layers (and thus the film thickness) of the gate insulating film is different between the first TFT 27 and the second TFT 29.

[0046] The pixel electrode 28 is made of a first transparent conductive film. As shown in FIGS. 6 and 7, the pixel electrode 28 has a contact portion 28A that penetrates the planarization film 37, and the contact portion 28A of the pixel electrode 28 is connected to the drain electrodes 27D and 29D.

[0047] The common electrode 39 is made of a first transparent conductive film. The common electrode 39 is disposed so as to overlap on the upper layer side of all the pixel electrodes 28 via a fifth insulating film 38. Slits 39A are respectively formed in the openings in the portions of the common electrode 39 that overlap a plurality of pixel electrodes 28. A common potential signal, which is a common potential (reference potential), is supplied to the common electrode 39. When the pixel electrode 28 is charged to a potential based on the image signal transmitted to the source wiring 26 along with the driving of the TFTs 27 and 29, a potential difference is generated between the pixel electrode 28 and the common electrode 39. Then, a fringe electric field (oblique electric field) including a component in the normal direction to the plate surface of the array substrate 21 in addition to the component along the plate surface of the array substrate 21 is generated between the opening edge of the slit 39A in the common electrode 39 and the pixel electrode 28. The alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by this fringe electric field. That is, the liquid crystal panel 11 according to the present embodiment has an operation mode of FFS (Fringe Field Switching) mode.

[0048] Also, in the display area AA, as shown in FIGS. 6 to 8, a light shielding portion 40 is provided at a position overlapping at least the entire areas of the bottom gate electrodes 27G2 and 29G2. The light shielding portion 40 blocks the light irradiated from the backlight device to each channel region of the semiconductor portions 27C and 29C from the lower layer side. Thereby, it is possible to suppress fluctuations in the characteristics of the TFTs 27 and 29 that may occur when the channel region is irradiated with light.

[0049] The array substrate 21 having the above-described configuration is manufactured by laminating various films in the above-described order while patterning and forming them on a glass substrate 21GS using a known photolithography method. Further, heat treatment may be performed on each film at an arbitrary timing. An alignment film is applied so as to cover the laminated film formed by the photolithography method on the uppermost layer (the layer closest to the liquid crystal layer 22) of the array substrate 21.

[0050] Here, "patterning" means processing of a film based on a general photolithography method. Specifically, it means forming a photoresist film on the film to be processed, exposing the photoresist film with an exposure apparatus through a photomask having a predetermined pattern, developing the photoresist film, and etching the film to be processed through the developed photoresist film.

[0051] Generally, the minimum dimension of a layout pattern patterned by a photolithography method depends on the resolution of the photoresist film. In order to further increase the definition of the liquid crystal panel 11, it is required to reduce the pixel pitch beyond the limit value due to the resolution of the photoresist film.

[0052] According to the present embodiment, by making the layers of adjacent semiconductor portions (the first semiconductor portion 27C and the second semiconductor portion 29C) different layers (the first semiconductor film and the second semiconductor film), the interval L3 between adjacent semiconductor portions can be made smaller than the minimum dimension of the layout pattern patterned by the photolithography method. More specifically, when the intervals L1 between the first semiconductor portions 27C and L2 between the second semiconductor portions 29C are the minimum values at the minimum dimension, the interval L3 between adjacent semiconductor portions can be made smaller than the intervals L1 and L2.

[0053] On the other hand, for the gate electrodes 27G, 29G, the source electrodes 27S, 29S, and the drain electrodes 27D, 29D, they are made of the same layer (the first gate metal film, the second gate metal film, and the source metal film) without making them different layers between the first TFT and the second TFT. As a result, an array substrate 21 with a small pixel pitch can be realized while suppressing an increase in the number of stacked thin films.

[0054] <Embodiment 2> The first semiconductor part 127C and the second semiconductor part 129C according to Embodiment 2 will be described with reference to FIGS. 9 to 10. The semiconductor parts 127C and 129C are different from Embodiment 1 in that at least one of the length (width) in the X-axis direction, the film thickness, and the composition is different from each other. In Embodiment 2, the same reference numerals are given to the same configurations, operations, and effects as in Embodiment 1, and redundant descriptions are omitted.

[0055] As described above with reference to FIGS. 6 and 7, a second insulating film 32 is interposed between the first semiconductor part 127C made of the first semiconductor film and the second semiconductor part 129C made of the second semiconductor film, and the number of layers (and thus the film thickness) of the gate insulating film is different between the first TFT 127 and the second TFT 129. As a result, the distance between the first gate electrode 27G and the first semiconductor part 127C is different from the distance between the second gate electrode 29G and the second semiconductor part 129C, and there is a concern that there will be a difference in TFT characteristics between the first TFT 127 and the second TFT 129. More specifically, the distance between the first top gate electrode 27G1 and the first semiconductor part 127C is larger than the distance between the second top gate electrode 29G1 and the second semiconductor part 129C, and there is a concern that the ion concentration when the same gate voltage is applied will be larger in the second semiconductor part 129C than in the first semiconductor part 127C.

[0056] Therefore, it is preferable that at least one of the length in the X-axis direction (and thus the channel width), the film thickness, and the composition of the first semiconductor portion 127C and the second semiconductor portion 129C is made different so as to suppress such differences in TFT characteristics. For example, when the first semiconductor portion 127C and the second semiconductor portion 129C are made of an In-Ga-Zn-O-based semiconductor material, the content ratio of In in the first semiconductor portion 127C is made larger than that in the second semiconductor portion 129C with respect to the composition ratio. More specifically, the film formation conditions and the target material (parent material) used during film formation are changed between the first semiconductor film and the second semiconductor film, or the degree of deoxidation and hydrogen diffusion between the first semiconductor film and the second semiconductor film is adjusted according to the film formation conditions of the second insulating film 32 and the third insulating film 33 in contact with the first semiconductor film and the second semiconductor film. Further, as shown in FIGS. 9 and 10, the length L6 of the first semiconductor portion 127C in the X-axis direction is made larger than the length L7 of the second semiconductor portion 129C in the X-axis direction, or the film thickness of the first semiconductor portion 127C is made smaller than that of the second semiconductor portion 129C.

[0057] <Embodiment 3> The first top gate electrode 227G1 and the second top gate electrode 229G1 according to Embodiment 3 will be described with reference to FIG. 11. The top gate electrodes 227G1 and 229G1 are different from those in Embodiment 2 in that the lengths in the Y-axis direction are different. In Embodiment 3, the same reference numerals are given to the same configurations, operations, and effects as those in Embodiments 1 and 2, and redundant descriptions are omitted.

[0058] The first top gate electrode 227G1 and the second top gate electrode 229G1 preferably have different lengths in the Y-axis direction (and thus channel lengths) so as to suppress differences in TFT characteristics between the first TFT 227 and the second TFT 229. For example, as shown in FIG. 11, the top gate wiring 225A is patterned such that the length L8 of the second top gate electrode 229G1 in the Y-axis direction is larger than the length L9 of the first top gate electrode 227G1 in the Y-axis direction.

[0059] <Other Embodiments> The technology described in this specification is not limited to the embodiments described by the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

[0060] (1) The first TFT 327 and the second TFT 329 may be TFTs having a bottom gate structure having only the bottom gate electrodes 27G2 and 29G2 as shown in FIGS. 12 and 13.

[0061] (2) The first semiconductor part 227C and the second semiconductor part 229C may be arranged such that their planar shapes (more specifically, the orientations of the pattern shapes) are alternately different in the Y-axis direction as shown in FIG. 14.

[0062] (3) The first semiconductor part 327C and the second semiconductor part 329C may be alternately arranged side by side in the Y-axis direction as shown in FIG. 15. That is, the second semiconductor part 329C is arranged between two first semiconductor parts 327C arranged side by side in the Y-axis direction when viewed in the plane. As a result, the first TFT 27 and the second TFT 29 are also alternately arranged side by side in the Y-axis direction.

[0063] (4) The layer configuration and the layout pattern of the array substrate 21 are not limited to those shown. For example, the array substrate 21 may include wiring for realizing a touch panel function.

[0064] (5) The TFTs constituting the first circuit part 14A and the second circuit part 14B in the non-display area NAA may use a polysilicon semiconductor material (LTPS, Low Temperature Polycrystalline Silicon) for the semiconductor film.

[0065] (6) The driving method of the liquid crystal panel 11 is not limited to the FFS mode, and may be other methods such as the IPS (In Plane Switching) mode. Also, depending on the driving method, the common electrode 39 may be provided on the counter substrate 20.

[0066] (7) This technology is also applicable to other types of display panels such as organic EL panels.

Explanation of Reference Numerals

[0067] 21... Array substrate, 21GS... Glass substrate (insulating substrate), 25... Gate wiring, 26... Source wiring, 27, 127, 227, 327... First TFT, 27C, 127C, 227C, 327C... First semiconductor portion, 27D... First drain electrode, 27G... First gate electrode, 27S... First source electrode, 29, 129, 229, 329... Second TFT, 29C, 129C, 229C, 329C... Second semiconductor portion, 29D... Second drain electrode, 29S... Second source electrode, 29G... Second gate electrode, 32... Second insulating film (insulating film)

Claims

1. A plurality of gate wirings made of a gate metal film, arranged on the upper layer side of an insulating substrate, extending in a first direction, and a plurality of source wirings made of a source metal film, extending in a second direction intersecting the first direction, and a plurality of first TFTs and a plurality of second TFTs arranged alternately along the first direction in a plan view, comprising: The plurality of first semiconductor portions constituting the plurality of first TFTs are made of a first semiconductor film, The plurality of second semiconductor portions constituting the plurality of second TFTs are made of a second semiconductor film arranged via an insulating film on the upper layer of the first semiconductor film, and are each arranged between the first semiconductor portions arranged in the first direction in a plan view, The plurality of first gate electrodes constituting the plurality of first TFTs and the plurality of second gate electrodes constituting the plurality of second TFTs are made of the same gate metal film, An array substrate in which the plurality of first source electrodes and the plurality of first drain electrodes constituting the plurality of first TFTs, and the plurality of second source electrodes and the plurality of second drain electrodes constituting the plurality of second TFTs are made of the same source metal film.

2. The array substrate according to claim 1, wherein the length of the second semiconductor portion in the first direction is different from the length of the first semiconductor portion in the first direction.

3. The array substrate according to claim 1 or claim 2, wherein the film thickness of the second semiconductor film is different from the film thickness of the first semiconductor film.

4. The array substrate according to claim 1 or claim 2, wherein the material of the second semiconductor film is a material having a composition different from that of the first semiconductor film.

5. The array substrate according to claim 1 or claim 2, wherein the length of the first gate electrode in the second direction is different from the length of the second gate electrode in the second direction.

6. The plurality of first TFTs and the plurality of second TFTs are arranged alternately along the second direction in a plan view, The array substrate according to claim 1 or claim 2, wherein the plurality of second semiconductor portions are arranged between two first semiconductor portions arranged in the second direction in a plan view.

7. The array substrate according to claim 1 or claim 2, wherein the gate metal film is arranged on the upper layer side of the first semiconductor film and the second semiconductor film.

8. The array substrate according to claim 1 or claim 2, wherein the gate metal film is arranged on the lower layer side of the first semiconductor film and the second semiconductor film.

9. The array substrate according to claim 1 or claim 2, wherein the materials of the first semiconductor film and the second semiconductor film are oxide semiconductor materials containing at least one metal element among In, Ga, and Zn.

10. The array substrate according to claim 9, wherein the length of the first semiconductor portion in the first direction is greater than the length of the second semiconductor portion in the first direction.

11. The array substrate according to claim 9, wherein the content rate of at least one metal element among In, Ga, and Zn in the oxide semiconductor material of the first semiconductor film is greater than that of the oxide semiconductor material of the second semiconductor film.

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