Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

To provide a semiconductor light-emitting element which can efficiently remove hydrogen from a p-type semiconductor layer, and a method for manufacturing the semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting element includes: a growth substrate (11); a plurality of light-emitting semiconductor layers standing vertically to the main surface of the growth substrate (11), the layers including an active layer in the inside; a burying semiconductor layer (30) including a gap (31) in the inside, the light-emitting semiconductor layers being buried in the burying semiconductor layer; and a removal region (28) from which a part of the burying semiconductor layer (30) is removed, the removal region exposing the gap (31).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor light-emitting element and a method for manufacturing the semiconductor light-emitting element.

Background Art

[0002] A semiconductor light-emitting element emits light by recombination of holes and electrons in an active layer. Conventionally, a flat sheet-like well layer has been used as the active layer. In recent years, active layers having a three-dimensional structure such as a columnar shape have been studied. Patent Document 1 discloses an example of such a semiconductor light-emitting element. The semiconductor light-emitting element according to Patent Document 1 includes a plurality of columnar semiconductor layers (nanowires) in which an active layer is formed around an n-type core layer and a p-type semiconductor layer is formed around the active layer. The plurality of nanowires are further embedded in a p-type embedded semiconductor layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, the p-type semiconductor layer constituting the semiconductor light-emitting element needs to be exposed to the outside and activated in the manufacturing process of the semiconductor light-emitting element. More specifically, heat treatment (annealing treatment) is performed in a state where the p-type semiconductor layer is exposed to the outside to remove hydrogen.

[0005] In the semiconductor light-emitting device according to the above prior art, since the p-type embedded semiconductor layer is exposed to the outside in the manufacturing process, it is conceivable to perform an activation process in that state. However, since the embedded semiconductor layer has a thickness only for embedding the columnar semiconductor layer, it is difficult to sufficiently remove hydrogen in a region deeper than a certain depth from the surface of the embedded semiconductor layer. That is, in such an activation process, there is a possibility that activation can be performed only up to a certain region from the surface exposed to the outside. If the activation is insufficient, the p-type semiconductor layer becomes highly resistive, and the device efficiency of the semiconductor light-emitting device decreases.

[0006] Therefore, the present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a semiconductor light-emitting device capable of efficiently removing hydrogen from a p-type semiconductor layer and a method for manufacturing the semiconductor light-emitting device.

Means for Solving the Problems

[0007] In order to solve the above problems, a semiconductor light-emitting device of the present invention includes a growth substrate, a plurality of light-emitting semiconductor layers erected in a direction perpendicular to the main surface of the growth substrate and having an active layer inside, an embedded semiconductor layer embedding the plurality of light-emitting semiconductor layers and having voids inside, and a removal region in which a part of the embedded semiconductor layer is removed to expose the voids.

[0008] In such a semiconductor light-emitting device of the present invention, in a semiconductor light-emitting device including a plurality of light-emitting semiconductor layers erected in a direction perpendicular to the main surface of the growth substrate and having an active layer inside, and an embedded semiconductor layer embedding the plurality of light-emitting semiconductor layers and having voids inside, since it has a removal region in which a part of the embedded semiconductor layer is removed to expose the voids, it becomes possible to efficiently remove hydrogen from the p-type semiconductor layer.

[0009] In one aspect of the present invention, the light-emitting semiconductor layer includes an n-type core layer disposed at the center, an active layer disposed on the outer periphery of the n-type core layer, and a p-type semiconductor layer disposed on the outer periphery of the active layer, and the embedded semiconductor layer is a p-type semiconductor layer.

[0010] In one aspect of the present invention, the light-emitting semiconductor layer is a columnar semiconductor layer extending in a direction perpendicular to the main surface of the growth substrate, and the voids are integrally connected.

[0011] In one aspect of the present invention, the light-emitting semiconductor layer is a wall-shaped semiconductor layer standing in a direction perpendicular to the main surface of the growth substrate and extending in the direction of the main surface of the growth substrate, and the removal region is formed in a direction intersecting the extending direction of the wall-shaped semiconductor.

[0012] In order to solve the above problems, a method for manufacturing a semiconductor light-emitting device of the present invention includes a mask forming step of forming a mask having an opening on a growth substrate, a step of forming an n-type core layer in the opening using selective growth, a step of forming an active layer on the outer periphery of the n-type core layer, and a step of forming a p-type semiconductor layer on the outer periphery of the active layer, a light-emitting semiconductor layer forming step of forming a plurality of light-emitting semiconductor layers including these steps, an embedded semiconductor layer forming step of embedding the plurality of light-emitting semiconductor layers and forming a p-type embedded semiconductor layer on the growth substrate so as to form voids inside, a removal region forming step of removing a part of the embedded semiconductor layer to expose the voids, and an activation step of performing heat treatment on the whole to activate the p-type semiconductor layer and the embedded semiconductor layer.

[0013] In one aspect of the present invention, the p-type semiconductor layer and the embedded semiconductor layer are GaN-based semiconductor layers, and the growth temperature and V / III ratio in the embedded semiconductor layer forming step are higher than the growth temperature and V / III ratio in the step of forming the p-type semiconductor layer.

Advantages of the Invention

[0014] The present invention can provide a semiconductor light-emitting device capable of efficiently performing hydrogen desorption from a p-type semiconductor layer, and a method for manufacturing the semiconductor light-emitting device.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Mode for Carrying Out the Invention

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and repeated explanations will be omitted as appropriate. Also, the materials and numerical values cited in the following description are merely examples and are not limited thereto.

[0017] Referring to FIGS. 1 to 4, a semiconductor light-emitting device and a method for manufacturing the semiconductor light-emitting device according to the present embodiment will be described. FIG. 1 is a perspective view showing a semiconductor light-emitting device 10 according to the present embodiment. As shown in FIG. 1, the semiconductor light-emitting device 10 includes a growth substrate 11, an underlying layer 12, a mask 13, an embedded semiconductor layer 30, a cathode electrode 20, an anode electrode 21, a void 31, and removal regions 28 and 29. Although not visible in FIG. 1, a nanowire 32 as a columnar semiconductor layer is disposed inside the embedded semiconductor layer 30 arranged on the mask 13. Note that the nanowire (columnar semiconductor layer) 32 is an example of the "light-emitting semiconductor layer" according to the present invention.

[0018] The growth substrate 11 is a substantially flat member made of a material capable of growing a semiconductor material. When the semiconductor light-emitting device 10 is made of a nitride semiconductor, it is preferable to use a GaN substrate as the growth substrate 11. Further, as the growth substrate 11, a hetero-substrate such as a c-plane sapphire substrate or a Si substrate made of a material different from the semiconductor material to be grown may be used, and a structure in which a plurality of semiconductor layers such as a buffer layer and an underlying layer are grown may be used.

[0019] A buffer layer (not shown) is a layer formed between the single crystal substrate and the underlying layer to relieve the lattice mismatch between the two. When a c-plane sapphire substrate is used as the single crystal substrate, it is preferable to use GaN for the buffer layer, but AlN, AlGaN, or the like may also be used.

[0020] The underlying layer 12 is a single crystal semiconductor layer formed on the growth substrate 11 or the buffer layer (not shown). It is preferable to form undoped GaN with a thickness of several micrometers and a plurality of layers including an n-type semiconductor layer such as an n-type contact layer thereon. The n-type contact layer is a semiconductor layer doped with an n-type impurity. For example, n-type Al doped with Si 0.05 Ga 0.95 N or the like is used as the material.

[0021] Mask 13 is a layer made of a dielectric material formed on the surface of the growth substrate 11 or the underlying layer 12. As the material constituting the mask 13, a material that makes it difficult for semiconductor crystal growth to occur from the mask 13 is selected. For example, SiO2, SiNx, Al2O3, etc. are suitable. A plurality of openings 13a (see FIG. 2(a)) described later are formed in the mask 13, and semiconductor layers can grow from the surface of the growth substrate 11 or the underlying layer 12 partially exposed from the openings 13a.

[0022] Referring to FIG. 2(a), the nanowire 32 will be described in more detail. FIG. 2(a) is a view of the semiconductor light-emitting element 10 shown in FIG. 1 excluding the embedded semiconductor layer 30. The nanowire 32 is a columnar semiconductor layer selectively grown (crystal grown) on the growth substrate 11 or the underlying layer 12 exposed from the opening 13a of the mask 13, and is formed by standing a substantially columnar semiconductor layer vertically with respect to the main surface of the growth substrate 11. Such a nanowire 32 can be obtained by setting appropriate growth conditions according to the semiconductor material constituting it and performing selective growth in which a specific crystal plane orientation grows. In the example shown in FIG. 2(a), since a plurality of openings 13a are formed two-dimensionally and periodically in the mask 13, the nanowires 32 are also formed periodically on the growth substrate 11.

[0023] Next, the internal structure of the nanowire 32 will be described. As shown in FIG. 2(a), the nanowire 32 is composed of an n-type core layer 14, an active layer 15, and a p-type semiconductor layer 16 from the center.

[0024] The n-type core layer 14 is composed of, for example, GaN doped with n-type impurities. When GaN is used as the n-type core layer 14, the n-type core layer 14 selectively grown on the growth substrate 11 has a substantially hexagonal column shape with six m-planes formed as facets. In FIG. 2(a), it appears that the n-type core layer 14 is grown only in the region where the opening 13a is formed, but actually, crystal growth also proceeds on the mask 13 by lateral growth, so a hexagonal column expanded around the opening 13a is formed. For example, when the opening 13a is formed as a circle with a diameter of about 150 nm, a hexagonal columnar n-type core layer 14 with a height of about 1 to 2 μm and a hexagonal shape inscribed in a circle with a diameter of about 240 nm can be formed as the bottom surface. However, the size of the n-type core layer 14 is not limited to this, and it may be, for example, about 0.2 to 1 μm in width and about 0.5 to 2.5 μm in height. Also, the interval (distance) between the n-type core layers 14 may be about 0.2 to 1.8 μm.

[0025] The active layer 15 is a semiconductor layer grown along the n-type core layer 14 on the outer periphery of the n-type core layer 14. Examples include a multiple quantum well active layer in which a GaInN quantum well layer with a thickness of 5 nm and a GaN barrier layer with a thickness of 10 nm are stacked in 5 cycles. Here, a multiple quantum well active layer is given as an example, but it may also be a single quantum well structure or a bulk active layer. Since the active layer 15 is formed on the side surface and the upper surface of the n-type core layer 14, the area of the active layer 15 can be ensured. Since the side surface of the n-type core layer 14 is composed of m-planes, the active layer 15 formed on the side surface is also a non-polar plane having an m-plane, and the droop characteristics can be improved.

[0026] The p-type semiconductor layer 16 is a semiconductor layer grown along the active layer 15 on the outer periphery of the active layer 15 and is composed of, for example, GaN doped with p-type impurities. Since the p-type semiconductor layer 16 is formed on the side surface and the upper surface of the active layer 15, a double heterostructure is formed by the n-type n-type core layer 14, the active layer 15, and the p-type semiconductor layer 16, and carriers can be well confined in the active layer 15 to improve the probability of radiative recombination.

[0027] Referring back to FIG. 1, the embedded semiconductor layer 30 is a p-type semiconductor layer grown outside the p-type semiconductor layer 16, and is composed of GaN in this embodiment. The embedded semiconductor layer 30 is formed to cover the side surface and the upper surface of the p-type semiconductor layer 16 and reach the growth substrate 11 or the underlying layer 12. As shown in FIG. 1, voids 31 are formed inside the embedded semiconductor layer 30. As will be described later, the voids 31 are used as flow paths when hydrogen is removed from the embedded semiconductor layer 30 and the p-type semiconductor layer 16 in the manufacturing process of the semiconductor light-emitting element 10.

[0028] FIG. 1 shows an example in which the embedded semiconductor layer 30 is configured as a single layer, but a multi-layer laminated structure may be used as long as the semiconductor layer is formed to be embedded from the surface of the growth substrate 11 to the upper surface of the columnar semiconductor layer. The embedded semiconductor layer 30 also has a function of fixing and protecting the thin nanowires 32. Although various materials are assumed as the material of the embedded semiconductor layer 30 as will be described later, a material having a band gap smaller than the band gap of the material constituting the active layer 15 absorbs the light emitted from the active layer 15, so it is necessary to select a material having a larger band gap than the band gap of the material constituting the active layer 15.

[0029] The removal region 28 is a region obtained by etching the embedded semiconductor layer 30 from its upper surface to the mask 13, and is provided to surely expose the voids 31 from the embedded semiconductor layer 30. The removal region 28 is provided on three side surfaces excluding the removal region 29. However, the present invention is not limited to this, and it may be provided on at least one side surface of the embedded semiconductor layer 30. Note that the removal region 28 may be formed by etching the embedded semiconductor layer 30 from its upper surface to the underlying layer 12. The removal region 29 is a region obtained by etching the embedded semiconductor layer 30 from its upper surface to the underlying layer 12, and is provided for arranging the cathode electrode 20 on the underlying layer 12.

[0030] The cathode electrode 20 is a negative electrode for supplying current to the semiconductor light-emitting element 10. As shown in FIG. 1, the cathode electrode 20 is formed in a removal region 29 where the underlying layer 12 is exposed, and is composed of a laminated structure of a metal material that makes ohmic contact with the exposed underlying layer 12 and a pad electrode. The anode electrode 21 is a positive electrode for supplying current to the semiconductor light-emitting element 10. The anode electrode 21 is formed on a part of the embedded semiconductor layer 30, and is composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the embedded semiconductor layer 30 and a pad electrode. Note that the anode electrode 21 may be a transparent electrode extended so as to cover substantially the whole of the embedded semiconductor layer 30. Although not shown in FIG. 1, known structures such as covering the surface of the semiconductor light-emitting element 10 with a passivation film may be applied as necessary.

[0031] The voids 31 are exposed to the outside through the removal region 28, and have an effect of efficiently releasing hydrogen from p-type semiconductor layers (in this embodiment, the p-type semiconductor layer 16 and the embedded semiconductor layer 30) to be activated in the activation step of the manufacturing process described later. With reference to FIGS. 2(b) to (e), the action of the voids 31 will be described more specifically.

[0032] FIG. 2(b) shows the configuration of a semiconductor light-emitting element according to the prior art, in which a plurality of nanowires 32 are formed on the underlying layer 12, and the plurality of nanowires 32 are embedded in the embedded semiconductor layer 30. In the semiconductor light-emitting element according to this prior art, as shown in FIG. 2(c), hydrogen near the surface of the embedded semiconductor layer 30 is relatively easily released. However, hydrogen existing in a relatively deep region of the embedded semiconductor layer 30 surrounded by the dotted circle is difficult to release. Therefore, there is a possibility that activation may be insufficient.

[0033] Figure 2(d) shows the configuration of the semiconductor light-emitting device 10 according to the present embodiment. The semiconductor light-emitting device 10 is different from the semiconductor light-emitting device according to the above-described prior art in that it has voids 31. Therefore, as shown in Fig. 2(e), in the semiconductor light-emitting device 10, hydrogen near the surface of the embedded semiconductor layer 30 is removed from the surface of the embedded semiconductor layer 30, and hydrogen existing in a relatively deep region of the embedded semiconductor layer 30 can be removed through the voids 31. Therefore, in the semiconductor light-emitting device 10, it is possible to efficiently perform hydrogen removal throughout the inside of the embedded semiconductor layer 30.

[0034] Referring to Fig. 3, a method for manufacturing the semiconductor light-emitting device 10 according to the present embodiment will be described. (a) in Fig. 3 shows a base layer formation step, (b) shows a mask formation step, (c) shows an opening formation step, (d) shows a columnar semiconductor layer formation step as a light-emitting semiconductor layer formation step, (e) shows a void formation / removal region formation / activation step, and (f) shows an electrode formation step. The semiconductor light-emitting device 10 is manufactured in the state of a semiconductor wafer in which a plurality of element formation regions are arranged. In the following description, one of the element formation regions will be focused on for explanation.

[0035] First, in the base layer formation step shown in Fig. 3(a), as an example, a buffer layer (not shown) made of GaN and a base layer 12 made of GaN and AlGaN are grown on a growth substrate 11 made of a sapphire single crystal using metal organic chemical vapor deposition (MOCVD). As the growth conditions of the buffer layer (not shown), for example, TMA (TriMethylAlminium), TMG (TriMethylGallium), and ammonia are used as source gases, the growth temperature is 1100°C, the V / III ratio is 1000, and hydrogen is used as a carrier gas at a pressure of 10 hPa. As the growth conditions of the base layer 12, for example, the growth temperature is 1050°C, the V / III ratio is 1000, and hydrogen is used as a carrier gas at a pressure of 500 hPa. As described above, as the growth substrate 11, a substrate made of a single material, for example, an n-type GaN substrate, may be used.

[0036] Next, in the mask formation step shown in FIG. 3(b), a mask 13 made of SiO2 is deposited on the base layer 12 by sputtering to a thickness of about 30 nm.

[0037] Next, in the opening formation step shown in FIG. 3(c), an opening 13a with a diameter of about 150 nm is formed using a fine pattern formation method such as nanoimprint lithography.

[0038] Next, in the columnar semiconductor layer formation step shown in FIG. 3(d), an n-type core layer 14 made of GaN is grown on the base layer 12 exposed from the opening 13a by selective growth using the MOCVD method. As the growth conditions for the n-type core layer 14, for example, TMG and ammonia are used as source gases, the growth temperature is 1050 °C, the V / III ratio is 10, and hydrogen is used as the carrier gas at a pressure of 100 hPa.

[0039] Next, an active layer 15 in which five cycles of a 5-nm-thick GaInN quantum well layer and a 10-nm-thick GaN barrier layer are stacked is grown on the side and top surfaces of the n-type core layer 14 using the MOCVD method. As the growth conditions for the active layer 15, for example, the growth temperature is 800 °C, the V / III ratio is 3000, nitrogen is used as the carrier gas at a pressure of 1000 hPa, and TMG, TMI (TriMethylIndium), and ammonia are used as source gases.

[0040] Thereafter, a p-type semiconductor layer 16 made of GaN doped with p-type impurities is grown around the active layer 15. This step, in combination with the void formation step of the void formation / removal region formation / activation step which is the next step, has the effect of forming voids 31 inside the embedded semiconductor layer 30. That is, in the present embodiment, first, a shell-shaped p-type semiconductor layer 16 surrounding the active layer 15 is grown, and then, in the void formation step of the next step, the embedded semiconductor layer 30 is grown laterally in a certain range above the nanowire 32. As a result, voids 31 are formed inside the embedded semiconductor layer 30. In this sense, this step is a pretreatment step for the void formation step, and hereinafter this step may be referred to as the "shell formation step", and the p-type semiconductor layer 16 may be referred to as the "shell layer". As an example, the growth conditions of the p-type semiconductor layer 16 in this shell formation step are a growth temperature of 950°C and a V / III ratio of 4000.

[0041] Next, in the void formation step of the void formation / removal region formation / activation step shown in Fig. 3(e), an embedded semiconductor layer 30 made of GaN is grown to embed a part of the upper surface and the outer periphery of a nanowire (columnar semiconductor layer) 32 composed of the n-type core layer 14, the active layer 15, and the p-type semiconductor layer 16 (shell layer). At this time, in the present embodiment, the embedded semiconductor layer 30 is controlled to grow as much as possible in the lateral direction and not reach the mask 13 as much as possible, so that voids 31 are intentionally generated inside the embedded semiconductor layer 30. In other words, the embedded semiconductor layer 30 follows a process in which it grows thickly above the shell layer (p-type semiconductor layer 16) and then eventually joins as a whole. As a result, voids 31 are formed inside the embedded semiconductor layer 30. As an example of the control method therefor, the growth temperature and V / III ratio of this step are made higher than the growth temperature and V / III ratio of the shell formation step. More specifically, for example, the growth temperature of the void formation step may be set to about 1000°C and the V / III ratio may be set to about 6000. By this step, as shown in Fig. 1, voids 31 integrally connected inside the embedded semiconductor layer 30 are formed. Note that it is not necessary for all of the voids 31 to be strictly connected, and they may be partially filled with the embedded semiconductor layer 30 as long as the subsequent activation step can be performed without problems.

[0042] In the next removal region formation step, a removal region 28 is formed by selectively etching from the upper surface of the embedded semiconductor layer 30 to the mask 13 around the embedded semiconductor layer 30, and a removal region 29 is formed by selectively etching from the upper surface of the embedded semiconductor layer 30 to the underlying layer 12. The removal region 28 is formed on three sides of the embedded semiconductor layer 30, excluding the removal region 29. In other words, the embedded semiconductor layer 30 is etched into a mesa shape. However, it is not always necessary to etch all three sides, and at least one side, and further at least a part of the one side may be etched. Also, the removal region 28 may be etched from the upper surface of the embedded semiconductor layer 30 to the underlying layer 12. For the etching in this step, for example, dry etching is used. As shown in FIG. 1, since the voids 31 inside the embedded semiconductor layer 30 are integrally connected, by forming the removal regions 28 and 29, the embedded semiconductor layer 30 is exposed to the outside including the inside.

[0043] In the next activation step, a heat treatment (annealing) is performed overall to remove hydrogen from the p-type embedded semiconductor layer 30 and the p-type semiconductor layer 16. Here, the method of the heat treatment is not limited, and as an example, heat treatment (annealing) at 600 ° C. in an air atmosphere can be mentioned. Although annealing in an air atmosphere is shown here, other heat treatments may be used as long as the embedded semiconductor layer 30 can be activated and the heat treatment is performed in an atmosphere where atomic hydrogen does not exist. In the semiconductor light emitting device 10, since the embedded semiconductor layer 30 is exposed to the outside including the inside, hydrogen is efficiently removed from the embedded semiconductor layer 30.

[0044] After the above activation step, a passivation film covering the surface of the semiconductor light emitting device 10 may be formed as necessary. Also, in order to ensure the strength of the embedded semiconductor layer 30 having the voids 31, the voids 31 may be filled with SiO2 or a transparent resin or the like.

[0045] In the electrode formation step shown in FIG. 3(f) below, a cathode electrode 20 is formed on the surface of the underlying layer 12 exposed in the removal region 29, and an anode electrode 21 is formed on the embedded semiconductor layer 30. Thereafter, the semiconductor wafer is subjected to a scribing (element division) process and diced into individual semiconductor light-emitting elements 10. The semiconductor light-emitting elements 10 are mounted on a package or the like as required and put into practical use.

[0046] In the semiconductor light-emitting element 10 of the present embodiment, when a voltage is applied between the cathode electrode 20 and the anode electrode 21, current flows in the order of anode electrode 21 → embedded semiconductor layer 30 → p-type semiconductor layer (shell layer) 16 → active layer 15 → n-type core layer 14 → underlying layer 12 → cathode electrode 20, and light is generated by radiative recombination in the active layer 15. The light emitted from the active layer 15 is taken out to the outside of the semiconductor light-emitting element 10. At this time, in the semiconductor light-emitting element 10 according to the present embodiment, since the side surface of the n-type core layer 14 is an m-plane formed by selective growth, the active layer 15 formed on the outer periphery thereof and the p-type semiconductor layer (shell layer) 16 are also in contact with each other on the m-plane. Since the m-plane is a non-polar plane and no polarization occurs, the light emission efficiency in the active layer 15 is also high. Moreover, since all the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light-emitting element 10 can be improved. Further, since the film thickness of the active layer 15 can be increased, the volume of the active layer 15 can be increased by about 3 to 10 times compared with the conventional semiconductor light-emitting element, and the injection carrier density can be reduced to significantly reduce the efficiency droop.

[0047] As described in detail above, according to the semiconductor light-emitting element and the method for manufacturing a semiconductor light-emitting element according to the present embodiment, it is possible to provide a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element capable of efficiently performing hydrogen detachment from a p-type semiconductor layer.

[0048] Next, with reference to FIG. 4, differences in the form of the void 31 based on differences in the form of the light-emitting semiconductor layer will be described. FIG. 4(a) shows the cutting position of the cross-sectional views shown in (b) to (d). That is, the views shown in FIGS. 4(b) to (d) are cross-sectional views seen from above, cut in a plane including the line A-A' crossing the nanowire 32 or the nanowall 22 and the void 31.

[0049] Figure 4(b) shows a semiconductor light-emitting device having a triangular lattice array of nanowires 32 arranged at the vertices of an equilateral triangle. Inside the embedded semiconductor layer 30, voids 31 where the embedded semiconductor layer 30 does not exist are continuously formed on one side. Although the voids 31 are not shown in Figure 4(b), it can be considered that the entire region of the mask layer 13 becomes voids 31. According to the semiconductor light-emitting device of this example, it can be seen that the embedded semiconductor layer 30 can be efficiently exposed to the outside. As a result, dehydrogenation of the embedded conductor layer 30, which is a p-type semiconductor layer, and the p-type semiconductor layer 16 can be efficiently performed.

[0050] Figure 4(c) shows a semiconductor light-emitting device having a square lattice array of nanowires 32 arranged at the vertices of a square. Inside the embedded semiconductor layer 30, voids 31 where the embedded semiconductor layer 30 does not exist are continuously formed on one side. Although the voids 31 are not shown in Figure 4(c), it can be considered that the entire region of the mask layer 13 becomes voids 31. According to the semiconductor light-emitting device of this example, it can be seen that the embedded semiconductor layer 30 can be efficiently exposed to the outside. As a result, dehydrogenation of the embedded conductor layer 30, which is a p-type semiconductor layer, and the p-type semiconductor layer 16 can be efficiently performed. Note that the semiconductor light-emitting device 10 according to the above embodiment employs the nanowires of the square lattice array of this example.

[0051] Figure 4(d) shows a semiconductor light-emitting device provided with a nanowall 22 as a light-emitting semiconductor layer instead of the nanowires 32. The nanowall 22 is a wall-shaped semiconductor layer that stands vertically with respect to the main surface of the growth substrate 11 and extends in a wall shape in the main surface direction of the growth substrate 11. The internal structure of the wall-shaped semiconductor layer also includes an n-type core layer 14 arranged at the center, an active layer 15 formed around the n-type core layer 14, and a p-type semiconductor layer (shell layer) 16 arranged around the active layer 15, similar to the nanowires 22.

[0052] In the case of the nanowalls 22, the voids 31 are formed between the nanowalls 22. That is, it can be considered that all the regions of the mask layer 13 shown in FIG. 4(d) become voids 31. In the case of the semiconductor light-emitting device shown in FIG. 4(d), the end face of the embedded semiconductor layer 30 in the direction orthogonal to the extending direction of the nanowalls 22 is etched to expose the voids 31. The nanowalls 22 can be manufactured by a manufacturing method similar to that of the nanowires 32 according to the above-described embodiment. According to the semiconductor light-emitting device of this example, it can be seen that the entire embedded semiconductor layer 30 can be efficiently exposed to the outside. As a result, the hydrogen desorption of the embedded conductor layer 30, which is a p-type semiconductor layer, and the p-type semiconductor layer 16 can be efficiently performed.

[0053] Note that the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

Explanation of Reference Numerals

[0054] 10…Semiconductor light-emitting device 11…Growth substrate 12…Underlayer 13…Mask 13a…Opening 14…n-type core layer 15…Active layer 16…p-type semiconductor layer 20…Cathode electrode 21…Anode electrode 22…Nanowall 28…Removal region 29…Removal region 30…Embedded semiconductor layer 31…Void 32…Nanowire

Claims

1. A growth substrate, A plurality of light-emitting semiconductor layers that are erected in a direction perpendicular to the main surface of the growth substrate and have an active layer inside, An embedded semiconductor layer that embeds the plurality of light-emitting semiconductor layers and has voids inside, A semiconductor light-emitting device, comprising: a removal region in which a part of the embedded semiconductor layer is removed to expose the voids.

2. The semiconductor light-emitting device according to Claim 1, The light-emitting semiconductor layer includes an n-type core layer disposed at the center, an active layer disposed on the outer periphery of the n-type core layer, and a p-type semiconductor layer disposed on the outer periphery of the active layer, The semiconductor light-emitting device, wherein the embedded semiconductor layer is a p-type semiconductor layer.

3. The semiconductor light-emitting device according to Claim 1, The light-emitting semiconductor layer is a columnar semiconductor layer that extends in a direction perpendicular to the main surface of the growth substrate, The semiconductor light-emitting device, wherein the voids are integrally connected.

4. The semiconductor light-emitting device according to Claim 1, The light-emitting semiconductor layer is a wall-shaped semiconductor layer that is erected in a direction perpendicular to the main surface of the growth substrate and extends in the direction of the main surface of the growth substrate, The semiconductor light-emitting device, wherein the removal region is formed in a direction intersecting the extending direction of the wall-shaped semiconductor.

5. A mask forming step of forming a mask having an opening on a growth substrate, A light-emitting semiconductor layer forming step of forming an n-type core layer in the opening using selective growth, a step of forming an active layer on the outer periphery of the n-type core layer, and a step of forming a p-type semiconductor layer on the outer periphery of the active layer, including a plurality of light-emitting semiconductor layers, An embedded semiconductor layer forming step of embedding the plurality of light-emitting semiconductor layers and forming a p-type embedded semiconductor layer on the growth substrate so as to form voids inside, A removal region forming step of removing a part of the embedded semiconductor layer to expose the voids, A method for manufacturing a semiconductor light-emitting device, including an activation step of performing heat treatment on the whole to activate the p-type semiconductor layer and the embedded semiconductor layer.

6. The method for manufacturing a semiconductor light-emitting device according to Claim 5, The p-type semiconductor layer and the embedded semiconductor layer are GaN-based semiconductor layers, The method for manufacturing a semiconductor light-emitting device, wherein the growth temperature and V / III ratio in the embedded semiconductor layer forming step are higher than the growth temperature and V / III ratio in the step of forming the p-type semiconductor layer.

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