Photoelectric conversion device, photoelectric conversion system, and mobile body

Abstract

To provide a photoelectric conversion device including a stack of a plurality of semiconductor element layers, in which the heat radiation unevenness can be reduced.SOLUTION: A photoelectric conversion device according to one embodiment includes a first chip including a first semiconductor element layer including a pixel region where a plurality of pixel circuits are disposed, and a second chip including a second semiconductor element layer. The first chip and the second chip are bonded to each other with a plurality of metal bonding parts between the first semiconductor element layer and the second semiconductor element layer. The metal bonding parts include a first metal bonding part and a second metal bonding part disposed in a region overlapping with the pixel region in a plan view. The first metal bonding part connects at least one pixel circuit among the pixel circuits, and the second semiconductor element layer. The second metal bonding part is connected to at least one pixel circuit among the pixel circuits and is not connected to the second semiconductor element layer in the region overlapping with the pixel region in the plan view.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] A photoelectric conversion device in which a chip including a pixel circuit and a chip including an electric circuit for processing a signal from the pixel circuit are stacked is known. Patent Document 1 discloses a photoelectric conversion device in which a chip having a plurality of pixel circuits and a chip having a plurality of electric circuits are stacked.

[0003] In the photoelectric conversion device shown in Patent Document 1, there is a conductive portion that electrically connects the pixel circuit and the electric circuit and joins the chip having the pixel circuit and the chip having the electric circuit. In Patent Document 1, the number of conductive portions is smaller than the number of pixel circuits. Specifically, in a pixel region where pixel circuits are arranged in an array, the conductive portions are selectively arranged at a ratio of one for a plurality of pixel circuits. Therefore, there are pixel circuits provided with conductive portions and pixel circuits not provided with conductive portions.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The conductive portion connects the pixel circuit and the electric circuit via a metal wiring. Generally, since the metal wiring has a high thermal conductivity with respect to the interlayer insulating film, heat transfer is large in the conductive portion. On the other hand, in a pixel circuit not provided with a conductive portion, heat transfer generated in at least one of the photoelectric conversion element and the signal processing circuit is less likely to occur than in a pixel provided with a conductive portion. Therefore, heat dissipation unevenness occurs between the pixel circuit provided with the conductive portion and the pixel circuit not provided with the conductive portion.

[0006] The present invention aims to reduce uneven heat dissipation in a photoelectric conversion device in which a plurality of semiconductor element layers are stacked.

Means for Solving the Problems

[0007] A photoelectric conversion device according to one embodiment includes a first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, and a second chip having a second semiconductor element layer. The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a first metal joint and a second metal joint arranged in a region overlapping the pixel region in plan view. The first metal joint connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer. The second metal joint is connected to at least one pixel circuit among the plurality of pixel circuits and is not connected to the second semiconductor element layer in a region overlapping the pixel region in plan view.

[0008] A photoelectric conversion device according to one embodiment includes a first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, and a second chip having a second semiconductor element layer. The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a first metal joint and a second metal joint arranged in a region overlapping the pixel region in plan view. The first metal joint connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer. The second metal joint is connected to the second semiconductor element layer and is not connected to any of the plurality of pixel circuits in a region overlapping the pixel region in plan view.

[0009] A photoelectric conversion device according to one embodiment includes a first chip having a first semiconductor element layer including a plurality of pixel circuits, and a second chip having a second semiconductor element layer. The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a first metal joint and a second metal joint. The first metal joint connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer. A fourth wiring pattern is disposed between four or more of the second metal joints among the plurality of metal joints and the first semiconductor element layer, and one fourth wiring pattern is connected to each of the four or more second metal joints. Alternatively, a second wiring pattern is disposed between four or more of the second metal joints among the plurality of metal joints and the second semiconductor element layer, and one second wiring pattern is connected to each of the four or more second metal joints.

[0010] A photoelectric conversion device according to one embodiment includes a first chip having a first semiconductor element layer including a plurality of pixel circuits, and a second chip having a second semiconductor element layer. The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a first metal joint and a second metal joint. The first metal joint connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer. One surface of the surface of the second metal joint on the side of the first semiconductor element layer and the surface of the second metal joint on the side of the second semiconductor element layer is connected to a fourth wiring pattern disposed between the first semiconductor element layer and the second metal joint, or a second wiring pattern disposed between the second semiconductor element layer and the second metal joint. The entire other surface of the surface of the second metal joint on the side of the first semiconductor element layer and the surface of the second metal joint on the side of the second semiconductor element layer is in contact with an insulating material.

Effect of the Invention

[0011] According to the present invention, in a photoelectric conversion device in which a plurality of semiconductor element layers are stacked, uneven heat dissipation can be reduced.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 6

Figure 7

Figure 8A

Figure 8B

Figure 8C

Figure 9A

Figure 9B

Figure 9C

Figure 10A

Figure 10B

Figure 10C

Figure 11

Figure 12A

Figure 12B

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Figure 14

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Figure 19A

Figure 19B

Figure 19C

Figure 19D

Figure 19E

Figure 19F

Figure 20

Figure 21

Embodiments for Carrying Out the Invention

[0013] The following embodiments are for embodying the technical idea of the present invention and do not limit the present invention. The sizes and positional relationships of the members shown in each drawing may be exaggerated for clarity of explanation. In the following description, the same components may be denoted by the same numbers and the description thereof may be omitted.

[0014] Figure 1 shows a photoelectric conversion device according to each embodiment. The photoelectric conversion device is, for example, a semiconductor device that can be used as an image sensor, a photometric sensor, or a distance measurement sensor.

[0015] The photoelectric conversion device is a laminate of chip 1 and chip 2. Chip 1 has a semiconductor element layer 11 (first semiconductor element layer) including a pixel circuit included in pixel 10 and a wiring structure 12 (first wiring structure). In this specification, the "semiconductor element layer" includes not only a semiconductor layer but also a gate of a transistor formed on the semiconductor layer. The wiring layer of the wiring structure is not included in the "semiconductor element layer". Chip 2 has a wiring structure 24 (second wiring structure) and a semiconductor element layer 23 (second semiconductor element layer) including an electric circuit. As will be described later, the wiring structure 12 of chip 1 and the wiring structure 24 of chip 2 are joined by a metal joint formed by joining the wiring layers included in each wiring structure. The metal joint is a structure in which the metal constituting the wiring layer and the metal constituting the wiring layer are directly joined.

[0016] Although details will be described later, the elements constituting pixel 10 are arranged in semiconductor element layer 11. Note that a part of the configuration of pixel 10 may be arranged in semiconductor element layer 11 and another part of the configuration may be arranged in semiconductor element layer 23. In this case, examples of the configuration of the pixel circuit arranged in semiconductor element layer 11 among pixel 10 include a photoelectric conversion element such as a photodiode. The pixel circuit including the photoelectric conversion element is arranged in a two-dimensional array in semiconductor element layer 11 in plan view. In this specification, "plan view" refers to viewing from a direction perpendicular to the bonding surface between chip 1 and chip 2. Semiconductor element layer 11 has a pixel region in which a plurality of pixel circuits are arranged in a two-dimensional array. In FIG. 1, a plurality of photoelectric conversion elements constituting a plurality of pixel circuits are arranged in a two-dimensional array in the row direction and the column direction in semiconductor element layer 11.

[0017] Wiring structure 12 includes M (M is an integer of 1 or more) layers of wiring layers and an interlayer insulating material. Wiring structure 24 includes N (N is an integer of 1 or more) layers of wiring layers and an interlayer insulating material.

[0018] The semiconductor element layer 23 includes an electric circuit. For convenience of explanation, in FIG. 1, the configuration illustrated on the upper surface of the chip 2 is the configuration arranged in the semiconductor element layer 23. The electric circuit is, for example, any one of the transistors constituting the row scanning circuit 20, the column scanning circuit 21, the signal processing circuit 22, etc. shown in FIG. 1. The signal processing circuit 22 is, for example, at least any one or a combination of a part of the configuration of the pixel 10 such as an amplification transistor, a selection transistor, a reset transistor, etc., an amplification circuit, a selection circuit, a logical operation circuit, an AD conversion circuit, a memory, a circuit performing compression processing, synthesis processing, etc.

[0019] The pixel 10 can refer to the minimum unit of the circuit repeatedly arranged to form an image. And the pixel circuit included in the pixel 10 and arranged in the semiconductor element layer 11 only needs to include at least a photoelectric conversion element. The pixel circuit may include a configuration other than the photoelectric conversion element. For example, the pixel circuit may further include at least any one of a transfer transistor, an FD, a reset transistor, an amplification transistor, a capacitive addition transistor, a selection transistor. Typically, a selection transistor and a group of elements connected to a signal line via the selection transistor constitute the pixel 10. That is, the selection transistor may be the outer edge of the pixel circuit. Alternatively, a combination of a photoelectric conversion element and a transfer transistor may constitute the pixel 10. In addition, a combination of one or more photoelectric conversion elements and one amplification circuit or one AD conversion circuit may also constitute the pixel 10.

[0020] In FIG. 2, the pixel circuit is constituted by photoelectric conversion elements 101A, 101B, transfer transistors 102A, 102B, an FD 103, a reset transistor 104, an amplification transistor 105, selection transistors 106A, 106B, capacitive addition transistors 107A, 107B. As shown in FIG. 2, a plurality of photoelectric conversion elements may be included in one pixel circuit, or one photoelectric conversion element may be included in one pixel circuit.

[0021] Each component included in the pixel circuit will be described below. In the following descriptions, when the explanations are common, the subscripts such as A and B will be omitted.

[0022] The photoelectric conversion element 101 is an element that generates electrons and holes by photoelectric conversion. As the photoelectric conversion element 101, for example, a photodiode can be used. The transfer transistor 102 controls whether to transfer the signal charges generated in the photoelectric conversion element 101 to the floating diffusion (FD) 103. The reset transistor 104 controls whether to set the potential of the FD 103 or the potential of the photoelectric conversion element 101 to the reference potential. The capacitance addition transistor 107 controls whether to add capacitance to the FD 103. The amplification transistor 105 amplifies and outputs a signal based on the signal charges transferred to the FD. The selection transistor 106 is connected to the amplification transistor 105 and the output line 17. When the selection transistor 106 is turned on, the signal output from the amplification transistor 105 is transmitted to the output line 17. When the pixel circuit does not include the selection transistor, the on / off of the amplification transistor is controlled to control whether to output a signal to the signal line. The output line 17 is connected to the signal processing circuit 22 in FIG. 1. Also, signals from the row scanning circuit 20 in FIG. 1 are supplied to the gates of the transfer transistor 102, the reset transistor 104, the amplification transistor 105, the selection transistor 106, and the capacitance addition transistor 107. Thereby, the on / off of each transistor is controlled.

[0023] It may be equipped with a rolling shutter function that sequentially reads out row by row from one side of the pixel region to the opposite side, or it may be equipped with a global shutter function that simultaneously transfers and accumulates charges throughout the pixel region. Also, within the pixel region, the exposure time may be different for each block containing a plurality of pixels. In this case, within one block, the number of metal joints 30B is preferably larger than the number of metal joints 30A.

[0024] In the following embodiments, it will be described assuming that the pixel circuit shown in FIG. 2 is arranged on chip 1. Note that since the area of the photoelectric conversion element 201 can be secured without increasing the area of chip 1, the components other than the photoelectric conversion element of the pixel may be arranged on chip 2.

[0025] FIG. 3 is a schematic cross-sectional view for showing the concept of the structure of the photoelectric conversion device. Chip 1 and chip 2 are bonded and laminated at the bonding surface 3. Between the semiconductor element layer 11 of chip 1 and the semiconductor element layer 23 of chip 2, the wiring structure 12 of chip 1 and the wiring structure 24 of chip 2 are located. In FIG. 3, the wiring structure 12 has three wiring layers of wiring layers 121, 122, and 123, and the wiring structure 24 has three wiring layers of wiring layers 241, 242, and 243. And insulating materials 124 and 244 are arranged between the respective wiring layers.

[0026] Each wiring layer has one or a plurality of wiring patterns and an insulating material arranged between the wiring patterns. For example, the wiring layer 122 includes a wiring pattern 122A (first wiring pattern) and a wiring pattern 122B (second wiring pattern). The wiring patterns included in each wiring layer are wiring patterns of wirings in the same layer. In this specification, two separate wirings in the same layer may be referred to as wiring pattern XA and wiring pattern XB. From one viewpoint, wiring pattern XA and wiring pattern XB may be wirings that transmit different potentials, respectively. From another viewpoint, wiring pattern XA and wiring pattern XB may be wirings that are separated from each other in the plane of the wiring layer in which the wiring pattern is arranged. For example, wiring pattern XA and wiring pattern XB are separated from each other by the insulating material arranged therebetween. In this case, wiring pattern XA and wiring pattern XB may constitute one wiring. In other words, the separated wiring pattern XA and wiring pattern XB of a certain wiring layer may be electrically connected via the wiring pattern of another wiring layer.

[0027] In this embodiment, the wiring pattern 122A is electrically connected to the gate of an amplification transistor of a certain pixel circuit. The wiring pattern 122B is electrically connected to a configuration other than the gate of the amplification transistor in the pixel circuit disposed in the semiconductor element layer 11. The wiring pattern 122B is, for example, a wiring for supplying the power supply voltage to the reset transistor or the amplification transistor. Further, the wiring pattern 122B may be a wiring for supplying the ground voltage to the photoelectric conversion element.

[0028] Each wiring pattern of the wiring layers 121, 122, 123, 241, 242, and 243 is made of a metal material. It is preferable that the main component of each wiring pattern of the wiring layers 121, 122, 123, 241, 242, and 243 is copper. That the main component is copper means that more than 50% of the total components are copper. It is preferable that more than 90% of the total components of each wiring pattern of the wiring layers 121, 122, 123, 241, 242, and 243 are copper. Note that each wiring layer may be made of a metal such as aluminum or tungsten. Further, the wiring layers 123 and 243 including the wiring pattern forming the metal junction may be mainly composed of copper, and the wiring layers other than the wiring layers 123 and 243 may be mainly composed of a metal such as aluminum or tungsten. The via plugs connecting the respective wiring layers and the contact plugs connecting the wiring layer and the gate of the transistor or the wiring layer and the semiconductor element layer are also made of a metal such as copper, aluminum, or tungsten.

[0029] Each wiring pattern of the wiring layers 123 and 243 is embedded in a recess formed in the interlayer insulating layer. Each wiring pattern of the wiring layers 123 and 243 can be formed by a damascene process. The wiring pattern of the wiring layer 123 and the wiring pattern of the wiring layer 243 constitute the metal junction 30 by being joined together.

[0030] In this embodiment, some or all of the plurality of metal joints 30 are classified into any one of the metal joints 30A (first metal joint), metal joints 30B (second metal joint), and metal joints 30C (third metal joint). Of course, the plurality of metal joints 30 may include those of types different from these classifications.

[0031] The metal joint 30A is arranged in a region overlapping the pixel region in plan view. The metal joint 30A connects the pixel circuit arranged in the semiconductor element layer 11 and the semiconductor element layer 23. In FIG. 3, it connects the source or drain of the selection transistor 106 of the pixel circuit and the electric circuit arranged in the semiconductor element layer 23. The signal from the photoelectric conversion element is transmitted to the electric circuit of the semiconductor element layer 23 via the metal joint 30A. In FIG. 3, the metal joint 30A and the wiring layers 122 and 242 are connected via the via plugs 15 and 25, but the metal joint 30A and the wiring layers 122 and 242 may be connected without passing through the via plugs. That is, the metal joint 30A and at least one of the wiring layer 122 and the wiring layer 242 may be directly in contact and connected. Further, the via plug 15 may be integrally formed with the wiring pattern of the wiring layer 123 constituting the metal joint 30A. The via plug 25 may be integrally formed with the wiring pattern of the wiring layer 243 constituting the metal joint 30A. By using the dual damascene process, the wiring pattern and the via plug can be integrally formed. The dual damascene process can also be applied to metal joints other than the metal joint 30A.

[0032] The metal joint 30B is electrically connected to one of the semiconductor element layer 11 and the semiconductor element layer 23 in a region overlapping the pixel region in plan view. Note that a contact plug in contact with the one for connecting the metal joint 30B to one of the semiconductor element layer 11 and the semiconductor element layer 23 is not shown in FIG. 3. Also, the metal joint 30B is not connected to the other of the semiconductor element layer 11 and the semiconductor element layer 23 at least in a region overlapping the pixel region in plan view. Not being electrically connected to the other of the semiconductor element layer 11 and the semiconductor element layer 23 in the pixel region means that the metal joint 30B and the other of the semiconductor element layer 11 and the semiconductor element layer 23 are not connected in a region overlapping the pixel region in plan view. In other words, in a region overlapping the pixel region in plan view, none of the contact plugs in contact with the other of the semiconductor element layer 11 and the semiconductor element layer 23 is electrically conductive to the metal joint 30B. On the other hand, those in which the metal joint 30B and the other of the semiconductor element layer 11 and the semiconductor element layer 23 are connected in a region not overlapping the pixel region in plan view are included. For example, in FIG. 3, a configuration in which a ground voltage is supplied to the wiring pattern 122B via a wiring pattern from a region not overlapping the pixel region of the semiconductor element layer 23 is included in the present invention. In FIG. 3, the metal joint 30B is connected to the semiconductor element layer 11 and not connected to the semiconductor element layer 23 in a region overlapping the pixel region in plan view. Also, the metal joint 30B may be connected to both the wiring layer 122 and the wiring layer 242 as long as it is not connected to any of the semiconductor element layer 11 and the semiconductor element layer 23 in a region overlapping the pixel region in plan view.

[0033] From another perspective, on the surface of the metal joint 30B on the semiconductor element layer 11 side, it is connected to the via plug or, via the via plug, to the wiring pattern of the wiring layer 122, and the entire surface of the semiconductor element layer 23 side is in contact with the insulating material. Alternatively, for example, for the metal joint 30B formed by the dual damascene method, a convex portion for connection to the wiring pattern of the wiring layer 122 is provided on the surface of the semiconductor element layer 11 side, and the entire surface of the semiconductor element layer 23 side is in contact with the insulating material. In other words, on one side of the semiconductor element layer 11 and the semiconductor element layer 23, the metal joint 30B is connected to the wiring pattern, and on the other side, it is not connected to the wiring pattern. The via plug and the metal joint 30B may be made of the same material or different materials.

[0034] When the metal joint 30B is configured from this perspective, the metal joint 30B may be connected to both the semiconductor element layer 11 and the semiconductor element layer 23 in the region overlapping the pixel region in plan view.

[0035] Although details will be described later, by connecting the metal joint 30B to the pixel circuit or the semiconductor element layer 23, uneven heat dissipation of the photoelectric conversion device can be reduced. Even if the number of metal joints 30B is one, the effect of reducing uneven heat dissipation can be obtained compared to the case where the metal joint 30B is not arranged. Therefore, the number and position of the metal joints 30B are not limited to the number and position described below.

[0036] The metal joint 30A and the metal joint 30B may be connected to one or both of the wiring layers 122 and 243 via the via plug, or may be directly in contact with and connected to at least one of the wiring layers 122 and 243.

[0037] The metal joint 30C in FIG. 3 is a metal joint that is not electrically connected to both the semiconductor element layer 11 and the semiconductor element layer 23. The metal joint 30C is used, for example, to ensure the bonding strength of each chip. Note that the metal joint 30C may not be provided. That is, even if each of the plurality of metal joints 30 is constituted by only one of the metal joint 30A and the metal joint 30B, the effect of reducing heat dissipation unevenness can be obtained.

[0038] (Embodiment 1) A photoelectric conversion device according to Embodiment 1 will be described with reference to FIGS. 4 to 6. The photoelectric conversion device according to Embodiment 1 includes all the configurations shown in FIGS. 1 to 3.

[0039] FIG. 4 is a schematic plan view showing the arrangement of the metal joints. Briefly, considering a pixel region in which two horizontal scanning lines 16 and one vertical output line 17 are arranged corresponding to each pixel 10, and the pixels 10 are arranged in a 5×5 matrix. Two of the control lines connected to the gates of the transistors in FIG. 2 are shown as the horizontal scanning lines 16 in FIG. 4. One of the output lines 17A and 17B in FIG. 2 is shown as the vertical output line 17 in FIG. 4. Also, wirings 19 are arranged for each column. The wiring 19 may be, for example, a wiring to which a fixed voltage is supplied, or may be floating. The wiring to which a fixed voltage is supplied is, for example, a wiring to which a power supply voltage (e.g., VDD) is supplied or a wiring to which a ground voltage (e.g., GND) is supplied. The reset line VDD in FIG. 2 is shown as the wiring 19 in FIG. 4.

[0040] To which wiring the metal joint 30B is connected can be appropriately set according to the arrangement of the wiring pattern. FIG. 4 shows an example in which the metal joint 30B is connected to the wiring 19. However, the metal joint 30B may be connected to the horizontal scanning line 16 or the vertical output line 17 as in the embodiments described later. Also, when providing the metal joint 30C, a part of the metal joint 30B can be replaced with the metal joint 30C by not connecting it to any wiring pattern.

[0041] In a pixel region arranged in a 5×5 matrix, at least two metal joints 30A for electrically connecting two horizontal scanning lines 16 and a horizontal scanning circuit 20 are provided for each row. Also, at least one metal joint 30A for electrically connecting one vertical output line 17 and a signal processing circuit 22 is provided for each column. In a plan view, the metal joints 30 (30A, 30B) are arranged so as to overlap the configuration (e.g., pixel circuit) of the pixels 10 arranged on the chip 1. In other words, in a plan view, a plurality of metal joints 30 are arranged in a plurality of rows and a plurality of columns. For convenience, a pixel 10 in which a metal joint 30A for electrically connecting the horizontal scanning line 16 and the horizontal scanning circuit 20 is arranged is referred to as a pixel 10A. Also, a pixel in which a metal joint 30A for electrically connecting the vertical output line 17 and the signal processing circuit 22 is arranged is referred to as a pixel 10B. Further, a pixel having a metal joint 30B that is connected to the semiconductor element layer 11 and not connected to the semiconductor element layer 23 in the pixel region is referred to as a pixel 10C.

[0042] FIG. 5A shows a plan schematic view of the wiring layer 122 of the chip 1, showing 7×7 pixels 10 in the pixel region. In FIG. 5A, in addition to the vertical output line 17 and the wiring 19 which are wiring patterns arranged in the wiring layer 122, the positions of the metal joints 30A, 30B, and via plugs 15 in a plan view are shown. In FIG. 5A, the metal joint 30A is indicated by a long dashed line, and the metal joint 30B is indicated by a dotted line. Note that the metal joint 30 is not limited to a quadrangular shape in a plan view, and may have rounded corners of the quadrangle or may be circular. The via plug 15 connects the wiring pattern of the wiring layer 122 and the metal joint 30.

[0043] FIG. 5B shows a plan schematic view of the wiring layer 121 of the chip 1, showing the horizontal scanning line 16 and the via plug 18.

[0044] FIG. 5C is a cross-sectional view taken along the line X-X' in FIGS. 5A and 5B, and FIG. 5D is a cross-sectional view taken along the line Y-Y' in FIGS. 5A and 5B. As shown in FIG. 5D, the pixel 10A and the pixel 10B have a metal joint 30A, and the pixel 10C has a metal joint 30B. In FIG. 5C, the metal joint 30A connects the semiconductor element layer 11 and the semiconductor element layer 23. Also, in FIG. 5C, as described above, the metal joint 30B is not connected to the semiconductor element layer 23 in a region overlapping the pixel region in a plan view. That is, the metal joint 30B does not connect the semiconductor element layer 11 and the semiconductor element layer 23 in a region overlapping the pixel region in a plan view, but is connected to the semiconductor element layer 11 via the wiring layer 122.

[0045] As shown in FIGS. 5A to 5D, two or more metal joints 30B and the wiring pattern 122B of the wiring layer 122 are connected. In the present embodiment, the wiring pattern refers to a wiring layer separated in a plan view. It is preferable that four or more metal joints 30B are connected to the wiring pattern 122B. By connecting the plurality of metal joints 30B to one continuous wiring pattern 122B in this way, the volume of the wiring pattern 122B can be ensured as compared with the case where each metal joint 30B is connected to a separated wiring pattern. Thereby, it becomes easier to radiate heat from the semiconductor element layer 11.

[0046] In a plan view, it is preferable that the area of the wiring pattern 122B is larger than that of the wiring pattern 122A. Thereby, a heat dissipation path can be secured. The comparison of the areas of the wiring pattern 122A and the wiring pattern 122B can be performed, for example, by comparing the wiring patterns corresponding to pixels of 5 rows and 5 columns.

[0047] Also, in the chip 1, when looking at a region of 1000 μm × 1000 μm, the area of the wiring pattern 122B is preferably 10 times or more, and more preferably 20 times or more, the area of the wiring pattern 122A.

[0048] FIG. 6 shows an example of the arrangement pattern of pixel 10A, pixel 10B, and pixel 10C in a pixel region where pixels are arranged in 25 rows and 25 columns with respect to the photoelectric conversion device according to the present embodiment. In the pixel region, there are two pixels 10A each having a metal junction portion 30A arranged in each row, and one pixel 10B having a metal junction portion 30A arranged in each column. And in the other pixels 10C, a metal junction portion 30B is arranged.

[0049] Although details will be described later, as shown in FIG. 6, in the present embodiment, when at least one of the rows and columns is viewed, a metal junction portion 30B is arranged in pixels (pixels 10C) other than the pixels (pixels 10A and 10B) in which the metal junction portion 30A is arranged. That is, the number of metal junction portions 30B is arranged more than that of the metal junction portion 30A. Thereby, in the pixel region, instead of locally connecting the pixel region and the metal junction portion, the region where the pixel region and the metal junction portion are connected can be increased. Therefore, compared with the case where the metal junction portion 30B is not arranged, the uneven heat dissipation can be reduced by arranging the metal junction portion 30B.

[0050] Further, as shown in FIG. 6, since one metal junction portion 30A or 30B is arranged in each pixel 10, the distance between the metal junction portions 30 can be made constant. Thereby, the uneven heat dissipation can be further reduced. Note that a plurality of metal junction portions 30 may be arranged in one pixel 10. Also, the number of metal junction portions 30 arranged may be different depending on the pixel 10. On the other hand, the metal junction portion 30 may not be arranged in some pixels. For example, only one of the pixels 10C in FIG. 6 may have a metal junction portion 30B arranged, and the other pixels 10C may not have a metal junction portion 30 arranged, or a metal junction portion 30C may be arranged.

[0051] Next, the effects of the present embodiment will be described with reference to the comparative examples of FIGS. 7 and 8. First, the configuration in the comparative example will be described.

[0052] FIG. 7 is a schematic plan view showing the arrangement of the metal joints in the comparative example. The difference from Embodiment 1 is that the metal joint 30B is not provided. FIG. 8A is a plan view of the wiring layer 122 in the comparative example. In FIG. 8A, the metal joint 30A is indicated by a long dashed line, and the metal joint 30C is indicated by a long two-dot chain line. Although not shown, the wiring corresponding to the wiring layer 121 is the same as that in FIG. 5B of Embodiment 1. FIG. 8B is a cross-sectional view of the position corresponding to X-X' in FIG. 8A, and FIG. 8C is a cross-sectional view of the position corresponding to Y-Y' in FIG. 8A.

[0053] As shown in FIGS. 8A, 8B, and 8C, in the comparative example, the metal joint 30B is not provided. That is, the plurality of metal joints 30 are constituted by the metal joint 30A or the metal joint 30C that is not connected to either the semiconductor element layer 11 or the semiconductor element layer 23.

[0054] FIG. 14 shows a dark-time image captured by the photoelectric conversion device according to the comparative example and a dark-time image captured by the photoelectric conversion device according to Embodiment 1 under the same conditions. In FIGS. 14(a) and 14(b), the color changes according to the output, and the smaller the output, the closer to black, and the larger the output, the closer to white.

[0055] In FIG. 14(a), it becomes black in the vicinity of the region of the pixel electrically connected via the metal joint 30A. On the other hand, it becomes white in the vicinity of the region of the pixel where the metal joint 30C not connected to the wiring layer 122 is provided. Thus, in the comparative example, output unevenness occurs for each pixel. In contrast, in FIG. 14(b), it is a color close to black as a whole. That is, the output unevenness for each pixel is reduced. Thus, it was confirmed that the output unevenness is reduced in Embodiment 1 compared to the comparative example.

[0056] The speculation of the mechanism of occurrence of output unevenness in the comparative example and the speculation of the mechanism of reduction of output unevenness according to the present embodiment will be described below. The mechanism described below is a speculation by the inventors, and does not limit that the effects of the present invention are obtained by this mechanism.

[0057] The thermal conductivity of copper wiring, which is a general wiring layer, is approximately 400 to 410 [W / mK], while the thermal conductivity of silicon oxide, which is a general interlayer insulating material, is 5 to 15 [W / mK]. In pixels 10A and 10B, the heat generated near the pixels is dissipated to the surroundings through the wiring layer and the metal joint 30A. That is, in pixels 10A and 10B, in addition to the wiring layers 121 and 122, the wiring layers 123 and 243 can also dissipate heat. Therefore, the heat generated near the photoelectric conversion elements of pixel 10A and the photoelectric conversion elements of pixel 10B is dissipated more than the heat generated by the photoelectric conversion elements of pixel 10D. On the other hand, in pixel 10D, there is no metal joint connected to the semiconductor element layer 11. That is, the heat generated near the photoelectric conversion element of pixel 10D can only be dissipated by the wiring layers 121 and 122 connected to pixel 10. Therefore, in the photoelectric conversion elements of pixel 10A with high heat dissipation and pixel 10B, the dark current becomes smaller compared to pixel 10D with low heat dissipation. Thus, it is presumed that output unevenness occurs due to uneven dark current caused by heat.

[0058] On the other hand, in the present embodiment, as shown in FIGS. 5A to 5D, the metal joint 30B and the wiring layer 122 are electrically connected. That is, pixel 10C can dissipate heat not only through the wiring layer 121 and the wiring layer 122 but also through the wiring layer 123 and the wiring layer 243 (metal joint 30B). Therefore, compared with the comparative example, the dark current can be reduced even in pixels other than pixels 10A and 10B. Therefore, since the heat dissipation levels of pixels 10A, 10B, and 10C are the same, it is considered that the output unevenness due to the dark current in the dark image is reduced.

[0059] As described above, in the comparative example, only the metal joint 30A serves as the exhaust heat path and the temperature locally decreases. However, in the present embodiment, the exhaust heat path of the heat generated in the photoelectric conversion element can be increased within the pixel region. Therefore, heat can be dissipated on average, and uneven dark current can be reduced or eliminated.

[0060] Note that the effect of increasing the heat dissipation path can be obtained even if there is only one metal joint 30B. When there is one metal joint 30B, for example, the power supply wiring can be connected to the metal joint 30B. Various variations are conceivable for the metal joint 30B, such as when one metal joint 30B is arranged for m×n pixels, or when one metal joint 30B is arranged for each column. Even in these cases, the effect of increasing the heat dissipation path can be obtained.

[0061] In this embodiment, all the metal joints 30 are constituted by either the metal joint 30A or the metal joint 30B, but it is not limited thereto. For example, the metal joints 30B may be arranged discretely. As an example, a configuration in which a metal joint 30C is arranged between the metal joints 30B can be cited. Even in this case, it is clear that the non-uniformity of the dark current is reduced as compared with FIG. 14(a). For example, a structure in which a metal joint 30C is arranged between the metal joints 30B is also included in the present invention. Also, even when a metal joint 30C is arranged between the metal joints 30B, the non-uniformity of the dark current can be reduced as compared with the comparative example. In this case, it is preferable that the metal joints 30B are arranged at a predetermined interval. Thereby, the non-uniformity of the dark current can be further reduced.

[0062] It is sufficient that the wiring pattern of the wiring layer 123 and the wiring pattern of the wiring layer 243 are in contact and joined, but in order to ensure the joining strength, it is preferable that the interlayer insulating material 124 of the wiring layer 123 and the interlayer insulating material 244 of the wiring layer 243 are also joined.

[0063] As described above, according to the configuration of Embodiment 1, the output non-uniformity due to the dark current can be reduced as compared with the comparative example.

[0064] (Embodiment 2) The photoelectric conversion device according to Embodiment 2 will be described with reference to FIG. 9. In the photoelectric conversion device according to Embodiment 2, a wiring layer 125 is disposed between a wiring layer 121 and a wiring layer 122, and the difference is that the wiring patterns of the wiring layer 122 are different from those in Embodiment 1. Since the configurations other than those described below are the same as those in Embodiment 1, the description may be omitted. Further, the photoelectric conversion device according to Embodiment 2 includes all the configurations of FIGS. 1 to 3.

[0065] FIG. 9A is a plan view of the wiring layer 122 in the photoelectric conversion device according to Embodiment 2, FIG. 9B is a cross-sectional view of a position corresponding to X-X' in FIG. 9A, and FIG. 9C is a cross-sectional view of a position corresponding to Y-Y' in FIG. 9A.

[0066] In FIG. 9A, wiring patterns 122A, 122B, 122C, metal joints 30A, 30B, and via plugs 15 are shown. The wiring patterns 122B and 122C are VDD wirings to which a power supply voltage is supplied or GND wirings to which a ground voltage is supplied. In the present embodiment, no vertical output line 17 is disposed in the wiring layer 122. A wiring layer 125 is disposed between the wiring layer 121 and the wiring layer 122. And the vertical output line 17 is included in the wiring layer 125. Thereby, the vertical output line 17 is not restricted by the arrangement in the plan view of the wiring patterns 122B and 122C. Therefore, it is possible to arrange a plurality of vertical output lines 17 in the pixel 10. Therefore, by simultaneously reading signals from the plurality of vertical output lines 17 in the signal processing circuit 22, the reading speed can be improved.

[0067] Further, since the wiring patterns 122B and 122C are power supply wirings or GND wirings, they can be arranged with wirings thicker than the output lines without restrictions on wiring capacitance. Therefore, the areas of the wiring patterns 122B and 122C become larger, and it becomes easier to connect to the plurality of metal joints 30B. The heat dissipation at the metal joint 30B becomes larger and becomes more uniform with the heat dissipation at the metal joint 30A. Therefore, the output unevenness due to dark current can be further reduced.

[0068] The area in plan view of the wiring patterns 122B and 122C connected via the metal joint 30B and the via plug 15 is larger than the area in plan view of the wiring pattern 122A connected via the metal joint 30A and the via plug 15. Also, two or more metal joints 30B are connected to the wiring pattern 122B and the wiring pattern 122C.

[0069] (Embodiment 3) The photoelectric conversion device according to Embodiment 3 will be described with reference to FIG. 10. The photoelectric conversion device according to Embodiment 3 is different from Embodiment 1 and Embodiment 2 in that the electric circuit of chip 2 is connected to the metal joint 30B, and the metal joint 30B is not connected to the semiconductor element layer 11 of chip 1. Since the configuration other than that described below is the same as that of Embodiment 1 or 2, the description may be omitted. Also, the photoelectric conversion device according to Embodiment 3 includes all the configurations of FIGS. 1 to 3.

[0070] FIG. 10A shows a plan view of the wiring layer 122 of chip 1 in Embodiment 3, FIG. 10B is a cross-section at a position corresponding to X-X' in FIG. 10A, and FIG. 10C is a cross-section at a position corresponding to Y-Y' in FIG. 10A.

[0071] In FIG. 10A, the wiring patterns 122A, 122B, 122C, the metal joint 30B, and the via plug 15 are shown. This embodiment is different from Embodiment 2 in that the wiring patterns 122B and 122C, which are power supply wiring or GND wiring, are not electrically connected to the metal joint 30B. Also, this embodiment is different from Embodiment 2 in that a wiring layer 245 is provided between the wiring layer 242 and the wiring layer 243. Further, in Embodiment 3, a pixel 10E in which the metal joint 30B and the wiring layer 245 are connected via the via plug 25 is arranged. Also, two or more metal joints 30B are connected to the wiring pattern of the wiring layer 245.

[0072] In Embodiment 3, the metal joint 30B disposed in the pixel 10E is connected to the wiring layer 245 by the via plug 25. That is, heat dissipation in the chip 2 disposed in the pixel 10E can be dissipated not only through the connected wiring layers 241, 242, and 245, but also through the wiring layer 243 and the wiring layer 123, similar to the pixels 10A and 10B. Therefore, heat can be dissipated in the pixel 10E as well, and heat dissipation unevenness is less likely to occur. Also, since the degree of heat dissipation in the pixels 10A and 10E is uniform, unevenness due to dark current in the dark-time image is reduced.

[0073] According to the present embodiment, when an electric circuit that easily generates heat is arranged in the semiconductor element layer 23, heat dissipation unevenness can be reduced.

[0074] (Embodiment 4) The photoelectric conversion device according to Embodiment 4 is different from Embodiment 1 in that the metal joint 30B is physically connected to the semiconductor element layer 23 but not electrically connected. Since the configuration other than that described below is the same as that of Embodiment 1, the description may be omitted. Also, the photoelectric conversion device according to Embodiment 4 includes all the configurations shown in FIGS. 1 to 3.

[0075] FIG. 11 shows a cross-sectional view of the photoelectric conversion device according to the present embodiment.

[0076] As shown in FIG. 11, the metal joint 30B in the present embodiment is connected to the pixel circuit of the semiconductor element layer 11 and is also connected to the semiconductor element layer 23, but is not connected to the signal processing circuit of the semiconductor element layer 23. That is, the signal passing through the metal joint 30B is not output as a signal from the pixel.

[0077] That is, in the present embodiment, the metal joint 30B is a metal joint that is not connected to the signal processing circuit of the semiconductor element layer 23. Four or more metal joints 30B are connected to one metal layer.

[0078] The joining position of the metal joint 30B and the semiconductor element layer 23 is preferably separated from the electric circuit so that noise does not enter the signal from the pixel.

[0079] According to this embodiment, similar to Embodiment 1, heat generated in the pixel circuit can be exhausted to the metal joint 30B, and uneven heat dissipation can be reduced. Furthermore, according to this embodiment, since heat can escape from the metal joint 30B to the semiconductor element layer 23, there is a possibility that uneven heat dissipation can be further reduced.

[0080] (Embodiment 5) The photoelectric conversion device according to Embodiment 5 is different from Embodiment 1 in that the metal joint 30B is connected to the same wiring pattern as the wiring pattern to which the metal joint 30A is connected, but is not electrically connected to the signal processing circuit of the semiconductor element layer 23. Since the configuration other than that described below is the same as that of Embodiment 1, the description may be omitted. In addition, the photoelectric conversion device according to Embodiment 5 includes all the configurations of FIGS. 1 to 3.

[0081] FIG. 12 shows a plan schematic view and a cross-sectional schematic view of the arrangement positions of the metal joints 30A and 30B of the photoelectric conversion device according to this embodiment. The metal joint 30A is a metal joint that connects the semiconductor element layer 11 and the semiconductor element layer 23. The metal joint 30B is connected to the semiconductor element layer 11 and is not connected to the semiconductor element layer 23 at a position overlapping the pixel region in plan view.

[0082] The metal joint 30B is connected to the same wiring pattern 122C as the metal joint 30A. The wiring pattern 122C is, for example, a wiring that supplies a fixed potential. For example, the wiring pattern 123C is a wiring connected to the source or drain of the reset transistor.

[0083] The surface of the metal joint 30B on the semiconductor element layer 23 side is in contact with an insulating material. That is, it is not electrically connected to the wiring pattern arranged in the wiring structure 24.

[0084] According to this embodiment, similar to Embodiment 1, when the metal joint 30B is not provided, that is, when the metal joint and the wiring layer are not connected, uneven heat dissipation can be reduced.

[0085] (Modification example) In Embodiments 1 to 5, the metal joint 30B is connected to one of the wiring layers arranged above and below the metal joint 30B and is not connected to the other. However, this is not the only case. As shown in FIG. 13, both of the wiring layers arranged above and below the metal joint 30B may be connected to the metal joint 30B. Specifically, the metal joint 30B only needs to be not electrically connected to the semiconductor element layer 11 or the semiconductor element layer 23 in the pixel region, and may be electrically connected to the wiring layer 122 or the wiring layer 241 through via plugs. In this case, although the number of steps for forming the via plugs increases, the wiring area can be increased, so that the dark current can be further reduced.

[0086] (Embodiment 6) FIG. 15 is a block diagram showing the configuration of the photoelectric conversion system 500 according to the present embodiment. The photoelectric conversion system 500 of this embodiment includes a photoelectric conversion device 2000 to which any of the configurations of the above-described photoelectric conversion devices is applied. In FIG. 15, an imaging system is shown as the photoelectric conversion system 500. Specific examples of the imaging system include a digital still camera, a digital camcorder, a surveillance camera, and the like. The photoelectric conversion system 500 includes a photoelectric conversion device 2000, a lens 5020, a diaphragm 504, and a barrier 506 for protecting the lens 5020. The photoelectric conversion system 500 includes a signal processing unit 5080 (image signal generation unit) that processes the output signal output from the photoelectric conversion device 2000. The signal processing unit 5080 performs signal processing operations such as various corrections and compressions on the input signal and outputs the result as necessary. The signal processing unit 5080 may have a function of performing AD conversion processing on the output signal output from the photoelectric conversion device 2000. The photoelectric conversion system 500 further includes a buffer memory unit 510 for temporarily storing image data, and an external interface unit (external I / F unit) 512 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 500 includes a recording medium 514 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 516 for recording or reading from the recording medium 514.

[0087] Furthermore, the photoelectric conversion system 500 includes an overall control and arithmetic unit 518 that performs various operations and controls the entire digital still camera, and a timing generation unit 520 that outputs various timing signals to the photoelectric conversion device 2000 and the signal processing unit 5080. The photoelectric conversion device 2000 outputs an image signal to the signal processing unit 5080. The signal processing unit 5080 performs predetermined signal processing on the image signal output from the photoelectric conversion device 2000 and outputs image data. In addition, the signal processing unit 5080 generates an image using the image signal.

[0088] By configuring a photoelectric conversion system using the photoelectric conversion device of each of the above-described embodiments, an imaging system capable of acquiring higher-quality images can be realized.

[0089] (Embodiment 7) The photoelectric conversion system and the moving body of this embodiment will be described with reference to FIG. 16. In this embodiment, an example of an imaging system for an in-vehicle camera is shown. FIG. 16 shows an example of a vehicle system and an imaging system mounted thereon. The photoelectric conversion system 701 includes a photoelectric conversion device 702, an image preprocessing unit 715, an integrated circuit 703, and an optical system 714. The optical system 714 forms an optical image of a subject on the photoelectric conversion device 702. The photoelectric conversion device 702 converts the optical image of the subject formed by the optical system 714 into an electrical signal. The photoelectric conversion device 702 is any one of the photoelectric conversion devices of the above-described embodiments. The image preprocessing unit 715 performs predetermined signal processing on the signal output from the photoelectric conversion device 702. At least two sets of the optical system 714, the photoelectric conversion device 702, and the image preprocessing unit 715 are provided in the photoelectric conversion system 701, and the output from each set of image preprocessing units 715 is input to the integrated circuit 703.

[0090] The integrated circuit 703 is an integrated circuit for photoelectric conversion system applications and includes an image processing unit 704 including a memory 705, an optical distance measurement unit 706, a parallax calculation unit 707, an object recognition unit 708, and an abnormality detection unit 709. The image processing unit 704 performs image processing such as development processing and defect correction on the output signal of the image preprocessing unit 715. The memory 705 stores the primary storage of the captured image and the defect positions of the captured pixels. The optical distance measurement unit 706 performs focusing and distance measurement of the subject. The parallax calculation unit 707 calculates the parallax (phase difference of the parallax image) from a plurality of image data acquired by a plurality of photoelectric conversion devices 702. The object recognition unit 708 recognizes subjects such as vehicles, roads, signs, and people. When the abnormality detection unit 709 detects an abnormality in the photoelectric conversion device 702, it reports the abnormality to the main control unit 713.

[0091] The integrated circuit 703 may be implemented by dedicatedly designed hardware, may be implemented by software modules, or may be implemented by a combination of these. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc., or may be implemented by a combination of these.

[0092] The main control unit 713 comprehensively controls the operations of the photoelectric conversion system 701, the vehicle sensor 710, the control unit 720, etc. Note that a method may also be adopted in which the photoelectric conversion system 701, the vehicle sensor 710, and the control unit 720 do not have the main control unit 713 and each has a communication interface, and each performs transmission and reception of control signals via a communication network (for example, the CAN standard).

[0093] The integrated circuit 703 has a function of receiving a control signal from the main control unit 713 or transmitting a control signal and a set value to the photoelectric conversion device 702 by its own control unit. For example, the integrated circuit 703 transmits settings for signal-driving a voltage switch in the photoelectric conversion device 702, settings for switching the voltage switch for each frame, etc.

[0094] The photoelectric conversion system 701 is connected to the vehicle sensor 710 and can detect the running state of the host vehicle such as vehicle speed, yaw rate, and steering angle, as well as the state of the external environment of the host vehicle and the state of other vehicles / obstacles. The vehicle sensor 710 is also a distance information acquisition means for acquiring distance information from the parallax image to the object. In addition, the photoelectric conversion system 701 is connected to a driving assistance control unit 711 that performs various driving assistances such as automatic steering, automatic cruise, and collision prevention functions. In particular, regarding the collision determination function, based on the detection results of the photoelectric conversion system 701 and the vehicle sensor 710, the collision with other vehicles / obstacles is estimated and the presence or absence of a collision is determined. Thereby, avoidance control when a collision is estimated and activation of a safety device at the time of a collision are performed.

[0095] In addition, the photoelectric conversion system 701 is also connected to an alarm device 712 that issues an alarm to the driver based on the determination result of the collision determination unit. For example, when the collision determination unit determines that there is a high possibility of a collision, the main control unit 713 performs vehicle control to avoid the collision and reduce damage, such as applying the brakes, returning the accelerator, and suppressing the engine output. The alarm device 712 warns the user by sounding an alarm such as a sound, displaying alarm information on the display screen of a display unit such as a car navigation system or a meter panel, or applying vibration to the seat belt or the steering wheel.

[0096] In this embodiment, the photoelectric conversion system 701 captures images of the surroundings of the vehicle, for example, the front or the rear. Fig. 16(b) shows an example of the arrangement of the photoelectric conversion system 701 when imaging the front of the vehicle with the photoelectric conversion system 701.

[0097] In addition, in this embodiment, although the control for not colliding with other vehicles has been described, it is also applicable to controls such as automatic driving while following other vehicles and automatic driving so as not to deviate from the lane. Furthermore, the photoelectric conversion system 701 can be applied not only to vehicles such as the host vehicle, but also to moving bodies (moving devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving bodies, but also to devices that widely utilize object recognition, such as advanced road traffic systems (ITS).

[0098] (Embodiment 8) The photoelectric conversion device according to Embodiment 8 will be described with reference to Figs. 17 and 18. The photoelectric conversion device according to Embodiment 8 is different from Embodiment 1 in that some of the plurality of pixels 10 arranged in the pixel region 100 are shielded from light. In addition, a pad region 27 in which pads 28 are arranged is arranged in the semiconductor element layer 11. Since the configurations other than these points and those described below are the same as those in Embodiment 1, the description may be omitted.

[0099] Fig. 17 shows a plan view of the corner of the semiconductor element layer 11, and Fig. 18 shows a cross-sectional view taken along the line X-X' of Fig. 17. As shown in Fig. 17, a pad region 27 in which a plurality of pads 28 are arranged is disposed on the outer periphery of the pixel region 100 in plan view. Each pad 28 conducts electricity between the photoelectric conversion device and a signal processing device or the like disposed outside the photoelectric conversion device. The plurality of pads 28 include a pad for outputting a signal from the photoelectric conversion device to the outside and a pad for inputting a power supply voltage or the like to the photoelectric conversion device. The pads for inputting the power supply voltage and the pads for outputting the signal can be arranged at arbitrary positions. For example, the pads for inputting the power supply voltage and the pads for outputting the signal may be arranged alternately, or the pads for outputting the signal may be arranged at a predetermined interval and the pads for inputting the power supply voltage may be arranged therebetween. Further, the output pads may be arranged together and the input pads may be arranged in other regions.

[0100] A power supply region 26 is disposed between the pad region 27 and the pixel region 100. The boundary between the pad region 27 and the power supply region 26 can be defined by, for example, a light-shielding film 13. The region where the light-shielding film 13 is disposed without the photoelectric conversion element can be used as the power supply region 26, and the region from the end of the light-shielding film 13 to the end of the semiconductor element layer 11 can be used as the pad region 27.

[0101] The light-shielding film 13 is disposed so as to overlap a plurality of pixels 10 disposed in the vicinity of the power supply region 26 and the pad region 27 in plan view. The pixels that overlap the light-shielding film 13 in plan view can function as optical black pixels (OB pixels) for detecting a reference value of the black level. As shown in Fig. 17, the pixel region 100 has an OB pixel region 100B in which a plurality of OB pixels are arranged and an effective pixel region 100A in which pixels that are not provided with the light-shielding film 13 and that receive light are arranged.

[0102] As shown in Fig. 18, the pad 28 includes a trench that penetrates the semiconductor element layer 11. The trench is formed in the depth direction from the light incident surface of the semiconductor element layer 11 and is formed to a depth that reaches the wiring pattern of the wiring layer 242 of the chip 2. In the pad 28, conduction is achieved by wire bonding to the wiring layer 242 formed on the chip 2.

[0103] In the OB pixel region 100B, a metal joint 30A is arranged. In FIG. 18, the metal joint 30A is connected to the semiconductor element layer 11 and the semiconductor element layer 23. The metal joint 30A arranged in the OB pixel region 100B in FIG. 18 outputs the signal of the OB pixel to the semiconductor element layer 23. Note that in the OB pixel region 100B, a metal joint that is connected to one of the semiconductor element layer 11 and the semiconductor element layer 23 and not connected to the other may be arranged.

[0104] In the power supply region 26, a metal joint 30D for inputting the power supply voltage input from the pad 28 to the semiconductor element layer 11 and the semiconductor element layer 23 is arranged. The metal joint 30D is arranged in a region that does not overlap the pixel region 100 in plan view, and is a metal joint that connects the semiconductor element layer 11 and the semiconductor element layer 23. Through the metal joint 30D, the power supply voltage is input to the pixels of the semiconductor element layer 11. When supplying a common power supply voltage to the semiconductor element layer 11 and the semiconductor element layer 23, the power supply voltage input from the pad 28 can be supplied to the semiconductor element layer 11 and the semiconductor element layer 23 through the metal joint 30D.

[0105] In the pad region 27, a metal joint 30C that is not connected to both the semiconductor element layer 11 and the semiconductor element layer 23 is arranged. Thereby, the bonding strength between the chip 1 and the chip 2 can be ensured.

[0106] Note that the pad 28 for supplying the power supply voltage may be divided for each semiconductor element layer. For example, a certain pad 28 may be configured to supply the power supply voltage to the semiconductor element layer 11 and not supply the power supply voltage to the semiconductor element layer 23. And different pads 28 may be configured not to supply the power supply voltage to the semiconductor element layer 11 but to supply the power supply voltage to the semiconductor element layer 23. In this case, a metal joint 30B is arranged in the power supply region 26.

[0107] Pads for inputting a power supply voltage to the semiconductor element layer 11 and the semiconductor element layer 23 and pads for supplying a power supply voltage to one of the semiconductor element layers may be mixed. Further, in the power supply region 26, a metal bonding portion 30C that is not connected to both the semiconductor element layer 11 and the semiconductor element layer 23 may be provided to ensure the bonding strength between the chip 1 and the chip 2. For example, in the power supply region 26, the metal bonding portion 30A disposed between each pad 28 and the pixel 1 closest to each pad 28 is connected to the semiconductor element layer 11 and the semiconductor element layer. And a metal bonding portion 30C may be arranged at other metal bonding portions.

[0108] Further, in the pad region 27, a metal bonding portion 30A that is not connected to the pad 28 and is connected to the semiconductor element layer 11 and the semiconductor element layer 23, and a metal bonding portion 30B that is connected to one of the semiconductor element layers may be provided.

[0109] According to the present embodiment, as in the first embodiment, unevenness in output due to dark current can be reduced as compared with the comparative example. Further, by arranging the metal bonding portion 30C at a suitable position, the bonding strength between the chip 1 and the chip 2 can be ensured.

[0110] (Embodiment 9) The photoelectric conversion device according to the present embodiment will be described with reference to FIGS. 19A to 19F and FIG. 21. The photoelectric conversion device according to the present embodiment is different from the eighth embodiment in that the wiring structure 12 of the chip 1 has five wiring layers. Since the configuration other than this point and the following description is the same as that of the eighth embodiment, the description may be omitted.

[0111] FIG. 21 shows a circuit diagram of a pixel in the present embodiment. In the present embodiment, the capacitive addition transistor 107A is different from the pixel circuit described with reference to FIG. 2 in that it is divided into a switch transistor 109 and a capacitor 108. This makes it easier to improve the dynamic range and linearity at low ISO sensitivity. The gate electrode of the switch transistor 109 is controlled by a control line, and a fixed power supply voltage (for example, VDD) is supplied to the gate of the capacitor 108.

[0112] The wiring structure 12 is arranged such that, in order from the side of the semiconductor element layer 11, there are a wiring layer 121 (metal 1), a wiring layer 127 (metal 2), a wiring layer 126 (metal 3), a wiring layer 125 (metal 4), a wiring layer 122 (metal 5), and a wiring layer 123 (metal 6).

[0113] FIG. 19A is a plan layout view showing the wiring layer 123, the wiring layer 122, and the via plug 15 connecting the wiring layer 123 and the wiring layer 122. As described above, the wiring layer 123 has a wiring pattern forming a metal joint. The wiring pattern of the wiring layer 123 is indicated by a broken line or a dotted line. The wiring pattern 122A of the wiring layer 122 is connected to the metal joint 30A connected to the semiconductor element layer 11 and the semiconductor element layer 23 via a via plug. Also, the wiring pattern 122B of the wiring layer 122 is connected to a metal joint 30B that is connected to the semiconductor element layer 11 but not to the semiconductor element layer 23 in a region overlapping the pixel region in plan view. Note that in FIG. 9A, it is not necessary that all the metal joints 30B are not connected to the semiconductor element layer 23, and some of the metal joints 30B may be connected to the VDD of the semiconductor element layer 23. In this embodiment, the case where the wiring pattern 122B is a VDD wiring will be described as an example, but it is not limited thereto.

[0114] The wiring pattern 122B is arranged in a mesh shape by partially forming slits in the wiring layer 122 in plan view. In this way, in the pixel region, by increasing the area of the wiring pattern 122B with respect to the wiring pattern A, heat from the semiconductor element layer 11 can be easily dissipated.

[0115] Note that instead of the wiring layer 123 in FIG. 19A, a wiring layer as shown in FIG. 20 may be used. In FIG. 20, the wiring pattern 122B is arranged between a plurality of metal joints 30B arranged in the row direction, column direction, and diagonal direction, which is different from the wiring layer shown in FIG. 19A. That is, in a plan view, an insulating material is not arranged except between the wiring pattern 122B and the wiring pattern 122A, and the wiring pattern 122B may be continuously arranged. In this case, compared with FIG. 19A, the area of the wiring pattern can be increased, so that the heat generated in the semiconductor element layer 11 can be more easily dissipated.

[0116] FIG. 19B is a plan layout diagram showing the wiring layer 125 and the via plug 18 connecting the wiring layer 125 and the wiring layer 122. The wiring layer 125 has a wiring pattern 125D connected to the wiring pattern 122B, and wiring patterns 125A, 125B, and 125C connected to the wiring pattern 122A. The wiring pattern 125D is a wiring pattern connected to the metal joint 30B. Also, the wiring patterns 125A, 125B, and 125C are wiring patterns connected to the metal joint 30A. The wiring patterns 125A, 125B, and 125C constitute the vertical output lines 17. In FIG. 19B, since a part of the pixels in the pixel region is enlarged and shown, the via plug 18 is connected only to some of the vertical output lines. In a region not shown, it is connected to the wiring pattern of the vertical output line 17 and the wiring layer 122 via the via plug 18.

[0117] In the wiring layer 125, the thickness of the wiring pattern 125D is thicker than that of the wiring patterns 125A, 125B, and 125C. This makes it easier to secure a heat exhaust path from the semiconductor element layer 11. In this layer, the thickness of the wiring pattern refers to the width in the left-right direction. For example, the width of each wiring pattern in a direction perpendicular to the longitudinal direction of the vertical output lines 17A to 17L is defined as the thickness.

[0118] FIG. 19C is a plan layout diagram showing a wiring layer 126 and via plugs connecting the wiring layer 126 and the wiring layer 125. Wiring patterns 126A and 126B constitute a vertical output line 17. The wiring pattern 126B is connected to the wiring pattern 125C. Among the vertical output lines, the wiring patterns 126A, 125B, and 125C have misaligned pitches. That is, the wiring pattern arranged in the wiring layer 126 and extending in the column direction like the wiring pattern 126A does not overlap in plan view with the wiring pattern arranged in the wiring layer 125 and extending in the column direction like the wiring patterns 125B and 125C. That is, the wiring pattern extending in the vertical direction of the wiring layer 126 is positioned between the wiring patterns extending in the vertical direction of the wiring layer 125. Then, the signal output from the pixel from the wiring pattern 125C is read via the wiring pattern 126B.

[0119] The wiring pattern 126C is connected to the wiring pattern 125D. Also, a wiring pattern 126D is arranged in the wiring layer 126. The wiring pattern 126D constitutes a GND wiring.

[0120] FIG. 19D is a plan layout diagram showing a wiring layer 127 and via plugs connecting the wiring layer 127 and the wiring layer 126. The wiring patterns 127A and 127B are wirings connected to the vertical output line. As shown in FIG. 19D, in the wiring patterns 127A and 127B, the positions of the via plugs are shifted row by row. Thereby, the vertical output lines connected in the wiring layer 126 and the wiring layer 126 are changed row by row.

[0121] The wiring pattern 127C is connected to the wiring pattern 126C and constitutes the VDD wiring. The wiring pattern 127D is connected to the wiring pattern 126D and constitutes the GND wiring. The wiring patterns 127E to 127K are the control lines of the respective transistors. The wiring patterns 127E to 127K are connected to the wiring pattern 126E in FIG. 19C at one or more points for each row of the pixel array. The control pulse signal output from the row scanning circuit shown in FIG. 1 is supplied to the wiring pattern 126E via the metal junction 30A and the via plug, and the respective transistors are controlled by the wiring patterns 127E to 127K connected to the wiring pattern 126E via the via plug. The wiring pattern 127L is arranged so that the potential of the source of the amplification transistor is supplied, and is arranged to overlap the FD and the FD wiring in a plan view. Thereby, the FD is shielded.

[0122] FIG. 19E is a plan layout diagram showing the wiring layer 121 and the via plug connecting the wiring layer 121 and the wiring layer 127. The wiring pattern 121A is connected to the wiring pattern 127A and is a wiring connected to the vertical output line. The wiring pattern 121B is connected to the wiring pattern 127B and is a wiring connected to the vertical output line. The wiring pattern 121C is connected to the wiring pattern 127C and constitutes the VDD wiring. The wiring pattern 127D is connected to the wiring pattern 127D and constitutes the GND wiring.

[0123] The wiring patterns 121E to 121K are the control lines of the respective transistors. The connection relationship between each of the wiring patterns 121E to 121K and each transistor will be described later.

[0124] The wiring pattern 121L is connected to the wiring pattern 127L. The wiring pattern 121M is a wiring connecting the FD and the gate of the amplification transistor.

[0125] FIG. 19F is a plan layout diagram showing a semiconductor region and polysilicon. Reference numerals 101 to 109 respectively correspond to each component of the circuit diagram of the pixel shown in FIG. 21.

[0126] The gate of transfer transistor 102A is connected to wiring pattern 121J. Wiring pattern 121J functions as a control line for transfer transistor 102A. The gate of transfer transistor 102B is connected to wiring pattern 121K. Wiring pattern 121K functions as a control line for transfer transistor 102B.

[0127] As described above, FD and the gate of amplification transistor 105 are connected by wiring pattern 121M. Also, the source of amplification transistor 105 is connected to wiring pattern 121L. The drain of amplification transistor 105 is connected to wiring pattern 121C, which constitutes the VDD wiring.

[0128] The gate of capacitive addition transistor 107B is connected to wiring pattern 121E. Wiring pattern 121E functions as a control line for capacitive addition transistor 107B.

[0129] As described above, capacitive addition transistor 107A includes switch transistor 109 and capacitor 108. The gate of switch transistor 109 is connected to wiring pattern 121F. Wiring pattern 121F functions as a control line for switch transistor 109. The gate of capacitor 108 is connected to wiring pattern 121C.

[0130] As shown in FIG. 19F, the channel length of capacitor 108 is made longer than the channel length of switch transistor 109. Thereby, the capacitance of capacitor 108 can be increased, so that it is possible to improve the dynamic range at low ISO sensitivity. Also, the channel length of switch transistor 109 is made shorter than the channel length of capacitor 108. As a result, the ON characteristics of the switch transistor 109 can be improved, so that it becomes possible to improve the linearity at low ISO sensitivity. Further, by separating into the capacitor 108 and the switch transistor 109, the threshold voltages Vth of the capacitor-added transistor 107B, the capacitor 108, and the switch transistor 109 can be changed. Therefore, it becomes possible to change the ON characteristics and the OFF characteristics of each transistor, and it becomes possible to achieve both the dynamic range and the linearity according to the ISO sensitivity.

[0131] The gate of the reset transistor 104 is connected to the wiring pattern 121I. The wiring pattern 121I is a control line of the reset transistor 104. The drain of the reset transistor 104 is connected to the wiring pattern 121C.

[0132] The drains of the selection transistor 106A and the selection transistor 106B are constituted by a common semiconductor region. And the drains of the selection transistor 106A and the selection transistor 106B are connected to the wiring pattern 121L. The gate of the selection transistor 106A is connected to the wiring pattern 121H. The wiring pattern 121H functions as a control line of the selection transistor 106A. The gate of the selection transistor 106B is connected to the wiring pattern 121G. The wiring pattern 121G functions as a control line of the selection transistor 106B. The source of the selection transistor 106A is connected to the wiring pattern 121A. Also, the source of the selection transistor 106B is connected to the wiring pattern 121B.

[0133] Each pixel is provided with a contact 110 for supplying a fixed potential to the well of the semiconductor element layer. The fixed potential is, for example, a power supply voltage (for example, VDD) or a set voltage (for example, GND). In this way, the contact 110 is preferably arranged for each pixel in consideration of the imaging performance for each pixel, but the contact 110 may be arranged at intervals.

[0134] Also in this embodiment, similar to Embodiment 1, output unevenness due to dark current can be reduced as compared with the comparative example.

[0135] In the drawings of this embodiment, although the area of the wiring pattern connected to the metal joint 30B is increased in the wiring layer 125 and the wiring layer 122, it is not limited thereto. For example, in other wiring layers such as the wiring layer 121 and the wiring layer 127, the area of the wiring pattern connected to the metal joint 30B may be increased.

[0136] (Other Embodiments) As described above, each embodiment has been described, but the present invention is not limited to these embodiments, and various changes and modifications are possible. Also, each embodiment can be applied to each other.

Description of Reference Numerals

[0137] 1 Chip 1 2 Chip 2 3 Bonding surface 11 First semiconductor element layer 23 Second semiconductor element layer 30A First metal joint 30B Second metal joint

Claims

1. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, A second chip having a second semiconductor element layer, and The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer, The plurality of metal joints include a first metal joint and a second metal joint arranged in a region overlapping the pixel region in a plan view, The first metal joint connects at least one of the plurality of pixel circuits to the second semiconductor element layer, The second metal joint is connected to at least one of the plurality of pixel circuits and is not connected to the second semiconductor element layer in a region overlapping the pixel region in a plan view. A photoelectric conversion device characterized by that.

2. A first wiring pattern and a second wiring pattern are arranged between the second semiconductor element layer and the plurality of metal joints, The first metal joint is connected to the first wiring pattern, The photoelectric conversion device according to claim 1, wherein the second metal joint is not connected to the second wiring pattern.

3. The surface of the second metal joint on the side of the second semiconductor element layer is in contact with an insulating material. The photoelectric conversion device according to claim 2.

4. A first wiring pattern and a second wiring pattern are arranged between the second semiconductor element layer and the plurality of metal joints, The first metal joint is connected to the first wiring pattern, The photoelectric conversion device according to claim 1, wherein the second metal joint is connected to the second wiring pattern.

5. The surface of the second metal joint on the side of the first semiconductor element layer is in contact with a via plug. The photoelectric conversion device according to any one of claims 1 to 4.

6. The photoelectric conversion device according to any one of claims 2 to 4, wherein the second metal joint has a convex portion connected to the second wiring pattern.

7. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, A second chip having a second semiconductor element layer, and The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer, The plurality of metal joints include a first metal joint and a second metal joint arranged in a region overlapping the pixel region in a plan view, The first metal bonding portion connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer. The second metal bonding portion is connected to the second semiconductor element layer and is not connected to any of the plurality of pixel circuits in a region overlapping the pixel region in a plan view. A photoelectric conversion device characterized by this.

8. A third wiring pattern and a fourth wiring pattern are arranged between the first semiconductor element layer and the plurality of metal bonding portions. The first metal bonding portion is connected to the third wiring pattern. The photoelectric conversion device according to claim 7, wherein the second metal bonding portion is not connected to the fourth wiring pattern.

9. The surface of the second metal bonding portion on the side of the first semiconductor element layer is in contact with an insulating material. The photoelectric conversion device according to claim 8.

10. A third wiring pattern and a fourth wiring pattern are arranged between the first semiconductor element layer and the plurality of metal bonding portions. The first metal bonding portion is connected to the third wiring pattern. The photoelectric conversion device according to claim 7, wherein the second metal bonding portion is connected to the fourth wiring pattern.

11. The surface of the second metal bonding portion on the side of the second semiconductor element layer is in contact with a via plug. The photoelectric conversion device according to any one of claims 7 to 10.

12. The photoelectric conversion device according to any one of claims 8 to 10, wherein the second metal bonding portion has a convex portion connected to the fourth wiring pattern.

13. A first chip having a first semiconductor element layer including a plurality of pixel circuits, A second chip having a second semiconductor element layer, The first chip and the second chip are joined by a plurality of metal bonding portions between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal bonding portions include a first metal bonding portion and a second metal bonding portion. The first metal bonding portion connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer. A fourth wiring pattern is disposed between four or more of the second metal joints among the plurality of metal joints and the first semiconductor element layer, and one fourth wiring pattern is connected to each of the four or more second metal joints, or a second wiring pattern is disposed between four or more of the second metal joints among the plurality of metal joints and the second semiconductor element layer, and one second wiring pattern is connected to each of the four or more second metal joints. A photoelectric conversion device characterized by this.

14. A first chip having a first semiconductor element layer including a plurality of pixel circuits, A second chip having a second semiconductor element layer, and The first chip and the second chip are joined by a plurality of metal joints between the first semiconductor element layer and the second semiconductor element layer, The plurality of metal joints include a first metal joint and a second metal joint, The first metal joint connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer, One of the surface of the second metal joint on the side of the first semiconductor element layer and the surface of the second metal joint on the side of the second semiconductor element layer is connected to a fourth wiring pattern disposed between the first semiconductor element layer and the second metal joint, or a second wiring pattern disposed between the second semiconductor element layer and the second metal joint, A photoelectric conversion device characterized in that the entire other surface of the second metal joint on the side of the first semiconductor element layer and the surface of the second metal joint on the side of the second semiconductor element layer is in contact with an insulating material.

15. The photoelectric conversion device according to claim 13 or 14, wherein the second metal joint is connected to the fourth wiring pattern via a via plug.

16. The photoelectric conversion device according to claim 14 or 15, wherein the second metal joint has a convex portion connected to the second wiring pattern or the fourth wiring pattern.

17. The photoelectric conversion device according to any one of claims 1 to 16, wherein a wiring to which a fixed voltage is supplied is connected to the second metal joint.

18. The photoelectric conversion device according to claim 17, wherein the wiring to which the fixed voltage is supplied is a VDD wiring.

19. The photoelectric conversion device according to any one of claims 1 to 18, wherein an output line is connected to the first metal joint.

20. The photoelectric conversion device according to any one of claims 1 to 19, wherein the main component of the metal joint is copper.

21. Each of the plurality of pixel circuits includes a photoelectric conversion element, The photoelectric conversion device according to any one of claims 1 to 20, wherein one of the metal joints is correspondingly arranged for one of the photoelectric conversion elements.

22. The plurality of metal joints are arranged in a plurality of rows and a plurality of columns in a plan view, The photoelectric conversion device according to claim 21, wherein, among the metal joints arranged in a predetermined row, the number of the second metal joints is larger than the number of the first metal joints.

23. The photoelectric conversion device according to claim 22, wherein, among the metal joints arranged in a predetermined column, the number of the second metal joints is larger than the number of the first metal joints.

24. In a plan view, the area of the wiring pattern connected to the second metal joint is arranged in the same layer as the second metal joint and is larger than the area of the wiring pattern connected to the first metal joint. The photoelectric conversion device according to any one of claims 1 to 23.

25. When looking at a region of 1000 μm × 1000 μm, the area of the wiring pattern connected to the second metal joint is arranged in the same layer as the second metal joint and is 10 times or more the area of the wiring pattern connected to the first metal joint. The photoelectric conversion device according to claim 24.

26. The photoelectric conversion device according to claim 24 or 25, wherein the wiring pattern connected to the second metal joint is arranged in a mesh shape.

27. The photoelectric conversion device according to any one of claims 1 to 26, wherein the second metal joint is connected to an electric circuit arranged in the second semiconductor element layer.

28. The photoelectric conversion device according to claim 27, wherein the electric circuit is a circuit that processes signals from the pixel circuit.

29. The photoelectric conversion device according to any one of claims 1 to 28, wherein the plurality of metal joints include a third metal joint that is not connected to the first semiconductor element layer and the second semiconductor element layer.

30. A photoelectric conversion system comprising the photoelectric conversion device according to any one of claims 1 to 29, and a signal processing unit that processes a signal obtained by the photoelectric conversion device.

31. The photoelectric conversion device according to any one of claims 1 to 29, distance information acquisition means for acquiring distance information to an object based on a signal from the photoelectric conversion device; and control means for controlling a moving body based on the distance information, wherein the moving body is characterized by having the above.

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