Ceramic electronic component, and method of manufacturing ceramic electronic component

Abstract

To provide: a ceramic electronic component which achieves larger capacity smaller size at low cost; and a method of manufacturing the ceramic electronic component.SOLUTION: A ceramic electronic component comprises a multilayer chip including a laminated portion where a plurality of dielectric layers and a plurality of internal layers are alternately laminated. The plurality of internal layers is alternately pulled out to opposed two end faces of the multilayer chip. The multilayer chip includes a side margin outside a capacitance part which is a region where a plurality of internal layers is opposed to each other in a third direction orthogonal to a first direction, in which the plurality of internal layers is opposed to each other, and a second direction in which the two end faces are opposed to each other. The plurality of internal layers includes a first internal layer and a second internal layer. The first internal layer includes a protruding region which protrudes from the second internal layer outward of the capacitance part in the third direction. The protruding region includes an oxidized part of a metal component. On a cross section including the second direction and the third direction, when a length of the oxidized part in the protruding region is defined as do1 and a length of an oxidized part in a side margin side end of the second internal layer is defined as do2, a relation of do1>do2 is satisfied.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the ceramic electronic component.

Background Art

[0002] In a high-frequency communication system typified by a mobile phone, ceramic electronic components such as multilayer ceramic capacitors are used (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For ceramic electronic components such as multilayer ceramic capacitors, thinning of the dielectric layer, thinning of the internal electrode layer, maximization of the area of the internal electrode layer (minimization of the margin portion), high stacking, etc. are required due to market demands for large capacity and miniaturization.

[0005] However, thinning of the dielectric layer is accompanied by an increase in the electric field strength. Therefore, depending on firing conditions such as the firing temperature and atmosphere, control of the solid solution state of trace additives in the dielectric material may be performed. Here, when the oxygen partial pressure is high, oxygen penetrates into the internal electrode layer, and local oxidation of the internal electrode layer and diffusion / segregation of metal elements added to the internal electrode layer and dielectric layer easily cause deterioration of characteristics. In addition, maximization of the area of the internal electrode layer (minimization of the margin portion) shortens the distance between the surface of the ceramic component and the internal electrode layer (oxygen intrusion path), making the above problems more likely to occur. In particular, oxygen easily penetrates from between the internal electrode layers on the side surface compared to the cover surface, and the above problems are likely to occur.

[0006] On the other hand, it is conceivable to suppress the oxidation of the internal electrode layer by adding a precious metal component to the internal electrode material or ensuring a margin amount. However, precious metals are precious and expensive, resulting in problems with securing components and profitability. In recent years, ceramic electronic components have been required to have large capacity and small size, and there may be a problem that the effective capacity area is limited by the method of ensuring the margin amount.

[0007] The present invention has been made in view of the above problems, and an object thereof is to provide a ceramic electronic component and a manufacturing method thereof that can achieve large capacity and small size at low cost.

Means for Solving the Problems

[0008] The ceramic electronic component according to the present invention includes a laminated chip including a laminated portion in which a plurality of dielectric layers and a plurality of internal layers are alternately laminated. The plurality of internal layers are alternately drawn out to two opposing end faces of the laminated chip. The laminated chip has a side margin outside a capacitance portion that is a region where the plurality of internal layers face each other in a third direction orthogonal to a first direction in which the plurality of internal layers face each other and a second direction in which the two end faces face each other. The plurality of internal layers include a first internal layer and a second internal layer containing a metal component in the capacitance portion. The first internal layer has a protruding region that protrudes outward from the capacitance portion in the third direction more than the second internal layer. The protruding region includes an oxidized portion of the metal component. In a cross section including the second direction and the third direction, the length of the oxidized portion of the protruding region is d o1 is defined as, and the length of the oxidized portion of the side margin side end of the second internal layer is d o2 When defined as, d o1 >d o2 The relationship of holds.

[0009] In the cross section of the ceramic electronic component, the length of the protruding region is d w is defined as, and the distance between the protruding regions of the two first internal layers adjacent to each other in the first direction is d T When defined as, d T ×0.5 <d wThe relationship may hold.

[0010] In the cross-section of the ceramic electronic component, the length of the protruding region is d w Let the distance between the protruding regions of the adjacent two layers of the first internal layer be d T When this is the case, d T ×0.2 < d o1 < d w ×1.0, and the relationship may hold.

[0011] In the cross-section of the ceramic electronic component, the length of the protruding region is d w Let the distance between the protruding regions of the adjacent two layers of the first internal layer be d T When this is the case, d w / d T is 50% or more, and d o1 / d w may be less than 100%.

[0012] In the ceramic electronic component, the plurality of internal layers may be alternately displaced in the third direction.

[0013] In the ceramic electronic component, the first internal layer has the protruding regions with respect to both of the side margins, more than the second internal layer, and among the plurality of internal layers, the two outermost layers in the first direction may be the first internal layer.

[0014] In the ceramic electronic component, the thickness from the end of the capacitance portion in the third direction to the outer surface of the side margin may be 150 μm or less.

[0015] The manufacturing method of the ceramic electronic component according to the present invention includes a step of forming an internal electrode pattern on a dielectric green sheet, a step of forming a dielectric pattern around the internal electrode pattern, laminating the dielectric green sheet on which the internal electrode pattern and the dielectric pattern are formed in a first direction, and shifting the ends of the internal electrode pattern alternately in a second direction so that at least two adjacent internal electrode patterns are shifted in a third direction orthogonal to the first direction and the second direction to obtain a laminate, a first firing of firing the laminate, then performing vacuum pulse firing, and then performing a second firing at an oxygen partial pressure higher than that of the first firing.

Advantages of the Invention

[0016] According to the present invention, it is possible to provide a ceramic electronic component and a manufacturing method thereof that can achieve large capacity and miniaturization at low cost.

Brief Description of the Drawings

[0017]

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MODE FOR CARRYING OUT THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings.

[0019] (First Embodiment) First, an overview of the structure of the multilayer ceramic capacitor 100 according to the first embodiment will be described. FIG. 1 is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a and 20b provided on two opposing end faces of the laminated chip 10. Among the four surfaces of the laminated chip 10 other than the two end faces, the two surfaces other than the upper and lower surfaces in the lamination direction are referred to as side surfaces. The external electrodes 20a and 20b extend on the upper surface, lower surface, and two side surfaces of the laminated chip 10 in the lamination direction. However, the external electrodes 20a and 20b are spaced apart from each other.

[0020] In FIGS. 1 to 3, the Z-axis direction (the first direction) is the stacking direction and is the direction in which each internal layer 12 faces. The X-axis direction (the second direction) is the length direction of the stacked chip 10, is the direction in which the two end faces of the stacked chip 10 face each other, and is the direction in which the external electrode 20a and the external electrode 20b face each other. The Y-axis direction (the third direction) is the width direction of the internal layer 12 and is the direction in which two side faces other than the two end faces of the four side faces of the stacked chip 10 face each other. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

[0021] The stacked chip 10 has a configuration in which a dielectric layer 11 containing a ceramic material that functions as a dielectric and internal layers 12 are alternately stacked. The edges of each internal layer 12 are alternately drawn out to the end face provided with the external electrode 20a of the stacked chip 10 and the end face provided with the external electrode 20b. Thereby, each internal layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are stacked via the internal layers 12. Further, in the stacking of the dielectric layer 11 and the internal layer 12, internal layers 12 are arranged in the outermost layers on both sides in the stacking direction, and the internal layer 12 of the outermost layer is covered with a cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the cover layer 13 may have the same composition as or a different composition from the dielectric layer 11.

[0022] The size of the multilayer ceramic capacitor 100 is, for example, a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm, or a length of 0.4 mm, a width of 0.2 mm, and a height of 0.2 mm, or a length of 0.6 mm, a width of 0.3 mm, and a height of 0.3 mm, or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm, or a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm, or a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm, but is not limited to these sizes.

[0023] The inner layer 12 is mainly composed of base metals such as nickel (Ni), copper (Cu), tin (Sn), and alloys thereof. As the main component of the inner layer 12, noble metals such as platinum (Pt), palladium (Pd), silver (Ag), gold (Au), and alloys containing these may also be used. The inner layer 12 may contain ceramic particles such as co-materials. The average thickness per layer of the inner layer 12 in the Z-axis direction is, for example, 0.5 μm or less, preferably 0.4 μm or less. The average thickness per layer of the inner layer 12 can be measured by observing the cross-section of the multilayer ceramic capacitor 100 with an SEM (scanning electron microscope), measuring the thickness at 10 points each for 10 different inner layers 12, and deriving the average value of all the measurement points.

[0024] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3, for example. Note that the perovskite structure contains ABO 3-α deviating from the stoichiometric composition. For example, as the ceramic material, at least one of barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), Ba forming a perovskite structure 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), etc. can be selected and used. Ba 1-x-y Ca x Sr y Ti 1-z Zr zO3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanium zirconate, calcium titanium zirconate, and barium calcium titanium zirconate. For example, in the dielectric layer 11, the main component ceramic is contained at 90 at% or more. The average thickness per layer of the dielectric layer 11 in the Z-axis direction is, for example, 1.0 μm or less, and preferably 0.8 μm or less. The average thickness per layer of the internal layer 12 in the Z-axis direction can be measured by observing a cross-section of the multilayer ceramic capacitor 100 with an SEM (scanning electron microscope), measuring the thickness at 10 points each for 10 different dielectric layers 11, and deriving the average value of all measurement points.

[0025] An additive may be added to the dielectric layer 11. Examples of additives to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0026] As illustrated in FIG. 2, the region where the internal layer 12 connected to the external electrode 20a and the internal layer 12 connected to the external electrode 20b face each other is the region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where the capacitance is generated is referred to as the capacitance portion 14. That is, the capacitance portion 14 is the region where adjacent internal layers 12 connected to different external electrodes face each other.

[0027] A region where the internal layers 12 connected to the external electrode 20a face each other without passing through the internal layer 12 connected to the external electrode 20b is referred to as an end margin 15. Also, a region where the internal layers 12 connected to the external electrode 20b face each other without passing through the internal layer 12 connected to the external electrode 20a is also the end margin 15. That is, the end margin 15 is a region where the internal layers 12 connected to the same external electrode face each other without passing through the internal layer 12 connected to a different external electrode. The end margin 15 is a region that does not generate capacitance.

[0028] As illustrated in FIG. 3, in the multilayer chip 10, the first side margin 16a and the second side margin 16b are regions provided so as to cover the respective end portions (end portions in the Y-axis direction) on both side surfaces of the dielectric layer 11 and the internal layer 12. That is, the first side margin 16a and the second side margin 16b are regions provided outside the capacitance portion 14 in the Y-axis direction. The first side margin 16a and the second side margin 16b are also regions that do not generate capacitance.

[0029] FIG. 4 is an enlarged cross-sectional view near the external electrode 20a. In FIG. 4, the hatching is omitted. As illustrated in FIG. 4, a plating layer 22 may be provided on the outer surface of the external electrode 20a with the external electrode 20a as an underlayer. The external electrode 20a has Cu as a main component. The external electrode 20a may contain a glass component. The plating layer 22 has a metal such as Cu, Ni, aluminum (Al), zinc (Zn), Sn, or an alloy of two or more of these as a main component. The plating layer 22 may be a plating layer of a single metal component or a plurality of plating layers of different metal components. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in order from the external electrode 20a side. The first plating layer 23 is, for example, a Cu plating layer. The second plating layer 24 is, for example, a Ni plating layer. The third plating layer 25 is, for example, a Sn plating layer. Note that although FIG. 4 illustrates the external electrode 20a, a plating layer 22 may be similarly provided on the outer surface of the external electrode 20b.

[0030] For the multilayer ceramic capacitor 100 to meet the market demand for large capacitance and small size, thinning of the dielectric layer 11, thinning of the internal layer 12, maximizing the facing area between the internal layers 12 in the capacitance portion 14 (minimizing the margin portion), high stacking, etc. are required. However, thinning of the dielectric layer 11 is accompanied by an increase in the electric field strength. Therefore, depending on the firing conditions such as the firing temperature and atmosphere, the solid solution state of trace additives to the dielectric material may be controlled. Here, when the oxygen partial pressure is high, oxygen penetrates into the internal layer 12, and local oxidation of the internal layer 12 and accompanying diffusion and segregation of metal elements added to the internal layer 12 and the dielectric layer 11 easily cause deterioration of characteristics. Also, maximizing the facing area between the internal layers 12 in the capacitance portion 14 (minimizing the margin portion) shortens the distance between the surface of the ceramic component and the internal layer 12 (the oxygen penetration path), making the above problems more likely to occur. In particular, the side surface of the Y-axis direction end face is more likely to have oxygen penetrate from between the internal layers 12 compared to the cover surface of the Z-axis direction end face, and the above problems are likely to occur.

[0031] On the other hand, it is conceivable to suppress the oxidation of the internal layer 12 by adding a precious metal component to the internal electrode material or ensuring a margin amount. However, precious metals are precious and expensive, causing problems in securing components and profitability. Also, in recent years, the multilayer ceramic capacitor 100 has been required to have a large capacitance and small size, and there may be a problem that the facing area between the internal layers 12 in the capacitance portion 14 is limited by the method of ensuring the margin amount.

[0032] Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration that can achieve large capacitance and small size at low cost. Details will be described below.

[0033] FIG. 5 is a schematic cross-sectional view for explaining the details of the laminated structure in the multilayer ceramic capacitor 100. The cross-sectional view of FIG. 5 corresponds to the YZ cross-section. As illustrated in FIG. 5, among the internal layers 12 included in the multilayer ceramic capacitor 100, the first internal layer 12a protrudes toward the first side margin 16a more than the second internal layer 12b. Among the internal layers 12, the second internal layer 12b protrudes toward the second side margin 16b more than the first internal layer 12a. The first internal layer 12a and the second internal layer 12b are alternately laminated. In the first internal layer 12a, a region that protrudes toward the first side margin 16a more than the second internal layer 12b is referred to as a first protruding region 31. In the second internal layer 12b, a region that protrudes toward the second side margin 16b more than the first internal layer 12a is referred to as a second protruding region 32.

[0034] In the Y-axis direction, the first side margin 16a is located outside each first internal layer 12a. In other words, the first side margin 16a is located outside the first internal layer 12a that is the outermost in the Y-axis direction among each first internal layer 12a. Between the first side margin 16a and the capacitor portion 14, a ceramic component and the first protruding region 31 are mixed. The region between the first side margin 16a and the capacitor portion 14 is referred to as the first mixed region 17a. On the other hand, in the Y-axis direction, the second side margin 16b is located outside each second internal layer 12b. In other words, the second side margin 16b is located outside the second internal layer 12b that is the outermost in the Y-axis direction among each second internal layer 12b. Between the second side margin 16b and the capacitor portion 14, a ceramic component and the second protruding region 32 are mixed. The region between the second side margin 16b and the capacitor portion 14 is referred to as the second mixed region 17b. When there are variations at both ends in the Y-axis direction of the first internal layer 12a and the second internal layer 12b in the capacitor portion 14, the end of the capacitor portion 14 on the first side margin 16a side in the Y-axis direction is the end on the first side margin 16a side of the ones that extend most toward the first side margin 16a among each second internal layer 12b, and the end of the capacitor portion 14 on the second side margin 16b side in the Y-axis direction is the end on the second side margin 16b side of the ones that extend most toward the second side margin 16b among each first internal layer 12a.

[0035] FIG. 6(a) is a partially enlarged view of FIG. 5. As illustrated in FIGS. 5 and 6(a), the first protruding region 31 includes an oxidized portion 33 at the end on the first side margin 16a side. The oxidized portion 33 is an oxide of the main component metal of the first inner layer 12a and the second inner layer 12b. The second inner layer 12b may or may not include the oxidized portion 33 at the end on the first side margin 16a side. Further, as illustrated in FIG. 5, the second protruding region 32 includes an oxidized portion 33 at the end on the second side margin 16b side. The first inner layer 12a may or may not include the oxidized portion 33 at the end on the second side margin 16b side. Note that the first inner layer 12a and the second inner layer 12b mainly contain metal in the capacitive portion 14 in the YZ cross section and function as electrodes.

[0036] As illustrated in FIG. 6(b), let the length of the first protruding region 31 be d w . Further, let the distance (shortest distance) between the first protruding region 31 of the first inner layer 12a and the first protruding region 31 of the adjacent first inner layer 12a be d T . Let the length of the oxidized portion 33 of the first protruding region 31 be d o1 . Let the length of the oxidized portion 33 at the end on the first side margin 16a side of the second inner layer 12b be d o2 . Note that d w , d o1 , d o2 are in the length direction in which the first protruding region 31 protrudes toward the inside of the first side margin 16a. For d T , it may be the average value of the shortest distances between the first protruding regions 31 of the first inner layer 12a of all layers. In the inner layer, by EPMA, a portion where the main component metal and oxygen coexist synchronously in the inner layer can be specified as the oxidized portion.

[0037] In the present embodiment, the relationship of d o1 >d o2 holds. Note that if the second inner layer 12b does not include the oxidized portion 33, d o2is zero. According to this configuration, even if oxygen enters from the side surface on the first side margin 16a side of the multilayer ceramic capacitor 100 in the Y-axis direction, it reaches the oxidized portion 33 of the first internal layer 12a before reaching the second internal layer 12b. Since the oxygen that has entered is used to cause the oxidation of the oxidized portion 33 to proceed prior to the oxidation of the metal region, the oxidized portion 33 captures the oxygen, making it difficult for the oxygen to reach the capacitor portion 14. Thereby, the oxidation of the metal component in the capacitor portion 14 is suppressed. Further, since the first internal layers 12a are separated from each other, even if the oxidized portion 33 is formed in the first internal layer 12a, local structural deterioration is suppressed, and reliability degradation and short circuits can be suppressed. That is, desired electrical characteristics can be realized.

[0038] Next, the upper diagram in FIG. 7 is a diagram illustrating a case where both ends of each internal layer 12 in the Y-axis direction are aligned and no oxidized portion is provided at both ends of each internal layer 12 in the Y-axis direction. As illustrated in the upper diagram of FIG. 7, in this case, since no oxidized portion for capturing the oxygen that has entered the first side margin 16a and the second side margin 16b is provided, the oxygen easily reaches the capacitor portion 14. Therefore, the first side margin 16a and the second side margin 16b have to be thickened in the Y-axis direction. In this case, since the margin amount increases, it becomes difficult to increase the capacitance in a limited size.

[0039] In contrast, the lower diagram of FIG. 7 is a diagram illustrating the present embodiment. As illustrated in the lower diagram of FIG. 7, since oxygen can be captured by the oxidized portions 33 of the first protruding region 31 and the oxidized portions 33 of the second protruding region 32, it becomes difficult for oxygen to reach the capacitive portion 14. Thereby, the first side margin 16a and the second side margin 16b can be thinned in the Y-axis direction. Further, since the first protruding region 31 and the second protruding region 32 contain a large amount of the oxidized portion 33, they are portions that do not contribute to the capacitance. Accordingly, since the distance (oxygen intrusion path) between the surface of the ceramic component and the internal layer 12 becomes longer, the first side margin 16a and the second side margin 16b can be thinned in the Y-axis direction. Further, not only can the side margin be thinned, but by adopting the present embodiment, each of the first internal layer 12a and the second internal layer 12b can be printed longer in the Y-axis direction. Therefore, the intersection area between the first internal layer 12a and the first internal layer 12b can be increased, and a higher capacitance than before can be realized. Thereby, it becomes possible to increase the capacitance within a limited size.

[0040] As described above, according to the present embodiment, since desired electrical characteristics can be realized without adding a large amount of noble metal to the internal layer, an inexpensive configuration can be achieved. Further, since the margin amount can be reduced, it is possible to realize a large-capacity and small-size configuration.

[0041] Next, referring to FIG. 6(b) again. The longer the first protruding region 31 is, the more oxygen can be captured by the first protruding region 31. Therefore, d w is preferably longer. If d T is small, the distance between the first protruding regions 31 of the first internal layers 12a of two adjacent layers becomes short. Therefore, it is preferable to define the lower limit of d w in relation to d T . In the present embodiment, it is preferable that d T ×0.5 < d w , and it is more preferable that d T < d w .

[0042] The longer the oxidation part 33 of the first protruding region is, the more oxygen can be captured in the first protruding region 31. For example, d T ×0.2 < d o1 < d w ×1.0 is preferable, and d T ×0.5 < d o1 < d w ×0.75 is more preferable.

[0043] In order to capture oxygen in the first protruding region 31, d w / d T is 50% or more, and d o1 / d w is preferably less than 100%. Here, the percentage means that if each ratio is 1, it is 100%.

[0044] FIG. 8 is a diagram illustrating a case where the first protruding region 31 of the first inner layer 12a extends in a direction different from the Y-axis direction. In this case, the length d w of the first protruding region 31 means the length between the end on the first side margin 16a side of the first inner layer 12a and the end on the first side margin 16a side of the second inner layer 12b in the direction in which the first protruding region 31 extends toward the first side margin 16a. Also, the length d o1 of the oxidation part 33 of the first protruding region 31 means the length of the oxidation part 33 of the first protruding region 31 in the direction in which the first protruding region 31 extends.

[0045] Note that, as illustrated in FIG. 9, in the first protruding region 31, there may be a case where the oxidation part 33 is interrupted in the Y-axis direction and becomes a plurality of spaced-apart oxidation parts. In this case, the length d o1 of the oxidation part 33 can be defined as the sum of the lengths of each oxidation part 33 in the first protruding region 31.

[0046] According to the present embodiment, the first side margin 16a and the second side margin 16b can be thinned in the Y-axis direction. For example, in the Y-axis direction, the total thickness of the first side margin 16a and the first mixed region 17a, and the total thickness of the second side margin 16b and the second mixed region 17b are preferably 150 μm or less, more preferably 70 μm or less, respectively. Alternatively, in the Y-axis direction, the total thickness of the first side margin 16a and the first mixed region 17a, and the total thickness of the second side margin 16b and the second mixed region 17b are preferably 5% or less, more preferably 2% or less, with respect to the width of the multilayer ceramic capacitor 100 in the Y-axis direction.

[0047] Subsequently, a method for manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 10 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100.

[0048] (Raw material powder production step) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, barium titanate is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate.

[0049] A predetermined additive compound is added to the obtained ceramic powder according to the purpose. Examples of the additive compound include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium), or oxides containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0050] For example, a compound containing an additive compound is wet-mixed with ceramic raw material powder, dried, and pulverized to prepare a ceramic material. For example, for the ceramic material obtained as described above, the particle size may be adjusted by pulverization treatment as necessary, or the particle size may be adjusted by combining with a classification treatment. Through the above steps, a dielectric material is obtained.

[0051] (Coating process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet-mixed. Using the obtained slurry, a dielectric green sheet 51 is coated on a substrate by, for example, the die coater method or the doctor blade method and dried. The substrate is, for example, a polyethylene terephthalate (PET) film. The figure illustrating the coating process is omitted.

[0052] (Internal electrode formation process) Next, as illustrated in FIG. 11(a), an internal electrode pattern 52 for an internal layer is arranged by printing a metal conductive paste for forming an internal electrode containing an organic binder on the surface of the dielectric green sheet 51 by screen printing, gravure printing, or the like. In addition to nickel, ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferably the same as the ceramic that is the main component of the dielectric layer 11.

[0053] Next, a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based organic solvent are added to the dielectric pattern material obtained in the raw material powder production process, and kneaded with a roll mill to obtain a dielectric pattern paste for a reverse pattern layer. As illustrated in FIG. 11(a), on the dielectric green sheet 51, a dielectric pattern 53 is arranged by printing the dielectric pattern paste in the peripheral region where the internal electrode pattern 52 is not printed, and the step with the internal electrode pattern 52 is filled. The dielectric green sheet 51 on which the internal electrode pattern 52 and the dielectric pattern 53 are printed is referred to as a lamination unit.

[0054] (Lamination process) Thereafter, as illustrated in FIG. 11(b), the internal layers 12 and the dielectric layer 11 are alternately arranged, and the edges of the internal layers 12 are alternately exposed at both end faces of the dielectric layer 11 in the X-axis direction and are alternately led out to a pair of external electrodes 20a and 20b having different polarities. Also, the internal layers 12 are alternately displaced in the Y-axis direction, and the lamination units are laminated. For example, the number of laminated internal electrode patterns 52 is set to 100 to 500 layers.

[0055] (Pressing process) A predetermined number (for example, 2 to 10 layers) of cover sheets are laminated on the top and bottom of the laminate in which the lamination units are laminated, and thermocompression bonding is performed. The cover sheet is also a green sheet containing ceramic powder.

[0056] (Chip formation process) The obtained ceramic laminate is cut into a predetermined size to form chips.

[0057] (Firing process) The ceramic laminate thus obtained is subjected to a debinding treatment in an N2 atmosphere, and then a metal paste that becomes the external electrodes 20a and 20b is applied by a dipping method. The oxygen partial pressure is 10 -12 MPa to 10 -9 MPa, and a first firing is performed for 5 minutes to 10 hours in a reducing atmosphere of 1160 °C to 1280 °C (for example, 1180 °C or higher and 1230 °C or lower). Thereafter, vacuum pulse firing is performed on the obtained laminated chip 10. In the vacuum pulse firing, for example, under the conditions of 1000 °C and N2 of 10 -3 MPa, the O2 partial pressure is increased to 10 -3 MPa and maintained for 3 seconds, and this is performed 5 times. Thereby, oxygen can be sent to the vicinity of both sides at both ends of the laminated chip 10 in the Y-axis direction. Thereafter, a second firing is performed in an atmosphere having a higher oxygen partial pressure than the first firing. In the second firing, for example, it is preferable that the oxygen partial pressure in the atmosphere is 0.015 atm or higher, and it is more preferable that the oxygen partial pressure is 0.02 atm or higher.

[0058] (Re-oxidation treatment process) In order to return oxygen to barium titanate, which is the partially reduced main phase of the dielectric layer 11 fired in a reducing atmosphere, heat treatment may be performed in a mixed gas of N2 and water vapor at about 1000 °C or in the atmosphere at 500 °C to 700 °C to such an extent that the internal layer 12 is not oxidized. This process is called a reoxidation treatment process.

[0059] (Plating process) Thereafter, metal coatings such as copper, nickel, and tin are formed on the external electrodes 20a and 20b by plating. Through the above processes, the multilayer ceramic capacitor 100 is completed.

[0060] According to the manufacturing method according to the present embodiment, since vacuum pulse firing is performed between the first firing and the second firing, as illustrated in FIG. 12(a), the end portion of the first protruding region 31 of the first internal layer 12a can be oxidized by oxygen invading from the first side margin 16a to form an oxidized portion 33. Thereafter, by performing the second firing at a higher oxygen partial pressure than the first firing, the oxidized portion 33 can be sufficiently formed. In this case, since oxidation proceeds from the previously formed oxidized portion 33, oxygen is trapped by the oxidized portion 33, and invasion of oxygen into the capacitor portion 14 can be suppressed.

[0061] As illustrated in FIG. 12(b), if the first protruding region 31 is not provided and vacuum pulse firing is not performed, the end portions of the respective internal layers are oxidized and expanded, resulting in local structural deterioration, which causes reliability degradation and short circuits.

[0062] (Second Embodiment) In the first embodiment, the internal layer 12 includes the first internal layer 12a and the second internal layer 12b, but is not limited thereto. In the second embodiment, as illustrated in FIG. 13, the internal layer 12 includes the first internal layer 12c and the second internal layer 12d. The first internal layer 12c and the second internal layer 12d are alternately laminated. Also, the internal layers 12 of the lowermost layer and the uppermost layer are the first internal layer 12c.

[0063] In the first embodiment, the first inner layer 12a included the first protruding region 31, and the second inner layer 12b included the second protruding region 32. However, in this embodiment, the first inner layer 12c includes both the first protruding region 31 and the second protruding region 32. Also, the second inner layer 12d does not include either the first protruding region 31 or the second protruding region 32.

[0064] FIG. 14(a) is an enlarged view of the vicinity of the topmost second inner layer 12b in the first side margin 16a of the first embodiment. In the configuration of FIG. 14(a), oxygen can penetrate from the first side margin 16a and the upper cover layer 13. Since the topmost second inner layer 12b does not include the first protruding region 31, oxygen can penetrate between the topmost second inner layer 12b and the adjacent first inner layer 12a. In contrast, FIG. 14(b) is an enlarged view of the vicinity of the topmost first inner layer 12c in the first side margin 16a of this embodiment. In the configuration of FIG. 14(b), oxygen can penetrate from the first side margin 16a and the upper cover layer 13, but the entry of oxygen is suppressed by the oxidized portion 33 of the first protruding region 31 of the topmost first inner layer 12c.

[0065] In this embodiment, in the internal electrode forming step of FIG. 10, an internal electrode pattern 52 corresponding to the shapes of the first inner layer 12c and the second inner layer 12d may be formed.

[0066] (Third Embodiment) In the second embodiment, the first inner layer 12c and the second inner layer 12d were alternately laminated, but it is not limited thereto. For example, as illustrated in FIG. 15, two or more second inner layers 12d may be laminated between two adjacent first inner layers 12c. In the example of FIG. 11, two second inner layers 12d are arranged between every two adjacent first inner layers 12c.

[0067] Also in this embodiment, in the internal electrode forming step of FIG. 10, an internal electrode pattern 52 corresponding to the shapes of the first inner layer 12c and the second inner layer 12d may be formed.

[0068] In each of the above embodiments, a multilayer ceramic capacitor has been described as an example of a multilayer ceramic electronic component, but the present invention is not limited thereto. For example, other multilayer ceramic electronic components such as varistors and thermistors may be used.

Example

[0069] Hereinafter, the multilayer ceramic capacitor according to the above embodiment was manufactured and its characteristics were examined.

[0070] (Examples 1 to 4) An internal electrode pattern of Ni with a thickness of 1.5 μm was printed on a dielectric green sheet with a thickness of 3.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated so that the internal electrode patterns were alternately shifted in the X-axis direction and alternately shifted in the Y-axis direction, pressed, and cut to obtain a ceramic laminate. Note that the total thickness in the Y-axis direction of the side margin and the mixed region described in FIG. 5 was 150 μm. Thereafter, after debinding, the first firing was performed in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa and a temperature of 1160°C to 1280°C, then vacuum pulse firing was performed, and then the second firing was performed in an atmosphere with an oxygen concentration of 1.5%.

[0071] In the sample of Example 1, d t was 9.0 μm, d o1 was 3.1 μm, d o2 was 1.0 μm, d w was 2.1 μm, d w / d t was 23%, and d o1 / d w was 150%. In the sample of Example 2, d t was 9.0 μm, d o1 was 2.9 μm, d o2 was 0.0 μm, d w was 4.8 μm, d w / d t was 53%, and d o1 / d wwas 62%. In the sample of Example 3, d t was 9.0 μm, d o1 was 3.1 μm, d o2 was 0.0 μm, d w was 10.3 μm, d w / d t was 114%, d o1 / d w was 30%. In the sample of Example 4, d t was 9.0 μm, d o1 was 3.1 μm, d o2 was 0.0 μm, d w was 20.2 μm, d w / d t was 224%, d o1 / d w was 15%.

[0072] (Examples 5 to 7) An internal electrode pattern of Ni with a thickness of 1.5 μm was printed on a dielectric green sheet with a thickness of 3.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated, pressed, and cut so that the internal electrode patterns were alternately shifted in the X-axis direction and alternately shifted in the Y-axis direction to obtain a ceramic laminate. Note that the total thickness in the Y-axis direction of the side margin and the mixed region described in FIG. 5 was 150 μm. Then, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa and a temperature of 1160°C to 1280°C, then vacuum pulse firing was carried out, and then the second firing was carried out in an atmosphere with an oxygen concentration of 2.0%.

[0073] In the sample of Example 5, d t was 9.0 μm, d o1 was 5.4 μm, d o2 was 0.5 μm, d w was 4.9 μm, d w / d t was 55%, d o1 / d w was 109%. In the sample of Example 6, dt is 9.0 μm, and d o1 is 5.8 μm, and d o2 is 0.0 μm, and d w is 10.1 μm, and d w / d t is 112%, and d o1 / d w was 57%. In the sample of Example 7, d t is 9.0 μm, and d o1 is 5.6 μm, and d o2 is 0.0 μm, and d w is 20.5 μm, and d w / d t is 228%, and d o1 / d w was 27%.

[0074] (Example 8) An internal electrode pattern of 1.5 μm of Ni was printed on a dielectric green sheet with a thickness of 3.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of stacked units were stacked so that the internal electrode patterns were alternately shifted in the X-axis direction and alternately shifted in the Y-axis direction, pressed, and cut to obtain a ceramic laminate. Among the internal electrode patterns, the internal electrode patterns with a wide width in the Y-axis direction were arranged in the uppermost layer, the lowermost layer, and in between, and the internal electrode patterns with a narrow width in the Y-axis direction were sandwiched in three layers between the two layers of the wide internal electrode patterns. The total thickness in the Y-axis direction of the side margin and the mixed region described in FIG. 5 was set to 150 μm. Then, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa, at 1160 °C to 1280 °C, and then vacuum pulse firing was carried out, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.5%.

[0075] In the sample of Example 8, d t is 13.5 μm, and d o1 is 3.0 μm, and d o2 is 0.0 μm, and d w is 10.3 μm, and d w / dt was 76%, and d o1 / d w was 29%.

[0076] (Examples 9, 10) An internal electrode pattern of Ni with a thickness of 1.5 μm was printed on a dielectric green sheet with a thickness of 3.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of stacked units were stacked, pressed, and cut so that the internal electrode patterns were alternately shifted in the X-axis direction and alternately shifted in the Y-axis direction to obtain a ceramic laminate. Among the internal electrode patterns, the internal electrode patterns with a wide width in the Y-axis direction were arranged in the uppermost layer, the lowermost layer, and in between, and the internal electrode patterns with a narrow width in the Y-axis direction were sandwiched in four layers between the two layers of the wide internal electrode patterns. The total thickness in the Y-axis direction of the side margin and the mixed region described in FIG. 5 was set to 150 μm. Thereafter, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa, at 1160°C to 1280°C, and then vacuum pulse firing was carried out, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.5%.

[0077] In the sample of Example 9, d t was 18.0 μm, d o1 was 3.0 μm, d o2 was 0.0 μm, d w was 10.3 μm, d w / d t was 57%, and d o1 / d w was 29%. In the sample of Example 10, d t was 18.0 μm, d o1 was 2.9 μm, d o2 was 0.0 μm, d w was 20.3 μm, d w / d t was 113%, and d o1 / d w was 14%.

[0078] (Examples 11 to 13) A Ni internal electrode pattern with a thickness of 1.5 μm was printed on a dielectric green sheet with a thickness of 5.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of stacked units were stacked, pressed, and cut so that the internal electrode patterns were alternately shifted in the X-axis direction and alternately shifted in the Y-axis direction to obtain a ceramic laminate. Incidentally, the total thickness in the Y-axis direction of the side margin and the mixed region described in FIG. 5 was set to 150 μm. After that, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa and a temperature range of 1160°C to 1280°C, then vacuum pulse firing was carried out, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.5%.

[0079] In the sample of Example 11, d t was 13.0 μm, d o1 was 3.1 μm, d o2 was 0.0 μm, d w was 4.8 μm, d w / d t was 37%, and d o1 / d w was 65%. In the sample of Example 12, d t was 13.0 μm, d o1 was 2.9 μm, d o2 was 0.0 μm, d w was 10.2 μm, d w / d t was 78%, and d o1 / d w was 28%. In the sample of Example 13, d t was 13.0 μm, d o1 was 2.9 μm, d o2 was 0.0 μm, d w was 20.2 μm, d w / d t was 156%, and d o1 / d w was 14%.

[0080] (Example 14) A dielectric green sheet with a thickness of 5.0 μm was printed with an internal electrode pattern of Ni with a thickness of 1.5 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated, pressed, and cut so that the internal electrode patterns were alternately shifted in the X-axis direction and alternately shifted in the Y-axis direction to obtain a ceramic laminate. Among the internal electrode patterns, the internal electrode patterns with a wide width in the Y-axis direction were arranged in the uppermost layer, the lowermost layer, and in between, and the internal electrode patterns with a narrow width in the Y-axis direction were sandwiched in groups of three layers between two layers of the wide internal electrode patterns. The total thickness in the Y-axis direction of the side margin and the mixed region described in FIG. 5 was set to 150 μm. Thereafter, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa and a temperature range of 1160°C to 1280°C, then vacuum pulse firing was carried out, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.5%.

[0081] In the sample of Example 14, d t was 19.5 μm, d o1 was 3.1 μm, d o2 was 0.0 μm, d w was 10.2 μm, d w / d t was 53%, and d o1 / d w was 30%.

[0082] (Example 15) A 5.0-μm-thick dielectric green sheet was printed with a 1.5-μm-thick Ni internal electrode pattern. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated such that the internal electrode patterns were alternately shifted in the X-axis direction and alternately shifted in the Y-axis direction, and then pressed and cut to obtain a ceramic laminate. Among the internal electrode patterns, the internal electrode patterns wide in the Y-axis direction were arranged in the uppermost layer, the lowermost layer, and in between, and the internal electrode patterns narrow in the Y-axis direction were sandwiched in four-layer units between the two layers of the wide internal electrode patterns. The total thickness in the Y-axis direction of the side margin and the mixed region described in FIG. 5 was set to 150 μm. Thereafter, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa and at 1160°C to 1280°C, then vacuum pulse firing was carried out, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.5%.

[0083] In the sample of Example 15, d t was 26.0 μm, d o1 was 3.0 μm, d o2 was 0.0 μm, d w was 19.1 μm, and d w / d t was 74%, and d o1 / d w was 16%.

[0084] (Comparative Example 1) A 3.0-μm-thick dielectric green sheet was printed with a 1.5-μm-thick Ni internal electrode pattern. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated such that the internal electrode patterns were alternately shifted in the X-axis direction, and then pressed and cut to obtain a ceramic laminate. The internal electrode patterns were not shifted in the Y-axis direction. The thickness in the Y-axis direction of each side margin was set to 150 μm. Thereafter, after debinding, the first firing was carried out with an oxygen partial pressure of 10 -12 MPa to 10 -9The first firing was carried out in a reducing atmosphere of MPa, 1160°C to 1280°C, followed by vacuum pulse firing, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.0%.

[0085] In the sample of Comparative Example 1, d o1 was 1.0 μm, d w was 0.0 μm, and d w / d t was 0%.

[0086] (Comparative Example 2) An internal electrode pattern of 1.5 μm of Ni was printed on a dielectric green sheet with a thickness of 3.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated so that the internal electrode patterns were alternately shifted in the X-axis direction, pressed, and cut to obtain a ceramic laminate. The internal electrode pattern was not shifted in the Y-axis direction. The thickness of each side margin in the Y-axis direction was set to 150 μm. Then, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10 -9 MPa, 1160°C to 1280°C, followed by vacuum pulse firing, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.5%.

[0087] In the sample of Comparative Example 2, d o1 was 2.9 μm, d w was 0.0 μm, and d w / d t was 0%.

[0088] (Comparative Example 3) An internal electrode pattern of 1.5 μm of Ni was printed on a dielectric green sheet with a thickness of 3.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated so that the internal electrode patterns were alternately shifted in the X-axis direction, pressed, and cut to obtain a ceramic laminate. The internal electrode pattern was not shifted in the Y-axis direction. The thickness of each side margin in the Y-axis direction was set to 150 μm. Then, after debinding, the first firing was carried out in a reducing atmosphere with an oxygen partial pressure of 10 -12 MPa to 10-9 The first firing was carried out in a reducing atmosphere of MPa, 1160 °C to 1280 °C, followed by vacuum pulse firing, and then the second firing was carried out in an atmosphere with an oxygen concentration of 2.0%.

[0089] In the sample of Comparative Example 3, d o1 was 5.7 μm, d w was 0.0 μm, and d w / d t was 0%.

[0090] (Comparative Examples 4 to 6) In Comparative Examples 4 and 5, an internal electrode pattern of 1.5 μm of Ni was printed on a dielectric green sheet with a thickness of 3.0 μm. In Comparative Example 6, an internal electrode pattern of 1.5 μm of Ni was printed on a dielectric green sheet with a thickness of 5.0 μm. A dielectric pattern was printed around the internal electrode pattern. A plurality of laminated units were laminated so that the internal electrode patterns were alternately shifted in the X-axis direction, pressed, and cut to obtain a ceramic laminate. The internal electrode pattern was not shifted in the Y-axis direction. In Comparative Example 4, the thickness of each side margin in the Y-axis direction was 300 μm. In Comparative Example 5, the thickness of each side margin in the Y-axis direction was 500 μm. In Comparative Example 6, the thickness of each side margin in the Y-axis direction was 150 μm. Then, after debinding, the first firing was carried out in a reducing atmosphere of 10 -12 MPa to 10 -9 MPa, 1160 °C to 1280 °C, followed by vacuum pulse firing, and then the second firing was carried out in an atmosphere with an oxygen concentration of 1.5%.

[0091] In the sample of Comparative Example 4, d o1 was 0.9 μm, d w was 0.0 μm, and d w / d t was 0%. In the sample of Comparative Example 5, d o1 was 0.2 μm, d w was 0.0 μm, and d w / d t was 0%. In the sample of Comparative Example 6, d o1 was 3.1 μm, dw is 0.0 μm, and d w / d t was 0%.

[0092] The manufacturing conditions and measurement results of Examples 1 to 15 and Comparative Examples 1 to 6 are shown in Table 1.

Table 1

[0093] (High-temperature load test) For the samples of Examples 1 to 15 and Comparative Examples 1 to 6, a high-temperature load test was carried out to examine the failure rate. In the high-temperature load test, the applied voltage was set to 10 V / μm in terms of electric field strength, and 100 hours passed at 125°C. The number of failed products out of 1000 input products was calculated as the failure rate. If the failure rate was 1 / 1000 or less, the high-temperature load test was judged as good "〇". If the failure rate was 2 / 1000 or more and 7 / 1000 or less, the high-temperature load test was judged as slightly good "△". If the failure rate was 8 / 1000 or more, the high-temperature load test was judged as slightly poor "×". The results are shown in Table 2.

[0094] (Electrical characteristics) For the samples of Examples 1 to 15 and Comparative Examples 1 to 6, the electrical characteristics were examined. Specifically, the capacitance was measured. As a result of the measurement, if the capacitance was 8 μF or more, it was judged as qualified "〇", and if the capacitance was less than 8 μF, it was judged as unqualified "×". The results are shown in Table 2.

[0095] (Comprehensive judgment) If both the high-temperature load test and the electrical characteristics were judged as "〇", the comprehensive judgment was judged as qualified "〇". If neither the high-temperature load test nor the electrical characteristics were judged as "×", but "△" was included, the comprehensive judgment was judged as slightly good "△". If "×" existed in at least one of the high-temperature load test and the electrical characteristics, the comprehensive judgment was judged as unqualified "×".

Table 2

[0096] Figure 16(a) shows a graph of the relationship between d o1 / d w and the number of failures in the high-temperature load test. Figure 16(b) shows a graph of the relationship between d w / d T and the number of failures in the high-temperature load test. When these results are organized, as illustrated in Figure 16(c), d w / d T is 50% or more, and d o1 / d w is less than 100%, it can be seen that the number of failures can be reduced.

[0097] As described in detail above with respect to the embodiments of the present invention, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

Explanation of Reference Numerals

[0098] 10 Multilayer chip 11 Dielectric layer 12 Inner layer 12a First inner layer 12b Second inner layer 12c Third inner layer 12d Fourth inner layer 13 Cover layer 14 Capacitance portion 15 End margin 16a First side margin 16b Second side margin 20a, 20b External electrodes 22 Plating layer 23 First plating layer 24 Second plating layer 25 Third plating layer 31 First protruding region 32 Second protruding region 33 Oxidized portion 51 Dielectric green sheet 52 Inner electrode pattern 53 Dielectric pattern 100, 100a, 100b multilayer ceramic capacitors

Claims

1. A laminated chip including a laminated portion in which a plurality of dielectric layers and a plurality of internal layers are alternately laminated, wherein the plurality of internal layers are alternately drawn out to two opposing end faces of the laminated chip, the laminated chip includes a side margin outside a capacitance portion which is a region where the plurality of internal layers face each other in a third direction orthogonal to a first direction in which the plurality of internal layers face each other and a second direction in which the two end faces face each other, the plurality of internal layers include a first internal layer and a second internal layer containing a metal component within the capacitance portion, the first internal layer includes a protruding region protruding outward from the capacitance portion in the third direction more than the second internal layer, the protruding region includes an oxidized portion of the metal component, In a cross-section including the second direction and the third direction, let the length of the oxidized portion of the protruding region be d ｏ１ and, when the length of the oxidized portion of the side margin side end of the second inner layer is d ｏ２ a ceramic electronic component in which the relationship d ｏ１ > d ｏ２ holds.

2. In the cross section, let the length of the protruding region be d ｗ and when the distance between the protruding regions of the first inner layers of two adjacent layers in the first direction is d Ｔ then, when d Ｔ ×0.5 < d ｗ The ceramic electronic component according to claim 1, in which the relationship holds.

3. In the cross section, let the length of the protruding region be d ｗ When the distance between the protruding regions of the first inner layers of two adjacent layers is d Ｔ If so, d Ｔ ×0.2 < d ｏ１ < d ｗ ×1.0, the ceramic electronic component according to claim 1

4. In the cross section, let the length of the protruding region be d ｗ and when the distance between the protruding regions of the first inner layers of two adjacent layers is d Ｔ in the case where, d ｗ / d Ｔ is 50% or more, and d ｏ１ / d ｗ is less than 100%, the ceramic electronic component according to claim 1.

5. The plurality of internal layers are alternately displaced in the third direction. The ceramic electronic component according to Claim 1.

6. The first internal layer includes the protruding region with respect to both of the side margins more than the second internal layer, Among the plurality of internal layers, the two outermost layers in the first direction are the first internal layer. The ceramic electronic component according to Claim 1.

7. In the third direction, the thickness from the end of the capacitance portion to the outer surface of the side margin is 150 μm or less. The ceramic electronic component according to Claim 1.

8. A step of forming an internal electrode pattern on a dielectric green sheet, a step of forming a dielectric pattern around the internal electrode pattern, a step of laminating the dielectric green sheet on which the internal electrode pattern and the dielectric pattern are formed in a first direction, displacing the ends of the internal electrode pattern alternately in a second direction, and obtaining a laminate such that at least two adjacent internal electrode patterns are displaced in a third direction orthogonal to the first direction and the second direction, a step of performing a first firing of firing the laminate, then performing a vacuum pulse firing, and then performing a second firing at a higher oxygen partial pressure than the first firing. A method for manufacturing a ceramic electronic component.

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