Semiconductor device

Abstract

To provide a semiconductor device including an oxide semiconductor to suppress decrease in on-state current.SOLUTION: A transistor 110 using an oxide semiconductor film has: a gate electrode 101; a gate insulating film 102 covering the gate electrode and including an oxide containing silicon; an oxide semiconductor film 103 provided in contact with the gate insulating film and in a region overlapping with at least the gate electrode; and a source electrode and a drain electrode 105a and 105b electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region with a thickness of 5 nm or less from an interface with the gate insulating film has the concentration of silicon of 1.0 atom% or less, and the concentration of silicon included in regions other than the first region in the oxide semiconductor film is lower than the concentration of silicon included in the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces These transistors are used in integrated circuits (ICs) and image display devices (display devices). It is widely used in such electronic devices. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. are.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide containing zinc (Zn) has been disclosed (see Patent Document 1). see).

[0005] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. It has higher on-state characteristics (on-state current, etc.) than conventional MOSFETs.

[0006] Regarding the oxide semiconductor used in such transistors, It is insensitive to metals, and there is no problem even if a considerable amount of metal impurities are contained in the film. "Inexpensive soda-lime glass, which contains a large amount of alkali metals such as sodium, can also be used." It has also been stated that (see Non-Patent Document 1). [Prior art documents]

Patent Document

[0007]

Patent Document 1

Non-Patent Document

[0008]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] However, according to the conventional technical understanding that oxide semiconductors are insensitive to impurities, when designing the device structure and process of a transistor using an oxide semiconductor film, the resistance of the source region and the drain region increases, or the on-current decreases below the designed value, resulting in problems such as this.

[0010] In view of such problems, one aspect of the disclosed invention aims to improve the performance of a transistor using an oxide semiconductor film or a semiconductor device composed of this transistor. For example, it aims to suppress the decrease in the on-current of a transistor using an oxide semiconductor film and improve the operating characteristics of a semiconductor device composed of such a transistor. This is one of the objectives.

Means for Solving the Problems

[0011] The inventors of the present invention have found that by adding impurities such as silicon into the oxide semiconductor film, the ​It has been found that the sheet resistance of the oxide semiconductor film increases.

[0012] In addition, the oxide semiconductor film used in a transistor is often formed by a sputtering method. However, during the sputtering of the oxide semiconductor film, ionized rare gas elements or particles ejected from the target surface may eject the constituent elements of the film that will become the surface to be formed of the oxide semiconductor film, such as the gate insulating film. In this way, the particles ejected from the film that will become the surface to be formed are incorporated into the oxide semiconductor film as impurity elements. In particular, there is a risk that impurity elements are incorporated at a high concentration in the vicinity of the surface to be formed of the oxide semiconductor film. Particles ejected from the film that will become the surface to be formed in this way are incorporated into the oxide semiconductor film as impurity elements. Especially in the vicinity of the surface to be formed of the oxide semiconductor film, there is a risk that impurity elements are incorporated at a high concentration.

[0013] Silicon or the like constituting the gate insulating film is incorporated as an impurity in the vicinity of the surface to be formed of the oxide semiconductor film, and the sheet resistance of the oxide semiconductor film increases. When a transistor is manufactured using such an oxide semiconductor, it is considered that the resistance of the channel formation region located in the vicinity of the surface to be formed of the oxide semiconductor film increases, and the on-current of the transistor decreases. Therefore, in one aspect of the disclosed invention, impurities such as silicon incorporated in the vicinity of the surface to be formed of the oxide semiconductor film are suppressed.

[0014] One aspect of the disclosed invention includes a gate electrode, a gate insulating film covering the gate electrode and containing an oxide containing silicon, an oxide semiconductor film provided in a region in contact with the gate insulating film and at least overlapping the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film is directed from the interface with the gate insulating film toward the oxide semiconductor film.

[0015] One aspect of the disclosed invention includes a gate electrode, a gate insulating film covering the gate electrode and containing an oxide containing silicon, an oxide semiconductor film provided in a region in contact with the gate insulating film and at least overlapping the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film is provided in a region in contact with the gate insulating film and at least overlapping the gate electrode, and the oxide semiconductor film is directed from the interface with the gate insulating film toward the oxide semiconductor film. and a source electrode and a drain electrode electrically connected to the oxide semiconductor film, and the oxide semiconductor film is directed from the interface with the gate insulating film toward the oxide semiconductor film. The oxide semiconductor film is provided in a region in contact with the gate insulating film and at least overlapping the gate electrode, and the oxide semiconductor film is directed from the interface with the gate insulating film toward the oxide semiconductor film. ​​A semiconductor device having a first region in which the concentration of silicon is distributed at a concentration of 1.0 atomic % or less. It is.

[0016] Another aspect of the disclosed invention is a gate electrode, a gate insulating film covering the gate electrode and containing silicon oxide, in contact with the gate insulating film, and at least in a region overlapping the gate electrode. An oxide semiconductor film provided, a channel protection film provided in contact with the oxide semiconductor film, and a source electrode and a drain electrode provided on the channel protection film and electrically connected to the oxide semiconductor film. And the oxide semiconductor film has a first region in which the concentration of silicon is distributed at a concentration of 1.0 atomic % or less from the interface with the gate insulating film toward the oxide semiconductor film. It is a semiconductor device. And, in the above, the first region exists in a range where the thickness from the interface with the gate insulating film is 5 nm or less, and the concentration of silicon contained outside the first region is the silicon contained in the first region. It is preferably smaller than the concentration of. Another aspect of the disclosed invention is a gate electrode, a gate insulating film covering the gate electrode and containing silicon oxide, in contact with the gate insulating film, and at least in a region overlapping the gate electrode. An oxide semiconductor film provided, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, and a protective insulating film covering the oxide semiconductor film, the source electrode and the drain electrode and containing silicon oxide. And in the oxide semiconductor film, the first region having a thickness of 5 nm or less from the interface with the gate insulating film has a silicon concentration of 1.0 atomic % or less, and in the oxide semiconductor film, the thickness from the interface with the protective insulating film is 5 nm or less. The second region has

[0017]

[0018] ​​​​​​​​​​The concentration of [the relevant element] is more than 1.0 atomic %, and the concentration of silicon contained in the region other than the first region and the second region of the oxide semiconductor film is smaller than the concentration of silicon contained in the first region. It is a semiconductor device.

[0019] Also, in the above, it is preferable that the concentration of silicon contained in the first region is 0.1 atomic % or less.

[0020] Also, in the above, the gate insulating film contains carbon, and in the first region, the carbon concentration may be contained at 1.0×10 20 atoms / cm 3 or less.

[0021] Also, in the above, the oxide semiconductor film may have crystallinity, or the oxide semiconductor film may have an amorphous structure.

Advantages of the Invention

[0022] One aspect of the disclosed invention can improve the performance of a transistor using an oxide semiconductor film or a semiconductor device constituted by the transistor.

[0023] Also, one aspect of the disclosed invention can suppress the decrease in the on-current of a transistor using an oxide semiconductor film and improve the operating characteristics of a semiconductor device constituted by the transistor.

Brief Description of the Drawings

[0024]

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Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. . However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

[0026] ​In addition, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like.

[0027] Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0028] Note that the terms "above" and "below" in this specification and the like do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", those including other components between the gate insulating layer and the gate electrode are not excluded.

[0029] Also, the terms "electrode" and "wiring" in this specification and the like do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0030] Also, the functions of "source" and "drain" may be interchanged when transistors of different polarities are employed, or when the direction of current changes in the circuit operation. For this reason, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable.

[0031] Note that in this specification and the like, "electrically connected" includes "having some electrical action". ​​​​​​​​including the case where it is connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0032] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method of manufacturing the semiconductor device will be described with reference to FIGS. 1 to 5.

[0033] <Example of the configuration of the semiconductor device> FIGS. 1(A) and 1(B) show a plan view and a cross-sectional view of a channel etch type transistor, which is one of the bottom gate structures, as an example of the semiconductor device. FIG. 1(A) is a plan view, and FIG. 1(B) is a cross-sectional view taken along the A-B cross-section in FIG. 1(A). In FIG. 1(A), for the sake of simplicity, some of the components of the transistor 110 (for example, the protective insulating film 109, etc.) are omitted.

[0034] The transistor 110 shown in FIGS. 1(A) and 1(B) includes a gate electrode 101, a gate insulating film 102 covering the gate electrode 101, an oxide semiconductor film 103 provided in a region in contact with the gate insulating film 102 and at least overlapping the gate electrode 101, source electrodes 105a and drain electrodes 105b that are electrically connected to the oxide semiconductor film 103, and a protective insulating film 109 covering the oxide semiconductor film 103, the source electrodes 105a, and the drain electrodes 105b on a substrate 100 having an insulating surface.

[0035] The oxide semiconductor film 103 may have an amorphous structure, or a crystalline structure such as single crystal or polycrystalline (polycrystal). Also, it may have a crystal-amorphous mixed phase structure having a crystal part in an amorphous phase, which is neither a complete single crystal nor completely amorphous. Further, the film thickness of the oxide semiconductor film 103 is greater than 5 nm and 200 nm or less, preferably 10 nm or more and 30 nm or less. Since the amorphous oxide semiconductor film 103 can relatively easily obtain a flat surface, the transistor using this can reduce interface scattering during operation, and relatively easily obtain a relatively high field-effect mobility. Further, as shown in Fig. 1(B), it is preferable that the oxide semiconductor film 103 has a taper of 20° to 50° at the end. When the end of the oxide semiconductor film 103 is perpendicular, oxygen easily escapes from the oxide semiconductor film 103 and oxygen deficiency is likely to occur. However, by having a taper at the end of the oxide semiconductor film 103, the generation of oxygen deficiency can be suppressed, and the generation of leakage current of the transistor 110 can be reduced. The oxide semiconductor used for the oxide semiconductor film 103 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. Also, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Also, it is preferable to have tin (Sn) as a stabilizer. Also, as stabilizers, hafnium (Hf), zirconium (Zr), titanium (Ti), scandium (Sc), yttrium (Y), etc.

[0036]

[0037]

[0038] ​ One or more selected from thulium (Y), lanthanoids (for example, cerium (Ce), neodymium (Nd), gadolinium (Gd)) are preferably included.

[0039] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, ternary metal oxides such as In-Ga-Zn oxide (also denoted as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide, In-Ti-Zn oxide, In-Sc-Zn oxide, In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, quaternary metal oxides such as In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide can be used.

[0040] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as main components. It means a substance, and the ratios of In, Ga, and Zn are not limited. Also, other metal elements besides In, Ga, and Zn may be contained.

[0041] Also, as the oxide semiconductor, InMO3(ZnO) m (m > 0, and m is not an integer ) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co, or an element as the above stabilizer . Also, as the oxide semiconductor, In2SnO5(ZnO) (n > 0, and n is an integer n ) may be used.

[0042] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1, In:Ga:Zn = 3:1:2, In:Ga :Zn = 1:3:2, or In:Ga:Zn = 2:1:3, or oxides in the vicinity of their compositions may be used. The oxide semiconductor film 103 can be formed in a single-layer structure or a stacked structure using the oxide semiconductor materials shown above.

[0043] It is preferable to use an oxide insulating film having sufficient breakdown voltage and insulating properties for the gate insulating film 102. When the gate insulating film 102 has a single-layer structure, for example, an insulating film containing an oxide containing silicon such as silicon oxide may be used.

[0044] Also, the gate insulating film 102 may have a stacked structure. When the gate insulating film 102 has a stacked structure, silicon oxide may be stacked on gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, yttrium oxide, lanthanum oxide, or silicon oxynitride. Also, hafnium oxide, hafnium silicate (HfSi ​ x O y (where x>0, y>0)), hafnium silicate (HfSiO x N y (where x>0, y>0)), hafnium aluminate (HfAl x O y (where x>0, y>0)) Silicon oxide may be laminated on high-k materials such as this. Also, by using a high-k material the gate leakage current can be reduced.

[0045] By using an oxide insulating film as the gate insulating film 102, a part of oxygen can be desorbed by heating the oxide insulating film so that oxygen can be supplied to the oxide semiconductor film 103, and oxygen vacancies in the oxide semiconductor film 103 can be filled. In particular, it is preferable that at least an amount of oxygen exceeding the stoichiometric ratio is present in the gate insulating film 102 (in the bulk). For example, as the gate insulating film 102, it is preferable to use a silicon oxide film represented by SiO (where α>0). By using such a silicon oxide film as the gate insulating film 102, oxygen can be supplied to the oxide semiconductor film 103, and the transistor characteristics of the transistor 110 using the oxide semiconductor film 103 can be improved. However, when a silicon oxide film is used as the gate insulating film 102, silicon in the gate insulating film 102 may be incorporated into the oxide semiconductor film 103 as an impurity. 2+α (where α>0) When such a silicon oxide film is used as the gate insulating film 102, oxygen can be supplied to the oxide semiconductor film 103, and the transistor characteristics of the transistor 110 using the oxide semiconductor film 103 can be improved.

[0046] However, when a silicon oxide film is used as the gate insulating film 102, silicon in the gate insulating film 102 may be incorporated into the oxide semiconductor film 103 as an impurity. When silicon or the like is incorporated into the oxide semiconductor film 103 as an impurity, the resistance of the oxide semiconductor film 103 increases.

[0047] ​​​​​​Therefore, in the semiconductor device according to the present embodiment, impurities such as silicon incorporated near the surface to be formed of the oxide semiconductor film are suppressed. As a result, in the oxide semiconductor film 103, a region where the concentration of silicon is distributed at a concentration of 1.0 atomic% or less from the interface with the gate insulating film 102 toward the oxide semiconductor film 103 is formed. As shown in FIG. 1(B), this region is denoted as region 103a. Further, the concentration of silicon contained in the region 103a is more preferably 0.1 atomic% or less. Further, the region 103a exists in a range where the thickness from the interface with the gate insulating film 102 is 5 nm or less. Note that, as shown in FIG. 1(B), a region other than the region 103a of the oxide semiconductor film 103 is denoted as region 103b. Further, the concentration of silicon contained in the region 103b is lower than the concentration of silicon contained in the region 103a. When the gate insulating film 102 contains impurities such as carbon, this may also be incorporated as an impurity into the oxide semiconductor film 103 in the same manner as the above silicon. Therefore, the carbon concentration contained in the region 103a is 1.0×10 atoms / cm or less, more preferably 1.0×10 atoms / cm or less.

[0048] By reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 in this way, a decrease in the on-current of the transistor 110 using the oxide semiconductor film 103 can be suppressed. Therefore, the operating characteristics of the semiconductor device configured by the transistor 110 can be improved. And, for the transistor using the oxide semiconductor film Note that, as shown in FIG. 1(B), a region other than the region 103a of the oxide semiconductor film 103 is denoted as region 103b. Further, the concentration of silicon contained in the region 103b is lower than the concentration of silicon contained in the region 103a. When the gate insulating film 102 contains impurities such as carbon, this may also be incorporated as an impurity into the oxide semiconductor film 103 in the same manner as the above silicon. Therefore, the carbon concentration contained in the region 103a is 1.0×10

[0049] atoms / cm or less, more preferably 1.0×10 atoms / cm 20 or less. 3 By reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 in this way, a decrease in the on-current of the transistor 110 using the oxide semiconductor film 103 can be suppressed. Therefore, the operating characteristics of the semiconductor device configured by the transistor 110 can be improved. And, for the transistor using the oxide semiconductor film atoms / cm 19 or less. 3 By reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 in this way, a decrease in the on-current of the transistor 110 using the oxide semiconductor film 103 can be suppressed. Therefore, the operating characteristics of the semiconductor device configured by the transistor 110 can be improved. And, for the transistor using the oxide semiconductor film

[0050] By reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 in this way, a decrease in the on-current of the transistor 110 using the oxide semiconductor film 103 can be suppressed. Therefore, the operating characteristics of the semiconductor device configured by the transistor 110 can be improved. And, for the transistor using the oxide semiconductor film By reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 in this way, a decrease in the on-current of the transistor 110 using the oxide semiconductor film 103 can be suppressed. Therefore, the operating characteristics of the semiconductor device configured by the transistor 110 can be improved. And, for the transistor using the oxide semiconductor film By reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 in this way, a decrease in the on-current of the transistor 110 using the oxide semiconductor film 103 can be suppressed. Therefore, the operating characteristics of the semiconductor device configured by the transistor 110 can be improved. And, for the transistor using the oxide semiconductor film By reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 in this way, a decrease in the on-current of the transistor 110 using the oxide semiconductor film 103 can be suppressed. Therefore, the operating characteristics of the semiconductor device configured by the transistor 110 can be improved. And, for the transistor using the oxide semiconductor film The performance of the resistor or the semiconductor device constituted by the transistor can be improved. 。

[0051] Regarding the details of other components, they will be described with reference to FIGS. 4(A) to 4(E) in the manufacturing method of the transistor 110 described later. Here, FIGS. 4(A) to 4(E) will be used for the description.

[0052] Note that a planarization insulating film may be further provided on the transistor 110. Also in order to electrically connect the gate electrode 101, the source electrode 105a or the drain electrode 105b, etc. to the wiring, openings may be formed in the gate insulating film 102, the protective insulating film 109, etc. Also, in the region overlapping the gate electrode 101 above the oxide semiconductor film 103, a second gate electrode may further be provided.

[0053] Also, FIGS. 2(A) and 2(B) show a transistor 120 having a configuration different from that of the transistor 110 shown in FIGS. 1(A) and 1(B). FIG. 2(A) is a plan view, and FIG. 2( B) is a cross-sectional view taken along the C-D cross-section in FIG. 2(A). Note that in FIG. 2(A), in order to avoid complication, a part of the components of the transistor 120 (for example, the protective insulating film 109, etc.) is omitted. 109, etc.) is omitted.

[0054] The transistor 120 shown in FIGS. 2(A) and 2(B) includes a gate electrode 101, a gate insulating film 102 covering the gate electrode 101, and a gate insulating film 102 on a substrate 10 0 having an insulating surface, an oxide semiconductor film 103 provided in contact with the gate insulating film 102 and at least in a region overlapping the gate electrode 101, and source electrodes 105a and drains that are electrically connected to the oxide semiconductor film 103. body film 103 and source electrodes 105a and drains that are electrically connected to the oxide semiconductor film 103. The source electrode 105b, the oxide semiconductor film 103, the source electrode 105a, and the drain electrode 105b are connected to the oxide semiconductor film 103. The transistor 120 includes a protective insulating film 109 that covers the transistor 105b. The difference from 10 is that the protective insulating film 109 is made of silicon, similar to the gate insulating film 102. The insulating film 103 is formed between the protective insulating film 109 and the oxide semiconductor film 103. The point is that there is a region 103c in the vicinity of the contact interface.

[0055] The oxide semiconductor film 103 of the transistor 120 includes regions 103a to 103c. As described above, the region 103a is formed in the oxide semiconductor film 103 by the gate insulating film 10 2 toward the oxide semiconductor film 103, the silicon concentration is 1.0 atomic % or less The region 103a is a region in which the thickness from the interface with the gate insulating film 102 is 5n. The region 103c preferably has a thickness of 100 nm or less. In this case, the concentration of silicon increases from the interface with the protective insulating film 109 toward the oxide semiconductor film 103. The region 103c is a region where the protective insulating film 109 is distributed at a concentration higher than 1.0 atomic %. It is preferable that the thickness from the interface with the oxide is in the range of 5 nm or less. The region of the semiconductor film 103 other than the region 103a and the region 103c is referred to as a region 103b.

[0056] The concentration of silicon contained in the region 103b is equal to that of silicon contained in the region 103a. The concentration of silicon contained in the region 103a is less than 0.1 atomic %. It is more preferable if it is lower.

[0057] In this way, the silicon oxide film 103 is formed in the region 103c corresponding to the back channel side of the oxide semiconductor film 103. By increasing the resistance by including a large amount of impurities such as Co, the off-current of the transistor 120 can be reduced. Also, similar to the transistor 110, by reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103, the decrease in the on-current of the transistor 120 using the oxide semiconductor film 103 can be suppressed. For other components, they are the same as the semiconductor device shown in FIGS. 1(A) and 1(B). Details can be referred to the descriptions regarding FIGS. 1(A) and 1(B). Also, the transistors shown in FIGS. 1 and 2 are so-called channel-etch type transistors, but the semiconductor device shown in this embodiment is not limited to this. FIGS. 3(A) and 3(B) show a configuration example of a channel-stop type transistor 130 different from the transistors shown in FIGS. 1 and 2. FIG. 3(A) is a plan view, and FIG. 3(B) is a cross-sectional view taken along the E-F cross-section in FIG. 3(A). Note that in FIG. 3(A), to avoid complexity, some components of the transistor 130 (for example, the protective insulating film 109, etc.) are omitted. Also, in FIG. 3(A), the shape of the channel protection film 108 is shown three-dimensionally for easy understanding. The transistor 130 shown in FIGS. 3(A) and 3(B) includes a gate electrode 101, a gate insulating film 102 covering the gate electrode 101, an oxide semiconductor film 103 in contact with the gate insulating film 102 and provided in at least a region overlapping the gate electrode 101, a channel protection film 108 provided in contact with the oxide semiconductor film 103, and a

[0058]

[0059]

[0060] ​ A source electrode provided on the channel protection film 108 and electrically connected to the oxide semiconductor film 105a and a drain electrode 105b, and a protective insulating film 109 covering the oxide semiconductor film 103, the source electrode 1 05a and the drain electrode 105b. The oxide semiconductor film 103 has regions 103a and 103b in the same manner as the transistor 110. That is, the difference between the transistor 130 and the transistor 110 is that the channel protection film 108 is provided.

[0061] As the channel protection film 108, it is preferable to use an inorganic insulating film containing oxygen. For example a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a hafnium oxide film, or other insulating films can be used. Also, the thickness of the channel protection film 108 is preferably 5 nm or more and 300 nm or less.

[0062] By providing the channel protection film 108 in contact with the oxide semiconductor film 103 in this way damage to the back channel side of the oxide semiconductor film 103 due to etching of the source electrode 105a and the drain electrode 105b (for example, damage caused by plasma or an etching agent during etching) can be prevented. Thereby, the electrical characteristics of the transistor 130 can be made stable. 103 can be prevented. Thereby, the electrical characteristics of the transistor 130 can be made stable. agent during etching) can be prevented. Thereby, the electrical characteristics of the transistor 130 can be made stable. characteristics can be made stable.

[0063] Also, it is preferable that the channel protection film 108 has a taper of 10° or more and 60° or less at the end. By forming the channel protection film 108 in such a shape, the electric field concentration near the lower end of the channel protection film 108 can be alleviated. film 108 in such a shape, the electric field concentration near the lower end of the channel protection film 108 can be alleviated. film 108 can be alleviated.

[0064] For other components, they are the same as those of the semiconductor device shown in FIGS. 1(A) and 1(B). That is. Details can be referred to the descriptions regarding FIGS. 1(A) and 1(B).

[0065] <Example of Fabrication Process of Transistor> Hereinafter, with reference to FIGS. 4 or 5, an example of the fabrication process of the transistor shown in FIGS. 1 to 3 will be described. will be described.

[0066] <Fabrication Process of Transistor 110> An example of the fabrication process of the transistor 110 shown in FIG. 1 will be described with reference to FIGS. 4(A) to 4(E). will be described.

[0067] First, a substrate 100 having an insulating surface is prepared. There is no major limitation on the substrate to be used for the substrate 100 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, if it has an insulating surface, single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, if it has an insulating surface, single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied. single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied.

[0068] Also, a flexible substrate may be used as the substrate 100. When using a flexible substrate, a transistor including an oxide semiconductor film 103 may be directly fabricated on the flexible substrate, or a transistor including an oxide semiconductor film 103 may be fabricated on another fabrication substrate and then peeled off and transferred to the flexible substrate. Also, a flexible substrate may be used as the substrate 100. When using a flexible substrate, a transistor including an oxide semiconductor film 103 may be directly fabricated on the flexible substrate, or a transistor including an oxide semiconductor film 103 may be fabricated on another fabrication substrate and then peeled off and transferred to the flexible substrate. substrate and then peeled off and transferred to the flexible substrate. In addition, in order to peel off and transfer from the fabrication substrate to the flexible substrate, the fabrication substrate and the oxide substrate and then peeled off and transferred to the flexible substrate. In addition, in order to peel off and transfer from the fabrication substrate to the flexible substrate, the fabrication substrate and the oxide It is advisable to provide a release layer between the transistor including the semiconductor film 103 and others.

[0069] An insulating film serving as an underlying film may be provided between the substrate 100 and the gate electrode 101. The underlying film has a function of preventing the diffusion of impurity elements such as hydrogen and moisture from the substrate 100, and is made of silicon nitride film, silicon oxide film, silicon oxynitride film, or silicon nitride oxide film, and can be formed by a laminated structure of one or a plurality of these films.

[0070] Next, a conductive film for forming a gate electrode (including wirings formed in the same layer as this) is formed on the substrate 100. As the conductive film used for the gate electrode, for example, metal materials such as molybdenum , titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or alloy materials mainly composed of these can be used. As the conductive film used for the gate electrode, it may be formed using a conductive metal oxide. As the conductive metal oxide are indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3 - SnO2, sometimes abbreviated as ITO), indium zinc oxide (In2O3 - ZnO), or those obtained by adding silicon or silicon oxide to these metal oxide materials can be used. The gate electrode can be formed as a single layer or by lamination using the above materials. The forming method is not particularly limited, and various film forming methods such as evaporation method, CVD method, sputtering method, spin coating method, etc. can be used.

[0071] Next, a resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the gate electrode 101, and then the resist mask is removed. Also A resist mask for forming the gate electrode 101 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Note that the etching of the gate electrode 101 may be dry etching, wet etching, or both may be used. Next, a gate insulating film 102 is formed covering the gate electrode 101 (see Fig. 4(A)). Here, the film thickness of the gate insulating film 102 can be, for example, 1 nm or more and 500 nm or less. Also, there is no particular limitation on the manufacturing method of the gate insulating film 102. For example, the gate insulating film 102 can be manufactured by appropriately using a sputtering method, MBE method, CVD method, pulsed laser deposition method, ALD method, etc.

[0072] It is preferable to use an oxide insulating film having sufficient breakdown voltage and insulation properties for the gate insulating film 102. When the gate insulating film 102 has a single-layer structure, for example, an insulating film containing an oxide containing silicon such as silicon oxide may be used. The gate insulating film 102 may also have a stacked structure. When the gate insulating film 102 has a stacked structure, silicon oxide may be stacked on gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, yttrium oxide, lanthanum oxide, or silicon oxynitride. Also, hafnium oxide, hafnium silicate (HfSi O (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSiO N

[0073] The gate insulating film 102 is preferably an oxide insulating film having sufficient breakdown voltage and insulation properties. When the gate insulating film 102 has a single-layer structure, for example, an insulating film containing an oxide containing silicon such as silicon oxide may be used. When the gate insulating film 102 has a single-layer structure, for example, an insulating film containing an oxide containing silicon such as silicon oxide may be used. When the gate insulating film 102 has a single-layer structure, for example, an insulating film containing an oxide containing silicon such as silicon oxide may be used.

[0074] The gate insulating film 102 may also have a stacked structure. When the gate insulating film 102 has a stacked structure, silicon oxide may be stacked on gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, yttrium oxide, lanthanum oxide, or silicon oxynitride. Also, hafnium oxide, hafnium silicate (HfSi O (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSiO N x O y (x > 0, y > 0)), hafnium silicate with nitrogen added (HfSiO x N y(x > 0, y > 0)), hafnium aluminate (HfAl x O y (x > 0, y > 0) ) or the like, silicon oxide may be laminated on the high-k material. Also, by using the high-k material, the gate leakage current can be reduced. By using an oxide insulating film as the gate insulating film 102, a part of the oxygen in the oxide insulating film can be desorbed by the heat treatment described later. Therefore, oxygen can be supplied to the oxide semiconductor film 103 to compensate for the oxygen deficiency in the oxide semiconductor film 103. In particular, it is preferable that at least an amount of oxygen exceeding the stoichiometric ratio exists in the gate insulating film 102 (in the bulk). For example, as the gate insulating film 102, it is preferable to use a silicon oxide film represented by SiO

[0075] (where α > 0). By using such a silicon oxide film as the gate insulating film 102, oxygen can be supplied to the oxide semiconductor film 103, and the transistor characteristics of the transistor 110 using the oxide semiconductor film 103 can be improved. 2+α (however, α > 0).

[0076]

[0077] Before forming the oxide semiconductor film 103, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove powdery substances (also called particles, dust) adhering to the surface of the gate insulating film 102. Reverse sputtering is a method of applying a voltage to the substrate, forming plasma in the vicinity of the substrate, and modifying the surface on the substrate side. In addition, instead of argon, gases such as nitrogen, helium, and oxygen may be used.

[0077]

[0077] Also, in the film forming process of the oxide semiconductor film 103, hydrogen or In order to minimize the inclusion of water, a pretreatment is performed before the deposition process of the oxide semiconductor film 103, and the substrate 100 on which the gate insulating film 102 has been deposited in the preheating chamber of the sputtering apparatus is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 100 and the gate insulating film 102 and exhaust them. Note that a cryopump is preferably used as the exhaust means provided in the preheating chamber.

[0078] Next, an oxide semiconductor film 103 with a film thickness greater than 5 nm and less than or equal to 200 nm is deposited on the gate insulating film 102 (see Fig. 4(B)). The oxide semiconductor film 103 may have an amorphous structure, or a crystalline structure such as a single crystal or polycrystal. Alternatively, it may have a crystal - amorphous mixed - phase structure having a crystalline portion in an amorphous phase, which is neither a perfect single crystal nor a perfect amorphous. Note that it is preferable to continuously deposit the gate insulating film 102 and the oxide semiconductor film 10 3 without exposing them to the atmosphere.

[0079] In this embodiment, the oxide semiconductor film 103 is deposited by a sputtering method using an In - Ga - Zn - based oxide target. Also, the oxide semiconductor film 103 can be formed by a sputtering method in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen.

[0080] Examples of targets for producing an In - Ga - Zn - O film as the oxide semiconductor film 103 by a sputtering method include an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 3:1:2, and an atomic ratio of In:Ga:Zn =... ​​​​​​An oxide target with In:Ga:Zn=2:1:3 can be used. The target for the nitride semiconductor film 103 is not limited to these target materials and compositions. It's not that.

[0081] The relative density of the oxide target is 90% or more and 100% or less, preferably 95% or more. By using an oxide target with a high relative density, the film The oxide semiconductor film 103 can be a dense film.

[0082] The sputtering gas used in forming the oxide semiconductor film 103 is hydrogen, water, a hydroxyl group, or the like. Alternatively, it is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0083] The oxide semiconductor film 103 was formed by holding the substrate 100 in a film formation chamber maintained under reduced pressure. At this time, the film may be formed while the substrate 100 is heated. In this case, the substrate temperature is set to 100° C. or higher and the distortion point of the substrate 100 or lower. By forming the oxide semiconductor film 103 while the temperature is low, impurities such as hydrogen and moisture contained in the formed oxide semiconductor film 103 can be reduced. It is possible to reduce the concentration of impurities. In addition, it is preferable because damage caused by sputtering is reduced. It is preferable to remove the residual moisture in the film forming chamber and to use a sputtering gas from which hydrogen and moisture have been removed. A gas is introduced, and the oxide semiconductor film 103 is formed on the substrate 100 using the target. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage may be a turbopump plus a cold trap. The film formation chamber evacuated using, for example, a compound containing hydrogen atoms such as hydrogen atoms, water (H2O), more preferably a compound containing carbon atoms, etc. is evacuated, so that the concentration of impurities such as hydrogen and moisture contained in the oxide semiconductor film 103 formed in the film formation chamber can be reduced.

[0084] When forming the oxide semiconductor film 103 using the sputtering method, if particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102, the elements constituting the gate insulating film 1 02 will mix into the oxide semiconductor film 103 (also referred to as the mixing or mixing effect). This mixing phenomenon occurs particularly significantly in the oxide semiconductor film 103 near the interface with the gate insulating film 102, specifically in the above-mentioned region 103a. In the transistor described in the present embodiment and other forms, since a channel region is formed in the oxide semiconductor film 103 near the gate insulating film 102, the elements constituting the gate insulating film 102 mix into the region as impurities, which may cause a factor to lower the on characteristics (for example, on-current, etc.) of the transistor. In the transistor described in the present embodiment and other forms, since a channel region is formed in the oxide semiconductor film 103 near the gate insulating film 102, the elements constituting the gate insulating film 102 mix into the region as impurities, which may cause a factor to lower the on characteristics (for example, on-current, etc.) of the transistor.

[0085] Here, when forming the oxide semiconductor film 103 on the gate insulating film 102, the possibility of mixing occurring near the interface between the gate insulating film 102 and the oxide semiconductor film 103 will be described based on the results of investigation by classical molecular dynamics calculation. For performing the above calculation classical molecular dynamics calculation software SCIGRESS ME manufactured by Fujitsu Limited was used.

[0086] An amorphous silicon oxide film (hereinafter referred to as a-SiO2) was used as the gate insulating film, and the model shown in FIG. 6 was fabricated. The size of the unit cell (calculation unit cell) related to the calculation is the x-axis​​​​​​ It was set to 3 nm in the x-axis direction, 3 nm in the y-axis direction, and 7.5 nm in the z-axis direction. Here, the x-axis and the y-axis are directions parallel to the a-SiO2 film, and the z-axis is the film thickness direction of the a-SiO2 film. Also, in the calculation, by applying periodic boundary conditions in the x-axis direction and the y-axis direction, it was assumed that the film was sufficiently wide in the x-axis direction and the y-axis direction.

[0087] Next, indium atoms, gallium atoms , zinc atoms, and oxygen atoms with an energy of 1 eV were incident from above (atom generation in FIG. 6) downward at a ratio of 1:1:1:4 (a total of 840 atoms), and classical molecular dynamics calculations were performed with the temperature set to 300 °C and the time set to 2 nsec (time step width of 0.2 fs and the number of steps of 10 million times).

[0088] FIGS. 7 and 8 show the results of the above calculations. FIG. 7(A) shows the arrangement of oxygen atoms and silicon atoms at 0 sec, FIG. 7(B) shows the arrangement of oxygen atoms, silicon atoms, gallium atoms, and zinc atoms after 1 nsec, and FIG. 7(C) shows the arrangement of oxygen atoms, silicon atoms, gallium atoms, and zinc atoms after 2 nsec. Also, FIG. 8(A) shows the arrangement of oxygen atoms, silicon atoms, gallium atoms, and zinc atoms after 2 nsec, FIG. 8(B) shows the arrangement of only silicon atoms after 2 nsec, and FIG. 8(C) shows the arrangement of indium atoms, gallium atoms, and zinc atoms after 2 nsec.

[0089] By comparing the arrangement of only silicon atoms shown in FIG. 8(B) with the arrangement of indium atoms, gallium atoms, and zinc atoms shown in FIG. 8(C), it was confirmed that indium atoms, gallium atoms, and zinc atoms had penetrated into the layer of silicon atoms. ​​​​​​

[0090] From the results of the above calculations, indium atoms, gallium atoms, zinc atoms, and oxygen atoms with an energy of 1 eV are incident on the a-SiO2 film, so that between the a-SiO2 film and the IG ZO film, a layer in which silicon atoms, indium atoms, gallium atoms, zinc atoms, and oxygen atoms are mixed was shown to be formed.

[0091] From the above results, in order not to generate mixing in the vicinity of the interface between the oxide semiconductor film 103 and the gate insulating film 102, it is effective to weaken the momentum with which the particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102. For example, there is a method of lowering the film formation power of the oxide semiconductor film 103 and increasing the film formation pressure. Or, the distance between the target and the film formation substrate (hereinafter, also referred to as the T-S distance) may be increased. Note that as described above, mixing by sputtering can occur in the oxide semiconductor film 103 in the vicinity of the interface with the gate insulating film 102. Therefore, if sputtering is performed by weakening the momentum with which the particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102 to reduce the mixing effect and form the oxide semiconductor film in the vicinity of the interface, then afterwards, the momentum of collision may be increased. For example, the film formation power of the oxide semiconductor film 103 may be lowered to form the oxide semiconductor film in the vicinity of the interface, and then the film formation power may be increased to form the oxide semiconductor film. Also, the film formation pressure of the oxide semiconductor film 103 may be increased to form the oxide semiconductor film in the vicinity of the interface, and then the film formation pressure may be lowered to form the oxide semiconductor film. Also, the T-S distance of the oxide semiconductor film 103 may be increased to form the oxide semiconductor film in the vicinity of the interface and then the oxide semiconductor film may be formed.

[0092] Note that as described above, mixing by sputtering can occur in the oxide semiconductor film 103 in the vicinity of the interface with the gate insulating film 102. Therefore, if sputtering is performed by weakening the momentum with which the particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102 to reduce the mixing effect and form the oxide semiconductor film in the vicinity of the interface, then afterwards, the momentum of collision may be increased. For example, the film formation power of the oxide semiconductor film 103 may be lowered to form the oxide semiconductor film in the vicinity of the interface, and then the film formation power may be increased to form the oxide semiconductor film. Also, the film formation pressure of the oxide semiconductor film 103 may be increased to form the oxide semiconductor film in the vicinity of the interface, and then the film formation pressure may be lowered to form the oxide semiconductor film. Also, it can occur in the oxide semiconductor film 103 near the interface with the gate insulating film 102. Thus, if sputtering is performed by weakening the momentum with which the particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102 to reduce the mixing effect and form the oxide semiconductor film near the interface, then afterwards, the momentum of collision may be increased. For example, the film formation power of the oxide semiconductor film 103 may be lowered to form the oxide semiconductor film near the interface, and then the film formation power may be increased to form the oxide semiconductor film. Also, the film formation pressure of the oxide semiconductor film 103 may be increased to form the oxide semiconductor film near the interface, and then the film formation pressure may be lowered to form the oxide semiconductor film. Also, the oxide semiconductor film 103 is formed by weakening the momentum with which the particles constituting it collide with the gate insulating film 102 and performing sputtering to reduce the mixing effect, and then the oxide semiconductor film near the interface is formed. After that, the momentum of collision may be increased. For example, the film formation power of the oxide semiconductor film 103 may be lowered to form the oxide semiconductor film near the interface, and then the film formation power may be increased to form the oxide semiconductor film. Also, the film formation pressure of the oxide semiconductor film 103 may be increased to form the oxide semiconductor film near the interface, and then the film formation pressure may be lowered to form the oxide semiconductor film. Also, the mixing effect is reduced and the oxide semiconductor film near the interface is formed. Then, the momentum of collision may be increased. For example, the film formation power of the oxide semiconductor film 103 may be lowered to form the oxide semiconductor film near the interface, and then the film formation power may be increased to form the oxide semiconductor film. Also, the film formation pressure of the oxide semiconductor film 103 may be increased to form the oxide semiconductor film near the interface, and then the film formation pressure may be lowered to form the oxide semiconductor film. Also, the film formation power of the oxide semiconductor film 103 is lowered to form the oxide semiconductor film near the interface, and then the film formation power is increased to form the oxide semiconductor film and it may be formed. Also, the film formation pressure of the oxide semiconductor film 103 may be increased to form the oxide semiconductor film near the interface, and then the film formation pressure may be lowered to form the oxide semiconductor film. Also, the film formation pressure of the oxide semiconductor film 103 is increased to form the oxide semiconductor film near the interface, and then the film formation pressure is lowered to form the oxide semiconductor film. Also, it may be formed. Also, the T-S distance of the oxide semiconductor film 103 is increased to form the oxide semiconductor film near the interface Alternatively, the distance between T and S may be reduced to form the oxide semiconductor film.

[0093] Specifically, the film formation power is 10 kW or less, preferably 1 kW or less, more preferably 500 W or less, and even more preferably 200 W or less. Note that the lower the film formation power, the lower the film formation rate of the oxide semiconductor film 103. Also, if the film formation power is extremely low, it becomes difficult to generate plasma in the sputtering apparatus, and there is an increased possibility that the film formation process cannot be performed normally. Therefore, it is desirable that the film formation power be 5% or more of the maximum power that can be applied with the sputtering apparatus used. Regarding how much to lower the film formation power, considering the performance of the sputtering apparatus and the film thickness of the oxide semiconductor film 103, etc., the operator can appropriately select an optimal power value within the range where film formation can be performed normally and the film formation time does not have a significant impact on the manufacturing process (tact time) of the transistor 110.

[0094] Specifically, the film formation pressure is 0.4 Pa or more, preferably 1.0 Pa or more , more preferably 2.0 Pa or more, and even more preferably 5.0 Pa or more. Note that the higher the film formation pressure, the more likely the film quality of the formed film deteriorates (for example, the film quality becomes sparse). Therefore, it is desirable that the film formation pressure be 100 Pa or less. Regarding how much to increase the film formation pressure, considering the characteristics required for the oxide semiconductor film 103 (for example, field effect mobility, etc.), the operator can appropriately select an optimal pressure value.

[0095] Specifically, the distance between T and S is 30 mm or more, preferably 50 mm or more , more preferably 100 mm or more, still more preferably 300 mm or more . Note that, the wider the distance between T and S is, the lower the film formation rate of the oxide semiconductor film 103 will be . Therefore, it is desirable that the distance between T and S be 500 mm or less. Regarding how much the distance between T and S is widened, the implementer may appropriately select an optimal distance between T and S within the range that does not significantly affect the film formation time with respect to the manufacturing process (tact time) of the transistor 110 .

[0096] . Note that, in order to weaken the momentum of the particles constituting the oxide semiconductor film 103 from colliding with the gate insulating film 102, the oxide semiconductor film 103 may be formed under any one of the conditions of film formation power, film formation pressure, or the distance between T and S within the above-mentioned range, or the oxide semiconductor film 103 may be formed under a plurality of conditions within the above-mentioned range .

[0097] . Note that, as the sputtering apparatus, in the case of using a magnetron sputtering apparatus (simply also referred to as a magnetron sputtering apparatus) in which the target and the film-forming substrate are installed substantially parallel to each other, in addition to the particles constituting the oxide semiconductor film 103, plasma and secondary electrons also collide with the gate insulating film 102. Therefore, it can be said that the elements constituting the gate insulating film 102 are in a state where they are very likely to be mixed into the oxide semiconductor film 103. For this reason, as the sputtering apparatus for forming the oxide semiconductor film 103, a facing target type sputtering apparatus (also referred to as a mirrortron sputtering apparatus) may be used. In the apparatus, two targets are installed in a facing state, and the film-forming substrate is installed in a state substantially perpendicular to the targets at a location other than the space sandwiched between the two targets. And, a high density is provided between the two facing targets Generate plasma, and by sputtering the surface of the target (the target used for forming the oxide semiconductor film 103) with the plasma, an oxide semiconductor film 1 03 is formed on the substrate to be film-formed. Therefore, the substrate to be film-formed is not (or very little) directly exposed to the plasma or secondary electrons.

[0098] Also, when performing sputtering film formation of the oxide semiconductor film 103 in a rare gas atmosphere, helium may be used instead of argon. By using helium, which has a smaller atomic weight than argon, the momentum of the particles constituting the oxide semiconductor film 103 colliding with the gate insulating film 102 can be weakened. Furthermore, after forming the film near the interface between the oxide semiconductor film 103 and the gate insulating film 102 in a helium atmosphere, by switching the inside of the film formation chamber to an argon atmosphere, the film formation speed of the oxide semiconductor film 103 can be improved.

[0099] Also, the oxide semiconductor film 103 may be formed by a method that has a weak impact on the gate insulating film 102, such as the ALD (Atomic Layer Deposit ion) method, vapor deposition method, coating method, etc.

[0100] As described above, by weakening the momentum of the particles constituting the oxide semiconductor film 103 colliding with the gate insulating film 102 and forming the oxide semiconductor film 103, as described above, in the oxide semiconductor film 103, a region 103a in which the concentration of silicon is distributed at a concentration of 1.0 atomic% or less from the interface with the gate insulating film 102 toward the oxide semiconductor film 103 and a region 103b in which the silicon concentration contained is smaller than that in the region 103a are formed. Here, the region 103b is the region other than the region 103a of the oxide semiconductor film 103. Also, the region 103a contains ​​​​​​​​ The silicon concentration is more preferably 0.1 atomic % or less.

[0101] In addition, by forming the oxide semiconductor film 103 in this manner, The incorporation of impurities such as carbon into the oxide semiconductor film 103 is also reduced. As mentioned above, the carbon concentration in the region 103a is 1.0×10 20 atoms / cm 3 below , more preferably 1.0 × 10 19 atoms / cm 3 The following is the result.

[0102] In this way, impurities such as silicon are taken into the region 103a of the oxide semiconductor film 103. By reducing the amount of material, the on-state property of the transistor 110 including the oxide semiconductor film 103 can be improved. The decrease in current can be suppressed.

[0103] In addition, the force with which particles constituting the oxide semiconductor film 103 collide with the gate insulating film 102 is weakened. By forming the oxide semiconductor film 103, the oxide semiconductor is not formed in the gate insulating film 102. This also prevents the elements constituting the gate insulating film 103 from being mixed in. 2, a highly conductive element such as a metal element constituting the oxide semiconductor film 103 is mixed in the oxide semiconductor film 103. Since the above can be suppressed, the resistivity of the gate insulating film 102 can be prevented from decreasing.

[0104] After the oxide semiconductor film 103 was formed, the oxide semiconductor film 103 was subjected to heat treatment. The temperature of the heat treatment may be 300°C or higher and 700°C or lower, or lower than the strain point of the substrate. By carrying out this heat treatment, it is possible to remove excess hydrogen (including water and hydroxyl groups). is.

[0105] The heat treatment can be carried out, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, under a nitrogen atmosphere at 450 °C for 1 hour. During this period, the oxide semiconductor film 103 is not exposed to the air, and water and hydrogen are prevented from mixing in.

[0106] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Ra pid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Th ermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by the radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp . The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, a noble gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used. . For example, as the heat treatment, a GRTA treatment may be performed in which the object to be treated is put into a heated inert gas atmosphere, heated for several minutes , and then taken out from the inert gas atmosphere. When the GRTA treatment is used, high-temperature heat treatment in a short time becomes possible. Also, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the object to be treated. During the treatment, the inert gas may be switched to a gas containing oxygen.

[0107] In addition, as the inert gas atmosphere, nitrogen or a noble gas (helium, neon, argon is used. .

[0108] ​​​ An atmosphere mainly composed of (etc.), and it is desirable to apply an atmosphere that does not contain water, hydrogen, etc. For example, the purity of nitrogen, helium, neon, argon, etc. introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0109] In addition, after heating the oxide semiconductor film 103 by the heat treatment, high-purity oxygen gas, nitrous oxide gas, high-purity nitrous oxide gas, or ultra-dry air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm (dew point conversion -55 °C) or less, preferably 1 ppm or less, more preferably 10 ppb or less of air) may be introduced. It is preferable that water, hydrogen, etc. are not contained in the oxygen gas or nitrous oxide gas. Or, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide gas is 1 ppm or less, preferably 0.1 ppm or less). By the action of the oxygen gas or nitrous oxide gas, by supplying oxygen, which is the main component material constituting the oxide semiconductor that has simultaneously decreased by the above heat treatment, the oxide semiconductor film can be made highly pure and i-type (intrinsic). Note that here, the configuration in which the heat treatment is performed before processing the oxide semiconductor film into an island shape has been described, but one aspect of the disclosed invention is not construed as being limited thereto. The heat treatment may be performed after processing the oxide semiconductor film into an island shape.

[0110]

[0111] ​​​​​Next, the oxide semiconductor film 103 is preferably processed into an island-shaped oxide semiconductor film 103 by a photolithography process (see FIG. 4(C)). Also, a resist mask for forming the island-shaped oxide semiconductor film 103 may be formed by an inkjet method. Since no photomask is used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced. Note that the etching of the oxide semiconductor film 103 may be dry etching, wet etching, or both may be used.

[0112] Here, as shown in FIG. 4(C), the oxide semiconductor film 103 preferably has a taper of 20° to 50° at the ends. When the ends of the oxide semiconductor film 103 are vertical, oxygen easily escapes from the oxide semiconductor film 103 and oxygen deficiency is likely to occur. However, by having a taper at the ends of the oxide semiconductor film 103, the occurrence of oxygen deficiency can be suppressed, and the leakage current of the transistor 110 can be reduced.

[0113] Next, a conductive film to be used for the source electrode and the drain electrode (including wiring formed in the same layer) is formed on the oxide semiconductor film 103. As the conductive film to be used for the source electrode and the drain electrode, for example, a metal film containing an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. A configuration in which a high melting point metal film such as titanium, molybdenum, tungsten or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on one or both of the lower side and the upper side of a metal film such as aluminum or copper may also be used. Also, the source​​​​​​​​ The conductive films used for the source electrode and the drain electrode may be formed of a conductive metal oxide. Conductivity metal oxides include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3-SnO2, abbreviated as ITO), indium zinc oxide (In2O3-ZnO) can be used. The conductive films used for the source electrode and the drain electrode can be formed into a single layer or a laminate using the above materials . The formation method is not particularly limited, and various film formation methods such as vapor deposition, CVD method, sputtering method, and spin coating method can be used.

[0114] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form the source electrode 105a and the drain electrode 105b, and then the resist mask is removed (see Fig. 4(D)). For the exposure during the resist mask formation in the photolithography process , it is preferable to use ultraviolet light, KrF laser light, or ArF laser light. Here , the channel length L of the transistor to be formed later is determined by the interval width between the lower ends of the adjacent source electrode 105a and the drain electrode 10 5b on the oxide semiconductor film 103. Therefore, when performing exposure with a channel length L < 25 nm, for example, extreme ultraviolet light with a very short wavelength of several nm to several 10 nm is used for the exposure during the resist mask formation in the photolithography process. Exposure using extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is possible to miniaturize the channel length L of the transistor to be formed later, and the operating speed of the circuit can be increased.

[0115] ​​​In addition, in order to reduce the number of photomasks and the number of processes used in the photolithography process, a resist mask formed by a halftone mask, which is an exposure mask in which the transmitted light has multiple intensities, may be used in the etching process. The resist mask formed using the halftone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing etching. Therefore, it can be used in a plurality of etching processes for processing into different patterns. Thus, with a single halftone mask, it is possible to form resist masks corresponding to at least two or more different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography processes can also be reduced, enabling simplification of the process. When etching the conductive film, it is desirable to optimize the etching conditions so that the oxide semiconductor film 103 is not etched and separated. However, it is difficult to obtain a condition where only the conductive film is etched and the oxide semiconductor film 103 is not etched at all. When etching the conductive film, only a part of the oxide semiconductor film 103 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 103 may be etched, resulting in an oxide semiconductor film 103 having a groove portion (concave portion). Next, a protective insulating film 109 that covers the source electrode 105a and the drain electrode 105b and is in contact with a part of the oxide semiconductor film 103 is formed (see FIG. 4(E)). As the protective insulating film 109, it is preferable to use an inorganic insulating film, such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, or a hafnium oxide film.

[0116] When etching the conductive film, it is desirable to optimize the etching conditions so that the oxide semiconductor film 103 is not etched and separated. However, it is difficult to obtain a condition where only the conductive film is etched and the oxide semiconductor film 103 is not etched at all. When etching the conductive film, only a part of the oxide semiconductor film 103 is etched. For example, 5% to 50% of the film thickness of the oxide semiconductor film 103 may be etched, resulting in an oxide semiconductor film 103 having a groove portion (concave portion).

[0117] Next, a protective insulating film 109 that covers the source electrode 105a and the drain electrode 105b and is in contact with a part of the oxide semiconductor film 103 is formed (see FIG. 4(E)). As the protective insulating film 109, it is preferable to use an inorganic insulating film, such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, or a hafnium oxide film. ​​​​​​​​​​​Any oxide insulating film may be used alone or in a stacked manner. Further, on the above-described oxide insulating film, , a single layer or a stack of nitride insulating films such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film may be further formed. For example, using a sputtering method, a stack of a silicon oxide film and an aluminum oxide film is formed in order from the source electrode 105a and drain electrode 105b sides.

[0118] In this process, an insulating film containing an oxide containing silicon is formed as the protective insulating film 109 by using a sputtering method, and silicon is mixed into the oxide semiconductor film 103. In the oxide semiconductor film 103, a region 103c is formed near the interface where the oxide semiconductor film 103 and the protective insulating film 109 are in contact, so that the transistor 1 shown in FIGS. 2(A) and 2(B) can be formed. Here, the region 103c is a region in the oxide semiconductor film 103 where the concentration of silicon is distributed at a concentration higher than 1.0 atomic % toward the oxide semiconductor film 103 from the interface with the protective insulating film 109. The region 103c preferably exists in a range where the thickness from the interface with the protective insulating film 109 is 5 nm or less. Here, as the protective insulating film 109, the same insulating film as the gate insulating film 102 can be used. Further, in order to mix silicon into the oxide semiconductor film 103, mixing may be generated near the interface between the oxide semiconductor film 103 and the protective insulating film 109. Therefore, the momentum of silicon constituting the protective insulating film 109 colliding with the oxide semiconductor film 103 during sputtering

[0119] may be increased. For example, the film formation power of the protective insulating film 109 is increased, and the protective insulation film 109 is made to collide with the oxide semiconductor film 103 with a stronger momentum. For example, the film formation power of the protective insulating film 109 is increased, and the protective insulation film 109 is made to collide with the oxide semiconductor film 103 with a stronger momentum. For example, the film formation power of the protective insulating film 109 is increased, and the protective insulation film 109 is made to collide with the oxide semiconductor film 103 with a stronger momentum. For example, the film formation power of the protective insulating film 109 is increased, and the protective insulation ​There are methods such as reducing the film formation pressure of the film 109 or shortening the distance between T and S.

[0120] In this way, in the region 103c corresponding to the back channel side of the oxide semiconductor film 103, by increasing the resistance by including a large amount of impurities such as silicon, the off-current of the transistor 120 can be reduced. Also, similar to the transistor 110, by reducing the amount of impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103, the decrease in the on-current of the transistor 120 using the oxide semiconductor film 103 can be suppressed.

[0121] Hereinafter, the transistor 120 can be manufactured by the same process as the manufacturing method of the transistor 110.

[0122] After forming the protective insulating film 109, it is preferable to perform heat treatment on the oxide semiconductor film 103. The temperature of the heat treatment is 300 °C or higher and 700 °C or lower, or less than the distortion point of the substrate.

[0123] The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (such as argon or helium), but it is preferable that the above atmosphere of nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Also, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.9999 9%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0124] ​​​​​​​By performing heat treatment after forming the oxide semiconductor film, one of the main component materials constituting the oxide semiconductor may simultaneously decrease. However, in the heat treatment, oxygen can be supplied to the oxide semiconductor film 103 from the gate insulating film 102 formed using an insulating film containing an oxide containing silicon so that the oxygen deficiency of the oxide semiconductor film 103 can be compensated .

[0125] By performing the above-described heat treatment, the oxide semiconductor film 103 can be made highly pure so as to contain as few impurities other than its main components as possible. In the highly purified oxide semiconductor film 10 3, carriers derived from donors are extremely few (close to zero), and the carrier concentration is 1× 10 10 14 / cm 3 less than, preferably 1×10 12 / cm 3 less than, more preferably 1×1 0 11 / cm 3 less than. In this way, an i-type (intrinsic) oxide semiconductor film 10 3 can be formed

[0126] The transistor 110 is formed in the above steps (see FIG. 4(E)). In the transistor 11 0, impurities such as silicon incorporated into the region 103a of the oxide semiconductor film 103 are reduced . Thereby, a decrease in the on-current of the transistor 110 can be suppressed .

[0127] Also, a planarization insulating film may be provided on the transistor 110. As the planarization insulating film, an organic material having heat resistance such as an acrylic resin, a polyimide resin, a benzocyclobutene-based resin, a polyamide resin, or an epoxy resin can be used. In addition to the above organic materials, a low resin, etc ​Dielectric materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG ( borophosphosilicate glass), etc. can be used. Note that insulating films formed of these materials may be laminated in multiple layers.

[0128] <Manufacturing Process of Transistor 130> Next, with reference to FIGS. 5(A) to 5(E), an example of the manufacturing process of transistor 130 shown in FIG. 3 will be described.

[0129] First, in the same manner as transistor 110 up to the process shown in FIG. 4(C), on substrate 100 a gate electrode 101, a gate insulating film 102, and an oxide semiconductor film 103 having regions 103a and 103b are formed (see FIG. 5(A)). For details of substrate 100, gate electrode 101, gate insulating film 102, and oxide semiconductor film 103, reference can be made to the descriptions regarding FIGS. 4(A) to 4(C).

[0130] Next, an insulating film 107 used for the channel protection film is formed to have a film thickness of 5 nm or more and 300 nm or less (see FIG. 5(B)). As the insulating film 107, it is preferable to use an inorganic insulating film containing oxygen, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, or a hafnium oxide film can be used. Also, there is no particular limitation on the manufacturing method of the insulating film 107, but for example, it can be formed by appropriately using a sputtering method, MBE method, CVD method, pulsed laser deposition method, ALD method, etc. can be used.

[0131] Next, a resist mask is formed on the insulating film 107 by a photolithography process, and etching After performing a ching to form the channel protection film 108, the resist mask is removed (see Fig. 5( C)). Also, a resist mask for forming the channel protection film 108 may be formed by an inkjet method. When forming the resist mask by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Here, the etching of the channel protection film 108 may be dry etching, wet etching, or both may be used.

[0132] Here, as shown in Fig. 5(C), it is preferable that the channel protection film 108 has a taper of 10° or more and 60° or less at the end. By making the channel protection film 108 have such a shape, the electric field concentration near the lower end of the channel protection film 108 can be alleviated.

[0133] Thus, by providing the channel protection film 108 in contact with the oxide semiconductor film 103, damage to the oxide semiconductor film 103 on the back channel side due to etching of the source electrode 105a and the drain electrode 105b (for example, damage by plasma or an etching agent during etching) can be prevented. Thereby, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided.

[0134] Next, a conductive film to be used for the source electrode and the drain electrode (including wiring formed in the same layer) is formed on the channel protection film 108 and the oxide semiconductor film 103, and the conductive film is selectively etched by a photolithography process to form the source electrode 105a and the drain electrode 105b (see Fig. 5(D)). This process is the same as the process shown in Fig. 4(D). ​​​​​Since it can be performed using the method, the source electrode 105a and the drain electrode 105b For details thereof, reference can be made to the description regarding FIG. 4(D).

[0135] Next, a protective insulating film 109 is formed to cover the source electrode 105a, the drain electrode 105b, and the channel protection film 108 (see FIG. 5(E)). This step can be performed using the same method as the step shown in FIG. 4(E). Therefore, for details of the protective insulating film 109, reference can be made to the description regarding FIG. 4(E). Since it can be performed using the same method as the step shown in FIG. 4(E), for details of the protective insulating film 109, reference can be made to the description regarding FIG. 4(E).

[0136] As described above, one aspect of the disclosed invention can reduce the impurity concentration in the vicinity of the formation surface of the oxide semiconductor film in a semiconductor device using an oxide semiconductor. Also, one aspect of the disclosed invention can suppress a decrease in on-current in a semiconductor device using an oxide semiconductor. And, the dynamic characteristics of the semiconductor device constituted by the transistor can be improved.

[0137]

[0138] one aspect of the disclosed invention can improve the performance of a transistor using an oxide semiconductor film or a semiconductor device constituted by the transistor.

[0138] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0139] (Embodiment 2) A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor exemplified in Embodiment 1. Also, part or all of a drive circuit including the transistor ​The body can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0140] In FIG. 9(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In FIG. 9 (A), a scanning line driving circuit 4004 and a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film are mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Further, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC (Flexible printed circu (it) 4018a, 4018b. In FIGS. 9(B) and 9(C), a sealing material 4005 is provided so as to surround the pixel portion 400 2 and the scanning line driving circuit 4004 provided on the first substrate 4001. Further, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 9(B) and 9( C), a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. In FIGS. 9(B) and 9( C), various signals and potentials given to the separately formed signal line driving circuit 4   003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC (Flexible printed circu

[0141] In FIGS. 9(B) and 9(C), a sealing material 4005 is provided so as to surround the pixel portion 400 2 and the scanning line driving circuit 4004 provided on the first substrate 4001. Further, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 9(B) and 9( C), a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. In FIGS. 9(B) and 9( C), various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC (Flexible printed circu In FIGS. 9(B) and 9(C), a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. In FIGS. 9(B) and 9( C), various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC (Flexible printed circu In FIGS. 9(B) and 9( C), a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. In FIGS. 9(B) and 9( Alternatively, various signals and potentials supplied to the pixel unit 4002 are supplied from the FPC 4018. It is.

[0142] In addition, in FIGS. 9(B) and 9(C), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line The driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit May be separately formed and mounted.

[0143] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG (C hip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method or the like can be used. FIG. 9(A) is An example of mounting the signal line driving circuit 4003 and the scanning line driving circuit 4004 by the COG method , FIG. 9(B) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 9( C) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0144] In addition, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC or the like including a controller Is mounted on the panel.

[0145] Note that the display device in this specification refers to an image display device, a display device, or A light source (including a lighting device). Also, a module to which a connector, for example, an FPC or a TAB tape or A TCP is attached, a module provided with a printed wiring board at the tip of the TAB tape or TCP, or an IC (integrated circuit) directly mounted on the display element by the COG method Are all included in the display device. ​

[0146] In addition, the pixel portion and the scanning line driving circuit provided on the first substrate include a plurality of transistors and the transistors exemplified in Embodiment 1 can be applied.

[0147] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. In addition, a display medium such as electronic ink, whose contrast changes by an electrical action, can also be applied.

[0148] One form of the semiconductor device will be described with reference to FIGS. 10 to 12. FIGS. 10 to 12 correspond to the cross-sectional view taken along M-N of FIG. 9(B).

[0149] As shown in FIGS. 10 to 12, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 40 16, and the connection terminal electrodes 4015 and terminal electrodes 4016 are electrically connected via an anisotropic conductive film 4019 to the terminals of the FPC 4018 owned.

[0150] The connection terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030, and the terminal electrode 4016 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 4010 and 4011 .

[0151] In addition, the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 include a plurality of transistors. In FIGS. 10 to 12, the transistors included in the pixel portion 4002 ​The transistor 4010 and the transistor 4011 included in the scanning line driving circuit 4004 are illustrated.

[0152] In the present embodiment, as the transistors 4010 and 4011, the transistors shown in Embodiment 1 can be applied. The transistors 4010 and 4011 have suppressed electrical characteristic variations and are electrically stable. Therefore, a highly reliable semiconductor device can be provided as the semiconductor device of the present embodiment shown in FIGS. 10 to 12.

[0153] The transistor 4011 included in the scanning line driving circuit 4004 has a structure in which a second gate electrode is provided on the insulating film 4034. By controlling the voltage applied to the second gate electrode, the threshold

[0154] voltage of the transistor 4011 can be controlled. The transistor 4010 provided in the pixel portion 4002 is electrically connected to the display element and constitutes a display panel. The display element is

[0155] not particularly limited as long as it can perform display, and various display elements can be used. FIG. 10 shows an example of a liquid crystal display device using a liquid crystal element as the display element. In FIG. 10, the liquid crystal element 4013, which is the display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that

[0156] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. It is a sensor provided to control the film thickness (cell gap) of the liquid crystal layer 4008 . It is also possible to use spherical spacers.

[0157] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can be in a cholesteric phase, smectic phase, cubic phase, or chromatic phase depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0158] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer, a liquid crystal composition containing a chiral agent of several weight percent or more is used. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. Since the liquid crystal display is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Since there is no need to provide a facing film, rubbing treatment is also unnecessary. This can prevent electrostatic damage caused by the electrostatic discharge, thereby reducing defects and damage to the liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0159] The specific resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12is Ω·cm or more. In this specification, the resistivity value is the value measured at 20°C.

[0160] The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold charges for a predetermined period in consideration of the leakage current etc. of the transistor arranged in the pixel portion. By using a transistor having a high-purity oxide semiconductor film, it is sufficient to provide a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, with respect to the liquid crystal capacitance in each pixel. etc. A transistor using the high-purity oxide semiconductor film used in this embodiment can lower the current value (off-current value) in the off state. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the writing interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, and the effect of suppressing power consumption can be achieved.

[0161] A transistor using the high-purity oxide semiconductor film used in this embodiment can obtain a relatively high field-effect mobility, so that high-speed driving is possible. Therefore, by using the above transistor in the pixel portion of the liquid crystal display device, a high-quality image can be provided. etc. In addition, since the transistor can be manufactured separately for the drive circuit portion or the pixel portion on the same substrate, the number of parts of the liquid crystal display device can be reduced.

[0162] Also, the transistor using the high-purity oxide semiconductor film used in this embodiment Since a relatively high field-effect mobility can be obtained, high-speed driving is possible. Therefore, by using the above transistor in the pixel portion of the liquid crystal display device, a high-quality image can be provided. In addition, since the above transistor can be manufactured separately for the drive circuit portion or the pixel portion on the same substrate, the number of parts of the liquid crystal display device can be reduced.

[0163] Liquid crystal display devices include TN (Twisted Nematic) mode, IPS (In- Plane-Switching) mode, FFS (Fringe Field Swi the (tching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liqu id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, etc. can be used.

[0164] Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel, and is a method in which the liquid crystal molecules face the vertical direction with respect to the panel surface when no voltage is applied. Examples of the vertical alignment mode include, but are not limited to, the MVA (Multi-Domain Vertical Alignm ent) mode, the PVA (Patterned Vertical Alignment ) mode, the ASV (Advanced Super-View) mode, etc. can be used. Also, a method called multi-domain formation or multi-domain design in which pixels are divided into several regions (sub-pixels) and the molecules are tilted in different directions can be used. For example, the vertical alignment mode is a method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel, and is a method in which the liquid crystal molecules face the vertical direction with respect to the panel surface when no voltage is applied. Examples of the vertical alignment mode include, but are not limited to, the MVA (Multi-Domain Vertical Alignm ent) mode, the PVA (Patterned Vertical Alignment ) mode, the ASV (Advanced Super-View) mode, etc. can be used. Also, a method called multi-domain formation or multi-domain design in which pixels are divided into several regions (sub-pixels) and the molecules are tilted in different directions can be used. ) mode, the ASV (Advanced Super-View) mode, etc. can be used. Also, a method called multi-domain formation or multi-domain design in which pixels are divided into several regions (sub-pixels) and the molecules are tilted in different directions can be used. Also, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, an anti-reflection member, etc. are provided as appropriate. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source. Also, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, an anti-reflection member, etc. are provided as appropriate. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source. Also, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, an anti-reflection member, etc. are provided as appropriate. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source.

[0165] Also, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, an anti-reflection member, etc. are provided as appropriate. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source. Also, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, an anti-reflection member, etc. are provided as appropriate. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source. Also, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, an anti-reflection member, etc. are provided as appropriate. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source. Also, a backlight, a side light, etc. may be used as the light source.

[0166] In addition, multiple light-emitting diodes (LEDs) are used as backlights to display the time-division information. It is also possible to use the field sequential driving method. By applying the char drive method, color display is possible without using a color filter. It is possible.

[0167] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is red, G is green, and B is blue). For example, RGBW (W is white) ), or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. The embodiment is not limited to a color display device, but can also be applied to a monochrome display device. You can also do this.

[0168] In addition, a light-emitting device using electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material. They are classified according to whether the material is an organic compound or an inorganic compound. The latter is called an inorganic EL element.

[0169] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and positive electrodes are released from a pair of electrodes. The holes are then injected into a layer containing a light-emitting organic compound, allowing a current to flow. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. The excited state is formed, and light is emitted when the excited state returns to the ground state. Such a light-emitting element is called a current-excited light-emitting element.

[0170] Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor- The thin-film inorganic EL element is an acceptor recombination type luminescence element. The luminescent layer is sandwiched between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of the metal ion. This is a localized light emission that utilizes organic EL elements. do.

[0171] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides, and light emitting elements of any emission structure can be applied. It is possible.

[0172] FIG. 11 shows an example of a light-emitting device using a light-emitting element as a display element. The transistor 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, a second electrode layer 4032, an electroluminescent layer 4513, a second electrode layer 4030, an electroluminescent layer 4511, a second electrode layer 4032 ... The electrode layer 4031 has a stacked structure, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed as appropriate according to the direction of the light to be extracted from the .

[0173] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferably formed using a photosensitive resin material to form an opening on the first electrode layer 4030 such that the side wall of the opening becomes an inclined surface formed with a continuous curvature. The electroluminescent layer 4511 may be composed of a single layer or may be composed of a plurality of layers laminated on top of each other. To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4513, a protective film may be formed on the second electrode layer 4031 and the partition wall 4510. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. Further, a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (encase) it with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing.

[0174] As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), an acrylic resin, a polyimide resin, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element.

[0175] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4513, a protective film may be formed on the second electrode layer 4031 and the partition wall 4510. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. Further, a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (encase) it with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), an acrylic resin, a polyimide resin, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. 01, the second substrate 4006, and the sealing material 4005. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (encase) it with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. 514 is provided and sealed. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (encase) it with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), an acrylic resin, a polyimide resin, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element.

[0176] As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), an acrylic resin, a polyimide resin, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. In addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4514, and PVC (polyvinyl chloride), an acrylic resin, a polyimide resin, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. For example, nitrogen can be used as the filler.

[0177] Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. , optical films such as a retardation plate (λ / 4 plate, λ / 2 plate), color filter, etc. may be provided as appropriate. This is acceptable. Also, an antireflection film may be provided on the polarizing plate or circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to surface irregularities and reduce reflections.

[0178] It is also possible to provide an electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and lightweight.

[0179] Although various forms of electrophoretic display devices are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0180] Thus, the electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0181] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. ​​​​​Color display is also possible by using particles having a color filter or a pigment.

[0182] Note that the first particles and the second particles in the microcapsules are made of a conductor material, an insulator material , a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. may be used.

[0183] In addition, as an electronic paper, a display device using a twist ball display method can also be applied. The twist ball display method is a method in which spherical particles painted white and black are arranged between a first electrode layer and a second electrode layer, which are electrode layers used in a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles to perform display.

[0184] FIG. 12 shows an active matrix type electronic paper as a form of a semiconductor device. The electronic paper in FIG. 12 is an example of a display device using the twist ball display method.

[0185] Between a first electrode layer 4030 connected to a transistor 4010 and a second electrode layer 4031 provided on a second substrate 4006, there are a black region 4615a and a white region 4615b, and spherical particles 4613 including a cavity 4612 filled with a liquid around them are provided. The periphery of the spherical particles 4613 is filled with a filler 4614 such as resin. The second electrode layer 4031 corresponds to a common electrode (opposing electrode). The second electrode layer 4031 is electrically connected to a common potential line.

[0186] In FIGS. 10 to 12, as the first substrate 4001 and the second substrate 4006, , in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmissivity can be used. As the plastic, an FRP (Fiberg lass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride ide) film, a polyester film, or an acrylic resin film can be used. Further, a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used.

[0187] The insulating layer 4021 can be formed using an inorganic insulating material or an organic insulating material. In addition, when using an organic insulating material having heat resistance such as an acrylic resin, a polyimide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin, it is suitable as a planarization insulating film. In addition to the above organic insulating materials, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that an insulating layer may be formed by laminating a plurality of insulating films formed of these materials.

[0188] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a spin coating method, a dipping method, spray coating, a droplet discharge method (such as an inkjet method), a printing method (screen printing, offset printing, etc.), roll coating, curtain coating ing, knife coating, etc. can be used.

[0189] The display device performs display by transmitting light from a light source or a display element. Therefore, the light is transmitted The thin films such as the substrate, insulating film, and conductive film provided in the pixel portion are all made transparent to light in the visible light wavelength region. Make it translucent.

[0190] In the first electrode layer 4030 and the second electrode layer 4031 (also referred to as the pixel electrode layer, common electrode layer, counter electrode layer, etc.) to which a voltage is applied to the display element, the light extraction direction, the location where the electrode layer is provided, and the pattern structure of the electrode layer can be selected for translucency and reflectivity. The place where it is provided, and the translucency and reflectivity may be selected according to the pattern structure of the electrode layer.

[0191] The first electrode layer 4030 and the second electrode layer 4031 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO). ), indium zinc oxide, indium tin oxide added with silicon oxide, etc., and a conductive material having translucency can be used. ), indium zinc oxide, indium tin oxide added with silicon oxide, etc., and a conductive material having translucency can be used. ), indium zinc oxide, indium tin oxide added with silicon oxide, etc., and a conductive material having translucency can be used.

[0192] Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or a plurality of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or an alloy thereof, or a nitride thereof. ), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc. ), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc. ), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc. ), or an alloy thereof, or a nitride thereof. <\

[0193] Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, ​​​For this purpose, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or derivatives thereof, polypyrrole or derivatives thereof, polythiophene or derivatives thereof, Or a copolymer consisting of two or more of aniline, pyrrole and thiophene or a derivative thereof Conductors, etc.

[0194] In addition, since transistors are easily damaged by static electricity, etc., a protective circuit for protecting the drive circuit is It is preferable to provide a path. The protection circuit is preferably constructed using a non-linear element.

[0195] As described above, by using the transistor described in Embodiment 1 as an example, a highly reliable semiconductor device can be obtained. The semiconductor device can be provided. Not only semiconductor devices with display functions, but also power devices mounted on power supply circuits, LSI semiconductor integrated circuits such as semiconductor devices with an image sensor function that reads information from an object, The present invention can be applied to semiconductor devices having various functions.

[0196] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0197] (Embodiment 3) The semiconductor device disclosed in this specification and the like is applicable to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called television receivers), computer monitors, digital cameras, digital video Cameras such as cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices) (hereinafter referred to as "games"), portable game machines, personal digital assistants, sound reproduction devices, large game machines such as pachinko machines Examples include the following. An example of an electronic device including the liquid crystal display device described in the above embodiments will be described.

[0198] FIG. 13(A) shows a notebook personal computer, which is composed of a main body 3001, a housing 30 02, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in Embodiment 1 or 2, a highly reliable notebook personal computer can be obtained.

[0199] FIG. 13(B) shows a personal digital assistant (PDA). The main body 3021 is provided with a display unit 3023 and , an external interface 3025, operation buttons 3024, etc. Also, as an accessory for operation there is a stylus 3022. By applying the semiconductor device shown in Embodiment 1 or 2 , a highly reliable personal digital assistant (PDA) can be obtained.

[0200] FIG. 13(C) shows an example of an electronic book. For example, the electronic book 2700 is composed of two housings, a housing 2 701 and a housing 2703. The housing 2701 and the housing 27 03 are integrated by a shaft portion 2711, and can perform an opening / closing operation around the shaft portion 2711 . With such a configuration, it becomes possible to perform operations similar to those of a paper book .

[0201] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703 . The display unit 2705 and the display unit 2707 may be configured to display a continuous screen , or may be configured to display different screens. When configured to display different screens Thus, for example, text can be displayed on the display unit on the right side (display unit 2705 in FIG. 13(C)), and an image can be displayed on the display unit on the left side (display unit 2707 in FIG. 13(C)). By applying the semiconductor device shown in Embodiment 1 or 2, a highly reliable electronic book 2700 can be obtained.

[0202] Further, FIG. 13(C) shows an example in which the housing 2701 is provided with an operation unit or the like. For example , in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, etc. are provided. Pages can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit. Also, the back surface or side surface of the housing may be configured to be provided with external connection terminals (such as earphone terminals, USB terminals), a recording medium insertion part, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0203] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. With wireless, it is also possible to purchase and download desired book data, etc. from an electronic book server.

[0204] FIG. 14(D) shows a smartphone, which includes a housing 2800, buttons 2801, a microphone phone 2802, a display unit 2803 with a touch panel, a speaker 2804, and a camera lens 2805, and has a function as a mobile phone. By applying the semiconductor device shown in Embodiment 1 or 2, a highly reliable smartphone can be obtained.

[0205] ​​​The display unit 2803 changes the display direction as appropriate according to the usage mode. Also, since the camera lens 2805 is provided on the same plane as the display unit 280 3, video phone is possible. The speaker 2804 and the microphone 2802 are not limited to voice calls, and are capable of video phone, recording, playback, etc. and the like.

[0206] Also, the external connection terminal 2806 can be connected to various cables such as an AC adapter and a USB cable, and is capable of charging and data communication with a personal computer, etc. Also, it is possible to insert a recording medium into an external memory slot (not shown) to support storage and transfer of a larger amount of data.

[0207] In addition to the above functions, it may be equipped with an infrared communication function, a television reception function, etc.

[0208] Fig. 13(E) shows a digital video camera, which is composed of a main body 3051, a display unit (A) 3057, an eyepiece 3053, an operation switch 3054, a display unit (B) 3055, a battery 3056, etc. By applying the semiconductor device shown in Embodiment 1 or 2, a highly reliable digital video camera can be obtained.

[0209] Fig. 13(F) shows an example of a television device. The television device 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display images. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. By applying the semiconductor device shown in Embodiment 1 or 2, a highly reliable television device 9600 can be obtained.

[0210] ​​​​​​ The operation of the television apparatus 9600 can be performed by operation switches provided on the housing 9601 or a separate remote controller. Also, the remote controller may be configured to include a display unit for displaying information output from the remote controller.

[0211] Note that the television apparatus 9600 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and can further be connected to a communication network by wire or wireless via the modem, so as to perform one-way (from sender to receiver) or two-way information communication (between sender and receiver, or between receivers, etc.).

[0212] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combinations with the configurations, methods, etc. shown in other embodiments.

Example

[0213] In this example, the results of SIMS measurement of the concentration of silicon contained in the oxide target will be described.

[0214] First, the oxide target used in this example will be described.

[0215] As sample A, an In-Ga-Zn-based oxide target (atomic ratio In:Ga:Z n = 2:1:3) was used, as sample B, an In-Ga-Zn-based oxide target (atomic ratio In:Ga:Zn = 3:1:2), and as sample C, an In-Sn-Zn-based oxide (atomic ratio In:Sn:Zn = 2:1:3) was used. Also, as a standard sample D, an In-Ga-Zn-based oxide target with silicon added (atomic ratio In:Ga:Z n = 1:1:1) was used.

[0216] For samples A, B, C, and standard sample D, SIMS measurements were performed to examine the concentration of silicon contained in each sample.

[0217] Figure 14 shows the results of SIMS measurements of samples A to C and standard sample D. shown.

[0218] As shown in Figure 14, the concentration of silicon in sample A is 4×10 18 atoms / cm 3 the concentration of silicon in sample B is 3×10 17 atoms / cm 3 the concentration of silicon in sample C is 2×10 17 atoms / cm 3 and the concentration of silicon in standard sample D is 2×10 18 atoms / cm 3 It was found that. Note that the SIMS measurement results of samples A to C in this example are the results quantified by standard sample D. to sample C are the results quantified by standard sample D.

[0219] The above data can be used as a material to determine whether silicon other than the silicon contained in the target (for example, silicon in the insulating film mixed in by mixing) is contained in the oxide semiconductor film when forming the oxide semiconductor film using the targets of samples A to C and standard sample D. For example, in an oxide semiconductor film formed using sample A (an oxide target with In:Ga:Zn = 2:1:3 (atomic ratio)) as a target, the silicon concentration in the film is 4×10 whether or not is contained in the oxide semiconductor film.

[0220] For example, in an oxide semiconductor film formed using sample A (an oxide target with In:Ga:Zn = 2:1:3 (atomic ratio)) as a target, the silicon concentration in the film is 4×10 is 4×10 18atoms / cm 3 When it is higher, it can be determined that silicon is mixed in from parts other than the target.

Example

[0221] In the above-described embodiment, it was described that the mixing of the insulating film constituent elements into the oxide semiconductor film is caused by the mixing that occurs when forming the oxide semiconductor film. However, by performing a heat treatment on the substrate after forming the oxide semiconductor film, it is also possible that the insulating film constituent elements diffuse into the oxide semiconductor. Therefore, in this example, an experiment for investigating whether the mixing of the insulating film constituent elements into the oxide semiconductor film is due to thermal diffusion will be described.

[0222] The experimental content is as follows. First, three substrates having a structure in which an insulating film and an oxide semiconductor film are formed on the substrate were prepared. Then, a sample without heat treatment (hereinafter referred to as sample E), a sample subjected to a heat treatment at 450 °C (hereinafter referred to as sample F), and a sample subjected to a heat treatment at 650 °C (hereinafter referred to as sample G) were produced. Then, for each sample, Time-of-flight secondary ion mass spectrometry (ToF-SIMS: Time-of-flight secondary ion mass spectrometer) was used to measure the silicon concentration near the interface with the gate insulating film in the oxide semiconductor film.

[0223] First, the structure of the sample used for the ToF-SIMS measurement is shown in FIG. 15.

[0224] The sample shown in FIG. 15 has a silicon oxide film 202 formed on a silicon substrate 200, and chemical mechanical polishing (CMP: Chemical Mechanical Polishing) The apparatus was used to enhance the flatness of the surface, the IGZO film 204 was formed, and finally heat treatment was performed. This is the case.

[0225] The silicon oxide film 202 was formed using a sputtering apparatus. The formation conditions of the silicon oxide film 20 2 were as follows: substrate temperature: 100 °C, gas flow rate: Ar / O2 = 25 sccm / 25 scc m, film formation power: 1.5 kW (RF power supply), film formation pressure: 0.4 Pa, film thickness: 300 nm. Note that a silicon oxide target was used as the sputtering target. Before forming the silicon oxide film 202, the oxide film formed on the surface of the silicon substrate 200 was removed with hydrofluoric acid.

[0226] The IGZO film 204 was formed using a sputtering apparatus. The formation conditions of the IGZO film 204 were as follows: substrate temperature: 200 °C, gas flow rate: Ar / O2 = 30 sccm / 15 sccm, film formation power: 0.5 kW (DC power supply), film formation pressure: 0.4 Pa, film thickness: 15 nm. Note that an oxide target with In:Ga:Zn = 3:1:2 [atomic ratio] was used as the sputtering target.

[0227] For the heat treatment, the substrate was introduced into an electric furnace using a resistance heating element or the like for heat treatment. The treatment conditions were as follows: for sample F, the heating temperature was 450 °C and the heating time was 1 hour; for sample G the heating temperature was 650 °C and the heating time was 1 hour. Note that the heating atmosphere for both samples was a mixed atmosphere of nitrogen and oxygen. Also, sample E was not subjected to heat treatment.

[0228] Next, for samples E to G, from the substrate surface side (IGZO film 204 side), T oF-SIMS measurement was carried out to measure the silicon concentration in the IGZO film near the interface with the silicon oxide film. The results are shown in Fig. 16.

[0229] From Fig. 16, in all samples, the silicon concentration in the oxide semiconductor film near the silicon oxide film interface is higher than the silicon concentration of 3×10 ato 17 ms / cm in the In-Ga-Zn-based oxide target (atomic ratio 3 is In:Ga:Zn = 3:1:2) described in Example 1. Therefore, it can be said that the silicon measured in the oxide semiconductor film near the gate insulating film interface is not silicon caused by the In-Ga-Zn-based oxide target.

[0230] Also, from Fig. 16, in the sample without heat treatment (Sample E) and the samples with heat treatment (Sample F and Sample G), no significant difference is confirmed in the slope of the silicon concentration in the IGZO film near the silicon oxide film interface (which can also be said to be the Si concentration gradient). Therefore, it can be said that the mixing of the insulating film constituent elements into the oxide semiconductor film is due to mixing rather than thermal diffusion.

Example

[0231] In this example, an experiment was investigated on whether the mixing of the insulating film constituent elements into the oxide semiconductor film caused by mixing can be suppressed by weakening the film formation power of the oxide semiconductor film. The experimental content is as follows: First, an insulating film was formed on a substrate, and four types of electric power was used to form an oxide semiconductor film on the insulating film.

[0232] ​​​​After deposition under the power conditions (1kW, 5kW, 9kW and 1kW + 5kW), Four types of samples were prepared by heat treatment. The silicon concentration near the interface with the gate insulating film in the body film was measured using the ToF-SIMS method. and measured.

[0233] First, the structure of the sample used for ToF-SIMS measurement is shown in FIG.

[0234] The sample shown in FIG. 17 is a glass substrate 300 on which a silicon oxynitride film 302 is formed. After that, an IGZO film 304 was formed, and finally, a heat treatment was performed.

[0235] The silicon oxynitride film 302 was formed using a high density plasma CVD apparatus. The conditions for forming the silicon film 302 were: substrate temperature: 325°C, gas flow rate: SiH4 / N2O / A r=250sccm / 2500sccm / 2500sccm, film-forming power: 5kW x 4 units ( The conditions were: microwave power source, film formation pressure: 30 Pa, film thickness: 100 nm. Before forming the contact film 302, the surface of the glass substrate 300 is cleaned to remove particles and the like. Ta.

[0236] The IGZO film 304 was formed using a sputtering device. The conditions were: substrate temperature: 170°C, gas flow rate: Ar / O2 = 100 sccm / 100 sccm The deposition pressure was 0.6 Pa, the film thickness was 35 nm, and the conditions were 1 kW, 5 kW, 9 kW, and 1 kW+ Film formation was carried out under four conditions of power of 5 kW (all using AC power). The target used was an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. there was.

[0237] Note that "1 kW + 5 kW" of the above-described film-forming power means that the first 5 nm of film formation was performed at a power of 1 kW , and the subsequent 30 nm of film formation was performed at a power of 5 kW. Also, hereinafter, a sample in which an oxide semiconductor film was formed at 9 kW is sample H, a sample formed at 5 kW is sample I, a sample formed at 1 kW is sample J, and a sample formed at 1 kW + 5 kW is referred to as sample K.

[0238] As the heat treatment, the substrate was introduced into an electric furnace using a resistance heating element or the like and heated. The treatment conditions were first heating at a heating temperature of 450 °C and a heating atmosphere of N2 for 1 hour, and then heating at a heating temperature of 650 °C and a heating atmosphere of N2 + O2 for 1 hour.

[0239] Next, for samples H to K, ToF-SIMS measurement was performed from the substrate surface side (IGZO film 304 side), and the silicon concentration in the IGZO film near the interface with the silicon oxynitride film was measured. The results are shown in FIG. 18. Note that FIG. 18(B) is an enlarged view of a part of FIG. 18(A).

[0240] From FIG. 18, it can be confirmed that in all samples, the silicon concentration in the IGZO film near the silicon oxynitride film interface is higher than 2 × 10 atoms / cm 3, which is the silicon concentration contained in the In-Ga-Zn-based oxide target (atomic ratio 18 is In:Ga:Zn = 1:1:1) described in Example 1. Therefore, it can be said that the silicon measured in the IGZO film near the silicon oxynitride film interface is not silicon caused by the In-Ga-Zn-based oxide target. 3 3

[0241] Also, from FIG. 18, the silicon concentration in the IGZO film near the interface of the silicon oxynitride film was confirmed to have a tendency to decrease as the film formation power was weakened. Therefore, by weakening the film formation power of the oxide semiconductor film, it was confirmed that the mixing of the insulating film constituent elements into the oxide semiconductor film caused by mixing

[0242] can be suppressed. In addition, since the silicon concentrations of Sample J and Sample K are substantially the same, even if the oxide semiconductor film is formed with weak power at the initial film formation stage and then the film formation power is increased to form the oxide semiconductor film, it was confirmed that the mixing of the insulating film constituent elements into the oxide semiconductor film caused by mixing can be suppressed.

[0243] In this example, an oxide semiconductor film containing silicon was fabricated, and the sheet resistance measurement of the oxide semiconductor film and the results of the composition analysis using X-ray photoelectron spectroscopy (XPS) will be described.

[0244] In this example, for targets added with SiO2 at different concentrations (0 wt%, 2 wt%, 5 wt%), sputtering was performed at different gas flow rates (33% oxygen, 100% oxygen) to form an oxide semiconductor film on a glass substrate to fabricate samples.

[0245] As the sputtering target, an IGZO target with In:Ga:Zn = 1:1:1 [atomic ratio], an IGZO target with In:Ga:Zn = 1:1:1 [atomic ratio], a target obtained by adding 2 wt% of SiO2 to the IGZO target, and an IGZO target with In:Ga:Zn = 1:1:1 [atomic ratio] A target with 5 wt% of SiO2 added to the IGZO target with a ratio was used.

[0246] For each target, the gas flow rate was set to O2 = 10 sccm or Ar / O2 = 1 0 sccm / 5 sccm, and sputtering deposition of the oxide semiconductor film was carried out. Also, the other film deposition conditions were common for all samples, with the substrate temperature: 200 °C, film deposition power: 100 W (DC power supply), film deposition pressure: 0.4 Pa, and film thickness: 100 nm.

[0247] That is, sample L deposited in an atmosphere of 100% oxygen using a target without adding SiO2, sample M deposited in an atmosphere of 100% oxygen using a target with 2 wt% of SiO2 added, sample N deposited in an atmosphere of 100% oxygen using a target with 5 wt% of SiO2 added, sample O deposited in an atmosphere of 33% oxygen using a target without adding SiO2, sample P deposited in an atmosphere of 33% oxygen using a target with 2 wt% of SiO2 added, sample Q deposited in an atmosphere of 33% oxygen using a target with 5 wt% of SiO2 added were prepared.

[0248] Furthermore, samples L to Q after the above treatment were introduced into an electric furnace using a resistance heating element or the like for heat treatment. The heat treatment was carried out by heating in an N2 atmosphere at 450 °C for 1 hour, and then heating in an O2 atmosphere at 450 °C for 1 hour.

[0249] Sheet resistance measurements were performed on samples L to Q after the above treatment. The measurement results of the sheet resistance of samples L to Q are shown in the graph of Fig. 19. The vertical axis of the graph in Fig. 19 takes the sheet resistance (Ω / sq), and the horizontal axis takes the SiO2 concentration (wt ​​(%) is taken.

[0250] From the graph of FIG. 19, as the SiO2 concentration in the target increases, the sheet resistance of the oxide semiconductor film also shows a tendency to increase. In samples L and O where no SiO2 is added to the target, the sheet resistance is about 1×10 Ω / □, which is a sheet resistance that can be used as an active layer such as a transistor 6 . Also, in samples M and P where the SiO2 concentration in the target is 2 wt%, the sheet resistance is 1×10 Ω / □ to 3×10 6 Ω / □, which is a preferable sheet resistance for use as an active layer such as a transistor . However, in samples N and Q where the SiO2 concentration in the target is 5 wt%, the sheet resistance is greater than the measurement upper limit, and there is a risk that the on-current will decrease when used as an active layer such as a transistor 6 . Thus, it is preferable that the SiO2 concentration in the target used for forming the oxide semiconductor film of the transistor is low. For example, the SiO2 concentration in the target may be about 2 wt% or less .

[0251] As described above, it is preferable that the SiO2 concentration in the target used for forming the oxide semiconductor film of the transistor is low. For example, the SiO2 concentration in the target may be about 2 wt% or less .

[0252] Furthermore, in this example, oxide semiconductor films were formed on silicon substrates under the same conditions as samples M and N to prepare samples, and composition analysis was performed using XPS .

[0253] As the sputtering target, a target obtained by adding 2 wt% of SiO2 to an IGZO target with In:Ga:Zn = 1:1:1 [atomic ratio], and a target obtained by adding 5 wt% of SiO2 to an IGZO target with In:Ga:Zn = 1 :1:1 [atomic ratio] were used. was used.

[0254] The film formation conditions were as follows: gas flow rate: O2 = 10 sccm, substrate temperature: 200 °C, film formation power: 100 W (DC power supply), film formation pressure: 0.4 Pa, film thickness: 15 nm.

[0255] That is, a sample R was formed by film formation in an atmosphere of 100% oxygen using a target with 2 wt% SiO2 added. A sample S was formed by film formation in an atmosphere of 100% oxygen using a target with 5 wt% SiO2 added. was prepared.

[0256] As a result of performing composition analysis on samples R and S using XPS, the concentration of silicon in the oxide semiconductor film of sample R was 1.1 atomic%, and the concentration of silicon in the oxide semiconductor film of sample S was 2.6 atomic%. That is, the concentration of silicon in the oxide semiconductor film using a target with 2 wt% SiO2 added was 1.1 atomic%, and the concentration of silicon in the oxide semiconductor film using a target with 5 wt% SiO2 added was 2 .6 atomic%. As described above, when impurities such as silicon are mixed in the vicinity of the interface between the oxide semiconductor film and the gate insulating film due to mixing or the like, the resistance of the channel formation region increases, and there is a risk that the on-current of the transistor decreases. Therefore, it is important to reduce the concentration of silicon as described above in the vicinity of the interface between the oxide semiconductor film and the gate insulating film.

[0257] As described above, when impurities such as silicon are mixed in the vicinity of the interface between the oxide semiconductor film and the gate insulating film due to mixing or the like, the resistance of the channel formation region increases, and the on-current of the transistor may decrease. Therefore, it is important to reduce the concentration of silicon as described above in the vicinity of the interface between the oxide semiconductor film and the gate insulating film. increases, and the on-current of the transistor may decrease. Therefore, it is important to reduce the concentration of silicon as described above in the vicinity of the interface between the oxide semiconductor film and the gate insulating film. As described above, when impurities such as silicon are mixed in the vicinity of the interface between the oxide semiconductor film and the gate insulating film due to mixing or the like, the resistance of the channel formation region increases, and the on-current of the transistor may decrease. Therefore, it is important to reduce the concentration of silicon as described above in the vicinity of the interface between the oxide semiconductor film and the gate insulating film. increases, and the on-current of the transistor may decrease. Therefore, it is important to reduce the concentration of silicon as described above in the vicinity of the interface between the oxide semiconductor film and the gate insulating film.

Explanation of symbols

[0258] 100 Substrate 101 Gate electrode 102 Gate insulating film 103 Oxide semiconductor film 103a Region 103b region 103c region 105a source electrode 105b drain electrode 107 insulating film 108 channel protective film 109 protective insulating film 110 transistor 120 transistor 130 transistor 200 silicon substrate 202 silicon oxide film 204 IGZO film 300 glass substrate 302 silicon oxynitride film 304 IGZO film 2700 e - book 2701 housing 2703 housing 2705 display unit 2707 display unit 2711 shaft portion 2721 power supply 2723 operation key 2725 speaker 2800 housing 2801 button 2802 microphone 2803 display unit 2804 speaker 2805 camera lens 2806 external connection terminal 3001 main body 3002 housing 3003 display unit 3004 keyboard 3021 main body 3022 stylus 3023 display unit 3024 operation button 3025 external interface 3051 main body 3053 eyepiece 3054 operation switch 3056 battery 4001 Substrate 4002 Pixel section 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4019 Anisotropic conductive film 4021 Insulating layer 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4034 Insulating film 4510 Partition wall 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 4612 Cavity 4613 Spherical particles 4614 Filling material 4615a Black region 4615b White region 9600 Television device 9601 Housing 9603 Display section 9605 Stand

Claims

【Claim 1】 A gate electrode, a gate insulating film covering the gate electrode and containing an oxide containing silicon, an oxide semiconductor film provided in a region that is in contact with the gate insulating film and overlaps at least the gate electrode, a source electrode and a drain electrode that are electrically connected to the oxide semiconductor film, and having the oxide semiconductor film has a first region in which silicon is distributed at a concentration of 1.0 atomic % or less from the interface with the gate insulating film toward the oxide semiconductor film. A semiconductor device.

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