Semiconductor memory device

Abstract

To improve reliability.SOLUTION: According to an embodiment, a semiconductor memory device includes: first to fifth memory pillars MP1 to MP5; and third to seventh contact plugs CH1 to CH5 provided on the first to fifth memory pillars, respectively. A first amount of shift by which the third contact plug is shifted with respect to the first memory pillar, a second amount of shift by which the fourth contact plug is shifted with respect to the third memory pillar, a third amount of shift by which the fifth contact plug is shifted with respect to the third memory pillar, a fourth amount of shift by which the sixth contact plug is shifted with respect to the fourth memory pillar, and a fifth amount of shift by which the seventh contact plug is shifted with respect to the fifth memory pillar are different from each other.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] As a semiconductor memory device, a three-dimensional stacked NAND flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one embodiment of the present invention, a semiconductor memory device capable of improving reliability is provided.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes a source line, a plurality of first insulating layers and a plurality of first wiring layers provided on the source line and alternately stacked one by one, a plurality of memory pillars extending in a first direction, passing through the plurality of first insulating layers and the plurality of first wiring layers, and having one end reaching the source line, a plurality of bit lines provided above the plurality of memory pillars, arranged side by side in a second direction intersecting the first direction, and each extending in a third direction intersecting the first direction and the second direction, a plurality of first contact plugs provided on the plurality of memory pillars, a plurality of second contact plugs provided on the plurality of first contact plugs and connected to any one of the plurality of bit lines, and a plurality of first members arranged side by side in the second direction, each extending in the third direction, and separating at least the first wiring layer provided at the position farthest from the source line among the plurality of first wiring layers in the second direction. The plurality of memory pillars include a first memory pillar, a second memory pillar, a third memory pillar, a fourth memory pillar, and a fifth memory pillar arranged side by side in the third direction while alternately changing positions in the second direction in a first region between two adjacent first members among the plurality of first members in the third direction. The plurality of first contact plugs include a third contact plug provided on the first memory pillar, a fourth contact plug provided on the second memory pillar, a fifth contact plug provided on the third memory pillar, a sixth contact plug provided on the fourth memory pillar, and a seventh contact plug provided on the fifth memory pillar. The first shift amount obtained by shifting the third contact plug in the second direction with respect to the first memory pillar, the second shift amount obtained by shifting the fourth contact plug in the second direction with respect to the second memory pillar, the third shift amount obtained by shifting the fifth contact plug in the second direction with respect to the third memory pillar, the fourth shift amount obtained by shifting the sixth contact plug in the second direction with respect to the fourth memory pillar, and the fifth shift amount obtained by shifting the seventh contact plug in the second direction with respect to the fifth memory pillar are all different from each other.

Brief Description of the Drawings

[0006]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are assigned common reference numerals. When distinguishing a plurality of components having the same common reference numeral, a subscript is added to the common reference numeral for distinction. When it is not particularly necessary to distinguish a plurality of components, only the common reference numeral is assigned to the plurality of components, and no subscript is added. Here, the subscript is not limited to a subscript or a superscript, and includes, for example, a lowercase alphabet added to the end of a reference numeral, and an index indicating an array.

[0008] A semiconductor memory device according to an embodiment will be described. Hereinafter, as the semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked on a semiconductor substrate will be described as an example.

[0009] 1. Overall Configuration of Semiconductor Memory Device First, with reference to FIG. 1, an example of the overall configuration of the semiconductor memory device 1 will be described. FIG. 1 is a block diagram showing the overall configuration of the semiconductor memory device 1. In FIG. 1, a part of the connection of each component is shown by an arrow line, but the connection between the components is not limited to these.

[0010] As shown in FIG. 1, the semiconductor memory device 1 includes a memory core unit 10 and a peripheral circuit unit 20.

[0011] The memory core unit 10 includes a memory cell array 11, a row decoder 12, and a sense amplifier 13.

[0012] The memory cell array 11 is a region where non-volatile memory cell transistors (hereinafter also referred to as "memory cells") are three-dimensionally arranged. The memory cell array 11 includes a plurality of blocks BLK. In the example shown in FIG. 1, the memory cell array 11 includes blocks BLK0 to BLK3. The block BLK is, for example, a set of a plurality of memory cells that are erased in a batch. The block BLK includes a plurality of memory cells associated with rows and columns. Each block BLK includes a plurality of string units SU. In the example shown in FIG. 1, the block BLK includes five string units SU0, SU1, SU2, SU3, and SU4. The string unit SU is, for example, a set of a plurality of NAND strings NS that are selected in a batch in a write operation or a read operation. The NAND string NS includes a set of a plurality of memory cells connected in series. Note that the number of blocks BLK in the memory cell array 11 and the number of string units SU in the block BLK are arbitrary. Details of the memory cell array 11 will be described later.

[0013] The row decoder 12 is a circuit that decodes a row address. The row decoder 12 receives information regarding a row address input from an external controller (not shown). The row decoder 12 selects the row-direction wiring (word line and selection gate line) of the memory cell array 11 based on the decoding result of the information regarding the row address. The row decoder 12 supplies a voltage to the selected row-direction wiring.

[0014] The sense amplifier 13 is a circuit that writes and reads data. When reading data, the sense amplifier 13 reads data from the memory cells of any one of the blocks BLK. Also, when writing data, the sense amplifier 13 supplies a voltage based on the write data to the memory cell array 11.

[0015] The peripheral circuit section 20 includes a sequencer 21 and a voltage generation circuit 22.

[0016] The sequencer 21 controls the operation of the entire semiconductor memory device 1. More specifically, the sequencer 21 controls the voltage generation circuit 22, the row decoder 12, the sense amplifier 13, etc. during the write operation, read operation, and erase operation.

[0017] The voltage generation circuit 22 generates the voltages used in the write operation, read operation, and erase operation, and supplies them to the row decoder 12, the sense amplifier 13, etc.

[0018] 2. Circuit Configuration of Memory Cell Array Next, with reference to FIG. 2, an example of the circuit configuration of the memory cell array 11 will be described. FIG. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 11. The example shown in FIG. 2 shows the circuit diagram of one block BLK.

[0019] As shown in FIG. 2, the block BLK includes a plurality of string units SU. In the example shown in FIG. 2, the block BLK includes five string units SU0 to SU4. The string unit SU is a set of a plurality of NAND strings NS.

[0020] The NAND string NS is a set of a plurality of memory cells MC connected in series. Each of the plurality of NAND strings NS in the string unit SU is connected to one of the bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes a plurality of memory cells MC, and selection transistors ST1 and ST2. In the example shown in FIG. 2, the NAND string NS includes eight memory cells MC0 to MC7.

[0021] The memory cell MC is a memory element that stores data non-volatilely. The memory cell MC includes a control gate and a charge storage film. The memory cell MC may be of the FG (Floating Gate) type or the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type. The FG type uses a conductor for the charge storage film. The MONOS type uses an insulating layer for the charge storage film. Hereinafter, the case where the memory cell MC is of the MONOS type will be described.

[0022] The selection transistors ST1 and ST2 are switching elements. The selection transistors ST1 and ST2 are respectively used for the selection of the string unit SU during various operations.

[0023] The current paths of the selection transistor ST2, the memory cells MC0 to MC7, and the selection transistor ST1 in the NAND string NS are connected in series. The drain of the selection transistor ST1 is connected to the bit line BL. The source of the selection transistor ST2 is connected to the source line SL.

[0024] The control gates of the plurality of memory cells MC0 to MC7 in the same block BLK are commonly connected to the word lines WL0 to WL7 respectively. More specifically, for example, each of the string units SU0 to SU3 includes a plurality of memory cells MC0. The control gates of these plurality of memory cells MC0 are connected to one word line WL0. The same applies to the memory cells MC1 to MC7. For example, the control gates of the plurality of memory cells MC1 in the block BLK are connected to one word line WL1.

[0025] The gates of the plurality of select transistors ST1 within each string unit SU are commonly connected to one select gate line SGD. More specifically, the gates of the plurality of select transistors ST1 within string unit SU0 are commonly connected to select gate line SGD0. The gates of the plurality of select transistors ST1 within string unit SU1 are commonly connected to select gate line SGD1. The gates of the plurality of select transistors ST1 within string unit SU2 are commonly connected to select gate line SGD2. The gates of the plurality of select transistors ST1 within string unit SU3 are commonly connected to select gate line SGD3. The gates of the plurality of select transistors ST1 within string unit SU4 are commonly connected to select gate line SGD4.

[0026] The gates of the plurality of select transistors ST2 within block BLK are commonly connected to select gate line SGS.

[0027] Word lines WL0 to WL7, select gate lines SGD0 to SGD3, and select gate line SGS are respectively connected to row decoder 12.

[0028] Bit line BL is commonly connected to one NAND string NS of each of the plurality of string units SU of each block BLK. For example, bit line BL0 is connected to one NAND string NS within string unit SU0, one NAND string NS within string unit SU1, one NAND string NS within string unit SU2, one NAND string NS within string unit SU3, and one NAND string NS within string unit SU4. The same applies to bit lines BL1 to BLm. Each bit line BL is connected to sense amplifier 13.

[0029] Source line SL is shared, for example, among a plurality of blocks BLK.

[0030] A set of a plurality of memory cells MC connected to one word line WL within one string unit SU is denoted as, for example, "cell unit CU". In other words, the cell unit CU is a set of a plurality of memory cells MC that are collectively selected in a write operation or a read operation. A page is a unit of data that is collectively written (or read) to the cell unit CU. For example, when the memory cell MC stores 1-bit data, the storage capacity of the cell unit CU is 1 page. That is, the cell unit CU stores 1-page data. The cell unit CU may have a storage capacity of 2 pages or more based on the number of bits of data stored by the memory cell MC. The memory cell MC may be a SLC (Single Level Cell) that stores 1-bit data, or an MLC (Multi Level Cell) that stores 2-bit data. Also, the memory cell MC may be a TLC (Triple Level Cell) that stores 3-bit data, or a QLC (Quad Level Cell) that stores 4-bit data, or a PLC (Penta Level Cell) that stores 5-bit data.

[0031] 3. Structure of Memory Cell Array Next, an example of the structure of the memory cell array 11 will be described. In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL. The Y direction corresponds to the extending direction of the bit line BL. The Z direction corresponds to the direction intersecting the X direction and the Y direction. In a plan view, hatching is appropriately added to make the figure easier to view. The hatching added to the plan view is not necessarily related to the material or characteristics of the component to which the hatching is added. In a cross-sectional view, the illustration of the configuration may be appropriately omitted to make the figure easier to view.

[0032] 3.1 Overview of Planar Layout First, referring to FIG. 3, an example of the planar layout of the memory cell array 11 will be described. FIG. 3 is a plan view showing an example of the memory cell array 11. The example shown in FIG. 3 shows regions corresponding to four blocks BLK0 to BLK3.

[0033] As shown in FIG. 3, the planar layout of the memory cell array 11 is divided, for example, in the X direction into a memory region MA, and lead-out regions HA1 and HA2. The memory cell array 11 also includes a plurality of members SLT and SHE.

[0034] The memory region MA is disposed between the lead-out region HA1 and the lead-out region HA2. The memory region MA is a region including a plurality of NAND strings NS. Each of the lead-out regions HA1 and HA2 is a region used for connection between the stacked wirings (for example, selection gate lines SGS, word lines WL0 to WL7, and selection gate line SGD) stacked in the Z direction and the row decoder 12.

[0035] The plurality of members SLT each extend in the X direction and are arranged in the Y direction. Each member SLT crosses the memory region MA and the lead-out regions HA1 and HA2 in the X direction in the boundary region between adjacent blocks BLK. Each member SLT may have, for example, a structure in which an insulator or a plate-like contact is embedded. Each member SLT disconnects adjacent stacked wirings via the member SLT.

[0036] The plurality of members SHE each extend along the X direction and are arranged in the Y direction. In this example, four members SHE are respectively arranged between adjacent members SLT. Each member SHE crosses the memory region MA in the X direction. Both ends of each member SHE are respectively included in the lead-out regions HA1 and HA2. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE disconnects adjacent selection gate lines SGD via the member SHE. Therefore, the selection gate line SGD is disconnected for each string unit SU by the member SLT and the member SHE.

[0037] Each region delimited by the member SLT corresponds to one block BLK. Also, each region delimited by the members SLT and SHE corresponds to one string unit SU.

[0038] Note that the planar layout of the memory cell array 11 is not limited to the layout described above. For example, the number of members SHE arranged between adjacent members SLT can be designed to be any number. The number of string units SU formed between adjacent members SLT can be changed based on the number of members SHE arranged between adjacent members SLT.

[0039] 3.2 Planar Layout of Memory Region Next, with reference to FIG. 4, the details of the planar layout in the memory region MA will be described. FIG. 4 is an enlarged plan view of the region V1 in FIG. 3. FIG. 4 shows a region including one block BLK (i.e., string units SU0 to SU4) and two members SLT sandwiching the block BLK.

[0040] As shown in FIG. 4, in the memory region MA, the memory cell array 11 includes a plurality of memory pillars MP, a plurality of contact plugs CH, a plurality of contact plugs VY, and a plurality of bit lines BL. Also, each member SLT includes a conductor LI and a spacer SP.

[0041] Each of the memory pillars MP functions as, for example, one NAND string NS. A plurality of memory pillars MP are arranged in a zigzag pattern of 25 columns in the X direction, for example, in the region between two adjacent members SLT. In other words, a plurality of memory pillars MP are arranged in a zigzag pattern of 25 columns in the X direction in the region corresponding to one block BLK. That is, a plurality of memory pillars MP are arranged in a zigzag pattern of 5 columns in the X direction in the region between two adjacent members SLT or SHE extending in the X direction, that is, in the region corresponding to one string unit SU. For example, between the memory pillar MP in the 5th column and the memory pillar MP in the 6th column, between the memory pillar MP in the 10th column and the memory pillar MP in the 11th column, between the memory pillar MP in the 15th column and the memory pillar MP in the 16th column, and between the memory pillar MP in the 20th column and the memory pillar MP in the 21st column, as counted from the left side of the paper surface of FIG. 4, members SHE are respectively provided.

[0042] A plurality of bit lines BL each extend in the Y direction and are arranged in the X direction. The bit lines BL are arranged above the memory pillars MP. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU in a plan view seen from the Z direction. In the example shown in FIG. 4, five bit lines BL are arranged so as to overlap with any one of the memory pillars MP arranged in a zigzag pattern of 5 columns in one string unit SU.

[0043] On each memory pillar MP, a contact plug CH is provided. In the present embodiment, the contact plug CH is arranged at a position where the central axis extending in the Z direction of the contact plug CH is shifted in the X direction from the central axis extending in the Z direction of the memory pillar MP. That is, in a plan view, the position of the central axis of the contact plug CH is different from the position of the central axis of the memory pillar MP. In the following description, the arrangement in which the contact plug CH is shifted in the X direction with respect to the memory pillar MP is referred to as "CH shift". Also, the shift amount of the CH shift is referred to as the "CH shift amount". For example, in one string unit SU, the CH shift amounts of the five contact plugs CH corresponding to the five memory pillars MP arranged in a staggered pattern in five columns in the X direction are different. Details of the CH shift amount will be described later.

[0044] On the contact plug CH, a contact plug VY is provided. The memory pillar MP is electrically connected to any one bit line BL via the contact plug CH and the contact plug VY. The contact plug VY is arranged so as to overlap the connected bit line BL in a plan view. For this reason, in a plan view, the position of the central axis of the contact plug VY is different from the position of the central axis of the contact plug CH.

[0045] Note that the number and arrangement of the memory pillars MP, the contact plugs CH, the contact plugs VY, and the member SHE, etc. between adjacent members SLT are not limited to the configuration described with reference to FIG. 4, and can be changed as appropriate.

[0046] The conductor LI is a conductor that spreads in the XZ plane provided in the member SLT. The spacer SP is an insulator provided on the side surface of the conductor LI. In other words, the conductor LI is surrounded by the spacer SP in a plan view. The conductor LI is electrically connected to the source line SL. Note that the conductor LI may be removed. In this case, the inside of the member SLT is filled with an insulator.

[0047] 3.3 Cross-sectional Structure of Memory Region Next, with reference to FIG. 5, an example of the cross-sectional structure of the memory region MA will be described. FIG. 5 is a cross-sectional view of the memory region MA along the V2-V2 line shown in FIG. 4.

[0048] As shown in FIG. 5, the memory cell array 11 includes a semiconductor substrate 30, insulating layers 31, 33, 35, and 36, a semiconductor layer 32, and wiring layers 34 and 37.

[0049] The semiconductor substrate 30 is, for example, a P-type semiconductor. An insulating layer 31 is provided on the semiconductor substrate 30. The insulating layer 31 includes, for example, silicon oxide (SiO). The semiconductor substrate 30 and the insulating layer 31 may include a circuit (not shown). The circuits included in the semiconductor substrate 30 and the insulating layer 31 correspond to a row decoder 12, a sense amplifier 13, and the like. A semiconductor layer 32 is provided on the insulating layer 31.

[0050] The semiconductor layer 32 is, for example, a plate-shaped semiconductor extending along the XY plane. The semiconductor layer 32 is used as a source line SL. The semiconductor layer 32 includes, for example, three semiconductor layers 32a, 32b, and 32c. The semiconductor layer 32a is provided on the insulating layer 31. The semiconductor layer 32b is provided on the semiconductor layer 32a. The semiconductor layer 32c is provided on the semiconductor layer 32b. The semiconductor layer 32b is formed, for example, by replacing a sacrificial layer provided between the semiconductor layer 32a and the semiconductor layer 32c. The semiconductor layers 32a to 32c include, for example, silicon. Further, the semiconductor layers 32a to 32c include, for example, phosphorus (P) as a semiconductor impurity.

[0051] On the semiconductor layer 32, for example, ten insulating layers 33 and ten wiring layers 34 are alternately stacked one by one. In the example shown in FIG. 5, the ten wiring layers 34 function as a selection gate line SGS, word lines WL0 to WL7, and a selection gate line SGD in order from the side closer to the semiconductor layer 32. Note that a plurality of wiring layers 34 functioning as the selection gate lines SGS and SGD may be provided respectively. The insulating layer 33 contains, for example, silicon oxide. As a conductive material of the wiring layer 34, for example, a stacked structure of titanium nitride (TiN) / tungsten (W) is used. In this case, titanium nitride is formed so as to cover tungsten. Titanium nitride has a function as a barrier layer for suppressing the oxidation of tungsten or an adhesion layer for improving the adhesion of tungsten when tungsten is formed by, for example, CVD (chemical vapor deposition).

[0052] Further, the wiring layer 34 may contain a high-k dielectric material such as aluminum oxide (AlO). In this case, the high-k dielectric material is formed so as to cover the conductive material. For example, in each of the wiring layers 34, the high-k dielectric material is provided so as to be in contact with the insulating layers 33 or 35 provided above and below the wiring layer 34 and the side surfaces of the memory pillars MP. Then, titanium nitride is provided so as to be in contact with the high-k dielectric material. Then, tungsten is provided so as to be in contact with titanium nitride and fill the inside of the wiring layer 34. For example, when aluminum oxide is used as the high-k dielectric material, the memory cell MC is also referred to as a MANOS (Metal - Aluminum - Nitride - Oxide - Silicon) type.

[0053] An insulating layer 35 is provided on the uppermost wiring layer 34 functioning as the selection gate line SGD. In other words, an insulating layer 35 is provided on the wiring layer 34 provided at the position farthest from the semiconductor layer 32. The insulating layer 35 contains, for example, silicon oxide.

[0054] Inside the memory cell array 11, a plurality of memory pillars MP are provided. For example, the memory pillar MP has a substantially cylindrical shape extending in the Z direction. The memory pillar MP penetrates through 10 wiring layers 34. The bottom surface of the memory pillar MP reaches the semiconductor layer 32. Note that the memory pillar MP may have a structure in which a plurality of pillars are connected in the Z direction.

[0055] Each memory pillar MP includes, for example, a core film 40, a semiconductor film 41, and a stacked film 42. The core film 40 extends in the Z direction. For example, the upper end of the core film 40 is located in a layer above the wiring layer 34, and the lower end of the core film 40 is located in the same layer as the semiconductor layer 32. The semiconductor film 41 extends in the Z direction and covers the periphery of the core film 40. The side surface of the semiconductor film 41 is in contact with the semiconductor layer 32b. The stacked film 42 covers the side surface and the bottom surface of the semiconductor film 41 except for the portion where the semiconductor film 41 and the semiconductor layer 32b are in contact. The core film 40 includes an insulator such as silicon oxide. The semiconductor film 41 includes, for example, silicon. The stacked film 42 includes a charge storage film. Details of the configuration of the stacked film 42 will be described later.

[0056] By combining the memory pillar MP with the wiring layer 34 that functions as word lines WL0 to WL7, memory cells MC0 to MC7 are formed. Similarly, by combining the memory pillar MP with the wiring layer 34 that functions as the selection gate line SGD, the selection transistor ST1 is formed. By combining the memory pillar MP with the wiring layer 34 that functions as the selection gate line SGS, the selection transistor ST2 is formed.

[0057] On the insulating layer 35, a wiring layer 37 is provided via an insulating layer 36. The insulating layer 36 includes, for example, silicon oxide. The wiring layer 37 is formed in a line shape extending in the Y direction, for example, and functions as a bit line BL. In a region not shown, a plurality of wiring layers 37 are arranged side by side in the X direction. The wiring layer 37 includes, for example, copper (Cu) as a conductive material.

[0058] On the semiconductor film 41 of each memory pillar MP, a contact plug CH is provided. The contact plug CH has, for example, a substantially cylindrical shape extending in the Z direction. More specifically, the contact plug CH has, for example, a frustum of a cone shape in which the area of the upper surface is larger than the area of the bottom surface. The contact plug CH contains, for example, copper as a conductive material.

[0059] On each contact plug CH, a contact plug VY is provided. The contact plug VY has, for example, a columnar shape extending in the Z direction. More specifically, the contact plug VY has, for example, a frustum of an ellipse shape in which the area of the upper surface is larger than the area of the bottom surface. In the example shown in FIG. 5, in each of the cross-sectional regions of the string unit SU separated by the members SLT and SHE, a plurality of contact plugs VY commonly connected to one wiring layer 37 are shown. The memory pillars MP in which the contact plugs VY are not shown are connected to different wiring layers 37 via contact plugs VY (not shown) in regions not shown.

[0060] The member SLT separates ten wiring layers 34. The conductor LI in the member SLT is provided along the spacer SP. The upper end of the conductor LI is located in the layer between the wiring layer 34 and the wiring layer 37. The lower end of the conductor LI is in contact with the semiconductor layer 32b. The spacer SP is provided between the conductor LI and the wiring layer 34. The space between the conductor LI and the wiring layer 34 is separated and insulated by the spacer SP.

[0061] The member SHE separates the wiring layer 34 that functions as the selection gate line SGD. In other words, the member SHE separates the wiring layer 34 provided at the position farthest from the semiconductor layer 32 among the plurality of wiring layers 34. The upper end of the member SHE is located in the layer between the wiring layer 34 and the wiring layer 37. The lower end of the member SHE is located in the layer between the wiring layer 34 that functions as the selection gate line SGD and the wiring layer 34 that functions as the word line WL. The lower end of the member SHE becomes deeper according to the number of the wiring layers 34 that function as the selection gate line SGD. The member SHE includes an insulator such as silicon oxide. The upper end of the member SHE and the upper end of the member SLT may or may not be aligned. Also, the upper end of the member SHE and the upper end of the memory pillar MP may or may not be aligned.

[0062] Next, with reference to FIG. 6, an example of the cross-sectional structure of the memory pillar will be described. FIG. 6 is a cross-sectional view taken along the line V4-V4 of FIG. 5. More specifically, FIG. 6 shows the cross-sectional structure of the memory pillar MP in a layer parallel to the XY plane and including the wiring layer 34.

[0063] As shown in FIG. 6, the stacked film 42 includes, for example, a tunnel insulating film 43, a charge storage film 44, and a block insulating film 45.

[0064] In the cross-section including the wiring layer 34, the core film 40 is provided, for example, at the central portion of the memory pillar MP. The semiconductor film 41 surrounds the side surface of the core film 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor film 41. The charge storage film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the charge storage film 44. The wiring layer 34 surrounds the side surface of the block insulating film 45.

[0065] The semiconductor film 41 is used as the channels (current paths) of the memory cells MC0 to MC7 and the selection transistors ST1 and ST2. Each of the tunnel insulating film 43 and the block insulating film 45 includes, for example, silicon oxide. The charge storage film 44 has a function of storing charges and includes, for example, silicon nitride. Thereby, each memory pillar MP can function as one NAND string NS.

[0066] 4. Arrangement of Contact Plug CH Next, the details of the arrangement of contact plug CH will be described.

[0067] 4.1 CH Shift First, referring to FIG. 7, the CH shift will be described. FIG. 7 is a diagram showing an example of the positional relationship among the memory pillar MP, the contact plug CH and VY, and the bit line BL with and without the CH shift. FIG. 7 shows a plan view and a cross section focusing on one memory pillar MP.

[0068] As shown in FIG. 7, a plurality of bit lines BL are arranged above one memory pillar MP. The memory pillar MP is electrically connected to any one of these plurality of bit lines BL via the contact plug CH and VY.

[0069] In the example shown in FIG. 7, the memory pillar MP is electrically connected to the bit line BL arranged on the right side of the paper surface among the three bit lines BL provided above the memory pillar MP. The contact plug VY is arranged under the connected bit line BL. Therefore, the arrangement of the contact plug VY in the X direction is determined corresponding to the arrangement of the connected bit line BL. For this reason, the contact plug VY can be arranged at a position shifted in the X direction from the center of the memory pillar MP.

[0070] FIG. 7(a) shows the case where the memory pillar MP and the contact plug CH are arranged on the same coaxial line, that is, the case where there is no CH shift. In this case, when the distance from the center of the memory pillar MP to the contact plug VY in the X direction increases, the contact area between the upper surface of the contact plug CH and the lower surface of the contact plug VY decreases. In other words, when the shift amount of the contact plug VY increases, the contact plug VY slips off. As a result, a connection failure (contact failure) occurs between the contact plug CH and the contact plug VY.

[0071] On the other hand, (b) of FIG. 7 shows a case where the memory pillar MP and the contact plug CH are not coaxially arranged, that is, a case where there is a CH shift. For example, the central axis CAc of the contact plug CH is shifted from the central axis CAm of the memory pillar MP toward the contact plug VY. As a result, even if the shift amount of the contact plug VY increases, a reduction in the contact area between the upper surface of the contact plug CH and the lower surface of the contact plug VY can be suppressed. Thereby, a connection failure (contact failure) between the contact plug CH and the contact plug VY can be suppressed due to the CH shift.

[0072] 4.2 Specific Examples of CH Shift Amount Next, with reference to FIGS. 8 and 9, specific examples of the CH shift amount of the contact plug CH will be described. FIG. 8 is an enlarged plan view of the region V3 in FIG. 4. FIG. 9 is a table showing an example of the CH shift amount in one block BLK. In FIG. 8, in each of the two string units SU0 and SU1, five memory pillars MP arranged in a staggered pattern in five columns in the X direction, the corresponding contact plugs CH and VY, and the bit line BL are extracted and shown. In the description using FIG. 8, the direction toward the upper side of the paper surface is denoted as the +X direction, and the direction toward the lower side of the paper surface is denoted as the -X direction. Further, the +X direction is defined as the + (plus) direction of the CH shift amount, and the -X direction is defined as the - (minus) direction of the CH shift amount.

[0073] As shown in FIG. 8, for example, in the string unit SU0, the five memory pillars MP arranged in a staggered pattern in five columns in the X direction are, in order from the left side of the paper surface, the memory pillars MP01, MP02, MP03, MP04, and MP05. Then, the contact plugs CH arranged on the memory pillars MP01, MP02, MP03, MP04, and MP05 are respectively the contact plugs CH01, CH02, CH03, CH04, and CH05. Further, the contact plugs VY arranged on the contact plugs CH01, CH02, CH03, CH04, and CH05 are respectively the contact plugs VY01, VY02, VY03, VY04, and VY05.

[0074] Similarly, in the string unit SU1, five memory pillars MP arranged in a staggered pattern in five columns in the X direction are, in order from the left side of the paper surface, the memory pillars MP11, MP12, MP13, MP14, and MP15. And the contact plugs CH arranged on the memory pillars MP11, MP12, MP13, MP14, and MP15 are respectively the contact plugs CH11, CH12, CH13, CH14, and CH15. Further, the contact plugs VY arranged on the contact plugs CH11, CH12, CH13, CH14, and CH15 are respectively the contact plugs VY11, VY12, VY13, VY14, and VY15.

[0075] Note that in the description of FIG. 8, when neither the string unit SU0 nor SU1 is limited, it is simply denoted as the memory pillars MP1 to MP5, the contact plugs CH1 to CH5, and the contact plugs VY1 to VY5.

[0076] Also, in each string unit SU, the five bit lines BL arranged above the five memory pillars MP1 to M5 are, in order in the +X direction, the bit lines BL(k), BL(k + 1), BL(k + 2), BL(k + 3), and BL(k + 4) (k is an integer of 0 or more and (m - 4) or less). Further, the CH shift amount of the entire contact plug CH is defined as the variable A, and the difference in the CH shift amount between two adjacent contact plugs CH in the Y direction is defined as the variable B.

[0077] First, the string unit SU0 will be described.

[0078] The memory pillars MP01 to MP05 are arranged on a staggered pattern in five columns in the Y direction. The memory pillars MP01, MP03, and MP05 have the same position in the X direction. Also, the memory pillars MP02 and MP04 have the same position in the X direction. The memory pillars MP01 to MP05 are arranged side by side in the Y direction while alternately changing their positions in the X direction.

[0079] For example, the memory pillar MP01 is connected to the bit line BL(k). That is, the contact plug VY01 is disposed under the bit line BL(k). The contact plug VY01 is disposed at a position shifted in the -X direction from the center of the memory pillar MP01. Therefore, the CH shift of the contact plug CH01 is in the -X direction from the center of the memory pillar MP01. For example, the CH shift amount of the contact plug CH01 at this time is A - 2B.

[0080] For example, the memory pillar MP02 is connected to the bit line BL(k + 3). That is, the contact plug VY02 is disposed under the bit line BL(k + 3). For example, two memory pillars MP adjacent to each other in the Y direction are connected to two different bit lines BL sandwiching one or more bit lines BL therebetween. Specifically, for example, the bit line BL connected to the memory pillar MP02 is selected from those other than the bit line BL(k + 1). The distance from the center of the memory pillar MP02 to the contact plug VY02 is shorter than the distance from the center of the memory pillar MP01 to the contact plug VY01. Therefore, the CH shift amount of the contact plug CH02 is obtained by adding +B to the CH shift amount (A - 2B) of the contact plug CH01 adjacent to it in the Y direction, and is A - B.

[0081] For example, the memory pillar MP03 is connected to the bit line BL(k + 1). That is, the contact plug VY03 is disposed under the bit line BL(k + 1). The CH shift amount of the contact plug CH03 is obtained by adding +B to the CH shift amount (A - B) of the contact plug CH02 adjacent to it in the Y direction, and is A.

[0082] For example, the memory pillar MP04 is connected to the bit line BL(k+4). That is, the contact plug VY04 is disposed under the bit line BL(k+4). The contact plug VY04 is disposed at a position shifted in the +X direction from the center of the memory pillar MP04. The CH shift amount of the contact plug CH04 is added with B to the CH shift amount (A) of the contact plug CH03 adjacent in the Y direction, resulting in A+B.

[0083] For example, the memory pillar MP05 is connected to the bit line BL(k+2). That is, the contact plug VY05 is disposed under the bit line BL(k+2). The contact plug VY05 is disposed at a position shifted in the +X direction from the center of the memory pillar MP05. The CH shift amount of the contact plug CH05 is added with B to the CH shift amount (A+B) of the contact plug CH04 adjacent in the Y direction, resulting in A+2B.

[0084] Next, the string unit SU1 will be described.

[0085] For example, the memory pillar MP11 is connected to the bit line BL(k+4) in the same manner as the memory pillar MP04. That is, the contact plug VY11 is disposed under the bit line BL(k+4). The CH shift amount of the contact plug CH11 is added with -B to the CH shift amount (A+2B) of the contact plug CH05 adjacent in the Y direction with the member SHE therebetween, resulting in A+B, the same as the contact plug CH04.

[0086] For example, the memory pillar MP12 is connected to the bit line BL(k+1) in the same manner as the memory pillar MP03. That is, the contact plug VY12 is disposed under the bit line BL(k+1). The CH shift amount of the contact plug CH12 is added with -B to the CH shift amount (A+B) of the contact plug CH11 adjacent in the Y direction, resulting in A, the same as the contact plug CH03.

[0087] For example, similar to memory pillar MP02, memory pillar MP13 is connected to bit line BL(k + 3). That is, contact plug VY13 is disposed under bit line BL(k + 3). The CH shift amount of contact plug CH13 is obtained by adding -B to the CH shift amount (A) of contact plug CH12 adjacent in the Y direction, and is A - B, similar to contact plug CH02.

[0088] For example, similar to memory pillar MP01, memory pillar MP14 is connected to bit line BL(k). That is, contact plug VY14 is disposed under bit line BL(k). The CH shift amount of contact plug CH14 is obtained by adding -B to the CH shift amount (A - B) of contact plug CH13 adjacent in the Y direction, and is A - 2B, similar to contact plug CH01.

[0089] For example, memory pillar MP15 is connected to bit line BL(k + 2). That is, contact plug VY15 is disposed under bit line BL(k + 2). Contact plug VY15 is disposed at a position shifted -X direction from the center of memory pillar MP5. The CH shift amount of contact plug CH15 is obtained by adding -B to the CH shift amount (A - 2B) of contact plug CH14 adjacent in the Y direction, and is A - 3B.

[0090] Note that the CH shift amounts of contact plugs CH corresponding to a plurality of memory pillars MP arranged side by side in the X direction (not shown) are the same. Specifically, for example, the CH shift amounts of a plurality of contact plugs CH01 respectively corresponding to a plurality of memory pillars MP01 arranged side by side in the X direction are A - 2B.

[0091] Next, with reference to FIG. 9, an example of the CH shift amount in one block BLK will be described. In FIG. 9, the CH shift amounts within parentheses indicate the CH shift amounts when variables A and B are in the relationship of A = 1 / 2B, shown using variable A. Hereinafter, the contact plugs CH1 to CH5 in the string unit SU2 will be denoted as CH21 to CH25. The contact plugs CH1 to CH5 in the string unit SU3 will be denoted as CH31 to CH35. The contact plugs CH1 to CH5 in the string unit SU4 will be denoted as CH41 to CH45.

[0092] As shown in FIG. 9, in the string unit SU0, the CH shift amount of each of the contact plugs CH01 to CH05 is, as described with reference to FIG. 8, A - 2B, A - B, A, A + B, A + 2B. For example, when A = 1 / 2B, the CH shift amount of each of the contact plugs CH01 to CH05 can be expressed as -3A, -A, A, +3A, +5A. The CH shift amount is incremented by B in order from the contact plug CH01. That is, the change amount (difference) in the CH shift amount between two adjacent contact plugs CH in the Y direction is B (constant). When A = 1 / 2B, the CH shift amount is incremented by 2A in order from the contact plug CH01. That is, the change amount in the CH shift amount between two adjacent contact plugs CH in the Y direction is 2A.

[0093] In the string unit SU1, the CH shift amount of each of the contact plugs CH11 to CH15 is A + B, A, A - B, A - 2B, A - 3B as described with reference to FIG. 8. For example, when A = 1 / 2B, the CH shift amount of each of the contact plugs CH11 to CH15 can be expressed as 3A, A, -A, -3A, -5A. In this case, the CH shift amount is incremented by -B (decremented by B) in order from the contact plug CH11. Similar to the string unit SU0, the change amount of the CH shift amount between two adjacent contact plugs CH in the Y direction is B (constant). When A = 1 / 2B, the CH shift amount is incremented by -2A (decremented by 2A) in order from the contact plug CH11. That is, similar to the string unit SU0, the change amount of the CH shift amount between two adjacent contact plugs CH in the Y direction is 2A.

[0094] In the string unit SU2, the CH shift amount of each of the contact plugs CH21 to CH25 is the same as that of the contact plugs CH01 to CH05.

[0095] In the string unit SU3, the CH shift amount of each of the contact plugs CH31 to CH35 is the same as that of the contact plugs CH11 to CH15.

[0096] In the string unit SU4, the CH shift amount of each of the contact plugs CH41 to CH45 is the same as that of the contact plugs CH01 to CH05.

[0097] In the example shown in FIG. 9, the maximum value of the absolute value of the CH shift amount is |A + 2B| or |A - 3B|. That is, when A = 1 / 2B, the maximum value of the absolute value of the CH shift amount is |5A|. These values are the CH shift amount of any one of the contact plugs CH05, CH15, CH25, CH35, and CH45. The contact plugs CH05, CH15, CH25, CH35, and CH45 are arranged adjacent to different members SHE. That is, the absolute value of the CH shift amount of the contact plug CH arranged adjacent to the member SHE becomes the maximum value.

[0098] 4.3 Maximum values of the shift amount of contact plug CH and the deviation amount of VY Next, with reference to FIGS. 10 to 12, an example of the maximum deviation amounts of contact plug CH and VY will be described. FIG. 10 is a cross-sectional view showing an example of the upper part of memory pillar MP, contact plug CH, and contact plug VY. FIG. 11 is a plan view of the upper end of memory pillar MP. FIG. 12 is a plan view of the upper end of contact plug CH.

[0099] First, the shift amount of contact plug CH, that is, the maximum value of the CH shift amount, will be described.

[0100] As shown in FIGS. 10 and 11, let the diameter of the memory pillar MP in the X direction at the upper end be Dmp. Let the diameter of the semiconductor film 41 in the X direction at the upper end of the memory pillar MP be Ds. Let the width of the laminated film 42 in the X direction at the upper end of the memory pillar MP be Wi. The diameter Dmp, the diameter Ds, and the width Wi are in the relationship of Dmp = Ds + 2Wi.

[0101] Let the diameter of contact plug CH in the X direction at the lower end be Dc_bm. Let the distance from the central axis CAm of the memory pillar MP to the central axis CAc of contact plug CH, that is, the CH shift amount, be Sf1. For example, when (the contact length between the upper surface of the semiconductor film 41 of the memory pillar MP and the bottom surface of contact plug CH)>0 is satisfied, the CH shift amount Sf1 can be expressed as Sf1 < (Ds + Dc_bm) / 2.

[0102] Next, the maximum deviation amount of contact plug VY with respect to contact plug CH will be described.

[0103] As shown in FIGS. 10 and 12, let the diameter in the X direction at the upper end of the contact plug CH be Dc_tp. Let the diameter in the X direction at the lower end of the contact plug VY be Dv. Let the distance from the central axis CAc of the contact plug CH to the central axis CAv of the contact plug VY, that is, the displacement amount Sf2 of the contact plug VY with respect to the contact plug CH. For example, when (the contact length between the upper surface of the contact plug CH and the bottom surface of the contact plug VY)>0 is satisfied, the VY displacement amount Sf2 can be expressed as Sf2 < (Dc_tp + Dv) / 2.

[0104] 5. Effects according to this embodiment With the configuration according to this embodiment, the semiconductor memory device can arrange the contact plug CH at a position where the central axis of the contact plug CH is shifted in the X direction from the central axis of the memory pillar MP. Further, in one string unit SU, the semiconductor memory device can set the CH shift amounts of the five contact plugs CH corresponding to the five memory pillars MP arranged in a staggered pattern in five columns in the X direction to different values. Furthermore, the semiconductor memory device can make the change amount of the CH shift amounts of the contact plugs CH adjacent in the Y direction constant. Thereby, the semiconductor memory device can suppress a reduction in the contact area between the upper surface of the contact plug CH and the lower surface of the contact plug VY due to the displacement between the contact plug CH and the contact plug VY. That is, a connection failure (contact failure) between the contact plug CH and the contact plug VY can be suppressed. Therefore, the reliability of the semiconductor memory device can be improved.

[0105] 6. Modifications, etc. The semiconductor memory device according to the above embodiment includes a source line (32), a plurality of first insulating layers (33) and a plurality of first wiring layers (34) which are provided on the source line and stacked alternately layer by layer, a plurality of memory pillars (MP) that extend in the first direction (Z direction), pass through the plurality of first insulating layers and the plurality of first wiring layers, and one end of which reaches the source line, a plurality of bit lines (BL) that are provided above the plurality of memory pillars, arranged side by side in a second direction (X direction) intersecting the first direction, and each extend in a third direction (Y direction) intersecting the first direction and the second direction, a plurality of first contact plugs (CH) provided on each of the plurality of memory pillars, a plurality of second contact plugs (VY) provided on each of the plurality of first contact plugs and connected to any one of the plurality of bit lines, and a plurality of first members (SHE) that are arranged side by side in the second direction, each extend in the third direction, and separate a first wiring layer (SGD) provided at least at a position farthest from the source line among the plurality of first wiring layers in the second direction. The plurality of memory pillars include a first memory pillar (MP1), a second memory pillar (MP2), a third memory pillar (MP3), a fourth memory pillar (MP4), and a fifth memory pillar (MP5) that are arranged side by side in the third direction while alternately changing their positions in the second direction in a first region (SU) between two adjacent first members among the plurality of first members. The plurality of first contact plugs include a third contact plug (CH1) provided on the first memory pillar, a fourth contact plug (CH2) provided on the second memory pillar, a fifth contact plug (CH3) provided on the third memory pillar, a sixth contact plug (CH4) provided on the fourth memory pillar, and a seventh contact plug (CH5) provided on the fifth memory pillar.The first shift amount (A - 2B) obtained by shifting the third contact plug in the second direction with respect to the first memory pillar, the second shift amount (A - B) obtained by shifting the fourth contact plug in the second direction with respect to the second memory pillar, the third shift amount (A) obtained by shifting the fifth contact plug in the second direction with respect to the third memory pillar, the fourth shift amount (A + B) obtained by shifting the sixth contact plug in the second direction with respect to the fourth memory pillar, and the fifth shift amount (A + 2B) obtained by shifting the seventh contact plug in the second direction with respect to the fifth memory pillar are all different from each other.

[0106] With the configuration according to the above embodiment, reliability can be improved.

[0107] Note that the present invention is not limited to the above-described embodiments, and various modifications can be applied.

[0108] For example, the memory cell array 11, the row decoder 12, the sense amplifier 13, the sequencer 21, and the voltage generation circuit 22 may be formed on different semiconductor substrates. In this case, the semiconductor memory device 1 may be formed by bonding the respective substrates together.

[0109] Furthermore, the "connection" in the above embodiment includes a state in which, for example, a transistor or a resistor or the like is interposed therebetween and is indirectly connected.

[0110] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0111] 1... Semiconductor memory device, 10... Memory core section, 11... Memory cell array, 12... Row decoder, 13... Sense amplifier, 20... Peripheral circuit section, 21... Sequencer, 22... Voltage generation circuit, 30... Semiconductor substrate, 31, 33, 35, 36... Insulating layer, 32, 32a to 32c... Semiconductor layer, 34, 37... Wiring layer, 40... Core film, 41... Semiconductor film, 42... Stacked film, 43... Tunnel insulating film, 44... Charge storage film, 45... Block insulating film

Claims

1. A source line, a plurality of first insulating layers and a plurality of first wiring layers provided on the source line and alternately stacked one layer at a time, a plurality of memory pillars extending in a first direction, passing through the plurality of first insulating layers and the plurality of first wiring layers, and having one end reaching the source line, a plurality of bit lines provided above the plurality of memory pillars, arranged side by side in a second direction intersecting the first direction, and each extending in a third direction intersecting the first direction and the second direction, a plurality of first contact plugs provided on the plurality of memory pillars, a plurality of second contact plugs provided on the plurality of first contact plugs and connected to any one of the plurality of bit lines, a plurality of first members arranged side by side in the second direction, each extending in the third direction, and separating, in the second direction, at least the first wiring layer provided at the position farthest from the source line among the plurality of first wiring layers, comprising, the plurality of memory pillars include a first memory pillar, a second memory pillar, a third memory pillar, a fourth memory pillar, and a fifth memory pillar arranged side by side in the third direction while alternately changing positions in the second direction in a first region between two adjacent first members among the plurality of first members in the third direction, the plurality of first contact plugs include a third contact plug provided on the first memory pillar, a fourth contact plug provided on the second memory pillar, a fifth contact plug provided on the third memory pillar, a sixth contact plug provided on the fourth memory pillar, and a seventh contact plug provided on the fifth memory pillar, a first shift amount obtained by shifting the third contact plug in the second direction with respect to the first memory pillar, a second shift amount obtained by shifting the fourth contact plug in the second direction with respect to the second memory pillar, a third shift amount obtained by shifting the fifth contact plug in the second direction with respect to the third memory pillar, a fourth shift amount obtained by shifting the sixth contact plug in the second direction with respect to the fourth memory pillar, and a fifth shift amount obtained by shifting the seventh contact plug in the second direction with respect to the fifth memory pillar are all different from each other, a semiconductor memory device.

2. The difference between the first shift amount and the second shift amount, the difference between the second shift amount and the third shift amount, the difference between the third shift amount and the fourth shift amount, and the difference between the fourth shift amount and the fifth shift amount are the same. The semiconductor memory device according to claim 1.

3. The absolute value of the fifth shift amount is larger than the absolute value of the fourth shift amount. The semiconductor memory device according to claim 1.

4. The plurality of bit lines include a first bit line, a second bit line, a third bit line, a fourth bit line, and a fifth bit line arranged in order in the second direction. The first memory pillar is electrically connected to the first bit line. The second memory pillar is electrically connected to the fourth bit line. The third memory pillar is electrically connected to the second bit line. The fourth memory pillar is electrically connected to the fifth bit line. The fifth memory pillar is electrically connected to the third bit line. The semiconductor memory device according to claim 1.

5. The first memory pillar includes a semiconductor film extending in the first direction. The first shift amount is less than the value obtained by adding the length in the second direction of the first surface of the semiconductor film in contact with the third contact plug and the length in the second direction of the second surface of the third contact plug in contact with the semiconductor film and dividing the sum by 2. The semiconductor memory device according to claim 1.

6. The plurality of second contact plugs include an eighth contact plug provided on the third contact plug. The sixth shift amount obtained by shifting the eighth contact plug in the second direction with respect to the third contact plug is less than the value obtained by adding the length in the second direction of the third surface of the third contact plug in contact with the eighth contact plug and the length in the second direction of the fourth surface of the eighth contact plug in contact with the third contact plug and dividing the sum by 2. The semiconductor memory device according to claim 1.

7. The plurality of memory pillars are separated by the plurality of first members, and in a second region adjacent to the first region, a sixth memory pillar, a seventh memory pillar, an eighth memory pillar, a ninth memory pillar, and a tenth memory pillar arranged side by side in the third direction while alternately changing positions in the second direction are further included. The plurality of first contact plugs further include a ninth contact plug provided on the sixth memory pillar, a tenth contact plug provided on the seventh memory pillar, an eleventh contact plug provided on the eighth memory pillar, a twelfth contact plug provided on the ninth memory pillar, and a thirteenth contact plug provided on the tenth memory pillar. A seventh shift amount obtained by shifting the ninth contact plug in the second direction with respect to the sixth memory pillar, an eighth shift amount obtained by shifting the tenth contact plug in the second direction with respect to the seventh memory pillar, a ninth shift amount obtained by shifting the eleventh contact plug in the second direction with respect to the eighth memory pillar, a tenth shift amount obtained by shifting the twelfth contact plug in the second direction with respect to the ninth memory pillar, and an eleventh shift amount obtained by shifting the thirteenth contact plug in the second direction with respect to the tenth memory pillar are all different. The semiconductor memory device according to claim 1.

8. The difference between the first shift amount and the second shift amount, the difference between the second shift amount and the third shift amount, the difference between the third shift amount and the fourth shift amount, the difference between the fourth shift amount and the fifth shift amount, the difference between the fifth shift amount and the seventh shift amount, the difference between the seventh shift amount and the eighth shift amount, the difference between the eighth shift amount and the ninth shift amount, the difference between the ninth shift amount and the tenth shift amount, and the difference between the tenth shift amount and the eleventh shift amount are the same. The semiconductor memory device according to claim 7.

9. The plurality of bit lines include a first bit line, a second bit line, a third bit line, a fourth bit line, and a fifth bit line arranged side by side in the second direction. The first memory pillar and the ninth memory pillar are electrically connected to the first bit line. The second memory pillar and the eighth memory pillar are electrically connected to the fourth bit line. The third memory pillar and the seventh memory pillar are electrically connected to the second bit line. The fourth memory pillar and the sixth memory pillar are electrically connected to the fifth bit line. The fifth memory pillar and the tenth memory pillar are electrically connected to the third bit line. The semiconductor memory device according to claim 7.

10. The plurality of memory pillars are separated by the plurality of first members, and in a third region adjacent to the second region, an 11th memory pillar, a 12th memory pillar, a 13th memory pillar, a 14th memory pillar, and a 15th memory pillar are arranged side by side in the third direction while alternately changing their positions in the second direction. The plurality of first contact plugs further include a 14th contact plug provided on the 11th memory pillar, a 15th contact plug provided on the 12th memory pillar, a 16th contact plug provided on the 13th memory pillar, a 17th contact plug provided on the 14th memory pillar, and an 18th contact plug provided on the 15th memory pillar. A 12th shift amount obtained by shifting the 14th contact plug in the second direction with respect to the 11th memory pillar is the same as the 1st shift amount. A 13th shift amount obtained by shifting the 15th contact plug in the second direction with respect to the 12th memory pillar is the same as the 2nd shift amount. A 14th shift amount obtained by shifting the 16th contact plug in the second direction with respect to the 13th memory pillar is the same as the 3rd shift amount. A 15th shift amount obtained by shifting the 17th contact plug in the second direction with respect to the 14th memory pillar is the same as the 4th shift amount. A 16th shift amount obtained by shifting the 18th contact plug in the second direction with respect to the 15th memory pillar is the same as the 5th shift amount. The semiconductor memory device according to claim 7.

11. Each of the plurality of memory pillars includes a semiconductor film extending in the first direction, and a laminated film including a charge storage film having a side surface in contact with the semiconductor film. The semiconductor memory device according to claim 1.

12. A plurality of first wiring layers laminated at intervals in the first direction and each extending in a second direction intersecting the first direction; a first memory pillar extending in the first direction and passing through the plurality of first wiring layers; a second memory pillar MP arranged adjacent to the first memory pillar; a plurality of bit lines provided above the first memory pillar and the second memory pillar MP, arranged side by side in the second direction, and each extending in a third direction intersecting the first direction and the second direction; a first contact plug provided on the first memory pillar; A second contact plug provided on the second memory pillar; A third contact plug provided on the first contact plug and connected to any one of the plurality of bit lines; A fourth contact plug provided on the second contact plug and connected to any one of the plurality of bit lines comprising: A first shift amount obtained by shifting the first contact plug in the second direction with respect to the first memory pillar, and a second shift amount obtained by shifting the second contact plug in the second direction with respect to the second memory pillar are different; A semiconductor memory device.

13. A third memory pillar adjacent to the second memory pillar and provided at a position different from the first memory pillar MP in the third direction; A fifth contact plug provided on the third memory pillar; A sixth contact plug provided on the fifth contact plug and connected to any one of the plurality of bit lines further comprising: A third shift amount obtained by shifting the fifth contact plug in the second direction with respect to the third memory pillar is different from the first shift amount and the second shift amount; The semiconductor memory device according to claim 12.

14. A difference between the first shift amount and the second shift amount is the same as a difference between the second shift amount and the third shift amount; The semiconductor memory device according to claim 13.

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