Self-aligned trench bottom protection region for trench gate metal oxide semiconductor field effect transistors

Abstract

To provide a method for forming a self-aligned trench bottom protection region at a bottom surface of a trench gate of a trench gate MOSFET.SOLUTION: A method of manufacturing a trench gate MOSFET 300d, is for forming a semiconductor source region 304 having a first conductivity type in a semiconductor body region 312 having a second conductivity type. The semiconductor body region separates the semiconductor source region from a semiconductor epitaxial layer 310. Trench gate openings 322a and 322b are etched in an exposed surface (an upper surface 342) of the semiconductor source region. A bottom surface 340a of a trench gate opening part is within the semiconductor epitaxial layer 310. A shielding dopant having a second conductivity type is implanted by a channeling implantation process. The exposed surface of the semiconductor source region is exposed to the shielding dopant during the channeling implantation process, and the shielding dopant forms trench bottom protection regions 350a and 350b at the bottom surface 340a of the trench gate opening part.SELECTED DRAWING: Figure 3D

Description

[Technical Field]

[0001] Embodiments of the present disclosure relate generally to trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and more particularly to forming a trench bottom protection region at the bottom of the trench gate of a trench-gate MOSFET. [Background technology]

[0002] A trench-gate MOSFET includes a trench gate positioned vertically within a semiconductor material to switch current through the MOSFET on and off. Certain advantages can be realized by utilizing trench-gate MOSFETs. In particular, the trench-gate configuration allows for a higher density of MOSFET devices to be fabricated on a semiconductor substrate. In addition, adjacent cells can be easily connected to operate in parallel. Trench-gate MOSFETs have been shown to exhibit additional advantages, such as low specific on-resistance, high power density, fast switching speeds, and low switching losses. Such advantages make trench-gate MOSFETs a promising solution for semiconductor devices.

[0003] Applicant has recognized many technical challenges and difficulties associated with the fabrication and operation of trench-gate MOSFETs. Through applied effort, ingenuity, and innovation, Applicant has solved the problems associated with the fabrication and operation of trench-gate MOSFETs as embodied in the present disclosure, as described in detail below. Summary of the Invention

[0004] Various embodiments are directed to an exemplary method for forming a self-aligned trench bottom protection region at a bottom surface of a trench gate in a trench-gated MOSFET. In some embodiments, the method may include forming a semiconductor body region on an upper surface of a semiconductor epitaxial layer and in the semiconductor epitaxial layer, where the semiconductor epitaxial layer comprises a first conductivity type and the semiconductor body region comprises a second conductivity type. The method further includes forming a semiconductor source region in the semiconductor body region, where the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer, where the semiconductor source region comprises the first conductivity type. The method further includes etching a trench gate opening in the exposed surface of the semiconductor source region, where the trench gate opening includes a bottom surface, where the bottom surface comprises the semiconductor epitaxial layer. The method further includes implanting a shielding dopant having the second conductivity type by a channeling implant process, wherein the exposed surface of the semiconductor source region is exposed to the shielding dopant during the channeling implant process, and the shielding dopant forms a trench bottom protection region at a bottom surface of the trench gate opening.

[0005] In some embodiments, the channeling implant process accelerates the screening dopants towards the MOSFET device at low ion energy.

[0006] In some embodiments, the low ion energy is between 30 kiloelectron volts and 3000 kiloelectron volts.

[0007] In some embodiments, the channeling implant process accelerates the shielding dopant towards the MOSFET device at an implant angle, where the implant angle is measured relative to a direction normal to the surface of the MOSFET device.

[0008] In some embodiments, the implant angle is between 3.5 degrees and 4.5 degrees.

[0009] In some embodiments, the method further includes forming a body contact region having the second conductivity type in the semiconductor source region, the body contact region electrically coupled to the semiconductor body region.

[0010] In some embodiments, the body contact region is doped with a body contact doping concentration.

[0011] In some embodiments, the semiconductor body region is doped at a semiconductor body concentration.

[0012] In some embodiments, the body contact doping concentration is higher than the semiconductor body concentration.

[0013] In some embodiments, the first conductivity type is an n-type semiconductor.

[0014] In some embodiments, the second conductivity type is a p-type semiconductor.

[0015] In some embodiments, the semiconductor epitaxial layer is doped with a first doping concentration.

[0016] In some embodiments, the semiconductor source region is doped with a second doping concentration.

[0017] In some embodiments, the first doping concentration is less than the second doping concentration.

[0018] In some embodiments, the semiconductor source region is formed using an ion implantation process.

[0019] In some embodiments, the source region lattice structure of the semiconductor source region is intentionally damaged during the ion implantation process.

[0020] In some embodiments, the body contact region is formed using an ion implantation process.

[0021] In some embodiments, the body contact region lattice structure of the body contact region is intentionally damaged during the ion implantation process.

[0022] An exemplary trench-gate MOSFET device is also provided. The exemplary trench-gate MOSFET device includes a semiconductor body region having a first conductivity type, a semiconductor source region formed on an upper surface of the semiconductor body region and having a second conductivity type, and a semiconductor epitaxial layer having the second conductivity type, the semiconductor body region being separated from the semiconductor source region by the semiconductor body region. The exemplary trench-gate MOSFET device further includes a trench gate opening etched into the exposed surface of the semiconductor source region, the trench gate opening including a bottom surface, the bottom surface including the semiconductor epitaxial layer. The exemplary trench-gate MOSFET device further includes a trench bottom protection region formed in the semiconductor epitaxial layer at a bottom surface of the trench gate opening, the trench gate opening being formed by implanting a shielding dopant having the second conductivity type by a channeling implant process, the exposed surface of the semiconductor source region being exposed to the shielding dopant during the channeling implant process, and the shielding dopant forming the trench bottom protection region at the bottom surface of the trench gate opening.

[0023] An exemplary product-by-process for a trench-gate MOSFET device is also provided. The exemplary MOSFET device is fabricated by a method including forming a semiconductor body region on an upper surface of a semiconductor epitaxial layer and within the semiconductor epitaxial layer, where the semiconductor epitaxial layer includes a first conductivity type and the semiconductor body region includes a second conductivity type. The method further includes forming a semiconductor source region within the semiconductor body region, where the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer, where the semiconductor source region includes the first conductivity type. The method further includes etching a trench gate opening in the exposed surface of the semiconductor source region, where the trench gate opening includes a bottom surface, the bottom surface including the semiconductor epitaxial layer. The method further includes implanting a shielding dopant having the second conductivity type by a channeling implant process, where the exposed surface of the semiconductor source region is exposed to the shielding dopant during the implant process, and the shielding dopant forms a trench bottom protection region at the bottom surface of the trench gate opening. [Brief explanation of the drawings]

[0024] Reference will now be made to the accompanying drawings, in which components shown in the figures may or may not be present in a particular embodiment described herein. Some embodiments may include fewer (or more) components than shown in the figures, in accordance with exemplary embodiments of the present disclosure. [Figure 1] 1A and 1B are cross-sectional views of an exemplary trench-gate MOSFET device including a trench bottom protection region according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 1 illustrates an exemplary, less desirable method requiring a hard mask for implanting a trench bottom protection region at the bottom of the trench gate in an exemplary trench-gate MOSFET. [Figure 3A] 1A-1C are cross-sectional views of an exemplary process for fabricating a trench-gate MOSFET according to an exemplary embodiment of the present disclosure. [Figure 3B]1A-1C are cross-sectional views of an exemplary process for fabricating a trench-gate MOSFET according to an exemplary embodiment of the present disclosure. [Figure 3C] 1A-1C are cross-sectional views of an exemplary process for fabricating a trench-gate MOSFET according to an exemplary embodiment of the present disclosure. [Figure 3D] 1A-1C are cross-sectional views of an exemplary process for fabricating a trench-gate MOSFET according to an exemplary embodiment of the present disclosure. [Figure 4] 1A-1C illustrate an exemplary channeling implantation process in an exemplary silicon carbide lattice structure according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 1 is an exemplary flow diagram illustrating a process for forming a self-aligned trench bottom protection region at the bottom surface of a trench gate of a trench-gate MOSFET in accordance with an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] Exemplary embodiments are described more fully below with reference to the accompanying drawings, in which some, but not all, embodiments of the invention(s) of this disclosure are shown. However, embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout.

[0026] As used herein, terms such as "front," "rear," "behind," "top," "vertical," "horizontal," "upper," "lower," "above," "under," and the like are used for illustrative purposes in the examples provided below to describe the relative position of particular components or portions of components with respect to the local reference frame of an electrical diode using any global reference frame.

[0027] In some examples, a Cartesian (three-axis) reference system is provided. Unless otherwise specified, the positive y direction generally corresponds to "up," "above," or "on top." Conversely, the negative y direction corresponds to "down," "below," "under," or "beneath."

[0028] Various exemplary embodiments address technical issues associated with forming a trench bottom protection region on the bottom surface of a trench gate opening on a trench-gate MOSFET device. As will be appreciated by those skilled in the art to which this disclosure pertains, there are numerous exemplary scenarios in which a user may need to form a trench gate protection region to protect components of a trench-gate MOSFET from destructive electric fields.

[0029] Referring now to FIG. 1 , an exemplary trench-gated MOSFET 100 is provided. As shown in FIG. 1 , a doped semiconductor body region 112 having a first doping type (e.g., p-type) and a heavily doped semiconductor source region 104 having a second doping type (e.g., n-type) are formed on a semiconductor epitaxial layer 110. A trench gate opening is etched into the surface of the semiconductor source region 104 such that the bottom of the trench gate opening reaches the semiconductor epitaxial layer 110. The trench gate opening is coated with a dielectric layer (e.g., oxide layer 116) and filled with a conductive material, such as polysilicon, to form a trench gate 102. As further shown in FIG. 1 , the semiconductor source region 104 is electrically coupled to a source conductive contact 106, and a semiconductor substrate region 114 on the surface of the semiconductor epitaxial layer 110 opposite the semiconductor body region 112 is electrically coupled to a conductive drain layer 108.

[0030] During operation, varying the voltage on the trench gate 102 changes the electron density at the surface of the trench gate 102. The change in electron density either allows or prevents current flow through the semiconductor body region 112, thus allowing current to flow vertically through the trench-gate MOSFET 100 between the conductive source contact 106 and the conductive drain layer 108.

[0031] Trench-gate MOSFETs are widely used in electrical devices, especially in high-power applications. A key advantage of trench-gate MOSFETs, such as the exemplary trench-gate MOSFET 100 shown in FIG. 1 , is their reduced on-resistance compared to planar-gate MOSFETs. The reduced on-resistance allows trench-gate MOSFETs to operate more efficiently by reducing the voltage drop across the trench-gate MOSFET. The vertical configuration of trench-gate MOSFETs allows a higher density of MOSFET devices to be fabricated on an electrical device. Additionally, adjacent cells may be connected to operate in parallel. Trench-gate MOSFETs have further been shown to exhibit high power density, fast switching speeds, and low switching losses, making trench-gate MOSFETs a popular solution in semiconductor devices.

[0032] In some embodiments, the semiconductor substrate region 114 and the semiconductor epitaxial layer 110 may comprise silicon carbide (SiC). SiC substrates can offer many benefits, especially in high-power applications. For example, SiC-based semiconductor components can dissipate heat more efficiently, be more tolerant of higher frequencies, have lower reverse leakage current and power loss, be more stable over a wide temperature range, have lower electromagnetic emissions, and offer other related advantages.

[0033] In some examples, the trench-gate MOSFET 100 may experience high electric fields in the dielectric layer of the trench gate 102. Such high electric fields may be particularly strong between the bottom surface of the trench gate 102 and the semiconductor epitaxial layer 110, especially at the corners of the trench gate 102 and at the interface between the semiconductor body region 112 and the trench gate 102. As shown in FIG. 1 , an oxide layer 116 is deposited between the trench gate 102 and the surrounding semiconductor layers. The high electric field in the oxide layer 116 may cause dielectric breakdown in the oxide layer 116. Breakdown of the oxide layer 116 may adversely affect the performance of the trench-gate MOSFET 100.

[0034] Due to the increased electric field in the oxide layer 116 at the bottom of the trench gate 102, many trench-gate MOSFET devices 100 require a shielding region disposed at the bottom of the trench gate 102. The shielding region protects the oxide layer 116 from excessive and harmful electric fields. In addition, the shielding region acts to shield the semiconductor body region 112 from the high potential difference that may exist between the conductive drain layer 108 and the conductive source contact 106. The shielding region therefore prevents excessive depletion in the body layer and can enhance the blocking capability of the body layer during operation.

[0035] Referring now to FIG. 2, in a less desirable process, shielding regions 220a, 220b can be formed at the bottom of trench gate openings 222a, 222b by protecting the top surface of semiconductor device 200 with a hard mask 224 and utilizing a high energy implantation process 226 for ion implantation.

[0036] 2, a hard mask 224 is deposited on the top layer of the semiconductor device 200, including the semiconductor source region 204. To form the trench gate of the trench-gate MOSFET, trench gate openings 222a, 222b are etched through the hard mask 224, the semiconductor source region 204, the semiconductor body region 212, and into the semiconductor epitaxial layer 210. The hard mask 224 provides a protective coating to components of the semiconductor device 200 (e.g., the semiconductor source region 204) during a damaging high-energy implantation process 226.

[0037] The less desirable approach of utilizing a high-energy implantation process 226 to form shielding regions 220a, 220b at the bottom of trench gate openings 222a, 222b may have several drawbacks. During the high-energy implantation process 226, dopants of a particular species (e.g., arsenic, phosphorus, boron, etc.) are accelerated in a high-energy beam. In some embodiments, the energy used to accelerate the dopants may be between 1000 kiloelectron volts and 3000 kiloelectron volts. The high-energy ion beam is directed toward the surface of semiconductor device 200. In portions of semiconductor device 200 not protected by a protective coating (e.g., hard mask 224), such as the bottom of trench gate openings 222a, 222b, the accelerated ions in the high-energy beam penetrate into the semiconductor surface.

[0038] In addition to the high energy (1000-3000 keV) associated with the high-energy implantation process 226, the high-energy implantation process may also be performed at high temperatures (e.g., 300-500 degrees Celsius). The high energy and temperature of the accelerated ions may damage any exposed surfaces of the semiconductor device 200. Additionally, the high-energy implantation process 226 may penetrate into the sidewalls of the trench gate openings 222 a, 222 b. Such lateral straggling of dopants may adversely affect the performance of the semiconductor device 200. Lateral straggling is particularly problematic when reducing the size of the semiconductor device 200. Therefore, a hard mask 224 is deposited on the surface of the semiconductor device 200 to protect the electrical properties of components of the semiconductor device 200 from the ions accelerated in the high-energy implantation process 226.

[0039] The deposition and removal of the hard mask 224 may also cause damage to the surface of the semiconductor device 200 that is in contact with the hard mask 224. For example, the hard mask 224 may cause strain on the surface of the semiconductor source region 204 and other regions of the semiconductor device 200. The strain in the semiconductor source region 204 may cause the hard mask 224 to have many adverse effects on the performance of the semiconductor device 200. For example, the strain in the semiconductor source region 204 may result in non-uniform distribution of implanted ions, especially when channeling implantation is used. Furthermore, the deposition and removal of the hard mask may cause irreparable damage to the lattice structure of the contact regions of the semiconductor device 200, further adversely affecting the performance of the semiconductor device 200. The deposition and removal of the hard mask 224 may also change the electrical properties of the surface of the semiconductor device 200. Changes in the electrical properties of components of the semiconductor device may further adversely affect the performance of the semiconductor device 200.

[0040] Additionally, the use of hard mask 224 can limit the minimum feature size of the trench gate. For example, hard mask 224 may be etched to form an opening in the hard mask, within which a trench gate opening may be formed. The minimum size of the opening in the hard mask may be limited based on the accuracy of the hard mask etch. Thus, the minimum size of the trench gate opening may be limited. Such characteristics can be problematic as manufacturers attempt to further reduce the size of trench-gate MOSFETs, and therefore the size of the trench gates that comprise trench-gate MOSFETs.

[0041] Various exemplary embodiments described herein utilize various techniques to form a trench bottom protection region at the bottom of a trench gate opening of a trench-gate MOSFET. For example, in some embodiments, the exposed surface of the trench-gate MOSFET may be intentionally damaged, resulting in disruption of the lattice structure of the semiconductor structure (e.g., silicon carbide). The disrupted lattice structure can minimize penetration of implanted ions during an ion implantation process, especially when compared to an undamaged semiconductor surface containing an undamaged lattice structure.

[0042] Several techniques can be utilized to intentionally damage exposed surfaces of semiconductor devices. For example, regions of semiconductor devices can be heavily doped with ions. The ion implantation process, particularly associated with heavy doping, can cause significant damage to the lattice structure of the doped regions. Therefore, semiconductor regions, such as semiconductor source and body contact regions, may be heavily doped to protect such surfaces from significant penetration during the implantation process associated with forming trench bottom protection regions. After the ion implantation process, an annealing process is performed to at least partially restore electrical contact between the various regions, but the doped regions remain intentionally damaged.

[0043] Additionally, a low-energy channeling implant process may be used to form the trench bottom protection region. The channeling implant process leverages the architecture of the target semiconductor to maximize implant penetration at low energy. Such a channeling implant may accelerate ions toward the target surface (e.g., the bottom surface of the trench gate opening) at a specific rotation and angle measured from the normal to the target surface. The rotation and angle are selected to maximize the penetration of the accelerated ions into the target surface. For example, by aligning the ion acceleration with the lattice structure of the semiconductor, the accelerated ions may experience fewer collisions and penetrate deeper into the lattice structure at lower energy. Furthermore, the rotation and angle of the channeling implant process may be selected to reduce collisions with nuclei in the crystalline structure. Reducing collisions with nuclei in the crystalline structure reduces lateral straggling or ion penetration into the sidewalls of the trench gate opening.

[0044] At the same time, the penetration of low energy implanted ions into damaged lattice structures, such as intentionally damaged regions, is limited, resulting in deep penetration into the bottom of the trench gate opening and minimal penetration into intentionally damaged surfaces, such as the semiconductor source region.

[0045] Additionally, the low energy channeling implant process may be performed at lower temperatures, for example, at or near room temperature. Reducing the temperature during the implant process allows for the use of simpler and less expensive equipment during the semiconductor manufacturing process.

[0046] As a result of the exemplary embodiments described herein, and in some instances, manufacturing processes associated with creating a trench bottom protection region at the bottom of a trench gate opening on a trench-gated MOSFET are significantly improved. For example, by utilizing intentionally damaged regions, a trench bottom protection region may be formed at the bottom of the trench gate opening without the need for a hard mask. Eliminating the need for a hard mask simplifies the difficult steps associated with aligning, depositing, and removing a hard mask layer. Additionally, the performance of trench-gated MOSFETs fabricated using the processes described herein can be significantly improved. Damage to the surface of electrical components due to hard mask deposition and removal can be avoided. Avoiding such damage can significantly improve the reliability and performance of trench-gated MOSFETs.

[0047] 3A-3D, an exemplary process for forming a trench bottom protection region at the bottom of a trench-gate MOSFET is provided.

[0048] Referring now to FIG. 3A, an exemplary semiconductor device 300a is shown during the formation of a trench bottom protection region on the bottom surface of a trench gate opening in a trench-gate MOSFET device. As shown in FIG. 3A, the exemplary semiconductor device 300a includes a semiconductor substrate layer 314 having a top surface 314a and a bottom surface 314b. A semiconductor epitaxial layer 310 is formed on the top surface 314a, and a conductive drain layer 308 is formed on the bottom surface 314b opposite the semiconductor epitaxial layer 310. As further shown in FIG. 3A, a semiconductor body region 312 is formed on the top surface 310a of the semiconductor epitaxial layer 310. A semiconductor source region 304 is further formed on the top surface 312a of the semiconductor body region 312. A body contact region 330 is formed in the semiconductor source region 304 and makes electrical contact with the semiconductor body region 312 through the semiconductor source region 304.

[0049] As shown in FIG. 3A , the exemplary semiconductor device 300a includes a semiconductor substrate layer 314. The semiconductor substrate layer 314 may be any semiconductor material that functions as a base layer for a semiconductor component (e.g., a trench-gate MOSFET). The semiconductor substrate layer 314 may include silicon, germanium, gallium arsenide, gallium nitride, silicon carbide (SiC), or other similar semiconductor materials. The semiconductor substrate layer 314 may serve as a base layer for epitaxial growth of additional semiconductor materials. Epitaxial growth may be used to grow additional crystalline layers, such as the semiconductor epitaxial layer 310, on the semiconductor substrate layer 314.

[0050] In some embodiments, the semiconductor substrate layer 314 may include SiC. SiC can offer many advantages in high-power applications. For example, SiC-based semiconductor components can dissipate heat more efficiently, be more resistant at higher frequencies, have lower reverse leakage current and power loss, be more stable over a wide temperature range, have lower electromagnetic emissions, and offer other related advantages.

[0051] In some embodiments, the semiconductor substrate layer 314 may be doped with a first dopant type to create a semiconductor having a particular conductivity type. A dopant may be any impurity intentionally added to a semiconductor to modify the semiconductor's conductivity. Adding a dopant with extra valence electrons to the semiconductor substrate layer 314 creates a semiconductor with n-type doping, or an n-doped semiconductor. Dopants with extra valence electrons may include phosphorus, arsenic, antimony, etc. Adding a dopant to a semiconductor substrate layer 314 that is valence electron deficient creates a semiconductor with p-type doping, or a p-doped semiconductor. Valence electron deficient dopants may include boron, aluminum, gallium, etc. As shown in FIG. 3A , the semiconductor substrate layer 314 of the exemplary semiconductor device 300a is an n-type semiconductor substrate layer 314.

[0052] In some embodiments, the semiconductor substrate layer 314 may include a doping concentration. The doping concentration may refer to the number of impurities introduced into the semiconductor substrate layer 314 structure relative to the number of intrinsic semiconductor atoms. A high doping concentration means that more impurities are introduced into the semiconductor substrate layer 314 relative to the number of intrinsic semiconductor atoms. In some embodiments, the doping concentration of the semiconductor substrate layer 314 may be higher than the doping concentration of the semiconductor epitaxial layer 310.

[0053] As further shown in FIG. 3A , the exemplary semiconductor device 300a includes a semiconductor epitaxial layer 310 on a top surface 314a of a semiconductor substrate layer 314. The semiconductor epitaxial layer 310 may be any semiconductor material configured to allow current flow from the semiconductor source region 304 to the conductive drain layer 308 as a result of majority carrier drift. The semiconductor epitaxial layer 310 allows current flow from the semiconductor source region 304 to the conductive drain layer 308 when a gate voltage at the trench gate of the trench-gated MOSFET is exceeded. Additionally, the semiconductor epitaxial layer 310 blocks or limits current flow in the reverse direction, e.g., from the conductive drain layer 308 to the semiconductor source region 304. As shown in FIG. 3A , the semiconductor epitaxial layer 310 is of the same dopant type as the semiconductor substrate layer 314, e.g., an n-type semiconductor. As further shown in FIG. 3A , the semiconductor epitaxial layer 310 may have a different doping concentration than the semiconductor substrate layer 314. For example, the semiconductor epitaxial layer 310 may have a lower doping concentration than the semiconductor substrate layer 314 .

[0054] As further shown in FIG. 3A , the exemplary semiconductor device 300a includes a semiconductor body region 312. The semiconductor body region 312 may be any region positioned between the semiconductor source region 304 and the conductive drain layer 308 such that current flow between the semiconductor source region 304 and the conductive drain layer 308 is blocked when the voltage at the trench gate does not exceed a threshold voltage. The semiconductor body region 312 may be doped with an opposite dopant type to the semiconductor source region 304 and the semiconductor epitaxial layer 310. As shown in FIG. 3A , the semiconductor body region 312 is a p-type semiconductor. As further shown in FIG. 3A , the semiconductor body region 312 may have a different doping concentration (e.g., a semiconductor body concentration) than the semiconductor body contact region 330. For example, the semiconductor body region 312 may have a lower doping concentration than the semiconductor body contact region 330. In some embodiments, the semiconductor body doping concentration is greater than 1×10 17 ions / cm 3 ~1×10 22 ions / cm 3 , more preferably 1.5 x 10 17 ions / cm3~1.5×10 21 ions / cm3, most preferably 1 x 10 18 ions / cm 3 ~1×10 21 ions / cm 3 may be.

[0055] 3A, the exemplary semiconductor device 300a includes a body contact region 330. The body contact region 330 may be any region of the same doping type as the semiconductor body region 312 and may be positioned to allow electrical contact with the semiconductor body region 312 from an exterior surface of the semiconductor device 300a. As shown in FIG. 3A, the semiconductor body contact region 330 may have a different doping concentration (e.g., a body contact doping concentration) than the semiconductor body region 312. For example, the semiconductor body region 312 may have a lower doping concentration than the semiconductor body contact region 330. In some embodiments, the body contact doping concentration is greater than 1×10 17 ions / cm 3 ~1×10 22 ions / cm 3 More preferably, it may be 1.5×10 17 ions / cm3~1.5×10 21 ions / cm3, and most preferably 1×10 18 ions / cm 3 ~1×10 21 ions / cm 3 The semiconductor body contact region 330 may allow a voltage to be applied to the semiconductor body region 312 to change the electrical properties of the semiconductor device 300a, for example, to change the barrier voltage of a transistor device.

[0056] In some embodiments, the semiconductor body contact region 330 may include a heavily doped semiconductor material of the same conductivity type (e.g., P+) as the semiconductor body region 312 and may be formed using an ion implantation process. The ion implantation process may be any ion implantation process in which the surface of the semiconductor body contact region 330 is intentionally damaged. For example, ions may be accelerated toward the surface of the semiconductor body contact region 330 to change the electrical properties of the semiconductor body contact region 330. The accelerated ions damage the lattice structure of the semiconductor base and become lodged within the semiconductor material. The damaged lattice structure increases the difficulty of subsequent implantation processes (e.g., forming trench bottom protection regions) penetrating the semiconductor body contact region 330. In particular, ion implantation processes that rely on channeling through the lattice structure of the semiconductor material cannot penetrate deeper into the semiconductor material compared to channeling implants in semiconductor materials with intact lattice structures. In some embodiments, ions utilized to create n-type doping in the semiconductor material include phosphorus, arsenic, and antimony, among others. In some embodiments, ions utilized to create p-type doping in semiconductor materials include boron, indium, aluminum, gallium, and thallium, among others.

[0057] 3A , the semiconductor device 300a includes a semiconductor source region 304. The semiconductor source region 304 may be any conductive material through which current enters the semiconductor device 300a, or equivalently, through which electrons exit the semiconductor device 300a. In some embodiments, the semiconductor source region 304 may be disposed on top of the semiconductor body region 312 and may provide a conductive path from an external contact through the semiconductor body region 312 to the semiconductor epitaxial layer 310. In a transistor semiconductor device, the semiconductor source region 304 may form a PN junction with the semiconductor body region 312.

[0058] As described herein, the semiconductor source region 304 may comprise a heavily doped semiconductor material of the same conductivity type (e.g., N+) as the semiconductor epitaxial layer 310 and may be formed using an ion implantation process. The ion implantation process may be any ion implantation process in which the surface of the semiconductor source region 304 is intentionally damaged. For example, ions may be accelerated toward the surface of the semiconductor source region 304 to change the electrical properties of the semiconductor source region 304. The accelerated ions damage the lattice structure of the semiconductor base and become lodged within the semiconductor material. The damaged lattice structure increases the difficulty of subsequent implantation processes (e.g., forming a trench bottom protection region) penetrating the semiconductor source region 304. In particular, ion implantation processes that rely on channeling through the lattice structure of the semiconductor material cannot penetrate as deeply into the semiconductor material as channeling implants in semiconductor materials with intact lattice structures. In some embodiments, ions utilized to create n-type doping in the semiconductor material include phosphorus, arsenic, and antimony, among others. In some embodiments, ions utilized to create p-type doping in semiconductor materials include boron, indium, aluminum, gallium, and thallium, among others.

[0059] As further shown in FIG. 3A , the semiconductor device 300a includes a conductive drain layer 308. The conductive drain layer 308 may be any conductive material (e.g., a backside metal) through which current exits the semiconductor device 300a, or equivalently, through which electrons enter the semiconductor device 300a. In some embodiments, the conductive drain layer 308 may include a metal or combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the conductive drain layer 308 may be disposed below the semiconductor substrate layer 314 and adjacent to the bottom surface of the semiconductor substrate layer 314. In some embodiments, such as trench-gate MOSFETs, as shown in FIG. 3A , the conductive drain layer 308 may be shared by one or more adjacent trench-gate MOSFET devices. Sharing the conductive drain layer 308 may allow for a higher concentration of trench-gate MOSFET devices in a given area.

[0060] Referring now to FIG. 3B, an exemplary semiconductor device 300b is provided that includes trench gate openings 322a, 322b having bottom surfaces 340a, 340b that include a semiconductor epitaxial layer 310.

[0061] 3B , the exemplary semiconductor device 300b includes trench gate openings 322a, 322b. The trench gate openings 322a, 322b are any channel, basin, cavity, hole, depression, groove, or other trench formed in the top surface 342 of the semiconductor device 300b and configured to receive a conductive material, such as polysilicon, to form a gate structure of a vertically oriented MOSFET. In some embodiments, the trench gate openings 322a, 322b may be etched into the top surface 342 of the semiconductor device 300b, including the semiconductor source region 304.

[0062] The trench gate openings 322 a, 322 b may be etched into the surface of the semiconductor device 300 b using standard etching techniques, such as dry etching. The dry etching technique may include depositing a protective layer, such as photoresist, on the top surface 342 of the semiconductor device 300 b and patterning the protective layer to expose the portions of the semiconductor device 300 b to be etched. The dry etching technique may include chemical dry etching, such as plasma dry etching. Etching the portions of the top surface 342 of the semiconductor device 300 b that are not protected by the protective layer creates cavities in the semiconductor device 300 b that include the trench gate openings 322 a, 322 b.

[0063] 3B , trench gate openings 322 a, 322 b defined in semiconductor device 300 b are etched through semiconductor source region 304 and semiconductor body region 312 such that bottom surfaces 340 a, 340 b of trench gate openings 322 a, 322 b, respectively, include semiconductor epitaxial layer 310. The bottom surfaces 340 a, 340 b, including semiconductor epitaxial layer 310, formed during the etching process, are configured to maintain the lattice structure of the underlying semiconductor material. For example, in embodiments in which the semiconductor epitaxial layer includes silicon carbide semiconductor material, the lattice structure of the silicon carbide remains intact at the bottom surfaces 340 a, 340 b of trench gate openings 322 a, 322 b upon completion of the etching process. Trench gate openings 322a, 322b formed in the semiconductor epitaxial layer 310 through the semiconductor source region 304 and the semiconductor body region 312 form openings for vertical structures to facilitate the transfer of current from the semiconductor source region 304 to the conductive drain layer 308.

[0064] Referring now to FIG. 3C , an exemplary semiconductor device 300c is provided. As shown in FIG. 3C , trench bottom protection regions 350a, 350b are formed on bottom surfaces 340a, 340b of trench gate openings 322a, 322b of the semiconductor device 300c. As further shown in FIG. 3C , the trench bottom protection region 350a is formed by a low-energy channeling implant process 352. The channeling implant process 352 is performed without the protection of a hard mask (e.g., hard mask 224 shown in FIG. 2 ), which may cause undesirable damage to the surfaces of the semiconductor source region 304 and the body contact region 330 during deposition and removal. Damage to the semiconductor source region 304 and the body contact region 330 due to hard mask deposition and removal may cause distortion on the top surface 342 of the semiconductor device 300c and other physical defects that adversely affect the performance of the semiconductor device 300c.

[0065] As described in connection with Figure 3A, the semiconductor source region 304 and the body contact region 330 are formed using an intentionally damaging ion implantation process that damages the lattice structure at the top surfaces 342 of the semiconductor source region 304 and the body contact region 330. Furthermore, as described in connection with Figure 3B, the etching process that forms the trench gate openings 322a, 322b exposes portions of the semiconductor epitaxial layer 310 at the bottom surfaces 340a, 340b of the trench gate openings 322a, 322b that contain the intact lattice structure.

[0066] The penetration depth of ions during ion implantation can be significantly affected by the state of the lattice structure of the target semiconductor surface. For example, if the lattice structure of the target semiconductor surface (e.g., top surface 342) is severely damaged, the penetration depth of accelerated ions may be shallower than the penetration depth of accelerated ions if the lattice structure of the target semiconductor surface (e.g., bottom surfaces 340a, 340b) is intact. Therefore, a semiconductor device (e.g., semiconductor device 300c) having both a severely damaged semiconductor surface (e.g., top surface 342) and a semiconductor surface (e.g., bottom surfaces 340a, 340b) with an intact lattice structure may experience significantly different ion penetration depths.

[0067] 3C , an intentionally damaged semiconductor surface may be utilized to form self-aligned trench bottom protection regions 350a, 350b at the bottom surfaces 340a, 340b of the trench gate openings 322a, 322b without adversely affecting the electrical properties of exposed regions on the top surface 342 of the semiconductor device 300c, such as the semiconductor source region 304. When the intentionally damaged top surface 342 of the semiconductor device 300c and the undamaged bottom surfaces 340a, 340b of the trench gate openings 322a, 322b are exposed to an ion implantation process, the penetration depth of the ions at the bottom surfaces 340a, 340b of the trench gate openings 322a, 322b is greater than the penetration depth of the ions at the top surface 342. The penetration depth of the ions at the bottom surfaces 340a, 340b of the trench gate openings 322a, 322b may form trench bottom protection regions 350a, 350b that provide sufficient protection to the trench gate oxide layer (e.g., oxide layers 360a, 360b shown in FIG. 3D ) and the semiconductor body region 312 while preserving the electrical properties of the semiconductor source region 304 and the body contact region 330.

[0068] As shown in FIG. 3C , trench bottom protection regions 350 a, 350 b are formed on the bottom surfaces 340 a, 340 b of the trench gate openings 322 a, 322 b using a low-energy channeling implant process 352. The channeling implant process 352 is any ion implantation process that takes advantage of the physical properties of a semiconductor lattice structure to maximize the penetration depth of low-energy accelerated ions. The channeling implant process 352 may be configured so that the accelerated ions impinge on the target surface at an implant angle relative to the normal to the target surface such that the target angle is aligned with an opening in the lattice structure of the semiconductor material at the target surface. An exemplary channeling implantation process 352 for silicon carbide semiconductor material is further described in connection with FIG. 4 . Utilizing the low-energy channeling implantation process 352 ensures sufficient ion penetration at the bottom surfaces 340 a, 340 b of the trench gate openings 322 a, 322 b, while negligible penetration at the intentionally damaged region of the top surface 342. The low-energy channeling implant process 352 may utilize a low ion energy to accelerate ions toward the surface of the semiconductor device 300c. For example, in some embodiments, the low ion energy is between 30 kiloelectron volts and 3000 kiloelectron volts, more preferably between 30 kiloelectron volts and 2000 kiloelectron volts, and most preferably between 30 kiloelectron volts and 1000 kiloelectron volts. In addition, a thermal annealing process is performed after each implantation process during semiconductor fabrication. Performing an annealing process after each implantation process, as opposed to a single annealing process after every implantation, allows for at least partial restoration of electrical contact between newly doped regions and adjacent regions of the semiconductor device. However, the doped regions remain intentionally damaged.

[0069] By utilizing the channeling implant process 352 to maximize the penetration depth of accelerated ions in undamaged regions of the semiconductor lattice structure, the channeling implant process 352 may be configured to avoid the high temperatures required during high-energy implant processes. In some embodiments, the temperature during the channeling implant process 352 may be at or near room temperature, e.g., 25 to 30 degrees Celsius, more preferably 23 to 24 degrees Celsius, and most preferably 20 to 22 degrees Celsius. Reducing the operating temperature during the channeling implant process 352 may allow for the use of simpler and less expensive equipment. Additionally, if a hard mask is desired, the channeling implant process 352 may allow for the use of a thinner hard mask for better control of the distribution of implanted ions.

[0070] 3D , an exemplary semiconductor device 300d is provided having vertically aligned trench gates 302a, 302b. As shown in FIG. 3D , oxide layers 360a, 360b are deposited on the interior surfaces of the trench gate openings 322a, 322b to form a barrier between the trench gates 302a, 302b and the semiconductor source region 304, semiconductor body region 312, and semiconductor epitaxial layer 310 of the semiconductor device 300d. Oxide layers 360a, 360b are further deposited on the top surfaces of the trench gates 302a, 302b to insulate the trench gates from external layers, such as the source conductive contact and body contact region electrical contact.

[0071] 3D, protective oxide layers 360a, 360b are deposited on the surfaces of trench gate openings 322a, 322b to form a dielectric layer between the layers of semiconductor device 300d and trench gates 302a, 302b. Oxide layers 360a, 360b allow an electric field to form between trench gates 302a, 302b and semiconductor source region 304, semiconductor body region 312, and semiconductor epitaxial layer 310. The formation of an electric field establishes a conductive channel between semiconductor source region 304 and semiconductor epitaxial layer 310 through semiconductor body region 312.

[0072] Overstressing the oxide layers 360a, 360b often leads to failure of semiconductor devices 300d, such as MOSFET devices. Failure due to overstressed oxide layers 360a, 360b is particularly common in high-power applications. When the semiconductor device 300d is in a blocking state, the electric field at the bottom surfaces 340a, 340b of the trench gate openings 322a, 322b can reach damaging levels. The sustained electric field at the bottom surfaces 340a, 340b of the trench gate openings 322a, 322b can destroy the oxide layers 360a, 360b, impairing the performance of the semiconductor device 300d.

[0073] As shown in FIG. 3D , trench bottom protection regions 350 a, 350 b are formed in an exemplary semiconductor device 300 d to reduce electric fields at the bottom surfaces 340 a, 340 b of the trench gate openings 322 a, 322 b, particularly in high-power applications. When the semiconductor device 300 d is in a blocking state, electric fields can build up at the bottom surfaces 340 a, 340 b of the trench gate openings 322 a, 322 b. Such electric fields can cause premature breakdown of the oxide layers 360 a, 360 b at the bottom surfaces 340 a, 340 b of the trench gate openings 322 a, 322 b. The trench bottom protection regions 350 a, 350 b are formed by doping the bottom surfaces 340 a, 340 b of the trench gate openings 322 a, 322 b with a dopant having a doping type opposite to that of the semiconductor epitaxial layer 310 (e.g., a p-type dopant). The trench bottom protection regions 350a, 350b can extend the effective operation of the semiconductor device 300d, especially in high power applications.

[0074] 4, an exemplary channeling implant process 452 for an exemplary silicon carbide lattice structure 400 is provided. As shown in FIG. 4, the exemplary channeling implant process 452 includes accelerating ions 476 toward a silicon carbide surface including silicon atoms 472 and carbon atoms 474 having an intact silicon carbide lattice structure 400. The ions 476 are accelerated toward the silicon carbide lattice structure 400 at an implant angle 470 relative to a normal 478 to the surface of the semiconductor such that the ions 476 penetrate into the silicon carbide lattice structure 400 through openings in the silicon carbide lattice structure 400.

[0075] 4, the channeling implant process 452 accelerates ions toward a silicon carbide lattice structure 400. Generally, the silicon atoms 472 and carbon atoms 474 of silicon carbide are organized into a lattice structure 400 having defined openings and channels. The channeling implant process 452 utilizes knowledge of the silicon carbide lattice structure 400 to accelerate ions 476 toward the lattice structure 400 such that interference with the silicon atoms 472 and carbon atoms 474 is minimized.

[0076] 4, implantation angle 470 is selected so that accelerated ions 476 are aligned with openings and channels in silicon carbide lattice structure 400. In some embodiments, the surface of the silicon carbide may be tilted during receipt of accelerated ions 476 such that ions 476 are received at implantation angle 470 relative to a normal 478 to the surface of the silicon carbide.

[0077] In some embodiments, for example, on a silicon carbide semiconductor having a cutoff angle of 4 degrees or close to 4 degrees, the implant angle 470 may be 3 degrees to 5 degrees, more preferably 3.25 degrees to 4.75 degrees, and most preferably 3.5 degrees to 4.5 degrees. A low-energy channeling implant process 452 may be utilized by aligning accelerated ions 476 with openings in the silicon carbide lattice structure 400. Such a channeling implant process 452 ensures ion penetration in an undamaged lattice structure sufficient for trench bottom protection, while penetration in a surface with an intentionally damaged lattice structure is negligible.

[0078] The implant angle 470 may depend on the manufacturing of the semiconductor wafer. Thus, the implant angle 470 may depend on the semiconductor type (e.g., silicon carbide, silicon, etc.) and the cutoff angle of the semiconductor wafer. Varying manufacturing conditions may result in a channeling angle tolerance. The channeling angle tolerance may be a range of implant angles 470 that can be configured to operate the channeling implant process 452 and still obtain sufficient ion implantation depth.

[0079] Referring now to FIG. 5 , an exemplary process 500 is provided for forming a self-aligned trench bottom protection region (e.g., trench bottom protection region 350a, 350b) on a bottom surface of a trench gate (e.g., trench gates 302a, 302b) of a trench-gated MOSFET. In block 502, a semiconductor body region (e.g., semiconductor body region 312) is formed on an upper surface of and within a semiconductor epitaxial layer (e.g., semiconductor epitaxial layer 310), where the semiconductor epitaxial layer comprises a first conductivity type and the semiconductor body region comprises a second conductivity type. As described herein, trench-gated MOSFETs may be utilized to control current flowing vertically through a MOSFET device. The semiconductor body region is formed adjacent to the semiconductor epitaxial layer, forming a PN junction at the intersection of the semiconductor body region and the semiconductor epitaxial layer. In some embodiments, the semiconductor body region is a doped p-type semiconductor and the semiconductor epitaxial layer is a doped n-type semiconductor.

[0080] In block 504, a semiconductor source region (e.g., semiconductor source region 304) is formed in the semiconductor body region, the semiconductor body region separating the semiconductor source region from the semiconductor epitaxial layer, the semiconductor source region comprising a first conductivity type. As described herein, the semiconductor body region may be formed between the semiconductor source region and the semiconductor epitaxial layer to block current flow from the semiconductor source region through the semiconductor body region to the semiconductor epitaxial layer when a voltage at the trench gate is below a threshold voltage and to allow current flow when the trench gate voltage exceeds the threshold voltage. The semiconductor source region may be formed using an ion implantation process intended to intentionally damage the lattice structure of the semiconductor source region. In some embodiments, the semiconductor source region may comprise a doped semiconductor having a heavily doped semiconductor doping concentration. In some embodiments, the semiconductor source region may comprise an n-type doping type.

[0081] In block 506, trench gate openings (e.g., trench gate openings 322a, 322b) are etched in the exposed surfaces (e.g., top surface 342) of the semiconductor source regions, and the trench gate openings include bottom surfaces (e.g., bottom surfaces 340a, 340b), which include the semiconductor epitaxial layer. As described herein, the trench gate openings are etched into the semiconductor epitaxial layer to facilitate current flow from the semiconductor source regions along the trench gate openings to the conductive drain layer (e.g., conductive drain layer 308). The etching process exposes the bottom surfaces of the trench gate openings, and the lattice structure of the semiconductor epitaxial layer, including the bottom surfaces, is intact. Conversely, the lattice structure of certain regions of the top surface, such as the semiconductor source regions and body contact regions, is intentionally damaged.

[0082] In block 508, a shielding dopant having the second conductivity type (e.g., a dopant forming a trench bottom protection region) is implanted by a channeling implant process (e.g., channeling implant process 352), exposing the exposed surface of the semiconductor source region to the shielding dopant during the implant process, and the shielding dopant forms a trench bottom protection region at the bottom of the trench gate opening. As described herein, the channeling implant process that forms the trench bottom protection region of the trench gate openings 322a, 322b is formed without using a hard mask to protect top surface structures such as the semiconductor source region and body contact region. Instead, these structures are protected by intentionally damaging the surfaces of these regions so that the lattice structure of the semiconductor material is damaged and the penetration of accelerated ions is minimized. The impact of the shielding dopant on the electrical properties of the semiconductor source region and body contact region is negligible because the penetration of implanted ions is limited compared to the depth of these doped regions. However, penetration of the shielding dopant into the bottom surface of the trench gate opening is sufficient to provide protection against elevated electric fields at the bottom surface of the trench gate opening during operation of the trench-gated MOSFET device. In some embodiments, the implant angle of the channeling implant process is aligned with the lattice structure of the semiconductor material to maximize penetration of the shielding dopant into the bottom surface of the trench bottom opening, forming a trench bottom protection region at the bottom surface of the trench bottom opening and reducing damaging electric fields in the oxide layer of the trench gate.

[0083] While this detailed description has described several embodiments of the present invention, the appended claims cover other embodiments of the present invention that differ from the described embodiments, in accordance with various modifications and improvements. For example, those skilled in the art will recognize that such principles may be applied to any electronic device utilizing a trench-gate MOSFET architecture.

[0084] Within the scope of the appended claims, no claim is intended to be construed under 35 U.S.C. 112, paragraph 6, unless the specific terms "means for" or "step for" are used in a given claim.

[0085] The use of broader terms such as "comprises," "includes," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting essentially of," and "comprised substantially of." The use of terms such as "optionally," "may," "might," and "possibly" with respect to any element of an embodiment means either that the element is not required, or that the element is required, and both alternatives are within the scope of the embodiment. Also, references to examples are provided merely for illustrative purposes and are not intended to be exhaustive.

Claims

1. 1. A method for forming a trench bottom protection region in a metal oxide semiconductor field effect transistor (MOSFET) device, the method comprising: forming a semiconductor body region on an upper surface of a semiconductor epitaxial layer and within the semiconductor epitaxial layer, the semiconductor epitaxial layer comprises a first conductivity type; forming a semiconductor body region, the semiconductor body region comprising a second conductivity type; forming a semiconductor source region in the semiconductor body region; the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer; forming a semiconductor source region, the semiconductor source region comprising the first conductivity type; etching a trench gate opening in the exposed surface of the semiconductor source region; the trench gate opening includes a bottom surface; etching a trench gate opening, the bottom surface of which includes the semiconductor epitaxial layer; implanting a shielding dopant having the second conductivity type by a channeling implantation process, the exposed surface of the semiconductor source region is exposed to the screening dopant during the channeling implant process; implanting a shielding dopant, the shielding dopant forming the trench bottom protection region at the bottom surface of the trench gate opening; A method comprising:

2. 10. The method of claim 1, wherein the channeling implant process accelerates the shielding dopants toward the MOSFET device at low ion energy.

3. The method of claim 2, wherein the low ion energy is between 30 kiloelectron volts and 3000 kiloelectron volts.

4. the channeling implant process accelerates the shielding dopant toward the MOSFET device at an implant angle; The method of claim 1 , wherein the implant angle is measured relative to a direction normal to a surface of the MOSFET device.

5. 5. The method of claim 4, wherein the implant angle is between 3.5 degrees and 4.5 degrees.

6. forming a body contact region having the second conductivity type in the semiconductor source region; The method of claim 1 , wherein the body contact region is electrically coupled to the semiconductor body region.

7. The method of claim 6 , wherein the body contact region is doped with a body contact doping concentration.

8. The method of claim 7 , wherein the semiconductor body region is doped at a semiconductor body concentration.

9. The method of claim 8 , wherein the body contact doping concentration is higher than the semiconductor body concentration.

10. The method of claim 1 , wherein the first conductivity type is an n-type semiconductor.

11. The method of claim 1 , wherein the second conductivity type is a p-type semiconductor.

12. The method of claim 1 , wherein the semiconductor epitaxial layer is doped with a first doping concentration.

13. The method of claim 12 , wherein the semiconductor source region is doped with a second doping concentration.

14. The method of claim 13 , wherein the first doping concentration is less than the second doping concentration.

15. 10. The method of claim 1, wherein the semiconductor source region is formed using an ion implantation process.

16. 16. The method of claim 15, wherein a source region lattice structure of the semiconductor source region is intentionally damaged during the ion implantation process.

17. The method of claim 6 , wherein the body contact region is formed using an ion implantation process.

18. 20. The method of claim 17, wherein a body contact region lattice structure of the body contact region is intentionally damaged during the ion implantation process.

19. 1. A trench gate MOSFET device comprising: a semiconductor body region comprising a first conductivity type; a semiconductor source region formed on an upper surface of the semiconductor body region and comprising a second conductivity type; a semiconductor epitaxial layer comprising the second conductivity type, the semiconductor body region being separated from the semiconductor source region by the semiconductor body region; a trench gate opening etched into the exposed surface of the semiconductor source region; the trench gate opening includes a bottom surface; a trench gate opening, the bottom surface of which includes the semiconductor epitaxial layer; a trench bottom protection region formed in the semiconductor epitaxial layer at the bottom of the trench gate opening, the trench gate opening comprising: implanting a shielding dopant having the second conductivity type by a channeling implantation process, the exposed surface of the semiconductor source region is exposed to the screening dopant during the channeling implant process; a trench bottom protection region formed by: the shielding dopant forming the trench bottom protection region on the bottom surface of the trench gate opening; 1. A trench-gate MOSFET device comprising:

20. 1. A product-by-process for a trench gate MOSFET device, comprising: forming a semiconductor body region on an upper surface of a semiconductor epitaxial layer and within the semiconductor epitaxial layer, the semiconductor epitaxial layer comprises a first conductivity type; forming a semiconductor body region, the semiconductor body region comprising a second conductivity type; forming a semiconductor source region in the semiconductor body region; the semiconductor body region separates the semiconductor source region from the semiconductor epitaxial layer; forming a semiconductor source region, the semiconductor source region comprising the first conductivity type; etching a trench gate opening in the exposed surface of the semiconductor source region; the trench gate opening includes a bottom surface; etching a trench gate opening, the bottom surface of which includes the semiconductor epitaxial layer; implanting a shielding dopant having the second conductivity type by a channeling implantation process, the exposed surface of the semiconductor source region is exposed to the screening dopant during the implantation process; implanting a shielding dopant, the shielding dopant forming the trench bottom protection region at the bottom surface of the trench gate opening; 1. A product-by-process of a tunnel-gate MOSFET device fabricated by a method comprising:

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