Analog-to-digital converter and image sensor including the same

Abstract

To provide an image sensor that operates stably in low-power environments.SOLUTION: According to one embodiment of the present invention, an image sensor is provided, including: a pixel array; and an ADC configured to convert a pixel signal into a digital signal. The ADC includes: an input circuit configured to receive a ramp signal and the pixel signal, and configured to output a first signal in which the ramp signal is applied to the pixel signal; an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply node and a ground node, the inverter being configured to output a second signal obtained by inverting the first signal input through an input node to an output node; and a code generation circuit configured to output the digital signal based on the second signal. The inverter includes at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and the ground node and configured to be controlled by a bias voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and more particularly to an analog-to-digital converter that converts pixel signals of an image sensor into digital signals, and an image sensor including the same. [Background technology]

[0002] Image sensors are devices that convert optical signals into electrical signals and include CCD (charge coupled device) image sensors and CMOS (complementary metal oxide semiconductor) image sensors.

[0003] As the number of pixels in image sensors increases, power consumption increases, but low-power operation is becoming increasingly important in mobile environments.

[0004] Related image sensors mainly use a 5T (5 transistors)-based OTA (operational transconductance amplifier) analog-to-digital converter (hereinafter referred to as ADC) to convert pixel signals into digital signals. However, the 5T-based OTA ADC has a problem in that it is difficult to secure full-well capacity (FWC) in a low-power environment using a low driving voltage due to its narrow signal input range. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent No. 11,140,346 B2 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide an image sensor that operates stably in a low-power environment.

[0007] SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensor that can be implemented in a small area. [Means for solving the problem]

[0008] An image sensor according to an embodiment of the present invention includes a pixel array including a plurality of active pixels; and an analog-to-digital converter (ADC) that converts pixel signals of the plurality of active pixels into digital signals. The ADC includes an input circuit that receives a ramp signal and the pixel signal and outputs a first signal in which the ramp signal is reflected in the pixel signal. The ADC also includes an inverter that includes a pull-up transistor and a pull-down transistor connected in series between a power supply voltage node and a power supply ground node and outputs a second signal at an output node, the second signal being an inverted version of the first signal input to the input node. The inverter may include at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and the power supply ground node and controlled by a bias voltage.

[0009] According to an embodiment of the present invention, an image sensor including a plurality of pixels includes: a photodetector, each of the plurality of pixels including a photoelectric conversion element; an input circuit that receives a ramp signal and pixel signals of the plurality of pixels and outputs a first signal in which the pixel signals are reflected in the ramp signal; an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply voltage terminal and a power supply ground terminal, and outputting a second signal that is an inversion of the first signal input to an input node to an output node; and a code generation circuit that outputs a digital signal based on the second signal, wherein the inverter includes at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and the power supply ground node and controlled by a bias voltage.

[0010] An image sensor according to an embodiment of the present invention includes a pixel array including a plurality of active pixels; and an ADC (analog-to-digital converter) circuit that converts pixel signals of the plurality of active pixels into digital signals. The ADC includes an input circuit that receives a ramp signal and the pixel signal and outputs a first signal in which the ramp signal is reflected in the pixel signal. The ADC also includes an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply voltage node and a power supply ground node, and that outputs a second signal at an output node by inverting the first signal input to the input node. The inverter may include at least one starving transistor configured to limit a magnitude of current flowing through at least one of the pull-up transistor and the pull-down transistor during inverter transition operation.

[0011] An ADC (analog-to-digital converter) according to an embodiment of the present invention includes a P-type pull-up transistor and an N-type pull-down transistor connected in series to each other through an output node between a power supply voltage node and a power ground node, with their gate electrodes connected to an input node; an inverter that outputs a second signal, which is an inverted version of a first signal input to the input node, to the output node; and a code generation circuit that outputs a digital signal based on the second signal, wherein the inverter may include at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and the power ground node and controlled by a bias voltage. [Effects of the Invention]

[0012] The image sensor according to the present invention can operate stably in a low-power environment.

[0013] The image sensor according to the present invention can be implemented in a small area. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a block diagram illustrating an exemplary image device according to an embodiment of the present invention; [Figure 2] 1 is a diagram illustrating an image sensor according to an embodiment of the present invention. [Figure 3A] 1 is a diagram illustrating a pixel of an image sensor according to an embodiment of the present invention. [Figure 3B] 1 is a diagram illustrating a pixel of an image sensor according to an embodiment of the present invention. [Figure 4] 1 is a diagram illustrating an ADC according to one embodiment of the present invention. [Figure 5] 1 is a diagram illustrating a bias circuit of an image sensor according to an embodiment of the present invention. [Figure 6] 5 is a diagram illustrating operation timing of an ADC according to the embodiment of FIG. 4. [Figure 7A] 5 is a diagram conceptually illustrating a signal swing of an ADC according to the embodiment of FIG. 4; [Figure 7B] 5 is a result of simulating pixel swing of an image sensor including an ADC according to the embodiment of FIG. 4. [Figure 8] 1 is a diagram illustrating an ADC according to another embodiment of the present invention. [Figure 9] 1 is a block diagram of an image sensor according to an embodiment of the present invention; [Figure 10] FIG. 10 is a block diagram of an image sensor according to another embodiment of the present invention. [Figure 11] FIG. 10 is a block diagram of an image sensor according to another embodiment of the present invention. [Figure 12] FIG. 10 is a block diagram of an image sensor according to another embodiment of the present invention. [Figure 13] 1 is a block diagram of an electronic device according to an embodiment of the present invention. [Figure 14] FIG. 2 is a block diagram of an application processor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] DETAILED DESCRIPTION OF THE INVENTION In the following, the embodiments of the present invention are described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

[0016] FIG. 1 is an exemplary block diagram of an image device 1000 according to one embodiment of the present invention.

[0017] The image device 1000 according to the embodiment of the present invention can perform analog-to-digital conversion of the pixel signal PXS using an inverter-based ADC 150 connected to a bias transistor.

[0018] Referring to FIG. 1, an image device 1000 may include an image sensor 100 and an image signal processor 200 .

[0019] The image device 1000 may be an electronic device such as a digital camera, a smartphone, a wearable device, an Internet of Things (IoT), a tablet computer, a personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation device, etc. The image device 1000 may also be an electronic device provided as an accessory included in a vehicle, manufacturing equipment, a door, various measuring instruments, etc.

[0020] The image sensor 100 generates image data, which is visual information of an object captured through a lens, and the image signal processor 200 can be implemented to process the image data generated by the image sensor 100 and output it to a display device or store it in a storage device.

[0021] The image signal processor 200 can demosaic the image signal according to the pixel pattern by interpolation, etc., perform color correction, adjust the dynamic range, or reduce noise through filtering, etc. The image signal processor ISP can additionally perform other methods to improve image quality.

[0022] 1, the image signal processor 200 is illustrated as being disposed outside the image sensor 100. However, depending on the embodiment, the image signal processor 200 may alternatively be disposed inside the image sensor 100. Alternatively, depending on the embodiment, some logic of the image signal processor 200 may be disposed in the image sensor 100, and the other part may be disposed in an external application processor (AP).

[0023] The image sensor 100 may include a pixel array 110 , a row driver 120 , a timing controller 130 , an ADC 150 , and an output buffer 160 .

[0024] The pixel array 110 includes a plurality of pixels. The plurality of pixels may be arranged, for example, in a matrix shape. The pixel array 110 may receive a plurality of pixel drive signals CSn from the row driver 120, such as a selection signal for controlling a selection transistor, a reset signal for controlling a reset transistor, and a transmission transistor control signal for controlling a transmission transistor. Each of the plurality of pixels in the pixel array 110 operates according to the control of the received pixel drive signals CSn.

[0025] The row driver 120 can drive any one row of the pixel array 110 under the control of the timing controller 130. The row driver 120 can generate a selection signal to drive any one row among the plurality of rows. The row driver 120 can activate pixels corresponding to the selected row. Pixel signals PXS of the pixels of the selected row can be transmitted to the ADC 150 through a plurality of column lines CLm.

[0026] The pixel signal PXS may include a reset voltage signal and a pixel voltage signal. The pixel voltage signal may be a voltage of a floating diffusion region to which charge generated in a photodiode PD included in each of the plurality of pixels is reflected. The reset voltage signal may be a voltage of a floating diffusion region to which charge generated in a photodiode PD is not reflected.

[0027] The timing controller 130 may control the pixel array 110, the row driver 120, the ramp signal generator 140, and the ADC 150. The timing controller 130 may provide a timing control signal (TC) to the row driver 120. The timing controller 130 may control the ramp signal generator 140 through a ramp control signal CS_RP and the ADC 150 through an ADC control signal CS_ADC. The ramp control signal CS_RP may include a ramp enable signal, a mode signal, etc.

[0028] The ramp signal generator 140 may generate a ramp signal RAMP in response to a ramp enable signal. The ramp signal generator 140 may generate a ramp signal RAMP having a preset slope. The ramp signal generator 140 may provide the generated ramp signal RAMP to the ADC 150. In one embodiment, the slope of the ramp signal RAMP may be set differently based on a mode signal. The mode signal may be a signal based on an imaging mode selected by a user, such as a wide-angle mode or a low-light mode.

[0029] The ADC 150 can convert the reset voltage signal and pixel voltage signal of the pixel signal PXS into a digital signal, pixel data PXD, based on the ramp signal RAMP. For example, the ADC 150 can convert the reset voltage signal and pixel voltage signal into digital signals based on the ramp signal RAMP using a correlated double sampling (CDS) method, and output the difference between the reset voltage signal and the pixel voltage signal as the digital signal, pixel data PXD.

[0030] The ADC 150 according to an embodiment of the present invention can convert a pixel signal PXS using an inverter 152_1 connected in series with a bias transistor to output pixel data PXD. The inverter-based ADC 150 can convert an analog pixel signal PXS and output digital pixel data PXD. The ADC 150 can perform analog-to-digital conversion using the inverter 152_1, which is configured with fewer transistors than a related art 5T (5 transistors)-based OTA ADC. Therefore, the ADC 150 has sufficient headroom for the operating voltage and can operate over a wide pixel swing range even in a low-power environment where a low driving voltage is provided. Furthermore, at least one bias transistor connected in series with the inverter 152_1 of the ADC 150 can operate as a dependent current source. As a result, the inverter 152_1 of the ADC 150 is less susceptible to the power supply voltage, allowing the ADC 150 to operate stably. In some embodiments, the operating voltage range of the inverter 152_1 may be set to be greater than 50% of the driving voltage provided at the power supply node.

[0031] The buffer 160 may be configured to temporarily store the pixel signal PXD output from the ADC 150, and then amplify and output the stored pixel signal PXD.

[0032] FIG. 2 is a diagram specifically illustrating an image sensor according to an embodiment of the present invention. The image sensor 100 of FIG. 2 may correspond to the image sensor 100 of FIG. 1. Referring to FIG. 2, the image sensor 100 according to an embodiment of the present invention includes a pixel array 110, a row driver 120, a timing controller 130, a ramp signal generator 140, an ADC 150, and a buffer 160. The embodiment described with reference to FIG. 2 will be described assuming that the ADCs 150 are arranged for each column line and that the ADCs 150 arranged for each column line operate in parallel. However, the embodiment described with reference to FIG. 2 is not limited to the ADCs 150 being arranged for each column line. That is, the ADCs 150 may be arranged for each pixel or for each pixel group, as in the embodiments described with reference to FIGS. 10 to 12 below. In this case, the ADCs 150 may operate in parallel for each pixel or for each pixel group.

[0033] The pixel array 110 includes a plurality of pixels PXs. Each of the pixels PXs may be electrically connected to one of a plurality of row lines and a plurality of column lines. In one embodiment, each pixel PX may include a plurality of transistors controlled by the row driver 120. Alternatively, in another embodiment, two or more adjacent pixels PXs may form a pixel group, and the two or more pixels PXs included in the pixel group may share at least some of the transfer transistors, drive transistors, selection transistors, and reset transistors with each other.

[0034] Each of the plurality of pixels PXs can include a photoelectric conversion element that converts an incident optical signal into an electrical signal. Each pixel PX can include at least one photoelectric conversion element.

[0035] The photoelectric conversion element may be a photodiode (PD). The photoelectric conversion element may be any one of a photodiode (PD), a photocapacitor, a photogate, a pinned photodiode (PPD), a partially pinned photodiode (Partially Pinned Photodiode), an organic photodiode (OPD), and a quantum dot (QD), or a combination thereof. Although the embodiments of the present specification will be described assuming that the photoelectric conversion element is a photodiode PD, other photoelectric conversion elements described above may also be used, and the photoelectric conversion element is not limited to a photodiode PD.

[0036] The pixel signal PXS generated in each pixel of a row selected by the selection signal of the row driver 120 can be transmitted to the ADC 150 through a column line corresponding to each pixel.

[0037] The ADC 150 may include an input circuit (INCT) 151 , a comparator 152 , and a code generation circuit 153 .

[0038] According to an embodiment of the present invention, there are a plurality of input circuits (INCT) 151, each corresponding to a respective one of a plurality of column lines. Each of the input circuits 151 may receive a pixel signal PXS from the column line and a ramp signal RAMP from the ramp signal generator 141. The input circuit 151 may generate a first output signal in which the ramp signal RAMP is reflected in the pixel signal PXS. The first output signal may be provided to the comparator 152. That is, the input signal input to the comparator 152 is a signal in which the ramp signal RAMP is reflected in the pixel signal PXS.

[0039] According to an embodiment of the present invention, the comparator 152 may generate a comparison result signal by comparing a first output signal, in which the ramp signal RAMP is reflected in the pixel signal PXS, with a reference level. The comparator 152 may generate a comparison result signal based on a correlated double sampling scheme. The comparator 152 may generate a comparison result signal by comparing each first output signal, in which the ramp signal RAMP is reflected in each of the reset voltage signal and the pixel voltage signal, with a reference level. The comparator 152 may compare each first output signal, in which the ramp signal RAMP is reflected in each of the reset voltage signal and the pixel voltage signal, with a reference level of the same voltage magnitude. That is, the decision points of each of the reset voltage signal and the pixel voltage signal may be maintained at the same voltage level. The generated comparison result signal may be provided to the code generation circuit 153.

[0040] The comparator 152 may be configured with multiple stages, with the first stage including an inverter INV and the second stage including an amplifier AMP. The inverter INV may receive the first output signal and provide the amplifier AMP with a second output signal obtained by inverting the first output signal. The inverter INV may include at least one bias transistor controlled by a bias voltage. The amplifier AMP may amplify the second output signal to generate a comparison result signal and provide the comparison result signal to the code generation circuit 153.

[0041] The code generation circuit 153 may include a counter CNT. The counter CNT can count clock signals corresponding to the levels of the reset voltage signal and the pixel voltage signal based on a comparison result signal in which the ramp signal RAMP is reflected in each of the reset voltage signal and the pixel voltage signal. The counter CNT can generate pixel data PXD, which is a digital signal, based on the difference between the level of the reset voltage signal and the level of the pixel voltage signal.

[0042] The buffer 160 may include a plurality of column memory blocks 161 corresponding to each column for storing the pixel signals PXD. The buffer 160 may include a sense amplifier (SA) 162 for amplifying the pixel signals PXD stored in the column memory blocks 161. The sense amplifier (SA) 162 may output the amplified pixel signals PXD as image data IDT.

[0043] 3A and 3B are diagrams illustrating pixels of an image sensor according to an embodiment of the present invention, where pixels PXa and PXb in FIGS. 3A and 3B correspond to pixels PX in the image sensor 100 in FIG.

[0044] Referring to FIG. 3A, the pixel PXa may include a photoelectric conversion element PD, a transfer transistor TX, a floating diffusion node FD, a reset transistor RX, a driving transistor DX, and a selection transistor SX.

[0045] The photoelectric conversion element PD can generate photocharges corresponding to incident light.

[0046] The transfer transistor TX electrically connects the photoelectric conversion element PD to the floating diffusion node FD based on a transfer transistor control signal TG. When the transfer transistor TX is turned on, photocharges of the photoelectric conversion element PD electrically connected to the floating diffusion node FD can be transferred to the floating diffusion node FD.

[0047] The reset transistor RX may electrically connect the floating diffusion node FD to a reset voltage. The reset transistor RX may reset the floating diffusion node FD to the voltage level of the power supply voltage node VDD in response to a reset control signal RS provided from the row driver 120 of Figures 1 and 2. Although Figure 3A illustrates the reset voltage being provided from the power supply voltage node VDD, the reset voltage may be provided from a voltage node having a voltage level other than the power supply voltage node VDD, depending on the embodiment.

[0048] The drive transistor DX is driven by a drive voltage provided by a power supply voltage node VDD. The drive transistor DX can output an output voltage Vout corresponding to the charge stored in the floating diffusion node FD. The drive transistor DX can output the output voltage Vout to the column line CLi through the selection transistor SX.

[0049] The reset voltage signal output after the reset transistor RX connects the floating diffusion node FD to the reset voltage, and the pixel voltage signal output after the photocharges of the photoelectric conversion element PD move to the floating diffusion node FD, can each be output to the column line CLi as an output voltage Vout.

[0050] The ADC 150 in FIGS. 1 and 2 can convert the reset voltage signal output to the column line CLi and the pixel voltage signal, in which the ramp signal RAMP is reflected, into pixel data using an inverter.

[0051] 3B, pixel PXb may include a plurality of photoelectric conversion elements PDs, a transfer transistor TX, a floating diffusion node FD, a reset transistor RX, a drive transistor DX, and a selection transistor SX. That is, a plurality of photoelectric conversion elements PDs may share the same transfer transistor TX, floating diffusion node FD, reset transistor RX, drive transistor DX, and selection transistor SX.

[0052] After the reset transistor RX couples the floating diffusion node FD to the reset voltage, the output reset voltage signal and the photocharges of the photoelectric conversion elements PDs are transferred to the floating diffusion node FD during the same time period, and each of the output pixel voltage signals can be output to the column line CLi as an output voltage Vout.

[0053] 3B illustrates that a single transfer transistor TX shared by multiple photoelectric conversion elements PDs is controlled by the same transfer transistor control signal TG, but it is not excluded that multiple photoelectric conversion elements PDs can also be connected to the floating diffusion node FD by different transfer transistors, in which case the different transfer transistors can be controlled by different transfer transistor control signals.

[0054] The pixel of the embodiment of the present invention is not limited to the pixels PXa and PXb of Figures 3A and 3B. Various pixel configurations and operations may be used, such as a configuration in which one microlens is shared by multiple photoelectric conversion elements PDs of one pixel, a configuration in which one microlens is shared by multiple photoelectric conversion elements PDs of multiple pixels, or a configuration in which one pixel or pixel group outputs multiple pixel signals based on different conversion gains.

[0055] FIG. 4 is a diagram illustrating in detail an ADC according to an embodiment of the present invention. The ADC 150 in FIG. 4 may correspond to the ADC 150 in FIG. 1 and FIG. 2. The embodiment described with reference to FIG. 4 will be described assuming that the ADCs 150 are arranged for each column line and operate in parallel for each column line. However, the embodiment described with reference to FIG. 4 is not limited to the ADCs 150 being arranged for each column line. That is, the ADCs 150 may be arranged for each pixel or for each pixel group, as in the embodiments described with reference to FIG. 10 to FIG. 12 below. In this case, the ADCs 150 may operate in parallel for each pixel or for each pixel group.

[0056] 4, the ADC 150 may include an input circuit 151, an inverter 152_1, an amplifier (AMP) 152_2, and a counter (CNT) 153_1. The input circuit 151, inverter 152_1, amplifier 152_2, and counter 153_1 shown in FIG. 4 correspond to one column line CLi. Therefore, the ADC 150 of the image sensor may include a respective input circuit, inverter, amplifier, and counter corresponding to each column line.

[0057] In one embodiment, the ADC 150 of FIG. 4 may be a single slope ADC.

[0058] An input circuit 151 according to an embodiment of the present invention may include multiple capacitors C1, C2.

[0059] The first capacitor C1 may be connected to the column line CLi and the input node IN. The pixel signal PXS output from the pixel PX through the column line CLi may be sampled by the first capacitor C1 and then transmitted to the input node IN. That is, the first capacitor C1 may sample each of the reset voltage signal and the pixel voltage signal of the analog signal components output from the pixel PX.

[0060] The second capacitor C2 may be connected to the ramp signal generator and the input node IN. The second capacitor C2 may receive the ramp signal RAMP generated by the ramp signal generator. Depending on the embodiment, the ramp signal RAMP may be an upward-sloping ramp signal with a single slope that increases at a constant gradient, or a downward-sloping ramp signal with a single slope that decreases at a constant gradient. The second capacitor C2 attenuates the direct current (DC) component of the ramp signal RAMP and transfers the voltage change amount of the ramp signal RAMP to the input node IN.

[0061] The voltage change amount of the ramp signal RAMP at the input node IN is reflected in the pixel signal PXS and can be input to the inverter 152_1 as the input signal Vf.

[0062] The inverter 152_1 may include a pull-up transistor PUT, a pull-down transistor PDT, an auto-zero transistor AZT, and a bias transistor BT.

[0063] The pull-up transistor PUT and the pull-down transistor PDT may be different types of transistors and may be connected in series between a power supply voltage node VDD and a power supply ground node GND. For example, the pull-up transistor PUT may be a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the pull-down transistor PDT may be an N-type MOSFET. The source terminal of the pull-up transistor PUT may be connected to the power supply voltage node VDD, and the drain terminal may be connected to the drain terminal of the pull-down transistor PDT and the output node OUT. The source terminal of the pull-down transistor PDT may be connected to the power supply ground node GND through the bias transistor BT. The gate terminal of the pull-up transistor PUT and the gate terminal of the pull-down transistor PDT may be commonly connected to an input node IN. The inverter 152_1 receives an input signal Vf at the input node IN and inverts the input signal Vf to output an output signal OUT1 at the output node OUT.

[0064] The input node IN and the output node OUT of the inverter 152_1 may be connected through an auto-zero transistor AZT. The source terminal of the auto-zero transistor AZT may be connected to the input node IN of the inverter 152_1, and the drain terminal may be connected to the output node OUT. The auto-zero transistor AZT may operate like a switch under the control of an auto-zero signal AZS. The auto-zero signal AZS may be provided from the timing controller 130 of FIGS. 1 and 2 as an initialization signal for determining an initial operating level when the ADC 150 starts operating.

[0065] An output signal OUT1 output from an output node OUT of the inverter 152_1 is input to an amplifier (AMP) 152_2, and a CDS signal OUT2 amplified by the amplifier 152_2 may be input to a counter (CNT) 153_1. The amplifier 152_2 may include a common source amplifier or an operational amplifier (OP-AMP).

[0066] The counter 153_1 may count the level of the input signal Vf based on the CDS signal OUT2. The counter 153_1 may count the level of the input signal Vf by taking into account the difference between the level of the reset voltage signal and the level of the pixel voltage signal. Information obtained by counting the level of the input signal Vf may be output as pixel data PXD, which is a digital signal. The counter 153_1 may include an up / down counter, a bit-wise counter, or the like.

[0067] According to an embodiment of the present invention, the inverter 152_1 may include at least one bias transistor BT connected in series with the pull-down transistor PDT between the pull-down transistor PDT and the power supply ground node GND. Although FIG. 4 illustrates one bias transistor BT, according to an embodiment, the bias transistor BT may be a plurality of bias transistors connected in series with each other.

[0068] When the bias transistor BT is implemented as an N-type MOSFET, the drain terminal of the bias transistor BT may be connected to the source terminal of the pull-down transistor PDT, and the source terminal may be connected to the power supply ground node GND. The gate terminal of the bias transistor BT may be connected to a bias circuit and controlled by a bias voltage BN. The magnitude of the bias current IB may be adjusted by the magnitude of the bias voltage BN.

[0069] Therefore, the bias transistor BT operates as a dependent current source due to the bias voltage BN, and a controlled bias current IB can flow through the bias transistor BT. As a result, when the pull-up transistor PUT and the pull-down transistor PDT transition from a turn-on state (or a turn-off state) to a turn-off state (or a turn-on state), a current path instantaneously generated in the inverter 152_1 can prevent the output signal OUT1 from significantly changing due to the influence of the power supply voltage node VDD. That is, the bias transistor BT allows the output signal OUT1 of the inverter 152_1 to be stably output. The bias transistor BT may be a starving transistor configured to limit the amount of current flowing through the pull-up transistor PUT or the pull-down transistor PDT during the transition operation of the inverter 152_1.

[0070] According to some embodiments, a cascode transistor (not shown) may be additionally disposed between the bias transistor BT and the pull-down transistor PDT, and connected in series with each of the bias transistor BT and the pull-down transistor PDT. The cascode transistor may include a gate electrode that receives a cascode voltage. The cascode transistor may act as a buffer between the power supply voltage node VDD and the bias transistor BT. When the cascode transistor is implemented as an N-type MOSFET and the cascode voltage is maintained at a high level, the magnitude of the bias current IB may be adjusted according to the magnitude of the bias voltage BN.

[0071] The ADC 150 described with reference to FIG. 4 may be implemented with a smaller number of transistors than the ADCs of the related art. Therefore, the ADC 150 according to the embodiment of the present invention may have a wider input signal swing range. Furthermore, unlike the embodiment of FIG. 4 in which the ADC 150 is arranged for each column line due to the small area of the image sensor, the ADC 150 may be arranged for each pixel and operate in parallel for each pixel.

[0072] 5 is a diagram illustrating a bias circuit of an image sensor according to an embodiment of the present invention. The bias voltage BN output from the bias circuit 170 of FIG. 5 may correspond to the bias voltage BN provided to the bias transistor BT described with reference to FIG.

[0073] The bias circuit 170 may include a constant current source IS, a first mirror circuit 171, a second mirror circuit 172, and an output circuit 173. The bias circuit 170 may be similar to the bias circuit 170 shown in FIG. 5, and may include various circuits that perform a current mirror.

[0074] In the bias circuit 170, a current supplied by a constant current source IS is mirrored by a first mirror circuit 171, a second mirror circuit 172, and an output circuit 173, and the gate voltage of the output circuit 173 can be output as a bias voltage BN. The bias voltage BN is provided to the gate terminal of the bias transistor BT of FIG. 4, and the magnitude of the bias current IB can be controlled by the bias voltage BN.

[0075] 4 is connected in series with the bias transistor BT, the cascode voltage supplied to the gate terminal of the cascode transistor may be the bias voltage BN output from the bias circuit 170. Alternatively, the cascode voltage may be a voltage of another magnitude output from a circuit having a similar structure to the bias circuit 170 shown in FIG.

[0076] FIG. 6 is a diagram showing the operation timing of an ADC. The operation timing of FIG. 6 may correspond to the operation of the ADC 150 according to the embodiment of FIG. 4. The operation timing of the ADC 150 will be described with reference to FIGS. 4 and 6. The operation timing of FIG. 6 is based on the assumption that the ramp signal RAMP input to the input circuit 151 of the ADC 150 according to the embodiment of FIG. 4 is an upward-sloping ramp signal with a single slope that increases at a constant gradient. However, a downward-sloping ramp signal with a single slope that decreases at a constant gradient can also be applied in a similar manner.

[0077] After a row of the pixel array is selected, the auto-zero transistor AZT may be turned on by the auto-zero signal AZS at time t0. The auto-zero signal AZS may maintain the turned-on state for a period between time t0 and time t1. The period between time t0 and time t1 may be referred to as an auto-zero period before the inverter 152_1 is activated.

[0078] Inverter 152_1 may be initialized in response to an auto-zero signal during the auto-zero period. When auto-zero transistor AZT is turned on, input node IN, to which input signal Vf is input, may be electrically connected to output node OUT, from which output signal OUT1 of inverter 152_1 is output. As a result, during the auto-zero period, the voltage levels of input node IN and output node OUT of inverter 152_1 may become equal to the common level voltage VCM. At time t1, auto-zero transistor AZT is turned off, and may maintain its turned-off state during the operating period of inverter 152_1.

[0079] After the offset of the ramp signal RAMP is reduced at time t2, the increasing ramp signal RAMP from time t3 is reflected in the reset voltage signal of the pixel signal PXS, thereby increasing the input signal Vf. The CDS signal OUT2 of the amplifier 152_2 maintains a high level until time t4 when the input signal Vf becomes equal to the first decision point DP1, and then inverts to a low level at time t4.

[0080] The counter 153_1 may count the counting clock signal CNT_CLK from time t3 to time t4, when the polarity of the CDS signal OUT2 of the amplifier 152_2 is inverted to a low level. If the counter 153_1 is an up / down counter, the counter 153_1 may count down the counting clock signal CNT_CLK from time t3 to time t4. The counter 153_1 stops counting the counting clock signal CNT_CLK at time t4, when the CDS signal OUT2 is inverted to a low level, and latches the count value from time t3 to time t4 as data in response to the turn-on of the hold signal HOLD. As a result, a count value corresponding to the voltage magnitude of the reset voltage signal may be stored. The hold signal HOLD may be provided by the timing controller 130 of FIG. 2.

[0081] 6 illustrates that the counting clock signal CNT_CLK is activated to toggle from time t3 to time t4, but in some embodiments, the counting clock signal CNT_CLK may be activated to toggle earlier and maintained until time t5, in which case only the counting operation of the counter 153_1 with respect to the counting clock signal CNT_CLK may be performed from time t3 to time t4.

[0082] The first decision point DP1 at which the counting operation of the counter 153_1 for the voltage magnitude of the reset voltage signal of the pixel signal PXS is stopped is the time point at which the input signal Vf becomes equal to the common level voltage VCM.

[0083] In order to count the voltage magnitude of the pixel voltage signal of the pixel signal PXS between time t5 and time t6, if the counter 153_1 is an up / down counter, the counting inversion signal RVS_CNT can be inverted and provided to the counter 153_1 to perform up-counting.

[0084] The input signal Vf, which reflects the offset of the pixel voltage signal reduced by the ramp signal RAMP at time t5, may reflect the increase of the ramp signal RAMP from time t6. The CDS signal OUT2 of the amplifier 152_2 maintains a high level until time t7 when the input signal Vf becomes equal to the second decision point DP2, and then inverts to a low level at time t7.

[0085] The counter 153_1 may count the counting clock signal CNT_CLK from time t6 to time t7 when the polarity of the CDS signal OUT2 of the amplifier 152_2 is inverted to a low level. If the counter 153_1 is an up / down counter, the counter 153_1 may up-count the counting clock signal CNT_CLK from time t6 to time t7. The counter 153_1 may stop counting the counting clock signal CNT_CLK at time t7 when the CDS signal OUT2 is inverted to a low level and latch the count value up to that time as data. As a result, a count value corresponding to the voltage magnitude of the pixel voltage signal may be stored.

[0086] The counter 153_1 can output the result of calculating a count value corresponding to the voltage size of the reset voltage signal and a count value corresponding to the voltage size of the pixel voltage signal as digital signal pixel data PXD.

[0087] The second decision point DP2, at which the counter 153_1 stops counting the voltage magnitude of the pixel voltage signal of the pixel signal PXS, is the point at which the input signal Vf becomes equal to the common level voltage VCM. That is, the voltage magnitudes of the pixel voltage signal and the reset voltage signal are all determined by comparing the magnitude of the input signal Vf with the magnitude of the common level voltage VCM. In summary, the decision points DP1 and DP2 of the reset voltage signal and the pixel voltage signal of the pixel signal PXS can be maintained at the same voltage level, the common level voltage VCM. Therefore, the magnitudes of the reset voltage signal and the pixel voltage signal can all be counted by comparing them with the same voltage level, which simplifies the structure and operation of the counter 153_1.

[0088] FIG. 7A is a diagram conceptually illustrating a signal swing of an ADC according to the embodiment of FIG. 4. The input signal Vf of FIG. 7A may correspond to the input signal Vf of the ADC 150 according to the embodiment of FIG. 4. FIG. 7B shows simulation results of pixel swing of an image sensor to which the ADC 150 according to the embodiment of FIG. 4 is applied in different temperature environments and with various power supply voltages. FIG. 7B shows simulation results assuming that C1 and C2 have the same capacitance. The pixel swing of the ADC 150 will be described with reference to FIGS. 4, 7A, and 7B. FIGS. 7A and 7B assume that the ramp signal RAMP input to the input circuit 151 of the ADC 150 according to the embodiment of FIG. 4 is an upward-sloping ramp signal with a single slope that increases at a constant gradient. However, a downward-sloping ramp signal with a single slope that decreases at a constant gradient may also be applied in a similar manner.

[0089] FIG. 7A illustrates a first input signal DARK based on an optical signal input to an image sensor in a dark environment and a second input signal BRIGHT based on an optical signal input to an image sensor in a bright environment.

[0090] The reset voltage signals of the first input signal DARK and the second input signal BRIGHT may be counted between time t1 and time t2, the pixel voltage signals of the first input signal DARK may be counted between time t3 and time t4, and the pixel voltage signals of the second input signal BRIGHT may be counted between time t3 and time t5.

[0091] Referring to FIG. 7A, this figure illustrates a signal swing SWING, which is the voltage level difference of the input signal Vf corresponding to each pixel voltage signal of the first input signal DARK and the second input signal BRIGHT.

[0092] The 5T-based OTA ADC of the related art has a much larger number of load transistors between the power supply voltage node and the output terminal, and between the output terminal and the power supply ground node, than the ADC 150 according to an embodiment of the present invention. Therefore, when a power supply voltage of 1V is used for the power supply voltage node, the operable pixel swing of the 5T-based OTA ADC of the related art has been experimentally confirmed to be approximately 250mV. As a result, within the pixel swing range, the signal swing range of the 5T-based OTA ADC of the related art may be further reduced. Therefore, when a low power supply voltage is used as a driving voltage in a low-power environment, the pixel swing range of the first input signal DARK and the second input signal BRIGHT in the 5T-based OTA ADC of the related art is such that a high bit resolution of the image signal cannot be achieved.

[0093] In contrast, the ADC 150 according to an embodiment of the present invention has a smaller number of load transistors between the output terminal and the power supply voltage node and the power supply ground node, thereby ensuring a large headroom. Therefore, even when a low power supply voltage is used as a driving voltage in a low-power environment, the ADC 150 according to an embodiment of the present invention has a large pixel swing range of the first input signal DARK and the second input signal BRIGHT, resulting in a wide signal swing range and therefore ensuring a high bit resolution of the image signal.

[0094] 7B shows the results of simulations performed on ADC 150 according to an embodiment of the present invention at various process corners at very low temperatures (e.g., -55°C), room temperatures (e.g., 25°C), and high temperatures (e.g., 105°C) with various power supply voltages. Referring to FIG. 7B, it can be seen that the narrowest range of pixel swing for ADC 150 according to an embodiment of the present invention is 500mV or more, even when a power supply voltage of 0.85V is applied in the simulations for each environment. Therefore, even when a low power supply voltage is used as the driving voltage in a low-power environment, ADC 150 according to an embodiment of the present invention has a high ratio of pixel swing to the low power supply voltage, ensuring high bit resolution of the image signal.

[0095] FIG. 8 is a diagram illustrating an ADC according to another embodiment of the present invention. The ADC 150b in FIG. 8 may correspond to the ADC 150 in FIGS. 1 and 2. The ADC 150b according to another embodiment of the present invention will be described with reference to FIG. 8. Detailed descriptions of portions overlapping with the description with reference to FIG. 4 will be omitted. The embodiment described with reference to FIG. 8 will be described assuming that the ADCs 150b are arranged for each column line and operate in parallel for each column line. However, the embodiment described with reference to FIG. 8 is not limited to the ADCs 150b being arranged for each column line. That is, the ADCs 150b may be arranged for each pixel or for each pixel group, as in the embodiments described with reference to FIGS. 10 to 12 below. In this case, the ADCs 150b may operate in parallel for each pixel or for each pixel group.

[0096] 8, the ADC 150b may include an input circuit 151, an inverter 152_1b, an amplifier (AMP) 152_2, and a counter (CNT) 153_1. The input circuit 151, the inverter 152_1b, the amplifier 152_2, and the counter 153_1 shown in FIG. 8 may be arranged for each column line.

[0097] The input circuit 151 may include a first capacitor C1 for sampling each of the reset voltage signal and the pixel voltage signal of the analog signal components output from the pixel PX, and a second capacitor C2 provided with a ramp signal RAMP.

[0098] The amount of voltage change of the ramp signal RAMP at the input node IN is reflected in the pixel signal PXS and can be input to the inverter 152_1b as the input signal Vf.

[0099] The inverter 152_1b according to the embodiment of the present invention may include a pull-up transistor PUT, a pull-down transistor PDT, an auto-zero transistor AZT, a bias transistor BT, and a plurality of pass transistors PT1 and PT2.

[0100] The pull-up transistor PUT and the pull-down transistor PDT may be different types of transistors connected in series between a power supply voltage node VDD and a power supply ground node GND, with their gate terminals commonly connected to an input node IN. The inverter 152_1b receives an input signal Vf at its input node IN and inverts the input signal Vf to output an output signal OUT1 at its output node OUT. The input node IN and the output node OUT of the inverter 152_1b may be connected to each other through an auto-zero transistor AZT.

[0101] The output signal OUT1 of the inverter 152_1b is input to the amplifier 152_2, which amplifies the output signal OUT1 and outputs the CDS signal OUT2. The counter 153_1 counts the level of the input signal Vf based on the CDS signal OUT2 and outputs the counted information as pixel data PXD, which is a digital signal.

[0102] Unlike the embodiment described with reference to FIG. 4, the inverter 152_1b of the ADC 150b according to the present embodiment may include a plurality of pass transistors PT1 and PT2.

[0103] The pass transistors PT1 and PT2 may be implemented using different types of transistors and may be connected in parallel between a power supply voltage node VDD and the bias transistor BT. That is, one terminal of the pass transistors PT1 and PT2 may be connected to the power supply voltage node VDD, and the other terminal may be connected to the drain terminal of the bias transistor BT. The gate terminals of the pass transistors PT1 and PT2 may be connected to the input node IN and controlled by an input signal Vf input to the ADC 150b.

[0104] When the level of the input signal Vf changes to a different level, the pull-up transistor PUT and the pull-down transistor PDT can transition from a turn-on state to a turn-off state, or can simultaneously transition from a turn-off state to a turn-on state. Similarly, with the same input signal Vf, the first pass transistor PT1 can transition to the same state as the pull-up transistor PUT, and the second pass transistor PT2 can transition to the same state as the pull-down transistor PDT. Therefore, when the states of the pull-up transistor PUT and the pull-down transistor PDT transition in response to the input signal Vf, one of the first pass transistor PT1 and the second pass transistor PT2 can simultaneously transition to the turn-on state. That is, a current path can always exist between the power supply voltage node VDD and the bias transistor BT. As a result, the current path through the first pass transistor PT1 or the second pass transistor PT2 prevents power fluctuations due to simultaneous state transitions of the pull-up transistor PUT and the pull-down transistor PDT. Therefore, the current path through the first pass transistor PT1 or the second pass transistor PT2 prevents instantaneous fluctuations in the magnitude of the bias current IB flowing through the bias transistor BT due to power fluctuations. The current path through the first pass transistor PT1 or the second pass transistor PT2 can stably maintain the magnitude of the bias current IB flowing through the bias transistor BT. Furthermore, the bias current IB of the bias transistor BT can also reduce the influence of the power supply voltage node VDD on the ADC 150b. The bias current IB can be maintained substantially constant during a first interval from when the output signal OUT1 of the inverter 152_1b starts to change until it reaches a decision point, and during a second interval from when the output signal OUT1 reaches the decision point until it is inverted. In addition, a stable operating voltage range for the pixel swing can be ensured by using a small number of load transistors in the ADC 150b.

[0105] The ADC 150b described with reference to Fig. 8 can be implemented with fewer transistors than the ADCs of the related art, yet can operate stably. Therefore, unlike the embodiment of Fig. 8 in which the ADCs are arranged by column line to reduce area, the ADCs 150b may be arranged by pixel and operate in parallel by pixel.

[0106] 9 is a block diagram of an image sensor 100a according to an embodiment of the present invention, and detailed descriptions of parts that overlap with those previously described will be omitted.

[0107] The image sensor 100a may include a first chip (or first die) 10a and a second chip (or second die) 20a that are stacked.

[0108] The first chip 10a may be stacked on the second chip 20a in a direction DR3 perpendicular to the plane of the substrate. The first chip 10a and the second chip 20a may be electrically connected to each other. For example, the first chip 10a and the second chip 20a may transmit pixel signals or control signals through through-silicon vias (TSVs) between pads located in the chip peripheral regions. The first chip 10a and the second chip 20a may also be electrically connected to each other through in-pixel contacts IN_CT within the pixels PXc. The in-pixel contacts may be, for example, Cu-to-Cu (C2C) bonding contacts. The pixel signals (or pixel data) of the first chip 10a may be transmitted to a readout circuit (or image signal processing logic) of the second chip 20a.

[0109] The pixel array may include a plurality of pixels PXc arranged in a matrix. The pixel circuits of the pixels PXc according to the present invention may be driven in a low-power environment. For example, the pixel circuits may be driven by a power supply voltage of approximately 1 V. The pixels PXc of the pixel array may output pixel signals including a reset voltage signal or a pixel voltage signal for the CDS method.

[0110] The second chip 20a may include a readout circuit, a timing controller, logic such as image signal processing logic, and an interface circuit. The readout circuit may include an ADC.

[0111] The second chip 20b according to an embodiment of the present invention may include any one of the ADCs 150 and 150b described above. Alternatively, some of the ADCs 150 and 150b may be disposed on the first chip 10a, and other parts may be disposed on the second chip 20a. When some or all of the ADCs 150 and 150b are disposed on the first chip 10a, some or all of the ADCs 150 and 150b may be disposed within the pixel PXc according to an embodiment. In this case, the pixel PXc may transmit pixel data to the second chip 20a.

[0112] 10 is a block diagram of an image sensor 100b according to another embodiment of the present invention, and detailed descriptions of parts that overlap with those previously described will be omitted.

[0113] The image sensor 100b may include a stacked first chip 10b and a second chip 20b. The first chip 10a and the second chip 20a may be connected to each other through a wafer bonding process using pixel-level C2C interconnections. The first chip 10a and the second chip 20a may be electrically connected not only through in-pixel contacts within the pixels PXd but also through a C2C (Cu-to-Cu) array located in the chip peripheral region. Control signals for controlling the pixel circuits may be transmitted through the C2C array. Pixel signals (or pixel data) of the first chip 10a may be transmitted to a readout circuit (or image signal processing logic) of the second chip 20a through the in-pixel contacts.

[0114] The second chip 20b according to the embodiment of the present invention may include any one of the ADCs 150 and 150b described above.

[0115] In one embodiment, the ADCs 150 and 150b may be disposed on the second chip 20b. In this case, the ADCs 150 and 150b may operate on a column line basis, or may be C2C interconnected with the pixel PXd at the pixel level and operate in parallel on a pixel basis, depending on the embodiment.

[0116] In another embodiment, some of the ADCs 150 and 150b may be disposed on the first chip 10b, and other parts may be disposed on the second chip 20b. Alternatively, all of the ADCs 150 and 150b may be disposed on the first chip 10b. When some or all of the ADCs 150 and 150b are disposed on the first chip 10b, some or all of the ADCs 150 and 150b may be disposed within the pixel PXd, depending on the embodiment. Some circuits of the ADCs 150 and 150b disposed within the pixel PXd may be electrically connected to other circuits of the ADCs 150 and 150b disposed on the second chip 20b via pixel-level C2C interconnections. Additionally, the ADCs 150 and 150b may operate in parallel for each pixel.

[0117] In one embodiment, the ADCs 150 and 150b are arranged for each column line as in the embodiment of FIG. 2, and can perform digital conversion of the outputs of the column lines in parallel.

[0118] In another embodiment, the ADCs 150 and 150b may operate on a pixel-by-pixel basis rather than on a column-by-column basis. That is, the ADCs 150 and 150b may be dedicated to each pixel or pixel group and operate in parallel with each other. Therefore, the output of each pixel PXd may be digitally converted in parallel. In this case, some or all of the ADCs 150 and 150b may be located on the first chip 10b, or some or all of the ADCs 150 and 150b may be located on the second chip 20b.

[0119] 11 is a block diagram of an image sensor 100c according to another embodiment of the present invention, and detailed descriptions of parts that overlap with those previously described will be omitted.

[0120] 11, the image sensor 100c may further include a third chip 30c in addition to the first chip 10c and the second chip 20c. The third chip 30c, the second chip 20c, and the first chip 10c may be stacked in order in a direction D3 perpendicular to the plane of the substrate. The third chip 30c may include a memory device. For example, the third chip 30c may include a volatile memory device such as a DRAM or an SRAM. The third chip 30c may receive signals from the first chip 10c and the second chip 20c and process the signals through the memory device.

[0121] In one embodiment, the ADCs 150 and 150b may be disposed on the second chip 20c. In this case, the ADCs 150 and 150b may operate on a column line basis, or may be C2C interconnected with the pixel PXd at the pixel level and operate in parallel on a pixel basis, depending on the embodiment.

[0122] In another embodiment, some or all of the ADCs 150, 150b may be disposed on the first chip 10c. When some of the ADCs 150, 150b are disposed on the first chip 10c, other parts may be disposed on the second chip 20c. When some or all of the ADCs 150, 150b are disposed on the first chip 10c, some or all of the ADCs 150, 150b may be disposed inside the pixel PXe, depending on the embodiment. When some of the ADCs 150, 150b are disposed inside the pixel PXe of the first chip 10c, some of the ADCs 150, 150b disposed inside the pixel PXe may be electrically connected to other parts of the ADCs 150, 150b disposed on the second chip 20c via pixel-level C2C interconnections. In addition, the ADCs 150, 150b may operate in parallel for each pixel.

[0123] In one embodiment, the ADCs 150 and 150b are arranged for each column line as in the embodiment of FIG. 2, and can perform digital conversion of the outputs of the column lines in parallel.

[0124] In another embodiment, the ADCs 150 and 150b may operate on a pixel-by-pixel basis rather than on a column-by-column basis. That is, the ADCs 150 and 150b may be dedicated to each pixel or pixel group and may operate in parallel with each other. Therefore, the output of each pixel PXe may be digitally converted in parallel.

[0125] Alternatively, the ADCs 150 and 150b may be partially separated and arranged on multiple chips, and electrically connected to each other. The number of chips is not particularly limited. For example, the ADCs 150 and 150b may be separated and arranged on multiple chips, and electrically connected to each other, in chips consisting of two chips as in the embodiment of FIG. 10, three chips as in the embodiment of FIG. 11, or more. The separated circuits of the ADCs 150 and 150b may be electrically connected to each other not only through in-pixel C2C interconnections within the pixels, but also through C2C arrays located in the peripheral regions of the chips.

[0126] Depending on the embodiment, the node separating the ADCs 150 and 150b may be determined in various ways. For example, the input circuit 151 of the ADCs 150 and 150b described above may be disposed on the first chip 10a of FIG. 9, the first chip 10b of FIG. 10, and the first chip 10c of FIG. 11. The converters 152_1 and 152_1b, the amplifier 152_2, and the counter 153_1 of the ADCs 150 and 150b may be disposed on the second chip 20a of FIG. 9, the second chip 20b of FIG. 10, and the second chip 20c of FIG. 11. Alternatively, either the pull-up transistor PUT or the pull-down transistor PDT of the input circuit 151 and the converters 152_1 and 152_1b may be disposed on the first chip 10a of FIG. 9, the first chip 10b of FIG. 10, and the first chip 10c of FIG. 11. FIG. 12 is a block diagram of an image sensor 100d according to an embodiment of the present invention. Detailed explanations of parts that overlap with those previously explained will be omitted.

[0127] 12, the image sensor 100d may include a first chip 10d and a second chip 20d. The first chip 10d and the second chip 20d may be stacked in order in a direction perpendicular to the plane of the substrate.

[0128] The first chip 10d and the second chip 20d can be connected to each other through a wafer bonding process using pixel-level C2C interconnections. The first chip 10d and the second chip 20d can be electrically connected not only through in-pixel contacts within the pixels PXf but also through C2C (Cu-to-Cu) arrays located in the chip peripheral regions.

[0129] According to an embodiment of the present invention, each pixel PXf of the first chip 10d may include one of the ADCs 150 and 150b described above. Alternatively, each pixel PXf may include some circuitry of the ADCs 150 and 150b. For example, the input circuit 151 of the ADCs 150 and 150b described above may be disposed within each pixel PXe of the first chip 10d, and the converters, amplifiers, and counters of the ADCs 150 and 150b may be disposed on the second chip 20d. Alternatively, the input circuit 151 and either the pull-up transistor PUT or the pull-down transistor PDT of the converter may be disposed within each pixel PXe of the first chip 10d. That is, one of the ADCs 150 and 150b may be dedicated to each pixel PXe or each pixel group composed of adjacent pixels. Therefore, depending on the embodiment, the ADCs 150 and 150b of each pixel PXf or each pixel group may perform analog-to-digital conversion in parallel for each pixel or each pixel group.

[0130] 13 is a block diagram of an electronic device according to an embodiment of the present invention, and detailed descriptions of parts that overlap with those previously described will be omitted.

[0131] The electronic device 1000b may include an imaging unit 1100, an image sensor 1200, and a processor 1300. The electronic device 1000b may perform autofocusing based on phase data provided from the image sensor 1200 to the processor 1300.

[0132] The processor 1300 can control the overall operation of the electronic device 1000b. The processor 1300 can provide a control signal to the lens driver 1120 to control the position of the lens 1110. As a result, the focal length can be controlled.

[0133] The imaging unit 1100 may include, as components that receive light, a lens 1110 and a lens driving unit 1120. The lens 1110 may include multiple lenses.

[0134] The lens driver 1120 can move the lens 1110 in a direction in which the distance from the object S increases or decreases based on a control signal from the processor 1300 .

[0135] The image sensor 1200 may generate image data and phase data based on incident light. The image sensor 1200 may include a pixel array 1210, a timing controller 1220, an ADC 1230, and an image signal processor 1240.

[0136] A pixel of pixel array 1210 can include at least one photoelectric conversion element.

[0137] According to an embodiment of the present invention, the ADC 1230 may be an inverter-based ADC. For example, the ADC 1230 may be any one of the ADCs 150 and 150b described above. Therefore, the electronic device 1000b according to an embodiment of the present invention may stably convert pixel signals into pixel data, which is a digital signal, even in a low-power environment.

[0138] The processor 1300 may perform a disparity calculation using the phase data and may provide a control signal based on the phase difference calculation result to the lens driver 1120 to move the position of the lens 1110.

[0139] The processor 1300 may provide an operation mode control signal INFO_MD to the timing controller 1220. The timing controller 1220 may control the operation of the pixel array 1210 based on the operation mode control signal INFO_MD.

[0140] 14 is a block diagram of an application processor 1300b according to an embodiment of the present invention. Detailed descriptions of parts that overlap with those previously described will be omitted.

[0141] The application processor 1300b may include an image signal processing unit 1310. The image signal processing unit 1310 may include a plurality of image signal processing units ISP1, ISP2, and ISP3, a camera module control unit 1314, and a camera interface 1315.

[0142] The camera module controller 1314 may transmit control signals CSa, CSb, and CSc to multiple camera modules based on a mode signal. While Figure 14 illustrates transmission of control signals CSa, CSb, and CSc to three camera modules, the embodiment is not limited thereto. Depending on the embodiment, the camera module controller 1314 may transmit control signals to two camera modules or to four or more camera modules.

[0143] According to an embodiment of the present invention, the image signals ISa, ISb, and ISc may be based on signals digitally converted by the ADCs of the multiple cameras. The ADCs of the multiple cameras may be inverter-based ADCs. The inverter-based ADC may have a bias transistor connected in series between the pull-down transistor PDT and a power supply ground node.

[0144] Image signals ISa, ISb, and ISc may be stored in the external memory 1400 through the camera interface 1315 from multiple cameras. Image signal processors ISP1 and ISP2 may process the image signals ISa, ISb, and ISc stored in the external memory 1400 and display them on a display or perform autofocusing. The image signals ISa, ISb, and ISc may include image data and phase data. The image signals ISa, ISb, and ISc stored in the external memory 1400 may be encoded image signals. The image signal processors ISP1 and ISP2 may read and decode the encoded image signals from the external memory 1400 and display image data generated based on the decoded image signals.

[0145] Meanwhile, the above content is a specific embodiment for carrying out the present invention. In addition to the above-described embodiments, the present invention may also include embodiments that can be simply modified or easily changed. Furthermore, the present invention may also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the following claims as well as equivalents to the claims of the present invention. [Explanation of symbols]

[0146] 100, 100a, 100b, 100c, 100d image sensors 110 pixel array 120 Low Driver 130 Timing Controller 140 Ramp Signal Generator 150, 150b ADC 160 output buffers 200 Image Signal Processor

Claims

1. a pixel array including a plurality of active pixels; an analog-to-digital converter (ADC) that converts pixel signals of the plurality of active pixels into digital signals; The ADC comprises: an input circuit that receives a ramp signal and the pixel signal and outputs a first signal in which the ramp signal is reflected in the pixel signal; an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply voltage node and a power supply ground node, the inverter inverting the first signal input to an input node and outputting a second signal at an output node; a code generation circuit that outputs a digital signal based on the second signal; The inverter is The image sensor includes at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and the power supply ground node, the bias transistor being controlled by a bias voltage.

2. 2. The image sensor of claim 1, wherein a drain terminal of the bias transistor is coupled to a source terminal of the pull-down transistor, and a drain terminal of the bias transistor is electrically coupled to the power ground node.

3. The image sensor of claim 1 , wherein the power supply voltage node is configured to provide a power supply of 1 V or less.

4. a size of each of the reset voltage signal of the pixel signal and the pixel voltage signal of the pixel signal is determined based on a comparison result of the first signal with a reference voltage level identical to the first signal; The image sensor of claim 1 , wherein the ramp signal is applied to each of the reset voltage signal and the pixel voltage signal.

5. The input circuit a first capacitor that samples the pixel signal and is coupled to the input node of the inverter; 2. The image sensor of claim 1, further comprising: a second capacitor transmitting a voltage change amount of the ramp signal to the input node of the inverter.

6. 2. The image sensor of claim 1, wherein the inverter includes an auto-zero transistor having one of a source terminal and a drain terminal connected to one of the input node and the output node, and controlled by an auto-zero signal input to a gate terminal of the auto-zero transistor.

7. the first transistor and the second transistor are connected in parallel between the power supply voltage node and the drain terminal of the bias transistor; The image sensor of claim 1 , wherein the first transistor and the second transistor are configured to be turned on in different time periods.

8. The image sensor of claim 7 , wherein the first transistor and the second transistor are different types of transistors and are configured to be controlled by the same control signal.

9. The image sensor of claim 8 , wherein the first transistor and the second transistor are configured to be controlled by the first signal.

10. The first signal includes a first section from when the first signal starts to change until it reaches a decision point, and a second section from when the first signal reaches the decision point until the first signal is inverted, The image sensor of claim 7 , wherein the first transistor and the second transistor are configured so that a magnitude of a current flowing through the bias transistor is constant in the first section and the second section.

11. The image sensor according to claim 1 , wherein an inverter operating voltage range is set to be equal to or greater than 50% of the driving voltage provided from the power supply voltage node.

12. the pixel array is disposed on a first die; 2. The image sensor of claim 1, wherein at least a portion of the ADC is disposed on the first die, and a remaining portion of the ADC is disposed on a second die that is electrically connected to the first die and vertically stacked.

13. The image sensor of claim 12 , wherein the input circuit is located on the first die, and the inverter and the code generation circuit are located on the second die.

14. 13. The image sensor of claim 12, wherein one of the pull-up transistor and the pull-down transistor in the inverter and the input circuit are disposed on the first die, and other circuits of the inverter and the code generation circuit are disposed on the second die.

15. In an image sensor containing multiple pixels, Each of the plurality of pixels is a photodetector including a photoelectric conversion element; an input circuit that receives a ramp signal and pixel signals of the plurality of pixels and outputs a first signal in which the pixel signals are reflected in the ramp signal; an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply voltage terminal and a power supply ground terminal, the inverter inverting the first signal input to an input node and outputting a second signal to an output node; a code generation circuit that outputs a digital signal based on the second signal; The inverter is The image sensor includes at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and a power ground node, the bias transistor being controlled by a bias voltage.

16. a pixel array including a plurality of active pixels; an ADC (analog-to-digital converter) circuit that converts pixel signals of the plurality of active pixels into digital signals; The ADC comprises: an input circuit that receives a ramp signal and the pixel signal and outputs a first signal in which the ramp signal is reflected in the pixel signal; an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply voltage node and a power supply ground node, the inverter inverting the first signal input to an input node and outputting a second signal at an output node; a code generation circuit that outputs a digital signal based on the second signal; The inverter is 1. An image sensor comprising: at least one starving transistor configured to limit a magnitude of a current flowing through at least one of the pull-up transistor and the pull-down transistor during an inverter transition operation.

17. an inverter including a P-type pull-up transistor and an N-type pull-down transistor connected in series between a power supply voltage node and a power supply ground node through an output node, the P-type pull-up transistor and the N-type pull-down transistor having gate electrodes connected to the input node, the inverter inverting a first signal input to the input node and outputting a second signal to the output node; a code generation circuit that outputs a digital signal based on the second signal; The inverter is An analog-to-digital converter (ADC) includes at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and the power supply ground node, the bias transistor being controlled by a bias voltage.

18. the first transistor and the second transistor are connected in parallel between the power supply voltage node and the drain terminal of the bias transistor; The ADC of claim 17 , wherein the first transistor and the second transistor are configured to be turned on at different time intervals by the same control signal.

19. 20. The ADC of claim 17, wherein the bias transistor is configured to operate as a dependent current source.

20. 20. The ADC of claim 17, further comprising an auto-zero transistor coupling the input node and the output node.

Images