Wiring board

Abstract

To provide a new connection method for connecting conductive layers on a core substrate.SOLUTION: A wiring board comprises: a core substrate having a cavity; a build-up layer stacked on front and back surfaces of the core substrate and including a conductive layer; a sub-substrate accommodated in the cavity and in which a plurality of conductive layers and a plurality of insulating layers are alternately arranged in a direction orthogonal to a thickness direction of the core substrate; and a plurality of linear conductors included in the sub-substrate and connected to the conductive layers of the build-up layer. An interval between the linear conductors is smaller than an interval between the through-hole conductors.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board having a core substrate. [Background technology]

[0002] BACKGROUND ART Known conventional wiring boards include those having conductors that connect conductive layers on the front and back of a core substrate (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-20516 A (paragraph

[0011] , Figure 1D) Summary of the Invention [Problem to be solved by the invention]

[0004] In this type of wiring board, it is necessary to suppress variations in the thickness of the conductive layer on the core substrate, even if the core substrate contains areas where the conductors connecting the front and back of the core substrate are present in high density and areas where they are present only in low density. [Means for solving the problem]

[0005] The wiring board of the present disclosure is a wiring board comprising a core substrate having a cavity, a plurality of through-hole conductors penetrating the core substrate, a build-up layer laminated on the front and back of the core substrate and including a conductive layer, a sub-substrate housed in the cavity and having a plurality of conductive layers and a plurality of insulating layers arranged alternately in a direction perpendicular to the thickness direction of the core substrate, and a plurality of straight conductors included in the sub-substrate and connected to the conductive layers of the build-up layer, wherein the spacing between the straight conductors is smaller than the spacing between the through-hole conductors. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a cross-sectional view of a wiring board according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a perspective view of the sub-board. [Figure 3] FIG. 3A is a cross-sectional view showing a method for manufacturing a sub-substrate, and FIG. 3B is a cross-sectional view showing a method for manufacturing a sub-substrate. [Figure 4] FIG. 4A is a cross-sectional view showing a method for manufacturing a sub-substrate, and FIG. 4B is a cross-sectional view showing a method for manufacturing a sub-substrate. [Figure 5] FIG. 5A is a cross-sectional view showing a method for manufacturing a wiring board, FIG. 5B is a cross-sectional view showing a method for manufacturing a wiring board, and FIG. 5C is a cross-sectional view showing a method for manufacturing a wiring board. [Figure 6] 6A is a cross-sectional view showing a method for manufacturing a wiring board, FIG. 6B is a cross-sectional view showing a method for manufacturing a wiring board, and FIG. 6C is a cross-sectional view showing a method for manufacturing a wiring board. [Figure 7] 7A is a cross-sectional view showing a method for manufacturing a wiring board, FIG. 7B is a cross-sectional view showing a method for manufacturing a wiring board, and FIG. 7C is a cross-sectional view showing a method for manufacturing a wiring board. [Figure 8] 8A is a cross-sectional view showing a method for manufacturing a wiring board, FIG. 8B is a cross-sectional view showing a method for manufacturing a wiring board, and FIG. 8C is a cross-sectional view showing a method for manufacturing a wiring board. [Figure 9] FIG. 9A is a cross-sectional view showing a method for manufacturing a wiring board, and FIG. 9B is a cross-sectional view showing a method for manufacturing a wiring board. DETAILED DESCRIPTION OF THE INVENTION

[0007] [First embodiment] Hereinafter, a wiring board 10 according to a first embodiment will be described with reference to Figures 1 to 9. As shown in Figure 1, wiring board 10 has a structure in which core substrate 11 has build-up portions 12 on the front and back sides thereof.

[0008] The buildup section 12 has interlayer insulating layers 31 and conductive layers 30 laminated on the front and back of the core substrate 11. Each interlayer insulating layer 31 does not have a core material and is formed of an insulating film for buildup substrates made of, for example, a thermosetting resin containing an inorganic filler. Note that the buildup section 12 may have multiple interlayer insulating layers 31 and multiple conductive layers 30 arranged alternately.

[0009] Each conductive layer 30 is formed in a predetermined pattern on each interlayer insulating layer 31. The conductive layers 30 are covered with a solder resist layer 32. The portions of the conductive layers 30 exposed from openings 32A formed in the solder resist layer 32 form pads 30A, and metal posts 20A for mounting electronic components (not shown) are formed on the pads 30A.

[0010] 1, core substrate 11 has insulating base material 13 and core conductive layers 14 formed on both the front and back surfaces of insulating base material 13. Insulating base material 13 is made of, for example, prepreg (a B-stage resin sheet made by impregnating a core material made of fibers such as glass cloth with resin).

[0011] Core conductive layer 14 has copper foil 14C on insulating base material 13, first plating film 14A on the copper foil, and second plating film 14B on first plating film 14A, and is partially or entirely an electric circuit. Furthermore, the electric circuit of core conductive layer 14 is connected to conductive layer 30 by a plurality of first via conductors 24 that penetrate interlayer insulating layer 31 laminated directly on core substrate 11. First via conductors 24 are formed by filling plated metal inside via holes 24H having tapered inner surfaces.

[0012] The core conductive layers 14 on both sides of the core substrate 11 are connected to each other by a plurality of through-hole conductors 25 that penetrate the insulating base material 13, and the core conductive layers 14 include through-hole lands 14T that extend laterally from the ends of each through-hole conductor 25. Specifically, a plurality of cylindrical through-holes 15 are formed in the insulating base material 13. On the inner surfaces of these through-holes 15, through-hole conductors 25 are formed in the form of a film that is continuous with the first plating film 14A. The insides of the through-hole conductors 25 are filled with filling resin 18, and both ends are closed with the second plating film 14B.

[0013] A cavity 19 is formed through the core substrate 11 of the wiring substrate 10 of this embodiment, and a sub-substrate 50 is housed in the cavity 19. The cavity 19 is formed, for example, in a rectangular parallelepiped shape, and the sub-substrate 50 has a planar shape that is one size smaller than the cavity 19. Note that the cavity 19 does not have to be a rectangular parallelepiped space, and may be tapered so that its width narrows toward either the front or back of the core substrate 11.

[0014] The gap between the side surface of the sub-substrate 50 and the inner surface of the cavity 19 is filled with the insulating resin of the interlayer insulating layer 31 .

[0015] Next, the sub-substrate 50 will be described. FIG. 2 shows a perspective view of the sub-substrate 50 alone. Similar to the wiring substrate 10, the sub-substrate 50 has a structure including build-up portions 52 on the front and back of a core substrate 51. The core substrate 51 has an insulating base material 53 and core conductive layers 54 formed on both the front and back of the core substrate 51, and the build-up portion 52 has an interlayer insulating layer 61 and a conductive layer 60. Note that in the sub-substrate 50, the thicknesses of the insulating base material 53 and the interlayer insulating layer 61 may be set so that the intervals between the core conductive layers 54 and the conductive layers 60 are approximately equal.

[0016] A plurality of linear conductors 54A, 60A are arranged in parallel on the core conductive layer 54 and the conductive layer 60. Each of the linear conductors 54A, 60A extends over the entire length of one side of the sub-substrate 50, and both end faces of the linear conductors 54A, 60A are exposed on the surface of the sub-substrate 50.

[0017] As shown in FIG. 1 , sub-substrate 50 is accommodated in cavity 19 with straight conductors 54A and 60A parallel to through-hole conductors 25, i.e., rotated 90 degrees. In this state, the top and bottom surfaces of sub-substrate 50 and the top and bottom surfaces of conductive layer 14 of core substrate 11 are flush with each other in the stacking direction of wiring board 10. As a result, straight conductors 54A and 60A of sub-substrate 50 penetrate core substrate 11, with their end faces exposed on both sides. These end faces are connected to conductive layer 30 by multiple second via conductors 26, which are arranged in a matrix when viewed from the stacking direction and penetrate interlayer insulating layer 31 stacked directly above core substrate 11. The end faces of each straight conductor 54A and 60A are larger than the bottom ends of second via conductors 26, and the entire bottom ends of second via conductors 26 are connected to the end faces of straight conductors 54A and 60A.

[0018] Furthermore, in the wiring board 10, the distance between the straight conductors 54A, 60A is narrower than the distance between the through-hole conductors 25. For example, the straight conductors 54A, 60A are arranged at equal pitches so that the distance between their centers is 40 μm to 60 μm, and the shortest distance between the through-hole conductors 25 is approximately 75 μm.

[0019] The method for manufacturing the wiring board 10 of this embodiment is, for example, as follows: First, the method for manufacturing the sub-board 50 will be described. (1) A copper clad laminate 53D is prepared as shown in Fig. 3A. The copper clad laminate 53D is made by laminating copper foil 14C on both the front and rear surfaces of an insulating base material 53.

[0020] (2) As shown in FIG. 3B, the front and back surfaces of the copper-clad laminate 53D are subjected to chemical plating and electrolytic plating, and core conductive layers 54 are laminated.

[0021] (3) An etching resist is formed on the core conductive layer 54. Next, the copper foil and core conductive layer 54 exposed from the etching resist are removed by etching, and the etching resist is then removed. As a result, the core conductive layer 54 has a plurality of linear conductors 54A, and the core substrate 51 is formed (see FIG. 3C).

[0022] (4) An insulating resin film is laminated on the core conductive layer 54 as the interlayer insulating layer 61 and hot-pressed. Next, chemical plating and electrolytic plating are performed on the interlayer insulating layer 61 to form the conductive layer 60 (see FIG. 4A).

[0023] The interlayer insulating layer 61 may be formed by laminating an insulating film, or by applying a paste-like thermosetting resin and then curing it.

[0024] (5) In the same manner as in step (3), after the linear conductors 60A are formed on the conductive layer 60, an interlayer insulating layer 61 is laminated on the conductive layer 60 (see FIG. 4B).

[0025] The above is the method for manufacturing the sub-substrate 50. Next, a method for manufacturing the parts of the wiring substrate 10 excluding the sub-substrate 50 will be described.

[0026] (1) A copper-clad laminate 13D is prepared as the insulating base material 13. The copper-clad laminate 13D is formed by laminating copper foil (not shown) on both the front and back surfaces of the insulating base material 13. Next, a plurality of through holes 15 are formed in the insulating base material 13 by, for example, drilling.

[0027] (2) Chemical plating and electrolytic plating are performed to form a first plating film 14A on the upper surface of the copper-clad laminate, and a cylindrical through-hole conductor 25 is formed inside the through-hole 15 (see FIG. 5A).

[0028] (3) As shown in Fig. 5B, filling resin 18 is filled into through-hole conductor 25. Next, the portion of filling resin 18 that protrudes higher than the surface of first plating film 14A is polished so that filling resin 18 and the surface of first plating film 14A are flush with each other.

[0029] (4) Next, chemical plating and electrolytic plating are performed to form a second plating film 14B on the upper surfaces of the insulating base material 13 and the first plating film 14A and on the end surface of the filling resin 18. Then, an etching resist is formed on the second plating film 14B, and then the copper foil, first plating film 14A, and second plating film 14B exposed from the etching resist are removed, and then the etching resist is removed. This results in the formation of a core substrate 11 having the first plating film 14A and the second plating film 14B as the core conductive layer 14 (see FIG. 5B).

[0030] (5) A cavity 19 is formed through the core substrate 11 using a router or a carbon dioxide laser (see FIG. 5C).

[0031] (6) A tape 90 made of a PET film is attached to one surface of the core substrate 11 so as to close the cavity 19 (see FIG. 6A).

[0032] (7) Sub-substrate 50 is prepared, and sub-substrate 50 is placed in cavity 19 by a mounter (not shown) so that straight conductors 54A and 60A are parallel to through-hole conductors 25 (see FIG. 6B).

[0033] (8) An insulating film for a build-up substrate is laminated as interlayer insulating layer 31 on the side of core substrate 11 opposite the side sealed with tape 90, and then hot-pressed. At this time, part of the melted insulating film fills the gap between the inside of cavity 19 and sub-substrate 50 (see FIG. 6C).

[0034] (9) Tape 90 is removed as shown in Figure 7A. Next, in step (8), an insulating film for a build-up substrate is laminated on the top surface of core substrate 11 with the side on which interlayer insulating layer 31 is laminated facing downward, and is hot-pressed to form interlayer insulating layer 31 (see Figure 7B). Note that even if the molten insulating film does not penetrate between the interior of cavity 19 and sub-substrate 50 in step (8) and a gap remains, the gap will be filled with part of the laminated insulating film in step (9).

[0035] (10) A laser is irradiated onto the interlayer insulating layer 31 on both sides of the core substrate 11, and a plurality of tapered via holes 24H, 26H are formed penetrating the interlayer insulating layer 31 (see FIG. 7C). Of the via holes, those formed on the through-hole conductors 25 are first via holes 24H, and those formed on the straight conductors 54A, 60A are second via holes 26H.

[0036] (11) An electroless plating process is carried out, and a plating resist 33 having a predetermined pattern is formed on the electroless plated film 30A on the interlayer insulating layer 31 (see FIG. 8A).

[0037] (12) An electrolytic plating process is performed, filling the inside of the first via hole 24H and the second via hole 26H with electrolytic plating, forming the first via conductor 24 and the second via conductor 26, and forming an electrolytic plating film 30B on the electroless plating film 30A (see Figure 8B).

[0038] (13) Next, the plating resist 33 is removed, and the remaining electroless plated film 30A and electrolytic plated film 30B form the conductive layer 30 (see FIG. 8C).

[0039] (14) Next, a solder resist layer 32 is laminated on the upper surface of the conductive layer 30, and openings 32A are formed at predetermined positions by laser or photolithography processing. Then, the conductive layer 30 exposed by the openings 32A forms pads 30A (see FIG. 9A).

[0040] (15) Next, by a known semi-additive method, an electroless plating film and an electrolytic plating film are formed on the solder resist layer 32. Next, when the plating resist is peeled off, as shown in FIG. 9B, the electroless plating film and the electrolytic plating film remaining on the solder resist layer 32 form the metal post 20A.

[0041] This completes the description of the wiring board 10 and its manufacturing method. The through-hole conductors are formed by plating the insulating substrate in which the through-holes are formed, but the plating thickness on the insulating substrate differs between areas where the through-hole conductors are densely arranged and areas where they are sparsely arranged, which can result in variations in the thickness of the conductive layer on the core substrate.

[0042] This is because the current density during electrolytic plating is smaller in areas with a larger area to be plated than in areas with a smaller area to be plated, resulting in thinner plating in areas with a larger area to be plated (parts of the conductive layer with a larger number of through-hole conductors) and thicker plating in areas with a smaller area to be plated (parts with a smaller number of through-hole conductors).

[0043] In contrast, in this embodiment, by selectively replacing densely arranged through-hole conductors with straight conductors 54A, 60A that penetrate sub-substrate 50, it becomes less likely that areas will have thin plating thickness, and it is possible to suppress variations in the thickness of core conductive layer 14 on core substrate 11. In other words, high-density connections can be made while maintaining a constant thickness of core conductive layer 14.

[0044] Furthermore, by embedding the sub-substrate 50 inside the cavity 19, it is possible to connect the front and back of the core substrate 11, which makes it possible to make easier and more accurate connections than when the straight conductors 54A, 60A are formed on the core substrate 11 by laser processing or plating processing.

[0045] Furthermore, by configuring the straight conductors 54A, 60A to extend linearly in the thickness direction of the core substrate 11, the conductor patterns on the core conductive layer 54 and conductive layer 60 are simplified, making it easier to form the sub-substrate 50.

[0046] Note that some of the straight conductors 54A, 60A may extend perpendicular to the thickness direction of the core substrate 11. Also, some of the straight conductors 54A, 60A may extend in the thickness direction and some of the straight conductors 54A, 60A may extend perpendicular to the thickness direction.

[0047] Furthermore, since the end faces of the straight conductors 54A, 60A are larger than the lower end of the first via conductor 24 to be connected, slight deviation within the allowable range of the position where the laser is irradiated can be tolerated when forming the via hole 24H, making the connection easier.

[0048] Furthermore, the end face of the sub-substrate 50 and the top surface of the core conductive layer 14 are located on the same plane; in other words, the opening depth of the cavity 19 and the height of the sub-substrate 50 are the same, so the top surfaces of the stacked interlayer insulating layer 31 and conductive layer 30 can be kept flat.

[0049] Furthermore, by filling the interior of through-hole conductor 25 with filling resin 18, it is possible to increase the strength of core substrate 11 in the thickness direction as a whole, compared to when through-hole conductor 25 is hollow.

[0050] [Other embodiments] (1) In the above embodiment, the thickness of the sub-substrate 50 is 1 mm to 2.5 mm, but any thickness may be used as long as the difference with the thickness of the core substrate 11 is within 0.3 mm.

[0051] (2) Furthermore, although the inner surface of cavity 19 and the outer surface of sub-substrate 50 are filled with a portion of interlayer insulating layer 31, they may be filled with sealing resin. In this configuration, sealing resin is filled into cavity 19 up to just before the top surface of core substrate 11 and heated to harden, and then a paste-like thermosetting resin is applied to the top surface of cavity 19 and hardened, or an insulating resin film is laid over it and hot-pressed.

[0052] (3) In the above embodiment, the wiring board 10 is rectangular, but is not limited to this and may be circular or another polygonal shape.

[0053] (4) In the above embodiment, the through-hole conductors 25 are formed only in the core substrate 11, but they may also be formed in the build-up portion 12. Also, instead of the through-hole conductors 25, multiple via conductors that do not form part of the electrical circuit may be formed. With this configuration, it is also possible to suppress the propagation of cracks in the interlayer insulating layer 31.

[0054] (5) The inside of the through-hole conductor 25 may not be filled with filling resin 18 and only a cylindrical plated metal may be provided, or the through-hole 15 may not be filled with plating metal and only a filling resin 18 may be provided in the through-hole conductor 25.

[0055] (6) Although the through-hole 15 is a circular hole, the opening shape may be an oval, a square, or any other polygonal shape.

[0056] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, and also includes parts of the specific examples taken out alone.

[0057] [Explanation of symbols] 10. Wiring board 11 Core board 12 Build-up section 14 Core conductive layer 18 Filling resin 19 Cavity 24,26 Via conductor 25 through-hole conductor 24H, 26H Beer Hall 30 Conductive layer 31 Interlayer insulating layer 50 Sub-board 54A, 60A straight conductor

Claims

1. a core substrate having a cavity; a plurality of through-hole conductors that penetrate the core substrate; build-up layers laminated on the front and back surfaces of the core substrate and including conductive layers; a sub-substrate accommodated in the cavity, the sub-substrate having a plurality of conductive layers and a plurality of insulating layers arranged alternately in a direction perpendicular to the thickness direction of the core substrate; a plurality of linear conductors included in the sub-substrate and connected to the conductive layers of the build-up layer; The wiring board has a smaller distance between the linear conductors than between the through-hole conductors.

2. 2. The wiring board according to claim 1, Each of the linear conductors extends linearly in the thickness direction of the core substrate within the conductive layer of the sub-substrate.

3. 2. The wiring board according to claim 1, a via conductor penetrating an insulating layer included in the buildup layer and connecting the conductive layer of the buildup layer and the linear conductor; The end faces of the linear conductors are larger than the lower ends of the via conductors.

4. 2. The wiring board according to claim 1, A portion of the insulating layer included in the build-up layer is filled between the inner surface of the cavity and the sub-substrate.

5. 2. The wiring board according to claim 1, The core substrate has core conductive layers on the front and back sides, The end surface of the sub-substrate is located on the same plane as the upper surface of the core conductive layer.

6. 6. The wiring board according to claim 1, the through-hole conductor covers the inner surface of a through-hole that penetrates the core substrate; The through-hole conductor is filled with resin.

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