Manufacturing method of laminated PCB and laminated PCB

Abstract

The invention relates to the technical field of PCBs, and provides a laminated PCB manufacturing method and a laminated PCB, and the method comprises the steps: S1, an upper sub-board and a lower sub-board are manufactured, the upper sub-board corresponds to a PCB top-layer connector wiring region, and the lower sub-board corresponds to a PCB bottom-layer connector wiring region; s2, forming a first through hole penetrating through the thickness of the upper daughter board in the upper daughter board, and forming a second through hole penetrating through the thickness of the lower daughter board in the lower daughter board; s3, back drilling processing is carried out on the first through holes and the second through holes so as to eliminate stubs on the inner layers of all the wires, and the stub length L meets the formula # imgabs0 #, wherein f is the cut-off frequency, c is the light velocity, epsilon r is the PCB dielectric constant, and L is the length of the stubs; and S4, laminating the upper daughter board and the lower daughter board which are subjected to the back drilling treatment to form an integral PCB structure. The problems of high cost and poor machinability in traditional blind hole production are solved by utilizing a method of respectively processing the two daughter cards and then carrying out through hole and back drilling.

Description

Technical Field

[0001] The present application relates to the field of PCB technology, and in particular to a manufacturing method of a laminated PCB and a laminated PCB. Background Art

[0002] The increased bandwidth of Ethernet switches is the core driving force behind the explosive growth of global data traffic. With the explosion of applications such as cloud computing, AI computing, and ultra-high-definition video, the demand for single-port bandwidth has rapidly increased from 1G / 10G to 100G, 400G, and even 800G, and is accelerating towards 1.6T and higher speeds.

[0003] Figure 1 This is the first background technology figure, Figure 2 The second background technology figure. Higher bandwidth requirements mean an increase in transmission rate and port density. The increase in transmission rate will bring about signal integrity issues for high-speed signals. The evolution of signal rate from 56Gbps PAM4 to 112Gbps leads to increased attenuation of high-frequency components of the signal, superimposed reflection effects, causing serious eye closure and a sharp increase in bit error rate (BER). The increase in port density has caused the optical port connector of the panel to be installed from one side to the upper layer connector 1 of the PCB layer 2 (see Figure 1 ) becomes the top layer mounted to the upper connector 1 and lower connector 3 on PCB layer 2 (belly to belly mode) (see Figure 2 ), with the increase of the number of connector layers, not only the routing density of PCB layer 2 in this area increases, which puts great pressure on the fan-out routing method, but the increase in routing density also brings about crosstalk problems, making the signal transmission environment worse.

[0004] As an important signal transmission carrier of the entire switch, the design of the PCB is particularly important. In particular, when designing the PCB stack and selecting materials, it is necessary to consider not only the loss, but also how to reduce the reflection of the via, the crosstalk of the traces, the fan-out method of the traces, and the production cost issues caused by the corresponding processing technology.

[0005] Therefore, in response to the current demand for 112Gbps or even higher 224Gbps rates, it is necessary to design an optimized high-speed PCB stacking and processing process to improve signal transmission quality while also reducing PCB production costs. Summary of the Invention

[0006] In order to help solve the above technical problems, the present application provides a manufacturing method of a laminated PCB and a laminated PCB.

[0007] In a first aspect, the present application provides a method for manufacturing a laminated PCB, which adopts the following technical solution:

[0008] A method for manufacturing a laminated PCB, comprising:

[0009] S1: Manufacturing an upper daughter board and a lower daughter board respectively, wherein the upper daughter board corresponds to the top-layer connector routing area of ​​the PCB, and the lower daughter board corresponds to the bottom-layer connector routing area of ​​the PCB;

[0010] S2: forming a first through hole through the thickness of the upper sub-board, and forming a second through hole through the thickness of the lower sub-board;

[0011] S3: Backdrilling the first through hole and the second through hole to eliminate the stubs in the inner layer of each trace, wherein the stub length L satisfies:

[0012]

[0013] Where f is the cutoff frequency, c is the speed of light, εr is the dielectric constant of the PCB, and L is the length of the stump;

[0014] S4: The back-drilled upper daughter board and the lower daughter board are stacked and pressed together to form an overall PCB structure.

[0015] Preferably, S2 includes:

[0016] Through-holes are drilled by laser drilling or mechanical drilling techniques.

[0017] Preferably, S3 includes:

[0018] The first through hole and the second through hole are back-drilled by laser back-drilling technology to obtain a first back-drilled through hole and a second back-drilled through hole.

[0019] In a second aspect, the present application provides a stacked PCB, which adopts the following technical solution:

[0020] A laminated PCB, comprising an upper daughter board and a lower daughter board that are laminated and pressed together, wherein:

[0021] The upper sub-board includes an independent first signal routing layer group, and the lower sub-board includes an independent second signal routing layer group;

[0022] The upper sub-plate is provided with a first back-drilled through-hole extending through the thickness thereof, and the lower sub-plate is provided with a second back-drilled through-hole extending through the thickness thereof;

[0023] The length L of the residual pile in the first back-drilled through hole and the second back-drilled through hole satisfies:

[0024]

[0025] Where f is the cutoff frequency, c is the speed of light, εr is the dielectric constant of the PCB, and L is the length of the stump.

[0026] Preferably, the laminated PCB includes copper sheet, non-conductor medium, and insulating medium.

[0027] The top and bottom layers of the stacked PCB are both copper sheets, the non-conductive medium is encapsulated with copper sheets on the top and bottom, an insulating medium is provided between the upper sub-board and the lower sub-board, the top layer of the upper sub-board is the top layer of the stacked PCB, and the bottom layer of the lower sub-board is the bottom layer of the stacked PCB.

[0028] In summary, compared with the prior art, this application has the following advantages:

[0029] 1. Replaces the traditional blind hole solution to solve the problem of optimizing signal quality when the top and bottom layer connectors are installed on the PCB;

[0030] 2. We proposed an N+N PCB stackup solution, utilizing a through-hole and back-drilling method after each daughter card is individually fabricated. This approach addresses the high cost and poor workability associated with traditional blind via production. This solution ensures high-speed signal transmission quality while ensuring low-cost and easy-to-manufacture manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is the first background technology figure;

[0032] Figure 2 It is the second background technology figure;

[0033] Figure 3 This is a first related art drawing;

[0034] FIG4 is a second related art drawing;

[0035] Figure 5 This is a third related art drawing;

[0036] FIG6 is a schematic diagram of the manufacturing process of the laminated PCB of the present application.

[0037] Reference numerals: 1-upper layer connector; 2-PCB layer; 3-lower layer connector; 4-blind hole; 5-through hole; 5.1-first through hole; 5.2-second through hole; 6-copper sheet; 7-insulating medium; 8-non-conductive medium. DETAILED DESCRIPTION

[0038] The present invention will be further described below with reference to the accompanying drawings. The structure and principle of the present invention will be very clear to those skilled in the art. It should be understood that the specific embodiments described herein are only intended to explain the present invention and are not intended to limit the present invention.

[0039] Figure 3 FIG is a first related technical drawing, FIG4 is a second related technical drawing, Figure 5This is a third related art drawing.

[0040] Combine Figure 3 , Figure 4 and Figure 5 It is understandable that in the existing technology, due to the high density of traces, most of the PCB traces need to be routed on the inner layer. The current mainstream practice is to connect the traces to the inner layer by drilling holes near the connector pin pads. The resonance problem caused by the via stub can be solved by back drilling ( Figure 3 ).

[0041] exist Figure 3 Plated through holes (PTHs) are a common hole structure in PCBs. Their metal-plated walls enable electrical connections between different circuit layers. Drilling is a necessary step in PCB manufacturing, and this process can produce unwanted copper pillars, or stubs. These stubs don't actually form an electrical connection, but they can negatively impact signal integrity, causing signal reflections and interference.

[0042] To address this issue, the figure also shows the state after the backdrilling operation. Backdrilling is a key PCB manufacturing process. Its primary purpose is to remove unnecessary parts from the PTH, including stubs that may affect signal integrity. Backdrilling effectively reduces reflections and interference during signal transmission, significantly improving signal integrity and ensuring PCB performance and reliability.

[0043] However, this method is not a problem for installing a single-layer connector on a PCB. However, it will cause problems for installing a top-layer connector on a PCB. Because the connectors on the top-layer are symmetrical, drilling a via from the same position on the top-layer to the inner layer will inevitably cause a via short circuit. Therefore, the method adopted is to drill a through hole near the connector pin pad on one side, and on the other side, it is necessary to run a line out of the surface layer and then drill a hole to the inner layer to avoid a via short circuit. As shown in Figure 4, the oval shape in Figure 4 is the connector pin pad. Figure 4a In the process, drill a through hole from the connector pin pad to the inner layer. Figure 4b In the process, pull a section of surface trace from the connector pin pad and then punch a hole to the inner layer.

[0044] This method of pulling out a section of wire and then punching a hole will cause relatively large signal problems. First, because the surface trace has only one side with a ground plane reference layer (the second top layer), and the other side is air without shielding, the crosstalk will be much greater than that of the inner layer trace, which will bring greater noise to the signal in the densely traced area. Second, because the pulled-out trace will pass through the area with the connector pad punched on the other side, and the via will be isolated from the ground plane to prevent short circuit, this will cause the copper foil of the second top layer reference ground plane to be incomplete in this area, resulting in insufficient reference surface for the pulled-out trace, causing impedance mutation and increased signal reflection. In this way, both crosstalk and reflection will deteriorate the signal quality and affect the accuracy of the transmitted signal.

[0045] In view of this situation, the prior art adopts a blind hole solution, such as Figure 5 As shown, the blind hole solution divides the entire PCB into two areas, the top and bottom layers. All the inner layers of the connectors installed on the top layer are in the upper layer, while all the inner layers of the connectors installed on the bottom layer are in the lower layer. The vias on the top and bottom layers are punched to their respective upper and lower dielectric areas. This way, there is no need to worry about the via short circuit problem, and it also solves the problem of poor signal when pulling out the traces and then punching holes.

[0046] While blind vias offer excellent performance and can avoid short circuits caused by vias, PCB blind and buried via technology achieves circuit interconnection by drilling holes between layers in a multi-layer circuit board. However, these holes do not penetrate all layers of the board. Due to the aspect ratio of traditional blind vias, the depth of the blind via is constrained by the diameter of the blind via. Equations 1 and 2 show the typical aspect ratios of blind vias 4 and through vias 5 in the industry, respectively:

[0047] Formula 1: S = 0.8*d;

[0048] Formula 2: S = 18*d;

[0049] Where S is the drillable depth, and d is the diameter of the drilled hole. Assuming the required hole diameter is 0.2mm, the drillable depth of through hole 5 is 3.6mm, while the drillable depth of blind hole 4 is 0.16mm. The depth of 0.16mm is only about the thickness of one layer of PCB, which obviously cannot meet the drilling requirements of multiple stacked traces of different depths.

[0050] If the drilling depth is met by increasing the hole diameter, the impedance of the via will decrease, as shown in the impedance Z0 of the via in Equation 3, exacerbating the capacitive effect of the high-speed via, causing signal reflection and thus affecting signal quality:

[0051] Formula 3:

[0052] Where Z0 is the via impedance, εr is the dielectric constant of the PCB, D is the distance from the via to the nearest copper sheet (anti-pad), and d is the diameter of the drilled hole.

[0053] From this, we can see that while ensuring the via impedance (without increasing the aperture), if you want to make blind vias 4 in multiple routing layers, you can only drill holes in each layer first, and then combine and press them together after each layer is completed. If there are many layers of inner routing, then many presses are required. This not only increases the time and processing costs, but also involves the process problem of drilling alignment accuracy due to multiple presses. Inaccurate alignment may cause the vias in different layers to be unable to connect together and open circuit, which directly affects the reliability of the PCB.

[0054] FIG6 is a schematic diagram of the manufacturing process of the laminated PCB of the present application, Figure 6a For the upper daughter board, Figure 6b For the lower sub-board, Figure 6c The PCB after lamination. To address these issues with traditional blind vias 4, this application proposes a new PCB stackup, dividing the PCB area into two parts, corresponding to the top-layer connector routing area and the bottom-layer connector routing area. These two areas are considered two daughter boards, manufactured separately during processing. After lamination and lamination, a through hole 5 is directly drilled from the top to the bottom of the daughter board, as shown in Figure 6.

[0055] After the two daughter cards are assembled and pressed together, the traces on each inner layer have corresponding stub effects. Backdrilling is then used to remove the stubs on the inner layers of each daughter card to eliminate the resonance caused by the stubs. After the stubs are removed, the two daughter cards are pressed together to complete the PCB. This method allows blind vias 4 to be created in just two press-fits, regardless of the number of inner layer traces. This ensures signal quality, production costs, and reliability.

[0056] After the two daughter cards are manufactured, the traces on different inner layers of each card will have corresponding stub effects. The impact of the stub effect on signal bandwidth is shown in Equation 4:

[0057]

[0058] Where f is the cutoff frequency, c is the speed of light, εr is the dielectric constant of the PCB, and L is the length of the stub. It can be seen that the smaller L is, the higher the cutoff frequency of f is, and the smaller the impact on the signal will be. Therefore, to address the stub effect, back drilling can be used to process the stubs on the inner layers of each trace of the two daughter cards. After back drilling, no more than 8 mils of stubs will remain. Assuming that the dielectric constant of the PCB is 3.2, according to Formula 4, the corresponding cutoff frequency can be calculated to be at least 200 GHz, which far exceeds the 50 GHz bandwidth required for 112 Gbps signal transmission. This can eliminate the resonance effect caused by the residual stub and achieve the same effect as blind via 4, so that this application can replace the traditional blind via 4 solution. After processing the stub, the two daughter cards are pressed together to complete the entire PCB production. The advantage of this is that no matter how many inner-layer traces there are, only two pressings are required to complete the production, which guarantees signal quality, production cost, and production reliability.

[0059] Specifically, the manufacturing method of the laminated PCB of the present application includes:

[0060] S1: Manufacturing an upper daughter board and a lower daughter board separately, wherein the upper daughter board corresponds to the top-layer connector wiring area of ​​the PCB, and the lower daughter board corresponds to the bottom-layer connector wiring area of ​​the PCB.

[0061] S2: Form a first through hole 5.1 through the thickness of the upper sub-plate, and a second through hole 5.2 through the thickness of the lower sub-plate. In this embodiment of the present application, the through holes 5 can be drilled by laser drilling or mechanical drilling technology.

[0062] S3: Backdrilling the first through hole 5.1 and the second through hole 5.2 to remove stubs on the inner layer of each routing, wherein the stub length L satisfies.

[0063]

[0064] Where f is the cutoff frequency, c is the speed of light, εr is the dielectric constant of the PCB, and L is the length of the stump.

[0065] In the embodiment of the present application, the back drilling process is performed on the through holes 5 on the upper sub-board and the lower sub-board by using a laser back drilling technology.

[0066] S4: The back-drilled upper daughter board and the lower daughter board are stacked and pressed together to form an overall PCB structure.

[0067] The laminated PCB of this application includes:

[0068] It includes an upper sub-board and a lower sub-board that are laminated and pressed together, wherein:

[0069] The upper sub-board includes an independent first signal routing layer group, and the lower sub-board includes an independent second signal routing layer group;

[0070] The upper sub-board is provided with a first back-drilled through-hole extending through the thickness thereof, and the lower sub-board is provided with a second back-drilled through-hole extending through the thickness thereof (a back-drilled through-hole refers to a through-hole processed by back drilling).

[0071] The laminated PCB includes a copper sheet 6, a non-conductor medium 8, and an insulating medium 7.

[0072] The top and bottom layers of the stacked PCB are both copper sheets 6, and the non-conductive medium 8 is encapsulated with copper sheets 6 above and below. An insulating medium 7 is provided between the upper sub-board and the lower sub-board. The top layer of the upper sub-board is the top layer of the stacked PCB, and the bottom layer of the lower sub-board is the bottom layer of the stacked PCB.

Claims

1. A method for manufacturing a laminated PCB, characterized in that: include: S1: Manufacturing an upper daughter board and a lower daughter board respectively, wherein the upper daughter board corresponds to the top-layer connector routing area of ​​the PCB, and the lower daughter board corresponds to the bottom-layer connector routing area of ​​the PCB; S2: forming a first through hole through the thickness of the upper sub-board, and forming a second through hole through the thickness of the lower sub-board; S3: Backdrilling the first through hole and the second through hole to eliminate the stubs in the inner layer of each trace, wherein the stub length L satisfies: Where f is the cutoff frequency, c is the speed of light, εr is the dielectric constant of the PCB, and L is the length of the stump; S4: The back-drilled upper daughter board and the lower daughter board are stacked and pressed together to form an overall PCB structure.

2. The method for manufacturing a laminated PCB according to claim 1, wherein: S2 includes: Through-holes are drilled by laser drilling or mechanical drilling techniques.

3. The method for manufacturing a laminated PCB according to claim 1, wherein: S3 includes: The first through hole and the second through hole are back-drilled by laser back-drilling technology to obtain a first back-drilled through hole and a second back-drilled through hole.

4. A laminated PCB, characterized in that: It includes an upper sub-board and a lower sub-board that are laminated and pressed together, wherein: The upper sub-board includes an independent first signal routing layer group, and the lower sub-board includes an independent second signal routing layer group; The upper sub-plate is provided with a first back-drilled through-hole extending through the thickness thereof, and the lower sub-plate is provided with a second back-drilled through-hole extending through the thickness thereof; The length L of the residual pile in the first back-drilled through hole and the second back-drilled through hole satisfies: Where f is the cutoff frequency, c is the speed of light, εr is the dielectric constant of the PCB, and L is the length of the stump.

5. The laminated PCB according to claim 4, characterized in that: The laminated PCB includes copper sheet, non-conductor medium and insulating medium. The top and bottom layers of the stacked PCB are both copper sheets, the non-conductive medium is encapsulated with copper sheets on the top and bottom, an insulating medium is provided between the upper sub-board and the lower sub-board, the top layer of the upper sub-board is the top layer of the stacked PCB, and the bottom layer of the lower sub-board is the bottom layer of the stacked PCB.

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