Wiring board and mounting structure using the same

Abstract

To provide a wiring board capable of easily recognizing a grounding conductor exposed from an opening part of a solder resist as an alignment mark even when the grounding conductor exposed from the opening part is coated with solder.SOLUTION: A wiring board according to the present disclosure includes: a first insulating layer having a first surface; a first conductor layer located on the first surface and having a second surface on a side opposite to the first surface; a solder resist having an opening part covering the first surface and the second surface and exposing a part of the first conductor layer, and having a third surface on a side opposite to the second surface; and solder located on the second surface in the opening part. The opening part includes: an opening side surface located from the third surface to the second surface; and an opening edge located on the second surface side. A gap is located between at least a portion of the periphery of the opening edge and the second surface.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board and a mounting structure using the same. [Background technology]

[0002] In wiring boards, conductors located directly below solder resist are sometimes exposed through openings in the solder resist to be used as alignment marks. In some cases, solder is provided in these openings, and the conductors exposed through the openings are coated with solder (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-68792 DISCLOSURE OF THE INVENTION [Problem to be solved by the invention]

[0004] If the conductor that functions as an alignment mark is coated with solder, the contrast between the solder resist and the solder becomes small, making it difficult to recognize it as an alignment mark.

[0005] An object of the present disclosure is to provide a wiring board in which the conductors exposed from the openings in the solder resist can be easily recognized as alignment marks even when the conductors exposed from the openings are coated with solder. [Means for solving the problem]

[0006] The wiring board according to the present disclosure includes a first insulating layer having a first surface, a first conductor layer located on the first surface and having a second surface opposite the first surface, a solder resist covering the first and second surfaces and having an opening exposing a portion of the first conductor layer and having a third surface opposite the second surface, and solder located on the second surface within the opening. The opening includes an opening side extending from the third surface to the second surface and an opening edge located on the second surface side. A gap is located between at least a portion of the periphery of the opening edge and the second surface.

[0007] A mounting structure according to the present disclosure includes the above-described wiring board and an electronic component located in a mounting area of the wiring board. [Effects of the Invention]

[0008] The wiring board according to the present disclosure has the configuration described in the section on means for solving the problem, so that even when the conductor exposed from the opening in the solder resist is coated with solder, the conductor exposed from the opening can be easily recognized as an alignment mark. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1A is an explanatory diagram illustrating one embodiment of a main part of a wiring board according to one embodiment of the present disclosure, FIG. 1B is an enlarged explanatory diagram illustrating an area X shown in FIG. 1A, and FIG. 1C is a schematic diagram illustrating an example of a state in which the main part shown in FIG. 1A is recognized as an alignment mark. [Figure 2] FIG. 2A is a photograph showing a state in which an embodiment of a main part of a wiring board according to an embodiment of the present disclosure is recognized as an alignment mark, and FIG. 2B is a binarized image of the photograph shown in FIG. 2A. [Figure 3] FIG. 3A is a photograph showing another embodiment of a main part of a wiring board according to an embodiment of the present disclosure, in which the main part is recognized as an alignment mark, and FIG. 3B is a binarized image of the photograph shown in FIG. 3A. [Figure 4]FIG. 4A is a photograph showing a state in which yet another embodiment of a key part is recognized as an alignment mark in a wiring board according to one embodiment of the present disclosure, and FIG. 4B is a binarized image of the photograph shown in FIG. 4A. [Figure 5] FIG. 5A is a photograph showing a state in which yet another embodiment of a main part is recognized as an alignment mark in a wiring board according to one embodiment of the present disclosure, and FIG. 5B is a binarized image of the photograph shown in FIG. 5A. DETAILED DESCRIPTION OF THE INVENTION

[0010] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1A to 1C. Figure 1A is an explanatory diagram illustrating an embodiment of a main part of a wiring board 10 according to an embodiment of the present disclosure. Although not shown, the wiring board 10 shown in Figure 1A includes, for example, a core layer and a build-up layer.

[0011] The core layer is located approximately at the center in the thickness direction of the wiring board 10. The core layer includes a core insulating layer and a core conductor layer. The core insulating layer is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used alone or in combination of two or more. The thickness of the core insulating layer is not particularly limited and may be, for example, 0.1 mm or more and 2.0 mm or less.

[0012] The core insulating layer may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Only one type of reinforcing material may be used, or two or more types may be used in combination. Furthermore, the core insulating layer may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Only one type of inorganic insulating filler may be used, or two or more types may be used in combination.

[0013] The core conductor layer is located on the surface of the core insulating layer. The core conductor layer is not particularly limited as long as it is made of a conductive material. Examples of conductive materials include metals such as copper. The thickness of the core conductor layer is not particularly limited and may be, for example, 5 μm or more and 50 μm or less.

[0014] A through-hole conductor is located in the core insulating layer to electrically connect the upper and lower surfaces of the core insulating layer. The through-hole conductor is located in a through-hole that penetrates the upper and lower surfaces of the core insulating layer. The through-hole conductor is formed of a metal such as copper, similar to the core conductor layer. The through-hole conductor may be formed only on the inner wall surface, or may fill the through-hole. The through-hole conductor is connected to the core conductor layer on the surface of the core insulating layer.

[0015] The build-up layer is located on one or both sides of the core layer, and has a structure in which at least one build-up insulating layer and at least one build-up conductor layer are laminated.

[0016] The build-up insulating layer, like the core insulating layer, is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used alone or in combination of two or more.

[0017] The build-up insulating layers may be made of the same resin or different resins. The build-up insulating layers and the core insulating layers may be made of the same resin or different resins. The thickness of the build-up insulating layers is not particularly limited and may be, for example, 10 μm or more and 50 μm or less. The build-up insulating layers may have the same thickness or different thicknesses.

[0018] The build-up insulating layer may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Only one type of reinforcing material may be used, or two or more types may be used in combination. Furthermore, the build-up insulating layer may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Only one type of inorganic insulating filler may be used, or two or more types may be used in combination.

[0019] The conductor layer for build-up is not limited as long as it is a conductor such as a metal. Specifically, the conductor layer for build-up is formed of a metal foil such as copper foil, or a metal plating such as copper plating. The thickness of the conductor layer for build-up is not particularly limited and may be, for example, 5 μm or more and 25 μm or less.

[0020] Via-hole conductors are located in the build-up insulating layer to electrically connect the upper and lower surfaces of the build-up insulating layer. The via-hole conductors are located in via holes that penetrate the upper and lower surfaces of the build-up insulating layer. The via-hole conductors are formed, for example, by metal plating such as copper plating. The via-hole conductors are connected to build-up conductor layers located on both sides of the build-up insulating layer. The via-hole conductors may fill the via holes, or may be located only on the inner surfaces of the via holes.

[0021] 1A shows the insulating layer located at the outermost layer of the insulating layers (build-up insulating layers) included in wiring board 10. This insulating layer located at the outermost layer corresponds to first insulating layer 1. First insulating layer 1 has a first surface 1a. In this specification, "first surface 1a of first insulating layer 1" refers to the surface of both sides of first insulating layer 1 that is farther from the center (core layer) of wiring board 10.

[0022] 1A shows the conductor layer located at the top of the conductor layers (build-up conductor layers) included in wiring board 10. This conductor layer located at the top corresponds to first conductor layer 2. First conductor layer 2 is located on first surface 1a of first insulating layer 1, and has second surface 2a on the opposite side to first surface 1a. First conductor layer 2 includes a ground conductor, a power conductor, and a signal conductor.

[0023] A solder resist 3 is located on the outermost layer of the wiring board 10. Specifically, the solder resist 3 is located so as to cover the first surface 1a of the first insulating layer 1 and the second surface 2a of the first conductor layer 2. In FIG. 1A, the solder resist 3 is not in contact with the first surface 1a, but is in contact with the first surface 1a where the first conductor layer 2 is not located.

[0024] The solder resist 3 may be located on at least one surface layer of the wiring board 10. The solder resist 3 is made of a resin, such as an acrylic-modified epoxy resin.

[0025] The solder resist 3 has an opening 31 exposing a portion of the first conductor layer 2 and a third surface 3a on the side opposite the second surface 2a of the first conductor layer 2. The first conductor layer 2 exposed through the opening 31 is, for example, a ground conductor and functions as an alignment mark for positioning or the like. In addition to the opening 31 functioning as an alignment mark, the solder resist 3 also has an electrode opening (not shown) in the mounting area of the wiring board 10, which allows a portion of the first conductor layer 2 to function as an electrode. The first conductor layer 2 functioning as an electrode may be, for example, the aforementioned ground conductor, a power conductor, or a signal conductor. The opening 31 in the solder resist 3 may have a polygonal shape, such as a circle, a cross, an ellipse, or a rectangle, when viewed in a plan view.

[0026] As shown in FIG. 1B, the opening 31 in the solder resist 3 includes an opening side surface 32 extending from the third surface 3a to the second surface 2a, and an opening edge 33 located on the second surface 2a side. The opening edge 33 may be, for example, a ridge between the opening side surface 32 and the surface of the solder resist 3 opposite the third surface 3a. FIG. 1B is an enlarged explanatory view illustrating region X shown in FIG. 1A. Furthermore, as shown in FIG. 1B, a gap 5 is located in the wiring board 10 between at least a portion of the periphery of the opening edge 33 and the second surface 2a.

[0027] 1A, the solder 4 is positioned within the opening 31 so as to cover the second surface 2a of the first conductor layer 2. The solder 4 may be positioned so as to flow into part of the gap 5, or it may not be positioned at all. Considering the effect of being easily recognized as an alignment mark, the solder 4 does not have to be positioned at all in the gap 5. If the solder 4 is positioned at the gap 5, the difference in brightness between the solder 4 and the opening edge 33 is reduced when imaging for alignment. Therefore, compared to when the solder 4 is not positioned at the gap 5, the boundary between the solder 4 and the opening edge 33 becomes unclear, making it difficult to recognize parts of a bright color region 51, which will be described later.

[0028] The first conductor layer 2, which functions as an alignment mark, is coated with solder 4 to protect the second surface 2a. When the second surface 2a is coated with solder 4, diffuse reflection by the solder 4 causes the boundary between the solder 4 and the opening edge 33 to become unclear when imaging for alignment. This makes it difficult to recognize it as an alignment mark.

[0029] Due to the presence of the gap 5, when the opening 31 is recognized as an alignment mark, as shown in FIG. 1C, the gap 5 functions as a light-tone region 51. That is, even if the solder 4 is located on the second surface 2a within the opening 31, the light-tone region 51 makes the boundary between the solder 4 and the opening edge 33 clear, allowing the alignment mark to be clearly recognized. FIG. 1C is a schematic diagram showing an example of a state in which the main part shown in FIG. 1A is recognized as an alignment mark. In FIG. 1C, the white portion of the solder 4 indicates the portion where the light irradiated during imaging is reflected.

[0030] As long as the alignment mark can be recognized by the light tone region 51, the gap 5 may be located between the second surface 2a and a portion of the periphery of the opening edge 33. In this case, the light tone region 51 is partially missing, i.e., has an intermittent state like a broken line. To make the light tone region 51 more clearly recognizable, the gap 5 may be located between the entire periphery of the opening edge 33 and the second surface 2a.

[0031] There are no limitations on the depth of gap 5, i.e., the length from opening edge 33 in the surface direction of first conductor layer 2. For example, gap 5 may have a length of 2 μm or more and 20 μm or less in the surface direction of first conductor layer 2 from opening edge 33, so long as the light color tone region 51 can be clearly recognized without affecting the adhesion between first conductor layer 2 and solder resist 3.

[0032] 1B formed between the opening side surface 32 and the third surface 3a of the opening 31 is not limited. The first angle θ1 may be 90° or more and 120° or less, as long as the alignment mark can be clearly recognized.

[0033] 2A is a photograph showing an embodiment of a main part of wiring board 10 recognized as an alignment mark. FIG. 2B is a binarized image of the photograph shown in FIG. 2A. FIG. 2A shows a portion of first conductor layer 2, whose second surface 2a exposed from opening 31 is covered with solder 4 (circular portion in FIG. 2A). In FIG. 2A, first conductor layer 2 is etched in the thickness direction by about 1.0 μm in opening 31, thereby forming gap 5 having a length of about 15 μm from opening edge 33 in the surface direction of first conductor layer 2.

[0034] As shown in Figure 2A, even though the second surface 2a of the first conductor layer 2 exposed from the opening 31 is covered with solder 4, the light-tone region 51 (gap 5) makes the boundary between the opening edge 33 of the solder resist 3 and the solder 4 clearly recognizable. Therefore, the alignment mark is clearly recognizable. In Figures 2A and 2B, the white parts present in the solder 4 indicate areas where light irradiated during imaging is reflected.

[0035] Next, Fig. 3A is a photograph showing another embodiment of a main part of wiring board 10 recognized as an alignment mark. Fig. 3B is a binarized image of the photograph shown in Fig. 3A. Fig. 3A shows a portion of first conductor layer 2's second surface 2a exposed from opening 31, covered with solder 4 (circular portion in Fig. 3A). In Fig. 3A, first conductor layer 2 is etched by about 0.2 µm in the thickness direction in opening 31, thereby forming gap 5 having a length of about 5 µm from opening edge 33 in the surface direction of first conductor layer 2.

[0036] As shown in FIG. 3A, even if the second surface 2a of the first conductor layer 2 exposed from the opening 31 is covered with solder 4, the light-tone region 51 (gap 5) allows the boundary between the opening edge 33 of the solder resist 3 and the solder 4 to be recognized. Specifically, as shown in FIG. 3B, even if the light-tone region 51 is discontinuous (the gap 5 is discontinuous), the boundary between the opening edge 33 of the solder resist 3 and the solder 4 can be recognized. Therefore, the alignment mark is clearly recognized. In FIGS. 3A and 3B, the white portions of the solder 4 indicate areas where light irradiated during imaging is reflected.

[0037] Next, FIG. 4A is a photograph showing a state in which yet another embodiment of a main part of wiring board 10 is recognized as an alignment mark. FIG. 4B is a binarized image of the photograph shown in FIG. 4A. In FIG. 4A, opening 31 has a cross shape in a plan view. FIG. 4A shows a portion of second surface 2a of first conductor layer 2 exposed from opening 31, which is covered with solder 4 (the cross-shaped portion in FIG. 4A). In FIG. 4A, first conductor layer 2 is etched by about 1.0 μm in the thickness direction in opening 31, thereby forming gap 5 having a length of about 15 μm from opening edge 33 in the surface direction of first conductor layer 2.

[0038] 4A , even if the second surface 2a of the first conductor layer 2 exposed from the opening 31 is covered with solder 4, the light-tone region 51 (gap 5) makes the boundary between the opening edge 33 of the solder resist 3 and the solder 4 clearly recognizable. In this way, regardless of the shape of the opening 31, the boundary between the opening edge 33 of the solder resist 3 and the solder 4 is recognizable. Therefore, regardless of the shape of the opening 31, the alignment mark is clearly recognizable.

[0039] Next, FIG. 5A is a photograph showing a state in which yet another embodiment of a main part of wiring board 10 is recognized as an alignment mark. FIG. 5B is a binarized image of the photograph shown in FIG. 5A. In FIG. 5A, opening 31 has a cross shape in plan view. The cross shape shown in FIG. 5A is thinner than the cross shape shown in FIG. 4A. FIG. 5A shows a portion of second surface 2a of first conductor layer 2 exposed from opening 31, which is covered with solder 4 (the cross-shaped portion in FIG. 5A). In FIG. 5A, first conductor layer 2 is etched by about 1.0 μm in the thickness direction in opening 31, thereby forming gap 5 having a length of about 15 μm from opening edge 33 in the surface direction of first conductor layer 2.

[0040] 5A, even if the second surface 2a of the first conductor layer 2 exposed from the opening 31 is covered with solder 4, the light-tone region 51 (gap 5) makes the boundary between the opening edge 33 of the solder resist 3 and the solder 4 clearly recognizable. In this way, the boundary between the opening edge 33 of the solder resist 3 and the solder 4 is recognizable regardless of the shape of the opening 31. Therefore, the alignment mark is clearly recognizable regardless of the shape of the opening 31.

[0041] Next, a mounting structure according to the present disclosure will be described. The mounting structure according to one embodiment includes a wiring board 10 according to one embodiment and an electronic component located in a mounting area of the wiring board 10. The wiring board 10 and the electronic component are connected via, for example, solder, such that electrodes located in the mounting area of the wiring board 10 are connected to electrodes of the electronic component. The electrodes are exposed through openings for electrodes formed in a solder resist 3 located in the mounting area of the wiring board 10. Examples of electronic components include semiconductor integrated circuit elements and optoelectronic elements. In the mounting structure according to one embodiment, electronic components may be located on both surfaces of the wiring board 10, or electronic components may be located on one surface and, for example, a motherboard may be located on the other surface.

[0042] Although the embodiments of the present disclosure have been described above, the invention according to the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) and (7) below.

[0043] (1) A wiring board according to the present disclosure includes a first insulating layer having a first surface, a first conductor layer located on the first surface and having a second surface opposite the first surface, a solder resist covering the first and second surfaces and having an opening exposing a portion of the first conductor layer and having a third surface opposite the second surface, and solder located on the second surface within the opening. The opening includes an opening side extending from the third surface to the second surface and an opening edge located on the second surface side. A gap is located between at least a portion of the periphery of the opening edge and the second surface.

[0044] The present disclosure further discloses the following embodiments (2) to (6).

[0045] (2) In the wiring board described in (1) above, the solder is not located in the gap. (3) In the wiring board according to (1) or (2) above, the gap is located between the entire periphery of the opening edge and the second surface. (4) In the wiring board according to any one of (1) to (3) above, the gap has a length of 2 μm or more and 20 μm or less from the edge of the opening in the surface direction of the first conductor layer. (5) In the wiring board according to any one of (1) to (4) above, the first angle formed between the side surface of the opening and the third surface of the solder resist is 90° or more and 120° or less. (6) In the wiring board according to any one of (1) to (5) above, the opening has a circular or cross shape when viewed from above.

[0046] (7) A mounting structure according to the present disclosure includes the wiring board according to any one of (1) to (6) above, and an electronic component located in a mounting area of the wiring board. [Explanation of symbols]

[0047] 1 First insulating layer 1a 1st page 2 First conductor layer 2a 2nd side 3 Solder resist 31 Opening 32 Opening side 33 Opening edge 4. Solder 5 Gap 51 Bright tone area 10. Wiring board

Claims

1. a first insulating layer having a first surface; a first conductor layer located on the first surface and having a second surface opposite the first surface; a solder resist covering the first surface and the second surface, having an opening exposing a portion of the first conductor layer, and having a third surface opposite the second surface; solder located on the second surface within the opening; Including, the opening includes an opening side surface located from the third surface to the second surface and an opening edge located on the second surface side, a gap is located between at least a portion of the periphery of the opening edge and the second surface; Wiring board.

2. The wiring board according to claim 1 , wherein the solder is not located in the gap.

3. The wiring board according to claim 1 , wherein the gap is located between the entire periphery of the opening edge and the second surface.

4. The wiring board according to claim 1 , wherein the gap has a length of 2 μm to 20 μm from the edge of the opening in the surface direction of the first conductor layer.

5. The wiring board according to claim 1 , wherein a first angle formed between the side surface of the opening and the third surface of the solder resist is equal to or greater than 90° and equal to or less than 120°.

6. The wiring board according to claim 1 , wherein the opening has a circular or cross shape in plan view.

7. A mounting structure comprising the wiring board according to any one of claims 1 to 6 and an electronic component located in a mounting area of the wiring board.

Images