Power semiconductor package and manufacturing method thereof

Abstract

To provide a power semiconductor device that provides a rectifier device with high power efficiency and low losses suitable for high speed switching applications.SOLUTION: A power semiconductor device 100 includes a base 101 including a substrate 101a and an epitaxial layer 101b located above the substrate. The base 101 comprises a unit area 100a and a peripheral area 100b surrounding the unit area. A junction layer 103a is located above the epitaxial layer within the peripheral area. A barrier layer 103b is located within the unit area and above the epitaxial layer. A first electrode 104a is located on the junction layer, and a second electrode 104b is located on the barrier layer. The epitaxial layer includes a doped channel 101c located within the peripheral area. A current flows from the substrate through the doped channel and the junction layer to the first electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to Chinese Patent Application No. CN 202410137256.0, entitled "Power Semiconductor Packaging and Manufacturing Method Thereof," filed on January 31, 2024, and is incorporated herein by reference as if reproduced in its entirety.

[0002]

[0002] The present disclosure relates generally to the field of semiconductors, and in particular embodiments to power semiconductor packages and methods of fabrication thereof. The present disclosure includes embodiments of power semiconductor devices packaged as integrated circuits (ICs) and their corresponding methods of fabrication, more specifically, junction barrier Schottky (JBS) rectifiers packaged at the chip level, known as chip-scale packages (CSPs), and their fabrication methods. [Background technology]

[0003]

[0003] Modern power circuits require rectifiers that can handle high power, low losses, and rapid switching. Schottky barrier rectifiers are often used when high switching speeds and extremely low forward bias voltages are required. Schottky barrier rectifiers are majority carrier devices that utilize a metal-oxide semiconductor (MOS) process, allowing minimal reverse leakage current to flow during the recovery process. Unfortunately, when operating at high temperatures, Schottky barrier rectifiers suffer from undesirably high reverse leakage current.

[0004]

[0004] Current improvements aim to enhance the high-temperature operating capabilities of Schottky rectifiers. One such approach involves replacing silicon with silicon carbide (SiC) as the substrate for Schottky barrier rectifiers, which offers high breakdown voltage, low forward voltage drop, short reverse recovery time, and high-temperature resistance. However, SiC is brittle, prone to wear, and difficult to machine, increasing manufacturing complexity. Furthermore, compared to silicon, SiC results in high leakage current in rectifiers, limiting their use to low-voltage applications.

[0005]

[0005] Therefore, there is a need for further improvements in rectifier devices to achieve high power efficiency and low losses suitable for high speed switching applications. Summary of the Invention

[0006] Technical advantages are generally realized by embodiments of the present disclosure, which describe an innovative power semiconductor package and method of manufacturing the same.

[0007]

[0007] The disclosed embodiments relate to a power semiconductor device. The power semiconductor device includes: a base defining a unit area and a peripheral area surrounding the unit area, the base including a substrate and an epitaxial layer located above the substrate; a junction layer located within the peripheral area and above the epitaxial layer; a barrier layer located within the unit area and above the epitaxial layer; a first electrode located on the junction layer; and a second electrode located on the barrier layer. The epitaxial layer includes a doped channel located within the peripheral area and extending between the junction layer and the substrate, allowing current to flow from the substrate through the doped channel and the junction layer to the first electrode.

[0008] Another embodiment includes a power semiconductor device comprising: a base defining a unit area and a peripheral area surrounding the unit area, the base including a substrate and an epitaxial layer above the substrate, a semiconductor component surrounded by the base and the epitaxial layer, a junction layer located within the peripheral area and above the epitaxial layer, and a first electrode located on the junction layer. The epitaxial layer includes a doped channel located within the peripheral area and extending between the junction layer and the semiconductor component part, allowing current to flow from the substrate through the semiconductor component, the doped channel, and the junction layer to the first electrode.

[0009] A method for fabricating a power semiconductor device is also disclosed. The method includes forming a first epitaxial sublayer above a substrate, implanting doping ions into a portion of the first epitaxial sublayer to create a first doped subchannel, forming a second epitaxial sublayer above the first epitaxial sublayer, implanting doping ions into a portion of the second epitaxial sublayer to form a second doped subchannel above the first doped subchannel, forming a junction layer above the second doped subchannel, and forming a first electrode above the junction layer. The formation includes a doped channel comprising first and second doped subchannels extending between the junction layer and the substrate.

[0010] For a complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: It is important to recognize that representations of the various structures may not be strictly to scale. In fact, for purposes of illustration, the dimensions of these structures may be intentionally exaggerated or minimized for clarity of illustration. [Brief explanation of the drawings]

[0011] [Figure 1]1 is a cross-sectional view illustrating an exemplary power semiconductor device according to various embodiments of the present disclosure. [Figure 2] FIG. 10 is a cross-sectional view illustrating another exemplary power semiconductor device according to various embodiments of the present disclosure. [Figure 3] FIG. 10 is a cross-sectional view illustrating another exemplary power semiconductor device according to various embodiments of the present disclosure. [Figure 4] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 5] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 6] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 7] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 8] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 9] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 10] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 11] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 12] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 13] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 14]1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 15] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 16] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 17] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 18] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 19] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 20] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 21] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 22] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 23] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 24] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 25] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 26] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 27]1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 28] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 29] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 30] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 31] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 32] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 33] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 34] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 35] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 36] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 37] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 38] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 39] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 40]1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 41] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 42] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 43] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 44] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 45] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 46] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 47] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 48] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 49] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 50] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 51] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 52] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 53]1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. [Figure 54] 1A-1D illustrate one or more stages in a method for manufacturing a power semiconductor device according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0015] The same or similar components are identified throughout the drawings and detailed description by the same reference numerals.From the detailed description, and taken in conjunction with the drawings, several embodiments of the present disclosure will be readily understood.

[0013]

[0016] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0014]

[0017] The following presents numerous exemplary embodiments or examples of various features for implementing the subject matter disclosed herein. Specific examples of components and configurations are described below. However, these are provided merely as examples and are not intended to be limiting. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features directly abut, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not directly abut. Furthermore, this disclosure may repeat graphic markings and / or text in various instances. This repetition is for simplicity and clarity and does not indicate a relationship between the described embodiments and / or configurations.

[0015]

[0018] Making and using embodiments of the present disclosure are described in detail below. However, it should be understood that the concepts disclosed herein can be embodied in a wide variety of specific contexts, and that the specific embodiments described herein are merely illustrative and do not serve to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure, as defined by the appended claims.

[0016]

[0019] Furthermore, one or more features from one or more of the embodiments described below may be combined to create alternative embodiments not expressly described, and features appropriate for such combinations are understood to be within the scope of this disclosure. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

[0017]

[0020] The present disclosure provides a power semiconductor package and manufacturing method. Unlike conventional methods of forming a silicon carbide epitaxial layer on a substrate, the power semiconductor device disclosed herein is constructed by sequentially stacking silicon carbide sub-epitaxial layers to form a silicon carbide epitaxial layer. Following the formation of each silicon carbide sub-epitaxial layer, a diffusion or ion implantation process is performed at designated locations to develop a doped channel extending within the silicon carbide epitaxial layer and consisting of multiple sub-doped channels. This method allows for the formation of doped channels within the power semiconductor device without the need to machine the silicon carbide epitaxial layer, thereby avoiding the difficulties associated with machining silicon carbide material. Additionally, this method of sequentially stacking silicon carbide sub-epitaxial layers can produce thick silicon carbide epitaxial layers, reducing leakage current and thus enabling the power semiconductor device to be used in high-voltage applications.

[0018]

[0021] FIG. 1 illustrates a cross-sectional view of a power semiconductor device 100 according to various embodiments of the present disclosure. The power semiconductor device 100 is, specifically, a power semiconductor device packaged as an integrated circuit (IC). In some embodiments, the power semiconductor device 100 is a junction barrier Schottky (JBS) rectifier packaged in a chip-level package (CSP). As shown in FIG. 1, the power semiconductor device 100 may include a base 101, a contact layer 103 above the base 101, and an electrode 104 above the contact layer 103. From a top view, the base 101 may include a unit area 100a and a peripheral area 100b, where the peripheral area 100b is adjacent to the unit area 100a. In some embodiments, the unit area 100a is an active area that houses active or passive components, and the peripheral area 100b is an edge termination area for connecting to circuit terminals. In some embodiments, the unit area 100a is surrounded by the peripheral area 100b.

[0019]

[0022] The base 101 may include a substrate 101a and an epitaxial layer 101b above the substrate 101a. In some embodiments, the substrate 101a may include a semiconductor material such as silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and gallium arsenide phosphide (GaAsP), among other semiconductor materials. The epitaxial layer 101b may include a semiconductor material such as silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and gallium arsenide phosphide (GaAsP), among other semiconductor materials. In some embodiments, both the substrate 101a and the epitaxial layer 101b may include the material silicon carbide. In some embodiments, substrate 101a is an N-type or P-type semiconductor material, and epitaxial layer 101b is an N-type or P-type semiconductor material. In some embodiments, substrate 101a and epitaxial layer 101b have the same type of conductivity doping, e.g., both substrate 101a and epitaxial layer 101b are N-type. In some embodiments, substrate 101a is part of a silicon carbide wafer. In some embodiments, the doping concentration of substrate 101a is higher than the doping concentration of epitaxial layer 101b. Both substrate 101a and epitaxial layer 101b include an N-type dopant, which may be, for example, phosphorus (P) or arsenic (As). In some embodiments, the thickness of epitaxial layer 101b is greater than the thickness of substrate 101a. In some embodiments, the thickness of epitaxial layer 101b is 6 μm or greater. The thicker the epitaxial layer 101b, the better the power semiconductor device 100 functions in high voltage applications (eg, 650 volts to 3000 volts).

[0020]

[0023] The epitaxial layer 101b includes a doped channel 101c located within the peripheral area 100b and extending between the electrode 104 and the substrate 101a. In some embodiments, the doped channel 101c extends vertically along the thickness of the epitaxial layer 101b. A height H1 of the doped channel 101c may be essentially equal to the thickness of the epitaxial layer 101b. In some embodiments, the height H1 of the doped channel 101c and the thickness of the epitaxial layer 101b are each approximately in the range of 2 μm to 6 μm. The substrate 101a and the doped channel 101c have the same conductivity type. In some embodiments, the substrate 101a, the epitaxial layer 101b, and the doped channel 101c are all N-type.

[0021]

[0024] The epitaxial layer 101b may include one or more stacked epitaxial sublayers, such as 101b-1, 101b-2, and 101b-3, with the doped channel 101c extending across these sublayers. The number of sublayers can vary and be one or more as needed to meet particular design requirements. In some embodiments, the epitaxial layer 101b includes a first epitaxial sublayer 101b-1, a second epitaxial sublayer 101b-2, and a third epitaxial sublayer 101b-3. The first epitaxial sublayer 101b-1 is disposed above the substrate 101a, the second epitaxial sublayer 101b-2 is disposed above the first epitaxial sublayer 101b-1, and the third epitaxial sublayer 101b-3 is disposed above the second epitaxial sublayer 101b-2. The first epitaxial sublayer 101b-1, the second epitaxial sublayer 101b-2, and the third epitaxial sublayer 101b-3 all have the same conductivity type, such as N-type. The first epitaxial sublayer 101b-1 has a thickness T1, the second epitaxial sublayer 101b-2 has a thickness T2, and the third epitaxial sublayer 101b-3 has a thickness T3. In some embodiments, thicknesses T1, T2, and T3 may be essentially the same, hi some embodiments, thicknesses T1, T2, and T3 may be in the range of about 1.5 μm to 2 μm.

[0022]

[0025] In some embodiments, the doped channel 101c may include a first doped subchannel 101c-1, a second doped subchannel 101c-2, and a third doped subchannel 101c-3, where the first doped subchannel 101c-1 extends across the first epitaxial sublayer 101b-1, the second doped subchannel 101c-2 extends across the second epitaxial sublayer 101b-2, and the third doped subchannel 101c-3 extends across the third epitaxial sublayer 101b-3. The first doped subchannel 101c-1 is above the substrate 101a, the second doped subchannel 101c-2 is above the first doped subchannel 101c-1, and the third doped subchannel 101c-3 is above the second doped subchannel 101c-2. The first, second, and third doped subchannels 101c-1, 101c-2, and 101c-3 have the same conductivity type, such as all N-type. In some embodiments, the doping concentration of the first doped subchannel 101c-1 may be heavier than the doping concentration of the second doped subchannel 101c-2, and the doping concentration of the second doped subchannel 101c-2 may be heavier than the doping concentration of the third doped subchannel 101c-3. In some embodiments, the first, second, and third doped sub-channels 101c-1, 101c-2, and 101c-3 may have essentially the same doping concentration.

[0023]

[0026] In some embodiments, the epitaxial layer 101b further includes guard rings 101d and 101f, which are utilized to reduce edge or surface electric fields and thereby increase the breakdown voltage of the power semiconductor device 100. The guard rings 101d and 101f function as field-limiting rings. The epitaxial layer 101b may include a first guard ring 101d disposed between the unit area 100a and the peripheral area 100b and extending over at least a portion of the epitaxial layer 101b to mitigate the effects of high electric fields at the edges of the electrode 104. The first guard ring 101d is located near the edges of the electrode 104. The first guard ring 101d is characterized by a conductivity type opposite to that of the epitaxial layer 101b. For example, if the first guard ring 101d is p-type, the epitaxial layer 101b is n-type. The first protective ring 101d may include a p-type dopant, such as boron, aluminum, gallium, or indium. In some embodiments, the height H2 of the first protective ring 101d may be substantially equal to or less than the thickness of the epitaxial layer 101b. In some embodiments, the height H2 of the first protective ring 101d is in the range of approximately 2 μm to 6 μm.

[0024]

[0027] In some embodiments, the first guard ring 101d may include a first guard sub-ring 101d-1 and a second guard sub-ring 101d-2. The first guard sub-ring 101d-1 extends across the second epitaxial sub-layer 101b-2, and the second guard sub-ring 101d-2 extends across the third epitaxial sub-layer 101b-3. The first guard sub-ring 101d-1 is located above the first epitaxial sub-layer 101b-1, and the second guard sub-ring 101d-2 is located above the first guard sub-ring 101d-1. In some embodiments, the first guard ring 101d may further include a third guard sub-ring (not shown) extending across the first epitaxial sub-layer 101b-1. Both the first and second protective sub-rings 101d-1 and 101d-2 are of the same conductivity type, e.g., p-type. In some embodiments, the doping concentration of the first protective sub-ring 101d-1 is higher than the doping concentration of the second protective sub-ring 101d-2. In some embodiments, the first and second protective sub-rings 101d-1 and 101d-2 have substantially the same doping concentration.

[0025]

[0028] In some embodiments, the epitaxial layer 101b may also include a second guard ring 101f disposed within the peripheral area 100b and extending over at least a portion of the epitaxial layer 101b to reduce the effects of surface electric fields. In some embodiments, the second guard ring 101f extends over at least a portion of the third epitaxial sublayer 101b-3. The second guard ring 101f is disposed between the doped channel 101c and the first guard ring 101d. The second guard ring 101f surrounds not only the unit area 100a but also the first guard ring 101d. The second guard ring 101f and the first guard ring 101d are of the same conductivity type, for example, both p-type. The second guard ring 101f has the opposite conductivity type to the epitaxial layer 101b; for example, if the second guard ring 101f is p-type, the epitaxial layer 101b is n-type.

[0026]

[0029] In some embodiments, the doping concentration of the second guard ring 101f is equal to or less than the doping concentration of the first guard ring 101d. In some embodiments, the height of the second guard ring 101f is substantially equal to or less than the thickness T3 of the third epitaxial sublayer 101b-3. In some embodiments, the height of the second guard ring 101f is about 2 μm or less. In some embodiments, the second guard ring 101f functions as a floating field limiting ring and is not electrically connected to circuits or components within the unit area 100a.

[0027]

[0030] The epitaxial layer 101b may also include a doped region 101e disposed within the unit area 100a and extending across at least a portion of the epitaxial layer 101b. The doped region 101e serves as an active area, and the electrode 104 is strategically positioned above it. In some embodiments, the doped region 101e is surrounded by a first guard ring 101d. The doped region 101e has an opposite conductivity type to the epitaxial layer 101b; for example, if the doped region 101e is p-type, the epitaxial layer 101b is n-type. The doped region 101e has an opposite conductivity type to the doped channel 101c; for example, if the doped region 101e is p-type, the doped channel 101c is n-type. The doped region 101e includes a p-type dopant, such as boron, aluminum, gallium, or indium. The deeper doped region 101e extends into the thickness of epitaxial layer 101b, the more it can reduce the effect of the surface electric field, thereby lowering the leakage current of power semiconductor device 100. In some embodiments, the height of doped region 101e is substantially equal to or less than the thickness of epitaxial layer 101b. In some embodiments, the height of doped region 101e is in the range of approximately 2 μm to 6 μm.

[0028]

[0031] The doped region 101e may include a first doped subregion 101e-1 and a second doped subregion 101e-2. The first doped subregion 101e-1 extends across the second epitaxial sublayer 101b-2, and the second doped subregion 101e-2 extends across the third epitaxial sublayer 101b-3. The first doped subregion 101e-1 is located above the first epitaxial sublayer 101b-1, and the second doped subregion 101e-2 is located above the first doped subregion 101e-1. In some embodiments, the doped region 101e may further include a third doped subregion (not shown) extending across the first epitaxial sublayer 101b-1. Both the first subregion 101e-1 and the second doped subregion 101e-2 are of the same conductivity type, for example, p-type. The first guard ring 101d, the second guard ring 101f, and the doped region 101e are of the same conductivity type, for example, all p-type. In some embodiments, the first doped subregion 101e-1 and the second doped subregion 101e-2 have substantially the same doping concentration. In some embodiments, the doping concentration of the first doped subregion 101e-1 is higher than the doping concentration of the second doped subregion 101e-2.

[0029]

[0032] The power semiconductor device 100 may also include a dielectric layer 102 disposed above the base 101. The dielectric layer 102 is located above the epitaxial layer 101b and surrounds at least a portion of the contact layer 103 and at least a portion of the electrode 104. In some embodiments, the dielectric layer 102 covers at least a portion of the second guard ring 101f and the first guard ring 101d. In some embodiments, the dielectric layer 102 may include an insulating material, such as an oxide, a nitride, or an oxynitride. In some embodiments, the dielectric layer 102 may include silica. In some embodiments, the dielectric layer 102 may be a field oxide.

[0030]

[0033] The contact layer 103 may include a junction layer 103a and a barrier layer 103b. The junction layer 103a is located above the epitaxial layer 101b in the peripheral area 100b. In some embodiments, at least a portion of the junction layer 103a is surrounded by the dielectric layer 102, and at least a portion of the junction layer 103a is above the dielectric layer 102. The junction layer 103a contacts at least a portion of the epitaxial layer 101b. The junction layer 103a contacts at least a portion of the doped channel 101c. In some embodiments, the junction layer 103a contacts a third doped channel 101c-3. The doped channel 101c extends between the junction layer 103a and the substrate 101a. In some embodiments, an ohmic or non-ohmic contact is formed between the junction layer 103a and the doped channel 101c, allowing current to flow from the junction layer 103a to the doped channel 101c or from the doped channel 101c to the junction layer 103a. In some embodiments, the junction layer 103a may include a metallic material such as aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc. In some embodiments, the junction layer 103a is ohmic or non-ohmic.

[0031]

[0034] Barrier layer 103b is disposed above epitaxial layer 101b within unit area 100a. In some embodiments, at least a portion of barrier layer 103b is surrounded by dielectric layer 102, and at least a portion of barrier layer 103b is above dielectric layer 102. Barrier layer 103b contacts at least a portion of epitaxial layer 101b. Doped region 101e extends between barrier layer 103b and substrate 101a. Barrier layer 103b contacts at least a portion of doped region 101e. In some embodiments, barrier layer 103b contacts second doped subregion 101e-2. In some embodiments, a Schottky contact or a non-ohmic contact is formed between barrier layer 103b and doped region 101e, allowing current to flow from barrier layer 103b to doped region 101e. In some embodiments, current is essentially unable to flow from doped region 101e to barrier layer 103b. In some embodiments, barrier layer 103b may include a metallic material such as platinum (Pt), titanium (Ti), nickel (Ni), or gold (Au). In some embodiments, barrier layer 103b is non-ohmic. In some embodiments, barrier layer 103b is a Schottky metal. Barrier layer 103b contacts at least a portion of first protective ring 101d. In some embodiments, barrier layer 103b contacts second protective sub-ring 101d-2. First protective ring 101d extends between barrier layer 103b and substrate 101a.

[0032]

[0035] The electrode 104 may include a first electrode 104a and a second electrode 104b. The first electrode 104a is disposed on the junction layer 103a, and the second electrode 104b is disposed on the barrier layer 103b. In some embodiments, both the first electrode 104a and the second electrode 104b are disposed on the top side of the power semiconductor device 100. In some embodiments, both the first electrode 104a and the second electrode 104b are disposed on the same side of the power semiconductor device 100. The first electrode 104a is disposed within the peripheral area 100b, and the second electrode 104b is disposed within the unit area 100a. In some embodiments, at least a portion of the first electrode 104a and at least a portion of the second electrode 104b are surrounded by the dielectric layer 102, and at least a portion of the first electrode 104a and at least a portion of the second electrode 104b are above the dielectric layer 102. The first electrode 104a contacts at least a portion of the junction layer 103a. The second electrode 104b contacts at least a portion of the barrier layer 103b. In some embodiments, the first electrode 104a and the second electrode 104b may each comprise a conductive material, such as a metallic material such as copper (Cu), silver (Ag), or gold (Au). In some embodiments, current may flow from the substrate 101a through the doped channel 101c and the junction layer 103a to the first electrode 104a. In some embodiments, current may flow from the second electrode 104b through the doped region 101e and the barrier layer 103b to the substrate 101a. In some embodiments, current may flow from the second electrode 104b through the barrier layer 103b, the doped region 101e, the substrate 101a, the doped channel 101c, and the junction layer 103a to the first electrode 104a. In some embodiments, the first electrode 104a is a cathode or negative electrode and the second electrode 104b is an anode or positive electrode.

[0033]

[0036] The power semiconductor device 100 may also include a passivation layer 105 disposed over the dielectric layer 102, the first electrode 104a, and the second electrode 104b. In some embodiments, the passivation layer 105 may include an insulating material such as a polymer, a polyimide (PI), an oxide, a nitride, or an oxynitride. In some embodiments, at least a portion of the first electrode 104a and at least a portion of the second electrode 104b are exposed by the passivation layer 105. The dielectric layer 102 and the passivation layer 105 separate the junction layer 103a and the first electrode 104a from the barrier layer 103b and the second electrode 104b.

[0034]

[0037] The power semiconductor device 100 may also include a plurality of conductive bumps 106 individually disposed above the electrodes 104. The plurality of conductive bumps 106 are surrounded by a passivation layer 105. In some embodiments, the conductive bumps 106 may include a conductive material such as tin, lead, silver, copper, or nickel. In some embodiments, the conductive bumps 106 may be solder balls or tin balls. The conductive bumps 106 can electrically connect the power semiconductor device 100 to an external circuit or component, enabling external electrical connection of the power semiconductor device 100. In some embodiments, the plurality of conductive bumps 106 includes a first conductive bump 106a and a second conductive bump 106b. The first conductive bump 106a is disposed within the peripheral area 100b, and the second conductive bump 106b is disposed within the unit area 100a. The first conductive bump 106a is disposed above the first electrode 104a, and the second conductive bump 106b is disposed above the second electrode 104b. In some embodiments, the first conductive bump 106a is disposed above at least a portion of the first electrode 104a exposed by the passivation layer 105, and the second conductive bump 106b is disposed above at least a portion of the second electrode 104b exposed by the passivation layer 105. The first conductive bump 106a is electrically connected to the first electrode 104a, and the second conductive bump 106b is electrically connected to the second electrode 104b. The first conductive bump 106a and the second conductive bump 106b are separated by the passivation layer 105. In some embodiments, the power semiconductor device 100 may not include the plurality of conductive bumps 106, for example, the plurality of conductive bumps 106 may be replaced by wire bonds contacting the electrodes 104.

[0035]

[0038] In some embodiments, the epitaxial layer 101b of the power semiconductor device 100 may be formed by stacking multiple sub-epitaxial layers 101b-1, 101b-2, and 101b-3. This configuration allows the epitaxial layer 101b to be thick, which reduces leakage current of the power semiconductor device 100 and enables its use in high voltage applications.

[0036]

[0039] FIG. 2 is a cross-sectional view of another power semiconductor device 200 according to various embodiments of the present disclosure. Specifically, the power semiconductor device 200 includes similar features to the power semiconductor device 100 shown in FIG. 1 , except that the power semiconductor device 200 further includes a semiconductor component 107 disposed between and extending between the doped channel 101c and the substrate 101a. The semiconductor component 107 is surrounded by the substrate 101a and the epitaxial layer 101b and extends through a portion of the epitaxial layer 101b. The semiconductor component 107 is located within the peripheral area 100b, and the doped channel 101c extends between the contact layer 103 and the semiconductor component 107. Current can flow from the substrate 101a through the semiconductor component 107, the doped channel 101c, and the contact layer 103 to the first electrode 104a. In some embodiments, the semiconductor component 107 may include a semiconductor material, such as polysilicon. The semiconductor component 107 does not participate in the diffusion or ion implantation process. Compared to the power semiconductor device 100, the power semiconductor device 200 including the semiconductor component 107 reduces the diffusion or ion implantation process, thereby lowering the thermal budget of the power semiconductor device 200 and increasing its reliability.

[0037]

[0040] In some embodiments, the semiconductor component 107 is surrounded by and extends through the first epitaxial sublayer 101b-1. In some embodiments, the height H3 of the semiconductor component 107 is substantially equal to or less than the height H1 of the doped channel 101c. In some embodiments, the height H3 of the semiconductor component 107 is substantially equal to or less than the thickness T1 of the first epitaxial sublayer 101b-1. In some embodiments, the height H3 of the semiconductor component 107 is about 2 μm.

[0038]

[0041] In some embodiments, the semiconductor component 107 may be surrounded by the first epitaxial sublayer 101b-1 and the second epitaxial sublayer 101b-2 and extends through both the first epitaxial sublayer 101b-1 and the second epitaxial sublayer 101b-2. In some embodiments, the height H3 of the semiconductor component 107 is substantially equal to or greater than the height H1 of the doped channel 101c. In some embodiments, the height H3 of the semiconductor component 107 is substantially greater than the thickness T1 of the first epitaxial sublayer 101b-1. In some embodiments, the height H3 of the semiconductor component 107 is substantially greater than the thickness T2 of the second epitaxial sublayer 101b-2. In some embodiments, the height H3 of the semiconductor component 107 may be greater than 2 μm.

[0039]

[0042] 3 is a cross-sectional view of another power semiconductor device 300 according to various embodiments of the present disclosure. Specifically, the power semiconductor device 300 includes similar features to the power semiconductor device 200 shown in FIG. 2 , except that the semiconductor component 107 includes multiple components. At least a portion of the epitaxial layer 101b is disposed between two adjacent components of the semiconductor component 107, and at least a portion of the epitaxial layer 101b extends between the doped channel 101c and the substrate 101a and is surrounded by multiple components of the semiconductor component 107. In some embodiments, the height H3 of the semiconductor component 107 is substantially equal to or greater than the height H1 of the doped channel 101c. In some embodiments, the height H3 of the semiconductor component 107 is substantially equal to the thickness T1 of the first epitaxial sublayer 101b-1. In some embodiments, the thickness T1 of the first epitaxial sublayer 101b-1 is substantially greater than the thickness T2 of the second epitaxial sublayer 101b-2 or the thickness T3 of the third epitaxial sublayer 101b-3. In some embodiments, the height H3 of the semiconductor component 107 is substantially 5 μm or greater. Compared to the semiconductor component 107 in the power semiconductor device 200, each element of the semiconductor component 107 in the power semiconductor device 300 has a high aspect ratio, which provides favorable uniformity when filling the semiconductor material between the layers of the epitaxial layer 101b, and therefore forms favorable and reliable components of the semiconductor component 107.

[0040]

[0043] 4-44 illustrate one or more stages in a method for manufacturing a power semiconductor device 100 according to various embodiments of the present disclosure. Some of these figures are simplified to facilitate understanding of the disclosure presented herein.

[0041]

[0044] 4-5, the manufacturing method includes forming a first epitaxial sublayer 101b-1 above a substrate 101a. Epitaxial growth is performed on the substrate 101a to form the first epitaxial sublayer 101b-1. In some embodiments, the substrate 101a and the first epitaxial sublayer 101b-1 have the same conductivity type doping, such as both being n-type. In some embodiments, ion implantation may be performed simultaneously with the epitaxial growth, implanting ions having n-type electrical properties, such as phosphorus (P) or arsenic (As), to form the n-type first epitaxial sublayer 101b-1. In some embodiments, both the substrate 101a and the first epitaxial sublayer 101b-1 may comprise silicon carbide. In some embodiments, the first epitaxial sub-layer 101b-1 has a thickness T1, which is in the range of about 1.5 μm to 2 μm.

[0042]

[0045] 6-10, the fabrication method includes implanting doping ions into a portion of the first epitaxial sublayer 101b-1 to form a first doped channel 101c-1. Referring to FIG. 6, a first patterned masking layer 108 is formed on the first epitaxial sublayer 101b-1 to define the location of the first doped channel 101c-1. In some embodiments, the first patterned masking layer 108 may include a material such as photoresist or oxide. The first patterned masking layer 108 features a first opening 108a that exposes a portion of the first epitaxial sublayer 101b-1 to form the first doped channel 101c-1. Referring to FIG. 7 , the first doped channel 101c-1 can be formed by a diffusion or ion implantation process performed through the surface of the first epitaxial sublayer 101b-1 exposed at the first opening 108a. The substrate 101a, the first epitaxial sublayer 101b-1, and the first doped channel 101c-1 have the same conductivity type. In some embodiments, doping ions, such as phosphorus ions or arsenic ions, are implanted through the surface of the first epitaxial sublayer 101b-1 exposed at the first opening 108a to form the first doped channel 101c-1. Referring to FIG. 8 , after the diffusion or ion implantation process, the first patterned masking layer 108 is removed. In some embodiments, an etching process, such as plasma dry etching, is performed to remove the first patterned masking layer 108. 9, after removal of the first patterned masking layer 108, a first protective layer 109 is formed on the first epitaxial sublayer 101b-1 to protect the first epitaxial sublayer 101b-1 and the first doped channel 101c-1 during an annealing process. In some embodiments, the first protective layer 109 may include carbon. After forming the first protective layer 109, the first doped channel 101c-1 is subjected to an annealing process, such as high temperature rapid annealing (RTA) or laser annealing, to activate doping ions in the first doped channel 101c-1.Referring to FIG. 10, after the annealing process, the first protective layer 109 may be removed by a process such as dry thermal oxidation, plasma etching, or other etching techniques.

[0043]

[0046] 11 , the fabrication method may also include forming a second epitaxial sublayer 101b-2 above the first epitaxial sublayer 101b-1. To form the second epitaxial sublayer 101b-2, epitaxial growth is performed above the first epitaxial sublayer 101b-1. In some embodiments, the substrate 101a, the first epitaxial sublayer 101b-1, and the second epitaxial sublayer 101b-2 have the same conductivity type doping, such as the second epitaxial sublayer 101b-2 and the first epitaxial sublayer 101b-1 both being n-type. In some embodiments, ion implantation may be performed simultaneously with epitaxial growth, implanting ions having n-type electrical properties, such as phosphorus (P) or arsenic (As), to form an n-type second epitaxial sublayer 101b-2. In some embodiments, the substrate 101a, the first epitaxial sublayer 101b-1, and the second epitaxial sublayer 101b-2 may all comprise silicon carbide. In some embodiments, the first epitaxial sublayer 101b-1 has a thickness T1, and the second epitaxial sublayer 101b-2 has a thickness T2, where T1 and T2 are substantially the same and are in the range of approximately 1.5 μm to 2 μm.

[0044]

[0047] 12-14, the fabrication method may include implanting doping ions into a portion of the second epitaxial sublayer 101b-2 to form a second doped channel 101c-2 above the first doped channel 101c-1. Referring to FIG. 12, a second patterned masking layer 110 is formed above the second epitaxial sublayer 101b-2 to define the location of the second doped channel 101c-2. In some embodiments, the second patterned masking layer 110 may comprise photoresist or oxide. The second patterned masking layer 110 features a second opening 110a through which the portion of the second epitaxial sublayer 101b-2 exposed at the second opening 110a forms the second doped channel 101c-2. 13, the second doped channel 101c-2 can be formed by a diffusion or ion implantation process performed through the surface of the second epitaxial sublayer 101b-2 exposed at the second opening 110a. The second epitaxial sublayer 101b-2 and the second doped channel 101c-2 have the same conductivity type. In some embodiments, doping ions, such as phosphorus ions or arsenic ions, are implanted through the surface of the second epitaxial sublayer 101b-2 exposed at the second opening 110a to form the second doped channel 101c-2. In some embodiments, the doping concentration of the first doped subchannel 101c-1 is higher than the doping concentration of the second doped subchannel 101c-2.

[0045]

[0048] 14, after the diffusion or ion implantation process, the second patterned masking layer 110 is removed. In some embodiments, an etching process, such as plasma dry etching, is performed to remove the second patterned masking layer 110.

[0046]

[0049] 15 , after removal of second patterned masking layer 110, a third patterned masking layer 111 is formed on second epitaxial sublayer 101b-2 to define the location of first protective sub-ring 101d-1 and first doped sub-region 101e-1. In some embodiments, third patterned masking layer 111 comprises photoresist or oxide. Third patterned masking layer 111 features third opening 111a, which may include multiple sub-openings, through which portions of second epitaxial sublayer 101b-2 are exposed to form first protective sub-ring 101d-1 and first doped sub-region 101e-1. Referring to FIG. 16, the first protective sub-ring 101d-1 and the first doped sub-region 101e-1 can be formed by a diffusion or ion implantation process performed from the surface of the second epitaxial sub-layer 101b-2 exposed at the third opening 111a. The first protective sub-ring 101d-1 and the first doped sub-region 101e-1 have the same conductivity type, such as both p-type. P-type dopants can include, for example, boron, aluminum, gallium, indium, etc. In some embodiments, doping ions, such as boron ions, can be implanted from the surface of the second epitaxial sub-layer 101b-2 exposed at the third opening 111a to form the first protective sub-ring 101d-1 and the first doped sub-region 101e-1. Referring to FIG. 17, after the diffusion or ion implantation process, the third patterned masking layer 111 is removed. In some embodiments, an etching process, such as plasma dry etching, is performed to remove the third patterned masking layer 111.

[0047]

[0050] 18, after removing the third patterned masking layer 111, a second protective layer 112 is formed on the second epitaxial sublayer 101b-2 to protect the second epitaxial sublayer 101b-2, the first protective subring 101d-1, the first doped subregion 101e-1, and the second doped channel 101c-2 during an annealing process. After forming the second protective layer 112, the first protective subring 101d-1, the first doped subregion 101e-1, and the second doped channel 101c-2 are subjected to an annealing process, such as high-temperature short-time annealing (RTA) or laser annealing, to activate doping ions in the first protective subring 101d-1, the first doped subregion 101e-1, and the second doped channel 101c-2. Referring to FIG. 19, after the annealing process, an etching process, such as plasma dry etching, is performed to remove the second protective layer 112.

[0048]

[0051] 20 , the fabrication method may include forming a third epitaxial sublayer 101b-3 above the second epitaxial sublayer 101b-2. Epitaxial growth is performed above the second epitaxial sublayer 101b-2 to form the third epitaxial sublayer 101b-3. In some embodiments, the substrate 101a, the first epitaxial sublayer 101b-1, the second epitaxial sublayer 101b-2, and the third epitaxial sublayer 101b-3 have the same conductivity type doping, such as the first epitaxial sublayer 101b-1, the second epitaxial sublayer 101b-2, and the third epitaxial sublayer 101b-3 all being n-type. In some embodiments, ion implantation is performed simultaneously with epitaxial growth, implanting ions having n-type electrical properties, such as phosphorus (P) or arsenic (As), to form n-type third epitaxial sublayer 101b-3. In some embodiments, substrate 101a, first epitaxial sublayer 101b-1, second epitaxial sublayer 101b-2, and third epitaxial sublayer 101b-3 may all comprise silicon carbide. In some embodiments, third epitaxial sublayer 101b-3 has a thickness T3, where thicknesses T1, T2, and T3 are substantially the same and thickness T3 is in the range of approximately 1.5 μm to 2 μm. In some embodiments, epitaxial layer 101b is composed of a first epitaxial sublayer 101b-1, a second epitaxial sublayer 101b-2, and a third epitaxial sublayer 101b-3, with substrate 101a and the combined epitaxial layers collectively forming base 101.

[0049]

[0052] 21-23, the fabrication method may include doping a portion of the third epitaxial sublayer 101b-3 to form a third doped channel 101c-3. As shown in FIG. 21, a fourth patterned masking layer 113 is formed on the third epitaxial sublayer 101b-3 to define the location of the third doped channel 101c-3. In some embodiments, the fourth patterned masking layer 113 may include a material such as photoresist or oxide. The fourth patterned masking layer 113 has a fourth opening 113a that exposes a portion of the third epitaxial sublayer 101b-3 to form the third doped channel 101c-3. 22, a third doped channel 101c-3 can be formed by a diffusion or ion implantation process performed through the surface of the third epitaxial sublayer 101b-3 exposed at the fourth opening 113a. The substrate 101a, the first epitaxial sublayer 101b-1, the first doped channel 101c-1, the second epitaxial sublayer 101b-2, the second doped channel 101c-2, the third epitaxial sublayer 101b-3, and the third doped channel 101c-3 all have the same conductivity type. In some embodiments, doping ions such as phosphorus or arsenic may be implanted through the surface of the third epitaxial sublayer 101b-3 exposed at the fourth opening 113a to form the third doped channel 101c-3. 23, the fourth patterned masking layer 113 is removed after the diffusion or ion implantation process. In some embodiments, the fourth patterned masking layer 113 is removed using an etching process, such as plasma dry etching. In some embodiments, the doped channel 101c is formed by the first doped subchannel 101c-1, the second doped subchannel 101c-2, and the third doped subchannel 101c-3.In some embodiments, the doping concentration of the first doping subchannel 101c-1 is heavier than the doping concentration of the second doping subchannel 101c-2, which is heavier than the doping concentration of the third doping subchannel 101c-3. In some embodiments, the first doping subchannel 101c-1, the second doping subchannel 101c-2, and the third doping subchannel 101c-3 each have substantially the same doping concentration.

[0050]

[0053] 24, after removal of the fourth patterned masking layer 113, a fifth patterned masking layer 114 is formed on the third epitaxial sublayer 101b-3 to define the location of the second protective subring 101d-2 and the second doped subregion 101e-2. The fifth masking layer 114 may comprise a material such as photoresist or oxide. The fifth masking layer 114 features a fifth opening 114a, which may include multiple subopenings, through which a portion of the third epitaxial sublayer 101b-3 is exposed to form the second protective subring 101d-2 and the second doped subregion 101e-2. As shown in FIG. 25, the second protective sub-ring 101d-2 and the second doped sub-region 101e-2 may be formed by diffusion or ion implantation from the surface of the third epitaxial sub-layer 101b-3 exposed by the fifth opening 114a. The first protective sub-ring 101d-1, the second protective sub-ring 101d-2, the first doped sub-region 101e-1, and the second doped sub-region 101e-2 are of the same conductivity type, such as p-type. P-type dopants may include, but are not limited to, boron, aluminum, gallium, and indium. In some embodiments, to form the second protective sub-ring 101d-2 and the second doped sub-region 101e-2, doping ions, such as boron ions, are implanted from the surface of the third epitaxial sub-layer 101b-3 exposed through the fifth opening 114a. 26 , following the diffusion or ion implantation process, the fifth patterned masking layer 114 is removed. In some embodiments, the fifth patterned masking layer 114 is removed using an etching process, such as plasma dry etching. In some embodiments, the first protective sub-ring 101d-1 and the second protective sub-ring 101d-2 together constitute the first protective ring 101d, while the first doped sub-region 101e-1 and the second doped sub-region 101e-2 together form the doped region 101e. In some embodiments, the doping concentration of the first doped sub-region 101e-1 is higher than the doping concentration of the second doped sub-region 101e-2.In various embodiments, the doping concentration of the first protective sub-ring 101d-1 is higher than the doping concentration of the second protective sub-ring 101d-2.

[0051]

[0054] 27, after removal of the fifth patterned masking layer 114, a sixth patterned masking layer 115 is formed on the third epitaxial sublayer 101b-3 to define the location of the second protective ring 101f. In some embodiments, the sixth patterned masking layer 115 may comprise a photoresist or an oxide material. The sixth patterned masking layer 115 features a sixth opening 115a, which may include multiple sub-openings, through which a portion of the third epitaxial sublayer 101b-3 is exposed to form the second protective ring 101f. As shown in FIG. 28, the second protective ring 101f may be formed by diffusion or ion implantation from the surface of the third epitaxial sublayer 101b-3 exposed through the sixth opening 115a. The first protective sub-ring 101d-1, the second protective sub-ring 101d-2, and the second protective ring 101f all share the same conductivity type, e.g., P-type. P-type dopants may include, but are not limited to, boron, aluminum, gallium, and indium. In some embodiments, to form the second protective ring 101f, dopant ions, such as boron ions, are implanted through the surface of the third epitaxial sub-layer 101b-3 exposed by the sixth opening 115a. Referring to FIG. 29 , following the diffusion or ion implantation process, the sixth patterned masking layer 115 is removed. In some embodiments, the sixth patterned masking layer 115 may be removed by an etching process, such as plasma dry etching. In some embodiments, the doping concentration of the second protective ring 101f is equal to or less than the doping concentration of the first protective sub-ring 101d-1. In some embodiments, the height of the second guard ring 101f is substantially equal to or less than the thickness T3 of the third epitaxial sub-layer 101b-3.

[0052]

[0055] 30, following removal of the sixth patterned masking layer 115, a third protective layer 116 is formed on the third epitaxial sublayer 101b-3 to protect the third epitaxial sublayer 101b-3, the second protective subring 101d-2, the second doped subregion 101e-2, and the third doped channel 101c-3 during the annealing process. After the formation of the third protective layer 116, the second protective subring 101d-2, the second doped subregion 101e-2, and the third doped channel 101c-3 are subjected to an annealing process, such as high-temperature short-time annealing (RTA) or laser annealing, to activate the dopant ions in these regions. As shown in FIG. 31, after the annealing process, the third protective layer 116 may be removed by an etching process, such as plasma dry etching.

[0053]

[0056] In some embodiments, with reference to FIGS. 32-34, a dielectric layer 102 is formed over epitaxial layer 101b. As shown in FIG. 32, a dielectric material 102′ (not shown) covers epitaxial layer 101b, and a seventh patterned masking layer 117 is formed on dielectric material 102′. In some embodiments, dielectric material 102′ is formed using thermal oxidation or other deposition techniques. Dielectric material 102′ may comprise an oxide. In some embodiments, seventh patterned masking layer 117 may comprise photoresist. Seventh patterned masking layer 117 features a seventh opening 117a, which may include multiple sub-openings, through which a portion of dielectric material 102′ is exposed. The exposed portion of dielectric material 102′ is removed to form dielectric layer 102, as shown in FIG. 33. In some embodiments, dielectric layer 102 is a field oxide. Following the formation of the dielectric layer 102, the seventh patterned masking layer 117 is removed, as shown in Figure 34. In some embodiments, the seventh patterned masking layer 117 is removed by an etching process, such as plasma dry etching.

[0054]

[0057] In some embodiments, a contact layer 103 and an electrode 104 are formed above the epitaxial layer 101b, as shown in Figures 35-39. In some embodiments, a junction layer 103a, a barrier layer 103b, a first electrode 104a, and a second electrode 104b are formed on the third epitaxial sublayer 101b-3, partially surrounded by a dielectric layer 102. Referring to Figure 35, a contact layer material 103' covers the epitaxial layer 101b and the dielectric layer 102. In some embodiments, the contact layer material 103' is deposited on the epitaxial layer 101b and the dielectric layer 102 using plating, chemical vapor deposition (CVD), or other deposition techniques. In some embodiments, the contact layer material 103′ may include a metal material such as aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), or gold (Au). As shown in FIG. 36, an electrode material 104′ covers the contact layer material 103′. In some embodiments, the electrode material 104′ is deposited on the contact layer material 103′ using plating, chemical vapor deposition (CVD), or other deposition methods. In some embodiments, the electrode material 104′ may include a conductive material including a metal such as copper (Cu), silver (Ag), or gold (Au). Following deposition, an eighth patterned masking layer 118 is formed on the electrode material 104′, as shown in FIG. 37. In some embodiments, the eighth patterned masking layer 118 may include a photoresist. The eighth patterned masking layer 118 features an eighth opening 118a, which may include multiple sub-openings, through which a portion of the electrode material 104' is exposed.

[0055]

[0058] 38 , the portions of the electrode material 104′ exposed through the eighth opening 118a, along with the portions of the contact layer material 103′ exposed by the subsequent removal of the electrode material 104′, result in the formation of the contact layer 103 and the electrode 104. In some embodiments, the exposed portions of the electrode material 104′ and the contact layer material 103′ exposed by the subsequent removal of the electrode material 104′ are subjected to an etching process to remove these exposed portions. In some embodiments, the formed contact layer 103 may include a junction layer 103a and a barrier layer 103b, and the formed electrode 104 may include a first electrode 104a and a second electrode 104b. In some embodiments, within the peripheral area 100b, above the doped channel 101c, a junction layer 103a is formed, and a first electrode 104a is formed thereon. In some embodiments, within the unit area 100a, a barrier layer 103b is formed above the doped region 101e and the guard ring 101d, and a second electrode 104b is formed thereon. In some embodiments, the doped channel 101c extends between the junction layer 103a and the substrate 101a. As shown in FIG. 39, after forming the contact layer 103 and the electrode 104, the eighth patterned masking layer 118 is removed. In some embodiments, the eighth patterned masking layer 118 is removed using an etching process, such as plasma dry etching.

[0056]

[0059] In some embodiments, a passivation layer 105 is formed on the dielectric layer 102, the first electrode 104a, and the second electrode 104b, as shown in Figures 40-43. Referring to Figure 40, a passivation layer material 105' coats the dielectric layer 102, the first electrode 104a, and the second electrode 104b. In some embodiments, the passivation layer material 105' is applied on the dielectric layer 102, the first electrode 104a, and the second electrode 104b using a deposition technique or other method. In some embodiments, the passivation layer material 105' may include an insulating material, such as a polymer, polyimide (PI), oxide, nitride, or oxynitride. Referring to Figure 41, after the passivation layer material 105' is applied, a ninth patterned masking layer 119 is formed on the passivation layer material 105'. In some embodiments, this ninth patterned masking layer 119 may comprise a photoresist material. The ninth patterned masking layer 119 features a ninth opening 119a, which may include multiple sub-openings, through which a portion of the passivation layer material 105′ is exposed. As shown in FIG. 42, the exposed portion of the passivation layer material 105′ is removed to create the passivation layer 105. In some embodiments, the exposed portion of the passivation layer material 105′ is subjected to an etching process to remove the portion. In some embodiments, at least a portion of the first electrode 104a and the second electrode 104b is exposed by the passivation layer 105. The dielectric layer 102 and the passivation layer 105 separate the junction layer 103a and the first electrode 104a from the barrier layer 103b and the second electrode 104b. 43, after the formation of the passivation layer 105, the ninth patterned masking layer 119 is removed. In some embodiments, the ninth patterned masking layer 119 is removed using an etching process, such as plasma dry etching.

[0057]

[0060] 44, a plurality of conductive bumps 106 are formed above the electrodes 104. In some embodiments, the conductive bumps 106 include a conductive material such as tin, lead, silver, copper, and nickel. In some embodiments, the conductive bumps 106 may be in the form of solder balls, tin balls, or the like. In some embodiments, the plurality of conductive bumps 106 include a first conductive bump 106a and a second conductive bump 106b. The first conductive bump 106a is located within the peripheral area 100b above the first electrode 104a, and the second conductive bump 106b is located within the unit area 100a above the second electrode 104b. In some embodiments, a first conductive bump 106a is formed on at least a portion of the first electrode 104a exposed by the passivation layer 105, and similarly, a second conductive bump 106b is formed on at least a portion of the second electrode 104b exposed by the passivation layer 105. The passivation layer 105 serves to electrically isolate the first conductive bump 106a from the second conductive bump 106b. As shown in FIG. 44, this configuration results in a power semiconductor device 100 similar to that shown in FIG. 1. In some embodiments, the power semiconductor device 100 may not include the plurality of conductive bumps 106; for example, the plurality of conductive bumps 106 may be replaced by wire bonds contacting the electrodes 104.

[0058]

[0061] 4-5, 45-48, 11-43, and 49 illustrate one or more various stages in the manufacturing process of power semiconductor device 200 according to some embodiments of the present disclosure.

[0059]

[0062] As shown in FIGS. 4-5, fabrication of the power semiconductor device 200 may include forming a first epitaxial layer 101b-1 on a substrate 101a. The first epitaxial layer 101b-1 is formed by epitaxial growth on the substrate 101a. Referring to FIG. 45, following the formation of the first epitaxial layer 101b-1, a first patterned masking layer 108 is formed on the first epitaxial layer 101b-1 to define the location of a subsequent semiconductor component 107. In some embodiments, the first patterned masking layer 108 includes a first opening 108a that exposes a portion of the first epitaxial layer 101b-1. As shown in FIG. 46, a portion of the exposed first epitaxial layer 101b-1 is removed to create a tenth opening 120, exposing a portion of the substrate 101a. In some embodiments, the exposed portions of the first epitaxial layer 101b-1 are removed by an etching process. Following the formation of the tenth opening 120, the first patterned masking layer 108 is removed, as shown in FIG. 47. In some embodiments, the first patterned masking layer 108 is removed by an etching process, such as plasma dry etching. As shown in FIG. 48, the tenth opening 120 is filled with a semiconductor material to form the semiconductor component 107. The semiconductor component 107 may be formed using methods such as sputtering, physical vapor deposition (PVD), or other deposition techniques. In some embodiments, the semiconductor component 107 comprises a semiconductor material, such as polycrystalline silicon. Following the formation of the semiconductor component 107, the steps shown in FIGS. 11-43 are performed. After these steps, the power semiconductor device 200, as shown in FIG. 2, is formed, as shown in FIG. 49. The semiconductor component 107 is located between the substrate 101 a and the doped channel 101 c, is surrounded by the substrate 101 a and the epitaxial layer 101 b, and extends through a portion of the epitaxial layer 101 b. The semiconductor component 107 is located in the peripheral area 100 b, and the doped channel 101 c extends between the junction layer 103 a and the semiconductor component 107.

[0060]

[0063] 4-5, 50-53, 11-43, and 54 illustrate one or more stages in the manufacturing process of a power semiconductor device 300 according to various embodiments of the present disclosure.

[0061]

[0064] As shown in FIGS. 4-5, the manufacturing process for the power semiconductor device 300 may include forming a first epitaxial layer 101b-1 above a substrate 101a. As shown in FIG. 50, following epitaxial growth on the substrate 101a to form the first epitaxial layer 101b-1, a first patterned masking layer 108 is formed on the first epitaxial layer 101b-1 to define the locations of various semiconductor components 107. In some embodiments, the first patterned masking layer 108 may include a plurality of first openings 108a through which various portions of the first epitaxial layer 101b-1 are exposed. As shown in FIG. 51, the exposed portions of the first epitaxial layer 101b-1 are removed to form a plurality of tenth openings 120 exposing portions of the substrate 101a. In some embodiments, the exposed portions of the first epitaxial layer 101b-1 are removed by an etching process. After forming the plurality of tenth openings 120, the first patterned masking layer 108 is removed, as shown in FIG. 52. In some embodiments, the first patterned masking layer 108 may be removed by an etching process, such as plasma dry etching. As shown in FIG. 53, the plurality of tenth openings 120 are filled with a semiconductor material to form various semiconductor components 107. These semiconductor components may be formed using methods such as sputtering, physical vapor deposition (PVD), or other deposition techniques. In some embodiments, each of the semiconductor components 107 comprises a semiconductor material, such as polycrystalline silicon. Following the formation of the various semiconductor components 107, the steps shown in FIGS. 11-43 are performed. After these steps, a power semiconductor device 300, such as that shown in FIG. 3, is formed, as shown in FIG. 54. The semiconductor components 107 are located between the substrate 101 a and the doped channels 101 c and are surrounded by the substrate 101 a and the epitaxial layer 101 b, with each component extending through a portion of the epitaxial layer 101 b. Each of the semiconductor components 107 is located within the peripheral area 100 b, with the doped channels 101 c extending between the junction layer 103 a and the various semiconductor components 107.

[0062]

[0065] According to the structures and methods disclosed herein, under the same purpose and concept, the steps of the above-described processes may be adjusted or their order changed to achieve the same or similar semiconductor structures.

[0063]

[0066] Further embodiments are provided below. A power semiconductor device comprises a base including a substrate and an epitaxial layer located above the substrate, the base having a unit area and a peripheral area surrounding the unit area. A junction layer is located above the epitaxial layer in the peripheral area. A barrier layer is located above the epitaxial layer in the unit area. A first electrode is located on the junction layer and a second electrode is located on the barrier layer. The epitaxial layer includes a doped channel located in the peripheral area extending between the junction layer and the base substrate. Current flows from the substrate through the doped channel and the junction layer to the first electrode.

[0064]

[0067] In a particular embodiment of the power semiconductor device, the height of the doped channel and the thickness of the epitaxial layer range from about 2 μm to 6 μm.

[0065]

[0068] In a particular embodiment of the power semiconductor device, the substrate comprises silicon carbide (SiC).

[0066]

[0069] In certain embodiments of the power semiconductor device, the substrate and the doped channel have the same conductivity type.

[0067]

[0070] In particular embodiments of the power semiconductor device, the junction layer is ohmic or non-ohmic and the barrier layer is non-ohmic.

[0068]

[0071] The power semiconductor device further includes a dielectric layer located above the epitaxial layer and at least partially surrounding the junction layer and the barrier layer. A passivation layer is located on the dielectric layer, the first electrode, and the second electrode. A plurality of conductive bumps are located on the first electrode or the second electrode, respectively. The junction layer and the first electrode are separated from the barrier layer and the second electrode by the dielectric layer and the passivation layer.

[0069]

[0072] This disclosure uses spatially relative terms such as "below," "beneath," "lower," "above," "top," "left," and "right" to describe the relationship between one component or feature and one or more other components or features shown in the figures. Aside from the orientation shown in the figures, these spatially relative terms are also intended to cover different operational orientations of the device. The device may be oriented in other ways (e.g., rotated 90 degrees or positioned in other directions), and the spatially relative descriptions used herein are intended to be interpreted accordingly. When a component is described as "connected" or "coupled" to another component, it should be understood that the component may be directly connected or coupled to the other component, or that intervening components may be present.

[0070]

[0073] As used herein, terms such as "nearly," "substantially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, these terms can refer to the exact occurrence of the event or circumstance, as well as instances close to such occurrence. When used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed from one endpoint to another endpoint, or as inclusive of everything between two endpoints. All ranges disclosed herein include their endpoints unless otherwise specified. The term "substantially coplanar" can refer to two surfaces positioned along the same plane within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm. When numerical values or characteristics are described as "substantially" the same, these terms can refer to values within ±10%, ±5%, ±1%, or ±0.5% of the stated mean value.

[0071]

[0074] The foregoing has outlined the functionality and detailed aspects of some embodiments of the present disclosure. The embodiments described herein may readily serve as a basis for designing or modifying other processes and structures to carry out similar purposes or to achieve the advantages introduced by the described embodiments.

[0072]

[0075] Although the description has been set forth in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure, as defined by the appended claims. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, as those skilled in the art will readily appreciate from this disclosure that now-existing or later-developed processes, machines, manufacture, compositions of matter, means, methods, or steps may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. [Explanation of symbols]

[0073] 100 Power Semiconductor Devices 100a unit area 100b surrounding area 101 Base 101a board 101b epitaxial layer 101b-1 First epitaxial sublayer 101b-2 Second epitaxial sublayer 101b-3 Third epitaxial sublayer 101c doped channel 101c-1 first doped subchannel 101c-2 second doped subchannel 101c-3 Third doped subchannel 101d First Protection Ring 101d-1 First Protected Sub-Ring 101d-2 Second Protection Sub-Ring 101e doped region 101e-1 first doped subregion 101e-2 second doped subregion 101f Second Protection Ring 102 dielectric layer 102' Dielectric Material 103 Contact layer 103a Junction Layer 103b Barrier layer 103' Contact layer material 104 Electrode 104a first electrode 104b second electrode 104' electrode material 105 Passivation Layer 105' Passivation Layer Material 106 Conductive Bump 106a First conductive bump 106b Second conductive bump 107 Semiconductor Components 108 First Patterned Masking Layer 108a First opening 109 First protective layer 110 Second Patterned Masking Layer 110a Second opening 111 Third Patterned Masking Layer 111a Third opening 112 Second protective layer 113 Fourth Patterned Masking Layer 113a Fourth Opening 114 Fifth Patterned Masking Layer 114a Fifth Opening 115 Sixth Patterned Masking Layer 115a Sixth Opening 116 Third Layer of Protection 117 Seventh Patterned Masking Layer 117a Seventh Opening 118 Eighth Patterned Masking Layer 118a Eighth Opening 119 9th Patterned Masking Layer 119a Ninth Opening 120 10th Opening 200 Power Semiconductor Devices 300 Power Semiconductor Devices H1 Height of doped channel 101c H2 Height of the first guard ring 101d H3 Height of semiconductor component 107 T1: Thickness of the first epitaxial sublayer 101b-1 T2: Thickness of the second epitaxial sublayer 101b-2 T3: Thickness of the third epitaxial sublayer 101b-3

Claims

1. a base including a substrate and an epitaxial layer disposed above the substrate, the base having a unit area and a peripheral area surrounding the unit area; a junction layer located above the epitaxial layer in the peripheral area; a barrier layer located above the epitaxial layer within the unit area; a first electrode located on the junction layer; a second electrode located on the barrier layer; and Equipped with the epitaxial layer including a doped channel located in the peripheral area and extending between the junction layer and the base.

2. The power semiconductor device of claim 1 , wherein a height of the doped channel is substantially equal to a thickness of the epitaxial layer.

3. 2. The power semiconductor device of claim 1, wherein the epitaxial layer comprises a plurality of epitaxial sublayers stacked on top of one another, and the doped channel extends across the plurality of epitaxial sublayers.

4. The power semiconductor device of claim 3 , wherein each of the plurality of epitaxial sub-layers has substantially the same thickness.

5. 2. The power semiconductor device of claim 1, wherein the epitaxial layer includes a doped region located within the unit area and extending between the barrier layer and the base.

6. The power semiconductor device of claim 5 , wherein a height of the doped region is substantially less than the height of the doped channel.

7. The power semiconductor device of claim 5 , wherein the conductivity type of the doped region is opposite to the conductivity type of the doped channel.

8. a base including a substrate and an epitaxial layer disposed above the substrate, the base having a unit area and a peripheral area surrounding the unit area; a semiconductor component surrounded by the base and the epitaxial layer; a junction layer located above the epitaxial layer in the peripheral area; a first electrode located on the junction layer; and Equipped with the epitaxial layer including a doped channel located within the peripheral area and extending between the junction layer and the semiconductor component.

9. The power semiconductor device of claim 8 , wherein the semiconductor component comprises polysilicon.

10. The power semiconductor device of claim 8 , wherein the height of the epitaxial layer is substantially greater than 5 μm.

11. The power semiconductor device of claim 8 , wherein the height of the semiconductor component is substantially less than the height of the doped channel.

12. 12. The power semiconductor device of claim 11, wherein the height of the semiconductor component is about 2 μm.

13. The power semiconductor device of claim 8 , wherein a portion of the epitaxial layer extends between the doped channel and the base and is surrounded by the semiconductor component.

14. The power semiconductor device of claim 8 , wherein the height of the semiconductor component is substantially equal to or greater than the height of the doped channel.

15. 15. The power semiconductor device of claim 14, wherein the height of the semiconductor component is substantially greater than 5 μm.

16. forming a first epitaxial layer above a substrate; implanting doping ions into a portion of the first epitaxial layer to form a first doped channel; forming a second epitaxial layer on the first epitaxial layer; implanting the doping ions into a portion of the second epitaxial layer to form a second doped channel above the first doped channel; forming a junction layer above the second doped channel; forming a first electrode on the junction layer; Including, A method for manufacturing a power semiconductor device, wherein the first and second doped channels extend between the junction layer and the substrate.

17. before the step of forming the first epitaxial layer, forming a third epitaxial layer above the substrate; removing a portion of the third epitaxial layer to create an opening; filling the opening with a semiconductor material to form a semiconductor component; 17. The method of claim 16, further comprising:

18. The method of claim 17 , wherein the semiconductor component is located between the substrate and the doped channel.

19. 18. The method of claim 17, wherein the thickness of the third epitaxial layer is substantially equal to or greater than the thickness of either the first or second epitaxial layer.

20. 17. The method of claim 16, further comprising the step of annealing to activate the first doped channel prior to forming the second epitaxial layer and implanting the doping ions into the portion of the second epitaxial layer.

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