Manufacturing method of wiring board with built-in component

Abstract

To improve a quality of a manufacturing method of a wiring board built-in a component.SOLUTION: A manufacturing method of a wiring board with built-in a component includes steps of: forming a first insulating layer 111, a first conductor layer 121 including a plurality of conductor pads 121p, and a second insulating layer 112 covering the first conductor layer 121; forming a cavity RP, disposing an electronic component EC including a first electrode ECp1 and a second electrode ECp2 in the cavity RP, and electrically connecting the first electrode ECp1 and the conductor pads 121p; forming a third insulating layer 113 that fills the cavity RP; and forming a conductor that penetrates the third insulating layer 113 and is connected to the plurality of second electrodes ECp2. The step of forming the cavity RP includes steps of forming a through hole 112t exposing the conductor pad 121p by irradiating the second insulating layer 112 with a first laser beam; and reducing a thickness of the second insulating layer 112.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a component-embedded wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a substrate with built-in electronic components. In the disclosed method for manufacturing a substrate with built-in electronic components, an inner conductor layer formed on an inner insulating layer is formed so as to include a plane layer, and an electronic component (interposer) is mounted on this plane layer via an adhesive layer. Electrode terminals are formed on the surface of the electronic component opposite the plane layer, and via conductors are formed on these electrode terminals. The electrode terminals are connected to conductor pads on the surface of the substrate via these via conductors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-58472 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing method of a substrate with built-in electronic components disclosed in Patent Document 1, the portion of the inner conductor layer where the electronic components are arranged is formed as a plane layer. On one side of the electronic component (the plane layer side), it may be difficult to individually electrically connect each conductor in the substrate to each of the multiple electrodes of the electronic component. It is considered that the degree of freedom in selecting electronic components for the manufactured substrate with built-in electronic components is relatively low. [Means for solving the problem]

[0005] A method for manufacturing a wiring board with built-in components according to the present invention includes forming a first insulating layer, forming a first conductor layer including a plurality of conductor pads on an upper surface of the first insulating layer, forming a second insulating layer covering the first conductor layer and the first insulating layer, forming a cavity in the second insulating layer to expose the first conductor layer, placing an electronic component in the cavity, the electronic component having a plurality of first electrodes formed on one surface and a plurality of second electrodes formed on another surface opposite the one surface, forming a third insulating layer that fills the cavity and covers the other surface of the electronic component, and forming a conductor that penetrates the third insulating layer and connects to the plurality of second electrodes. Forming the cavity includes irradiating a component mounting area in the second insulating layer with a first laser light to form a plurality of through holes that penetrate the second insulating layer and expose the plurality of conductor pads, and reducing the thickness of the second insulating layer in the component mounting area, and placing the electronic component in the cavity includes electrically connecting the plurality of first electrodes and the plurality of conductor pads.

[0006] According to an embodiment of the present invention, a first electrode formed on one surface of an electronic component and a second electrode formed on the other surface thereof can be electrically connected to a conductor constituting a wiring board, thereby providing a method for manufacturing a component-embedded wiring board with a high degree of freedom in selecting an electronic component to be built in and a relatively high degree of freedom in the electrical connection structure between the electronic component and the conductor constituting the wiring board. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing an example of a component-embedded wiring board manufactured by a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention; [Figure 2] FIG. 2 is a partially enlarged view of the component-embedded wiring board of FIG. 1. [Figure 3A] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. [Figure 3B] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. [Figure 3C] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. [Figure 3D] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. [Figure 3E] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. [Figure 3F] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. [Figure 3G] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. [Figure 3H] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a component-embedded wiring board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] A component-embedded wiring board according to one embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a cross-sectional view showing a component-embedded wiring board 100, which is an example of a component-embedded wiring board manufactured by a method for manufacturing a component-embedded wiring board according to one embodiment. Fig. 2 shows an enlarged view of an area II surrounded by a dashed line in Fig. 1. In the description of this specification, component-embedded wiring board 100 is also simply referred to as wiring board 100.

[0009] 1 includes a core substrate 1. The core substrate 1 includes an insulating layer 3, and a conductor layer 2 is formed on each of two surfaces of the core substrate 1 that face each other in the thickness direction. The insulating layer 3 that constitutes the core substrate 1 is also referred to as a core insulating layer 3, and the conductor layer 2 that constitutes the core substrate 1 is also referred to as a core conductor layer 2.

[0010] Insulating layers and conductor layers are alternately laminated on one surface 1A and the other surface 1B of the core substrate 1 in the thickness direction. In the illustrated example, insulating layers 11, 111, 112, 110, 113, and 114 and conductor layers 12, 121, 122, and 123 are laminated on one surface 1A of the core substrate 1. Furthermore, insulating layers 21 and 214 and conductor layer 22 are laminated on the other surface 1B of the core substrate 1. The wiring board 100 has, as its outermost surface, a first surface 100A constituted by the insulating layer 114 and the conductor layer 123 exposed from the insulating layer 114, and a second surface 100B on the opposite side of the first surface 100A in the thickness direction, constituted by the insulating layer 214 and the conductor layer 22 exposed from the insulating layer 214.

[0011] In the description of each embodiment in this specification, the side of component-embedded wiring board 100 farther from core substrate 1 in the thickness direction is also referred to as the "upper side," "outer side," or "upper," or simply "upper" or "outer," and the side closer to core substrate 1 is also referred to as the "lower side," "inner side," or "lower." Furthermore, in each component of wiring board 100, the surface facing away from core substrate 1 is also referred to as the "upper surface," and the surface facing core substrate 1 is also referred to as the "lower surface."

[0012] In the illustrated example of wiring board 100, insulating layers 112 and 110 have recesses (cavities) RP formed therein that penetrate the insulating layers 112 and 110 in the thickness direction and expose conductive layers 121. An electronic component EC is disposed in the cavity RP, and the electronic component EC is electrically connected to the conductive layer 121 exposed on the bottom surface of the cavity RP. Specifically, a plurality of conductive pads (component mounting pads) 121p of the conductive layer 121 are exposed on the bottom surface of the cavity RP, and electrodes ECp1 of the electronic component EC are electrically connected to the conductive pads 121p via conductive connecting members BE. Resin that constitutes insulating layer 113 is filled into the cavity RP, and the electronic component EC is sealed in the cavity RP.

[0013] The component-embedded wiring board 100 in the illustrated example includes, as its outermost layers, an insulating layer 114 that covers the insulating layer 113 and the conductor layer 123, and an insulating layer 214 that covers the insulating layer 21 and the conductor layer 22. The insulating layers 114 and 214 may be solder resist layers. The outermost conductor layer 123 of the component-embedded wiring board 100 is exposed from an opening 114a formed in the insulating layer 114. The outermost conductor layer 22 of the component-embedded wiring board 100 is exposed from an opening 214a formed in the insulating layer 214.

[0014] In the drawings, the insulating layer 111 formed on the upper side of one surface 1A of the core substrate 1 and in contact with the lower surfaces of the multiple conductor pads 121p is also referred to as the first insulating layer 111. The conductor layer 121 formed in contact with the upper surface of the first insulating layer 111 is also referred to as the first conductor layer 121. The insulating layer 112 covering the first conductor layer 121 and the first insulating layer 111 exposed from the pattern of the first conductor layer 121 is also referred to as the second insulating layer 112. The conductor layer 122 formed in contact with the upper surface of the second insulating layer 112 is also referred to as the second conductor layer 122. The insulating layer 110 covering the second conductor layer 122 and the second insulating layer 112 exposed from the pattern of the second conductor layer 122 is also referred to as the covering insulating layer 110. The insulating layer 113 covering the covering insulating layer 110 and filling the cavity RP is also referred to as the third insulating layer 113. The conductor layer 123 formed in contact with the upper surface of the third insulating layer 113 is also referred to as the third conductor layer 123 .

[0015] The core insulating layer 3 includes a cylindrical through-hole conductor 4 that penetrates the core insulating layer 3 in the thickness direction and connects the core conductor layers 2 formed on both sides of the core insulating layer 3. The interior of the cylindrical through-hole conductor 4 is filled with a resin body 41 containing any resin such as epoxy resin. The wiring board 100 includes via conductors 13 that penetrate each of the insulating layers 11, 111, and 112 and the insulating layers 110 and 113. The via conductors 13 that penetrate each of the insulating layers 11, 111, and 112 connect adjacent conductor layers via the insulating layers 11, 111, and 112, and the via conductors 13 that penetrate the insulating layers 110 and 113 connect adjacent conductor layers via the insulating layers 110 and 113. The wiring board 100 also includes via conductors 23 that penetrate each of the insulating layers 21 and connect adjacent conductor layers via the insulating layers 21. Furthermore, the wiring board 100 has a via conductor 13e that penetrates the third insulating layer 113 and connects the electrode ECp2 formed on the top surface of the electronic component EC to the third conductor layer 123.

[0016] The insulating layers 3, 11, 111, 112, 110, 113, and 21 may be formed of any insulating resin. Examples of insulating resins include epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin. In the example shown in FIG. 1, the insulating layer 3 includes a core (reinforcing material) made of glass fiber or aramid fiber, while the insulating layers 11, 111, 112, 110, 113, and 21 do not include a core. However, any of the insulating layers 11, 111, 112, 110, 113, and 21 may include a core made of glass fiber or the like. The insulating layers 3, 11, 111, 112, 110, 113, and 21 may further include an inorganic filler. Examples of the inorganic filler included in each resin insulating layer include fine particles made of silica (SiO2), alumina, or mullite. The insulating layers 114, 214, which may be solder resist layers, may be formed using, for example, a photosensitive epoxy resin or a polyimide resin.

[0017] The conductor layers 2, 12, 121, 122, 123, and 22, the through-hole conductors 4, and the via conductors 13, 23, and 13e are formed using any metal, such as copper or nickel, and may be composed of, for example, a metal foil, such as copper foil, and / or a metal film formed by plating or sputtering. Although the conductor layers 2, 12, 121, 122, 123, and 22, the through-hole conductors 4, and the via conductors 13, 23, and 13e are shown as single-layer structures in FIG. 1 , they may have a multilayer structure having two or more metal layers. For example, the conductor layer 2 formed on the surface of the insulating layer 3 may have a five-layer structure including a metal foil (preferably copper foil), an electroless plated film (preferably electroless copper plated film), and an electrolytic plated film (preferably electrolytic copper plated film). Furthermore, the conductor layers 12, 121, 122, 123, and 22, the through-hole conductors 4, and the via conductors 13, 23, and 13e may have a two-layer structure including, for example, an electroless plated film (preferably an electroless copper plated film) and an electrolytic plated film (preferably an electrolytic copper plated film). Note that the conductor layers 12, 121, 122, and 123 and the via conductors 13 and 13e are shown as single layers in Fig. 1, but in the enlarged view of Fig. 2, two layers of an electroless plated film and an electrolytic plated film are shown.

[0018] Each of the conductor layers 2, 12, 121, 122, 123, and 22 can be formed to have any conductor pattern. As shown in the figure, the first conductor layer 121 formed on the first insulating layer 111 has multiple conductor pads 121p in an area (component mounting area) EA where electronic components EC are mounted. An insulating portion 112d made of insulating resin is interposed between adjacent conductor pads 121p among the multiple conductor pads 121p. As will be described in detail later in the manufacturing method for a component-embedded wiring board, the insulating portion 112d is a portion formed of the insulating resin that constitutes the second insulating layer 112. Specifically, the insulating portion 112d is a remaining portion obtained by removing a portion of the upper side of the insulating layer 112, and the conductor pad 121p is exposed at the bottom surface of a through-hole formed in the insulating portion 112d. The top surface of the conductor pad 121p and the top and side surfaces of the insulating portion 112d form the bottom surface of the cavity RP.

[0019] The outermost conductor layer 123 of the wiring board 100 is formed to have conductor pads 123p and 123pe that can be connected to, for example, an external circuit. The conductor layer 22 that constitutes the second surface 100B of the wiring board 100 has a conductor pad 22p. The insulating layer 114, which may be a solder resist layer, has an opening 114a that exposes the conductor pads 123p and 123pe, and the insulating layer 214 has an opening 214a that exposes the conductor pad 22p. The conductor pads 123p and 123pe exposed through the opening 114a can be electrically connected to connection pads of an external element, such as an electronic component EC, when the wiring board 100 is in use. The conductor pad 123pe is connected to a via conductor 13e that is connected to an electrode ECp2 formed on the upper surface of the electronic component EC. The conductor pad 22p can be used to connect the wiring board 100 to, for example, a motherboard of an electronic device or a package substrate of a semiconductor device having a stacked structure.

[0020] The electronic component EC accommodated in the cavity RP may be an active component such as a semiconductor device or a passive component such as a resistor. The connecting member BE may be made of any conductive material. Examples of the connecting member BE include solder or a conductive adhesive containing any conductive particles such as silver.

[0021] Next, the structure in the vicinity of the electronic component EC built into the component-embedded wiring substrate 100 will be described in detail with reference to Fig. 2, which is an enlarged view of region II surrounded by a dashed line in Fig. 1. As described above, a cavity RP is formed in the second insulating layer 112 and the covering insulating layer 110 above the first insulating layer 111. The cavity RP is formed by removing a portion of the covering insulating layer 110 and the second insulating layer 112, as will be described in detail later.

[0022] In the illustrated example, conductor pads 121p are also formed outside the component mounting area EA. Specifically, of the five conductor pads 121p shown in the figure, the rightmost conductor pad 121p and some of the leftmost conductor pads 121p are not included in the component mounting area EA and are not connected to the electronic component EC. The rightmost conductor pad 121p and the leftmost conductor pad 121p in the figure also form the bottom surface of the cavity RP, as do the three conductor pads 121p connected to the electronic component EC. No connecting member BE is disposed on the top surfaces of the rightmost conductor pad 121p and the leftmost conductor pad 121p in the figure, but the resin constituting the third insulating layer 113 filling the cavity RP is in contact with them. Thus, in the illustrated example of the component-embedded wiring substrate 100, the cavity RP is formed wider than the component mounting area EA in a direction perpendicular to the thickness direction of the wiring substrate 100. In addition, the first conductor layer 121 formed outside the component mounting area EA and constituting the bottom surface of the cavity RP, which corresponds to the conductor pads 121p at the right and left ends in the figure, may be a conductor pattern formed to surround the entire periphery of the component mounting area EA in a planar view.

[0023] When placed in the cavity RP, the electronic component EC has electrodes on two surfaces that are approximately perpendicular to the thickness direction of the wiring substrate 100. When placed in the cavity RP, the electronic component EC has a plurality of electrodes ECp1 located on the surface facing the bottom surface of the cavity RP, and a plurality of electrodes ECp2 located on the surface facing the opposite side to the bottom surface. The electrodes ECp1 are also referred to as first electrodes ECp1, and the electrodes ECp2 are also referred to as second electrodes ECp2.

[0024] In the illustrated example, each of the multiple first electrodes ECp1 of the electronic component EC is electrically connected to each of the multiple conductor pads 121p via a conductive connecting member BE. Furthermore, each of the multiple second electrodes ECp2 is electrically connected to each of the multiple conductor pads 123pe via a via conductor 13e. That is, in the component-embedded wiring board 100, the embedded electronic component EC can be electrically connected to each of the individual conductors constituting the wiring board 100 via the multiple electrodes formed on each of the two surfaces. Therefore, compared to a wiring board incorporating an electronic component that can be electrically connected to a signal line only on one surface, the component-embedded wiring board 100 can have a highly flexible electrical connection structure between the electronic component and the conductors constituting the wiring board.

[0025] An insulating portion 112d, which forms the bottom surface of the cavity RP and is interposed between adjacent conductor pads 121p among the plurality of conductor pads 121p, is made of the insulating resin that forms the second insulating layer 112. As will be described in detail later, the insulating portion 112d is a portion formed by removing a portion of the upper side in the thickness direction of the second insulating layer 112. A through hole 112t is formed in the insulating portion 112d. The through hole 112t exposes the conductor pad 121p at its bottom surface. A connection member BE is filled in the through hole 112t, and the first electrode ECp1 and the conductor pad 121p are connected via this connection member BE. The insulating portion 112d suppresses the degree of expansion of the connection member BE in the planar direction (the extension direction of the conductor layer 121), thereby suppressing the occurrence of short circuits between adjacent conductor pads 121p.

[0026] The insulating portion 112d can be formed to any thickness from the viewpoint of suppressing short circuits between the conductor pads 121p as described above, and from the viewpoint of suppressing an increase in the dimension in the thickness direction of the wiring board 100 taking into consideration the thickness of the built-in electronic component EC (the dimension in the depth direction of the cavity RP). Specifically, the shortest distance D between the upper surface of the insulating layer 112 and the upper surface of the first conductor layer 121 at the bottom of the cavity RP (i.e., the shortest distance D between the upper surface of the conductor pad 121p and the upper surface of the insulating portion 112d) can be set to, for example, 10 μm or more and 30 μm or less.

[0027] In the illustrated example, an underfill material UF is filled between the electronic component EC placed in the cavity RP and the bottom surface of the cavity RP (specifically, the upper surface of the insulating portion 112d). The underfill material UF can be formed, for example, by filling the gap between the electronic component EC and the insulating portion 112d in a fluid state and solidifying it when the electronic component EC is connected to the second conductor layer 121 via the connecting member BE. The upper surface of the electronic component EC may be roughened, which allows the electronic component EC to adhere relatively well to the third insulating layer 113 and be sealed relatively stably within the wiring substrate 100.

[0028] Next, a method for manufacturing a component-embedded wiring board according to one embodiment will be described with reference to FIGS. 3A to 3H using the component-embedded wiring board 100 of FIG. 1 as an example.

[0029] First, as shown in FIG. 3A, a core substrate 1 is prepared. To prepare the core substrate 1, for example, a double-sided copper-clad laminate having a metal foil provided on the surface of an insulating layer 3 is prepared. A through hole 4a is formed in the double-sided copper-clad laminate by, for example, drilling. An electroless plating film, for example, is formed on the inner wall of the through hole 4a and on the upper surface of the metal foil, and an electrolytic plating film is formed on the electroless plating film using the electroless plating film as a power supply layer. As a result, although shown as a single layer in the figure, a cylindrical through-hole conductor 4 is formed, which has a two-layer structure of an electroless plating film and an electrolytic plating film and covers the inner wall of the through hole 4a.

[0030] The inside of the cylindrical through-hole conductor 4 formed on the inner wall of the through-hole 4a is filled with a resin body 41 by injecting, for example, epoxy resin into the inside of the through-hole conductor 4. After the filled resin body 41 hardens, an electroless plated film and an electrolytic plated film are further formed on the upper surfaces of the resin body 41 and the electrolytic plated film. As a result, although shown as a single layer in the figure, a conductor layer 2 having a five-layer structure of metal foil, electroless plated film, electrolytic plated film, electroless plated film, and electrolytic plated film is formed on both sides of the insulating layer 3. Then, by patterning the conductor layer 2 using a subtractive method, a core substrate 1 having a predetermined conductor pattern is obtained.

[0031] 3B, four insulating layers and four conductor layers are laminated on one surface 1A and the other surface 1B of the core substrate 1. Specifically, three insulating layers 11 and three conductor layers 12 are alternately laminated on one surface 1A of the core substrate 1, and a first insulating layer 111 is formed on the outside thereof, and a first conductor layer 121 is formed on the first insulating layer 111. Four insulating layers 21 and four conductor layers 22 are alternately laminated on the other surface 1B of the core substrate 1.

[0032] For example, each insulating layer 11, 21, 111 can be formed by thermocompression bonding a film-like insulating resin (e.g., epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin) onto the conductor layer and insulating layer below each insulating layer 11, 21, 111 (e.g., onto the core insulating layer 3 and conductor layer 2 in the case of the innermost insulating layer 11). The conductor layers 12, 121, 22 are formed using any conductor pattern forming method such as a semi-additive method, simultaneously with via conductors 13, 23 that fill openings that can be formed in the insulating layers 11, 111, 21 by, for example, laser light.

[0033] Specifically, in forming the conductor layers 12, a metal film is first formed by electroless plating or sputtering over the entire upper surface of the insulating layer 11 that serves as the base for each conductor layer 12 and in through holes drilled in the insulating layer 11. A plating film is then formed by pattern plating, including electrolytic plating, using the metal film as a power supply layer. Via conductors 13 are formed in the through holes drilled in each insulating layer 11. Then, unnecessary portions of the metal film are removed by, for example, etching. As a result, each conductor layer 12 has a two-layer structure with a predetermined conductor pattern. Each conductor layer 12 is formed using any metal, such as copper or nickel. The conductor layer 22 on the insulating layer 21 and the conductor layer 121 on the insulating layer 111 can also be formed by the same method as the conductor layer 12.

[0034] Forming the first conductor layer 121 includes forming a plurality of conductor pads 121p in a predetermined region. The conductor pads 121p are formed at least in a component mounting region EA (see FIG. 3F ) where an electronic component EC is to be mounted in a subsequent process. As shown in the figure, the first conductor layer 121 may also be formed outside the component mounting region EA in the planar direction (extension direction of the conductor layer 121) in the region constituting the bottom surface of the cavity RP to be formed. In the example shown in the figure, conductor pads 121p are also formed outside the component mounting region EA, and of the five conductor pads 121p, two conductor pads 121p located at the right and left ends are located outside the component mounting region EA. In some cases, a conductor pattern that continuously surrounds the entire periphery of the component mounting region EA in a planar view is formed as the first conductor layer 121 outside the component mounting region EA in the region constituting the bottom surface of the cavity RP.

[0035] Next, as shown in FIG. 3C, on the upper side of one surface 1A of the core substrate 1, a second insulating layer 112 is formed by the same method as the insulating layer 11 described above. The second insulating layer 112 covers the first conductor layer 121 and the first insulating layer 111 exposed from the conductor pattern of the first conductor layer 121. Furthermore, a second conductor layer 122 is formed on the second insulating layer 112 by the same method as the conductor layer 12 described above. Furthermore, a covering insulating layer 110 is formed on the second conductor layer 122 to cover the second conductor layer 122 and the second insulating layer 112 exposed from the conductor pattern of the second conductor layer 122. Note that, in forming the second conductor layer 122, no conductor pattern is formed in the region where the through hole 112t (see FIG. 3D) will be formed in the subsequent process. On the upper side of the other surface 1B of the core substrate 1, two more insulating layers 21 and one conductor layer 22 are formed from the state shown in FIG. 3B. As shown in the figure, one of the two outermost surfaces is made up of the covering insulating layer 110, and the other opposite surface is made up of the insulating layer 21.

[0036] Next, the formation of the cavity RP and the arrangement of the electronic component EC will be described in detail with reference to Figures 3D to 3G, which show enlarged views of the area near the conductor pad 121p, which corresponds to the area shown in Figure 2. Note that, in Figures 3D to 3G, as in Figure 2, electroless plated films and electrolytic plated films are shown as the conductor layers and via conductors of the two-layer structure, respectively.

[0037] First, as shown in FIG. 3D, a through-hole 112t is formed by penetrating the insulating layers 110 and 112 and exposing the first conductor layer 121 (conductor pad 121p) at the bottom. The through-hole 112t is formed by irradiating the insulating layer 110 with a laser beam BM1 from outside. The conductor pad 121p can function as a stopper for the laser beam BM1 when forming the through-hole 112t. The laser beam BM1 may be selected according to the diameter of the through-hole 112t, and may be, for example, a CO2 laser (wavelength 10,600 nm) or a UV-YAG laser (wavelength 355 nm). The laser beam BM1 used to form the through-hole 112t is also referred to as a first laser beam BM1.

[0038] The through holes 112t are formed so as to expose the conductor pads 121p located within the region where the cavity RP (see FIG. 3E) is to be formed, and are formed so as to expose at least the conductor pads 121p located within the component mounting region EA (see FIG. 3F) within the cavity RP to be formed. As shown in the following FIGS. 3E and 3F, when the cavity RP is formed to be wider in the planar direction than the component mounting region EA, the through holes 112t may be formed to also expose the conductor pads 121p located outside the component mounting region EA. In the drawing, of the five conductor pads 121p shown, the through holes 112t are formed to expose the two conductor pads 121p located at the right and left ends, which are located outside the component mounting region EA.

[0039] 3E, portions of the insulating layer 110 and the insulating layer 112 located within the area where the cavity RP is to be formed are removed, thereby forming the cavity RP. The remaining portion of the second insulating layer 112 (the portion that forms the bottom of the cavity RP) whose thickness is reduced by the removal is referred to as the insulating portion 112d. The bottom surface of the formed cavity RP is composed of the upper surface of the conductor pad 121p exposed at the bottom surface of the through hole 112t, the side surface of the insulating portion 112d (the side wall surface of the through hole 112t), and the upper surface of the insulating portion 112d. The portions of the insulating layer 110 and the insulating layer 112 can be removed by, for example, wet etching using a chemical solution, dry etching using oxygen or carbon tetrafluoride as a reactive gas, or skiving using laser light.

[0040] When removing portions of the insulating layer 110 and the insulating layer 112 by irradiation with laser light, the laser light used may be a laser light (second laser light) having a wavelength different from that of the first laser light BM1. The second laser light may be, for example, a CO laser (wavelength 10,600 nm). In forming the cavity RP, the insulating portion 112d may be formed to have any thickness in order to prevent short-circuiting between the conductor pads 121p in the subsequent process of mounting electronic components EC (see FIG. 3F). For example, the insulating portion 112d may be formed so that the shortest distance between the upper surface of the insulating portion 112d and the upper surface of the conductor pad 121p is 10 μm or more and 30 μm or less. In the illustrated example, the cavity RP is formed over a range wider than the component mounting area EA in the planar direction.

[0041] 3D and 3E, the formation of the cavity RP in the manufacturing method of the component-embedded wiring board of the embodiment includes exposing the plurality of conductor pads 121p by forming a plurality of through holes 112t in the insulating layer 112, and forming the insulating portion 112d by partially removing the insulating layer 112. In the present embodiment, by employing such a cavity RP formation process, the cavity RP having, at its bottom, a plurality of conductor pads each electrically isolated by an insulating portion can be formed relatively easily.

[0042] After the cavity RP is formed, the inner surface of the cavity RP may be subjected to a desmear treatment. Resin residue that may remain in the cavity RP may be removed by treatment using a chemical solution containing, for example, permanganate. Note that during the desmear treatment, the second conductor layer 122 is protected from the chemical solution by the covering insulating layer 110.

[0043] Next, as shown in FIG. 3F, an electronic component EC is placed in the cavity RP, and the electronic component EC and the first conductor layer 121 are electrically connected. The prepared electronic component EC has a plurality of first electrodes ECp1 on one side and a plurality of second electrodes ECp2 on the opposite side. As described above, the electronic component EC is, for example, an active component such as a semiconductor device or a passive component such as a resistor. A connection member BE, for example, a solder ball, is placed on the conductor pad 121p exposed on the bottom surface of the cavity RP, and the electronic component EC is then placed using a die bonder or the like so that the first electrode ECp1 contacts the top of the connection member BE. Note that solder may be placed on the surface of the first electrode ECp1 of the electronic component EC, and the solder and the electronic component EC may be integrally placed on the conductor pad 121p.

[0044] The subsequent reflow process bonds and electrically connects the conductor pad 121p, the connection member BE, and the first electrode ECp1. When placing the electronic component EC in the cavity RP, the cavity RP is formed wider than the component-mounting area EA in the planar direction, as shown in the figure, which can prevent interference between the electronic component EC and the inner wall of the cavity RP. Therefore, the electronic component EC can be placed relatively accurately in the desired position.

[0045] Next, as shown in the figure, after the conductor pad 121p, the connection member BE, and the first electrode ECp1 are bonded, an underfill UF may be filled into the gap between the electronic component EC and the bottom surface of the cavity RP and then cured. After the electronic component EC is placed in the cavity RP, the top surface of the electronic component EC may be roughened by, for example, wet etching using a chemical solution to improve adhesion with the insulating layer 113 (see FIG. 3G) that will be formed subsequently and that will cover the electronic component EC.

[0046] Next, as shown in FIG. 3G, a third insulating layer 113 is formed. When the insulating layer 113 is formed, a film-like epoxy resin, for example, laminated to form the insulating layer 113, flows into the cavity RP by heating and pressure. As a result, the insulating resin forming the third insulating layer 113 fills the cavity RP and covers the surface of the electronic component EC. The electronic component EC is sealed in the cavity RP by the third insulating layer 113. The insulating layer 113 is formed to cover the entire upper surface of the insulating layer 110. Note that, as shown in the figure, the cavity RP is formed wider than the component mounting area EA in the planar direction, so that the side surfaces of the electronic component EC can also be covered by the insulating layer 113. This allows the electronic component EC to be more stably sealed in the cavity RP.

[0047] Next, as shown in FIG. 3H , via conductors 13 and 13e penetrating the third insulating layer 113 and a third conductor layer 123 in contact with the upper surface of the third insulating layer 113 are formed. The via conductor 13 is formed integrally with the third conductor layer 123 formed on the third insulating layer 113, in a through hole that continuously penetrates the third insulating layer 113 and the covering insulating layer 110 to expose the second conductor layer 122. The via conductor 13e is formed integrally with the third conductor layer 123 formed on the third insulating layer 113, in an opening that penetrates the third insulating layer 113 to expose the second electrode ECp2. The second conductor layer 122 is connected to the third conductor layer 123 via the via conductor 13, and the second electrode ECp2 is connected to the third conductor layer 123 via the via conductor 13e. The third conductor layer 123 is formed in a pattern having conductor pads 123p and 123pe used for connection to an external circuit. Specifically, the via conductor 13e formed in the opening that exposes the second electrode ECp2 can be formed integrally with the conductor pad 123pe.

[0048] As described above, in the method for manufacturing a component-embedded wiring board of this embodiment, an electronic component EC is prepared as an electronic component to be built in, the electronic component having a first electrode ECp1 on one surface and a second electrode ECp2 on the other opposite surface. Both the first and second electrodes ECp1 and ECp2 are electrically connected to the conductors that make up the wiring board. Specifically, each of the multiple first electrodes ECp1 is connected to each of the multiple conductor pads 121p, and each of the multiple second electrodes ECp2 is connected to the third conductor layer 123. Therefore, the method for manufacturing a component-embedded wiring board of this embodiment offers greater freedom in selecting the electronic component to be built in, compared to a manufacturing method that simply connects each of the multiple electrodes provided on one surface of the electronic component to an individual conductor pad.

[0049] As shown in the figure, simultaneously with the formation of the third insulating layer 113 and the formation of the via conductors 13, 13e and conductor layer 123, the formation of the outermost insulating layer 21, the formation of the outermost via conductor 23 and the outermost conductor layer 22 can also be carried out on the opposite side of the core substrate 1. When the outermost conductor layer 22 is formed, a conductor pad 22p is provided as its conductor pattern.

[0050] Thereafter, an insulating layer 114, which may be a solder resist layer, is formed on the insulating layer 113 exposed from the conductor layer 123 and the conductor pattern of the conductor layer 123, and an insulating layer 214 is formed on the insulating layer 21 exposed from the conductor layer 22 and the conductor pattern of the conductor layer 22. An opening 114a exposing the conductor pad 123p is formed in the insulating layer 114, and an opening 214a exposing the conductor pad 22p is formed in the insulating layer 214. The insulating layers 114, 214 and the openings 114a, 214a in each insulating layer 114, 214 can be formed by forming a resin layer containing a photosensitive epoxy resin or polyimide resin, and then exposing and developing the resin using a mask with an appropriate opening pattern. The component-embedded wiring substrate 100 shown in FIG. 1 is completed.

[0051] The manufacturing method of the above-described component-embedded wiring board is not limited to the method described with reference to the drawings. The manufacturing method of the component-embedded wiring board of the embodiment may include at least the following steps: forming a first insulating layer, a first conductor layer having multiple conductor pads, and a second insulating layer; forming through holes exposing the multiple conductor pads by irradiating the second insulating layer with laser light; reducing the thickness of the second insulating layer in the component mounting area to form a cavity; placing an electronic component having a first electrode and a second electrode in the cavity; electrically connecting the first electrode to the conductor pad; forming a third insulating layer filling the cavity; and electrically connecting the conductor penetrating the third insulating layer to the second electrode. The conditions and order of these steps may be modified as appropriate. Depending on the structure of the wiring board to be manufactured, some steps may be omitted or other steps may be added. Therefore, for example, the second conductor layer 122 may not be covered by the covering insulating layer 110, but may be directly covered by the third insulating layer 113. The formation of the core substrate 1 and the formation of the insulating layer 21 and the conductor layer 22 on the upper side of the other surface 1B of the core substrate 1 may be omitted. [Explanation of symbols]

[0052] 100 Component embedded wiring board 1 Core board 1A One side 1B The other side 2 Core conductor layer 3 Core insulation layer 4 through-hole conductors 11, 21, 114, 214 Insulating layer 110 Insulating layer (coating insulating layer) 111 Insulating layer (first insulating layer) 112 Insulating layer (second insulating layer) 112t through hole 112d Insulation 113 Insulation layer (third insulation layer) 12, 22 Conductor layer 121 Conductor layer (first conductor layer) 121p contact pad 122 Conductor layer (second conductor layer) 123 Conductor layer (third conductor layer) RP Cavity EC electronic parts EA component mounting area ECp1 electrode (1st electrode) ECp2 electrode (second electrode)

Claims

1. forming a first insulating layer; forming a first conductor layer including a plurality of conductor pads on an upper surface of the first insulating layer; forming a second insulating layer covering the first conductor layer and the first insulating layer; forming a cavity in the second insulating layer to expose the first conductor layer; placing an electronic component in the cavity, the electronic component having a plurality of first electrodes formed on one surface and a plurality of second electrodes formed on another surface opposite to the one surface; forming a third insulating layer that fills the cavity and covers the other surface of the electronic component; forming a conductor that penetrates the third insulating layer and connects to the plurality of second electrodes; A method for manufacturing a component-embedded wiring substrate, comprising: forming the cavity includes: irradiating a component mounting region in the second insulating layer with a first laser light to form a plurality of through holes that penetrate the second insulating layer and expose the plurality of conductor pads; and reducing a thickness of the second insulating layer in the component mounting region; Placing the electronic component in the cavity includes electrically connecting the first electrodes to the contact pads.

2. 2. The method for manufacturing a component-embedded wiring board according to claim 1, wherein reducing the thickness of the second insulating layer includes irradiating the second insulating layer with a second laser beam.

3. 3. The method for manufacturing a component-embedded wiring board according to claim 2, wherein the wavelength of the first laser light is different from the wavelength of the second laser light.

4. 4. The method for manufacturing a component-embedded wiring board according to claim 3, wherein the first laser beam is a UV-YAG laser, and the second laser beam has a wavelength of CO 2 It's a laser.

5. 2. The method for manufacturing a component-embedded wiring board according to claim 1, wherein electrically connecting the first electrode and the conductor pad includes connecting the first electrode and the conductor pad with solder.

6. 2. The method for manufacturing a component-embedded wiring board according to claim 1, wherein forming the cavity includes reducing the thickness of the second insulating layer on the conductor pad to 10 μm or more and 30 μm or less.

7. 2. The method for manufacturing a component-embedded wiring board according to claim 1, further comprising roughening the other surface of the electronic component after placing the electronic component in the cavity.

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